A semiconductor structure and its manufacturing method

Abstract

This disclosure provides a semiconductor structure including a substrate and a multi-channel heterojunction layer stacked together. The multi-channel heterojunction layer includes multiple heterojunction layers, each including a channel layer and a barrier layer, and the multi-channel heterojunction layer has multiple grooves. A P-type epitaxial layer includes multiple first P-type regions filling the grooves. A lateral PN junction is formed by the first P-type regions and the two-dimensional electron gas in the heterojunction. Under reverse bias, the depletion region of the PN junction widens, thus pinching off the current path and effectively shielding the low-barrier-height Schottky junction. This suppresses the Schottky barrier reduction effect and controls the reverse leakage current, thereby increasing the breakdown voltage and maintaining a low turn-on voltage. Simultaneously, the stacking of multiple heterojunctions forms multiple parallel two-dimensional electron gas paths between the anode and cathode, compensating for the depletion of the two-dimensional electron gas by the first P-type regions and ensuring the forward current of the diode.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and specifically to a semiconductor structure and its manufacturing method. Background Technology

[0002] Junction barrier Schottky diodes (JBS), as a type of enhancement-mode Schottky diode, have become a research hotspot. The outstanding advantages of JBS diodes are that they possess the on-state and fast switching characteristics of Schottky barrier diodes, as well as the off-state and low leakage current characteristics of PIN diodes. GaN, with its larger bandgap, higher critical breakdown electric field, and higher electron saturation drift velocity, along with its excellent physical and chemical properties such as chemical stability, high temperature resistance, and radiation resistance, stands out in the fabrication of high-performance power devices and has enormous application potential.

[0003] Due to dislocation issues in GaN material, junction barrier Schottky diodes exhibit significant leakage current, preventing them from fully realizing their structural advantages. In high-voltage switching applications, achieving GaN diodes with low reverse leakage current, high reverse withstand voltage, low forward voltage drop, and simple manufacturing processes remains a significant technological challenge. Summary of the Invention

[0004] In view of this, the present disclosure provides a semiconductor structure and a method for manufacturing the same, to further reduce the reverse leakage current of GaN-based junction barrier Schottky diodes and fully utilize the structural advantages of junction barrier Schottky diodes.

[0005] According to one aspect of this disclosure, an embodiment of this disclosure provides a semiconductor structure, characterized in that it includes:

[0006] A substrate and a multi-channel heterojunction layer are stacked together. The multi-channel heterojunction layer is a first, second, ..., nth heterojunction layer in the direction away from the substrate, where n ≥ 2. Each heterojunction layer includes a channel layer and a barrier layer. The multi-channel heterojunction layer has a plurality of grooves. The bottom surface of at least one groove is located in the channel layer of the first heterojunction layer. The plurality of grooves are located at one end of the multi-channel heterojunction layer and are spaced apart along a first direction. Each groove extends along a second direction that is perpendicular to the first direction and parallel to the plane of the substrate.

[0007] The P-type epitaxial layer includes a plurality of first P-type regions that fill the grooves.

[0008] As an optional embodiment, the contact interface between the channel layer and the barrier layer in each heterojunction layer has a two-dimensional electron gas, and the length of the first P-type region along the second direction and / or along the first direction is different at different two-dimensional electron gases.

[0009] As an optional embodiment, the length of each first P-type region along the second direction increases uniformly or in a stepped manner in the direction away from the substrate.

[0010] As an optional embodiment, the length of each of the first P-type regions along the first direction increases uniformly or in a stepped manner in the direction away from the substrate.

[0011] As an optional embodiment, the bottom surface of the groove has a (1-100) crystal plane or a (11-20) crystal plane.

[0012] As an optional embodiment, the P-type epitaxial layer further includes a second P-type layer located on the multi-channel heterojunction layer and the plurality of first P-type regions, the second P-type layer being connected to the plurality of first P-type regions.

[0013] As an optional embodiment, the length of the second P-type layer along the second direction is greater than or equal to the length of the first P-type region along the second direction.

[0014] As an optional embodiment, the second P-type layer completely covers the multi-channel heterojunction layer.

[0015] As an optional embodiment, at least two of the first P-type regions have different lengths along the first direction.

[0016] As an optional embodiment, at least two of the first P-type regions are spaced at different distances along the first direction.

[0017] As an optional embodiment, the material of the P-type epitaxial layer includes a P-type gallium nitride-based material.

[0018] As an optional embodiment, the semiconductor structure further includes:

[0019] The anode and cathode are located at opposite ends of the multi-channel heterojunction layer, with the anode in contact with the first P-type region and located at the same end of the multi-channel heterojunction layer.

[0020] As an optional embodiment, at least one of the first P-type regions has a tip at one end near the cathode.

[0021] As an optional embodiment, the semiconductor structure further includes:

[0022] A passivation layer covers the entire surface of the multi-channel heterojunction layer and the P-type epitaxial layer.

[0023] According to another aspect of this disclosure, one embodiment of this disclosure provides a method for manufacturing a semiconductor structure, characterized by comprising the following steps:

[0024] S1. A substrate is provided, on which a multi-channel heterojunction layer is grown, wherein the multi-channel heterojunction layer is a heterojunction layer of the first, second, ..., nth layer in the direction away from the substrate, where n≥2, and each heterojunction layer includes a channel layer and a barrier layer.

[0025] S2. A plurality of grooves are etched at one end of the multi-channel heterojunction layer, the bottom surface of at least one of the grooves is located in the channel layer of the first heterojunction layer, the plurality of grooves are spaced apart along a first direction, and each groove extends along a second direction that is perpendicular to the first direction and parallel to the plane of the substrate.

[0026] S3. Extend the first P-type region twice in the groove.

[0027] As an optional embodiment, the method for manufacturing the semiconductor structure further includes:

[0028] S4. Continue to extend the first P-type region to form a healed second P-type layer.

[0029] As an optional embodiment, the method for manufacturing the semiconductor structure further includes:

[0030] S5. Etch the two ends of the multi-channel heterojunction layer to form an anode region and a cathode region. The anode region is in contact with the first P-type region and is located at the same end of the multi-channel heterojunction layer. An anode is provided in the anode region and a cathode is provided in the cathode region.

[0031] This disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate and a multi-channel heterojunction layer stacked together. The multi-channel heterojunction layer is a first, second, ..., n heterojunction layer in the direction away from the substrate, where n ≥ 2. Each heterojunction layer includes a channel layer and a barrier layer. The multi-channel heterojunction layer has a plurality of grooves. The bottom surface of at least one groove is located in the channel layer of the first heterojunction layer. The plurality of grooves are located at one end of the multi-channel heterojunction layer and are spaced apart along a first direction. Each groove extends along a second direction perpendicular to the first direction and parallel to the plane of the substrate. A P-type epitaxial layer is also provided, which includes a plurality of first P-type regions that fill the grooves.

[0032] This disclosure utilizes a first P-type region to form a lateral PN junction with a two-dimensional electron gas in the heterojunction. Under reverse bias, the depletion region of the PN junction widens, effectively pinching off the current path and shielding the low-barrier-height Schottky junction. This suppresses the Schottky barrier reduction effect and controls reverse leakage current, increasing the breakdown voltage while maintaining a low turn-on voltage. Simultaneously, the stacking of multiple heterojunctions between the anode and cathode forms multiple parallel two-dimensional electron gas pathways, significantly reducing the diode's on-resistance and compensating for the depletion of the two-dimensional electron gas by the first P-type region, ensuring a large forward current. The first P-type region and the second P-type layer work synergistically to redistribute the surface electric field of the heterojunction structure between the anode and cathode, improving the electric field distribution at the anode edge, preventing avalanche breakdown, further increasing the device's breakdown voltage, and reducing reverse leakage current. Attached Figure Description

[0033] Figure 1 The diagram shown is a schematic diagram of a semiconductor structure provided in an embodiment of this disclosure.

[0034] Figure 2 The diagram shown is a schematic diagram of a semiconductor structure provided in an embodiment of this disclosure.

[0035] Figure 3 The diagram shown is a schematic diagram of a semiconductor structure provided in an embodiment of this disclosure.

[0036] Figures 4a to 4b The image shown is a front view of a semiconductor structure provided in an embodiment of this disclosure.

[0037] Figures 5a to 5b The image shown is a side view of a semiconductor structure provided in an embodiment of this disclosure.

[0038] Figure 6 The diagram shown is a schematic diagram of a semiconductor structure provided in an embodiment of this disclosure.

[0039] Figures 7a to 7b The image shown is a side view of a semiconductor structure provided in an embodiment of this disclosure.

[0040] Figure 8 The image shown is a top view of a semiconductor structure provided in an embodiment of this disclosure.

[0041] Figure 9 The diagram shown is a schematic diagram of a semiconductor structure provided in an embodiment of this disclosure.

[0042] Figure 10 The diagram shown is a flowchart of a semiconductor structure manufacturing method according to an embodiment of this disclosure.

[0043] Figure 11-14 The diagram shown is an intermediate structure diagram of a semiconductor structure provided in an embodiment of this disclosure during the manufacturing process. Detailed Implementation

[0044] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0045] To further reduce the reverse leakage current of GaN-based junction barrier Schottky diodes and fully utilize their structural advantages, this disclosure provides a semiconductor structure and its manufacturing method. The semiconductor structure includes a substrate and a multi-channel heterojunction layer stacked together. The multi-channel heterojunction layer comprises multiple heterojunction layers, each including a channel layer and a barrier layer, and has multiple grooves. A P-type epitaxial layer includes multiple first P-type regions filling the grooves. A lateral PN junction is formed between the first P-type regions and the two-dimensional electron gas in the heterojunction. Under reverse bias, the depletion region of the PN junction widens, effectively pinching off the current path and shielding the low-barrier-height Schottky junction. This suppresses the Schottky barrier reduction effect and controls the reverse leakage current, thereby increasing the breakdown voltage and maintaining a low turn-on voltage. Simultaneously, the stacking of multiple heterojunctions forms multiple parallel two-dimensional electron gas pathways between the anode and cathode, compensating for the depletion of the two-dimensional electron gas by the first P-type regions and ensuring the forward current of the diode.

[0046] The following is combined with Figures 1 to 14 A further example illustrates a semiconductor structure and its manufacturing method mentioned in this disclosure.

[0047] Figure 1 The diagram shown is a schematic diagram of a semiconductor structure provided in an embodiment of this disclosure. Figure 2 The diagram shown is a schematic representation of a semiconductor structure provided in an embodiment of this disclosure. Figure 1 As shown, the semiconductor structure includes a substrate 10 and a multi-channel heterojunction layer 20 stacked together. The multi-channel heterojunction layer 20 has 1st, 2nd, ..., nth heterojunction layers in the direction away from the substrate 10, where n ≥ 2. Each heterojunction layer includes a channel layer 21 and a barrier layer 22. The multi-channel heterojunction layer 20 has multiple grooves 201, the bottom surface of at least one groove 201 is located in the channel layer 21 of the first heterojunction layer, the multiple grooves 201 are located at one end of the multi-channel heterojunction layer 20 and are spaced apart along a first direction, and each groove 201 extends along a second direction perpendicular to the first direction and parallel to the plane of the substrate 10; a P-type epitaxial layer 30 includes a first P-type region 31 filling the multiple grooves 201. Figure 2As shown, the semiconductor structure further includes an anode 41 and a cathode 42, located at both ends of the multi-channel heterojunction layer 20. The anode 41 is in contact with the first P-type region 31 and is located at the same end of the multi-channel heterojunction layer 20.

[0048] In this embodiment, the multi-channel heterojunction layer 20 may include only two heterojunction layers, namely, a first heterojunction layer and a second heterojunction layer stacked away from the substrate 10. In other embodiments, the multi-channel heterojunction layer 20 may include three or more heterojunction layers, namely, a first heterojunction layer, a second heterojunction layer, ..., an nth heterojunction layer stacked away from the substrate 10, where n ≥ 3. Each heterojunction layer includes a channel layer 21 and a barrier layer 22. The bandgap of the material of the barrier layer 22 is greater than the bandgap of the material of the channel layer 21. The materials of the channel layer 21 and the barrier layer 22 may include group III nitride materials, and a two-dimensional electron gas may be formed at the interface between the channel layer 21 and the barrier layer 22. In one optional embodiment, the channel layer 21 is a GaN layer, and the barrier layer 22 is an AlGaN layer. In other alternatives, the material combination of the channel layer 21 and the barrier layer 22 can also be GaN / AlN, GaN / InN, GaN / InAlGaN, GaAs / AlGaAs, GaN / InAlN, or InN / InAlN. The materials of the multilayer heterojunction layers can be the same or different, and this disclosure does not impose specific limitations.

[0049] In this embodiment, the bottom surface of the groove 201 in the multi-channel heterojunction layer 20 has a (1-100) crystal plane or a (11-20) crystal plane. The groove 201 with a (1-100) or (11-20) crystal plane on its bottom surface helps to reduce the electric field intensity at the sharp corners of the groove in the subsequently manufactured device. The groove 201 can also be etched a second time to form a rounded bottom corner structure, which can similarly reduce the electric field intensity at the sharp corners of the groove in the subsequently manufactured device. The material of the P-type epitaxial layer 30 disposed in the groove 201 includes a P-type gallium nitride-based material. Figure 3 The diagram shown is a schematic representation of a semiconductor structure according to an embodiment of this disclosure. In this embodiment, the groove 201 can be located inside and at both ends of the multi-channel heterojunction layer 20, such as... Figure 1 As shown, in another embodiment, the groove 201 may be located only inside the multi-channel heterojunction layer 20, such as... Figure 3 As shown.

[0050] Figures 4a to 4b The image shown is a front view of a semiconductor structure provided in an embodiment of this disclosure. Figures 5a to 5bThe image shown is a side view of a semiconductor structure provided in an embodiment of this disclosure. In one embodiment, the contact interface between the channel layer 21 and the barrier layer 22 in each heterojunction layer has a two-dimensional electron gas, and the lengths of the first P-type regions 31 at different two-dimensional electron gases along the second direction and / or along the first direction are different. Specifically, the length of each first P-type region 31 along the second direction increases uniformly in the direction away from the substrate 10 (e.g., Figure 4a (as shown) or step-like increase (such as) Figure 4b As shown), and / or, the length of each first P-type region 31 along the first direction increases uniformly in the direction away from the substrate 10 (e.g. Figure 5a (as shown) or step-like increase (such as) Figure 5b (As shown). By changing the length of the first P-type region 31 along the second and first directions, the channel shape can be changed to increase the electron movement path, thereby reducing the on-state resistance. On the other hand, the depletion layer width can be changed to reduce the peak electric field, thereby increasing the breakdown voltage.

[0051] Figure 6 The diagram shown is a schematic representation of a semiconductor structure provided in an embodiment of this disclosure. In one embodiment, as... Figure 1 As shown, the P-type epitaxial layer 30 further includes a second P-type layer 32 located on the multi-channel heterojunction layer 20 and the plurality of first P-type regions 31, the second P-type layer 32 being connected to the plurality of first P-type regions 31. The length of the second P-type layer 32 along the second direction is greater than or equal to the length of the first P-type regions 31 along the second direction. Optionally, as... Figure 6 As shown, the second P-type layer 32 covers the entire surface of the multi-channel heterojunction layer 20. The first P-type region 31 and the second P-type layer 32 can work together to redistribute the surface electric field of the heterojunction structure between the anode 41 and the cathode 42, which can improve the electric field distribution at the edge of the anode 41, prevent avalanche breakdown, further improve the device breakdown voltage and reduce the reverse leakage current.

[0052] Figures 7a to 7b The image shown is a side view of a semiconductor structure provided in an embodiment of this disclosure. In one embodiment, as... Figure 7a As shown, at least two first P-type regions 31 have different lengths (a1, a2) along the first direction. In another embodiment, as... Figure 7b As shown, at least two first P-type regions 31 have different spacing distances along the first direction (b1, b2). By changing the length and spacing distance of the multiple first P-type regions 31 along the first direction, the channel shape and depletion layer width can be further changed, the electron movement path and peak electric field can be adjusted, thereby reducing the on-state resistance and increasing the breakdown voltage.

[0053] Figure 8 The image shown is a top view of a semiconductor structure provided in an embodiment of this disclosure. In one embodiment, as... Figure 8As shown, at least one of the first P-type regions 31 has a pointed tip at one end near the cathode 42. Designing a pointed tip at one end of the first P-type region 31 can further improve the electric field distribution between the anode 41 and the cathode 42.

[0054] Figure 9 The diagram shown is a schematic representation of a semiconductor structure provided in an embodiment of this disclosure. In one embodiment, as... Figure 9 As shown, the semiconductor structure also includes a passivation layer 43, which covers the entire surface of the multi-channel heterojunction layer 20 and the P-type epitaxial layer 30. The material of the passivation layer 43 can be SiN, SiO2, SiON, Al2O3, MgO, Ga2O3 or HfO2, and it is used to prevent external water and oxygen from entering the P-type epitaxial layer 30 and the multi-channel heterojunction layer 20.

[0055] According to another aspect of this disclosure, Figure 10 The diagram shown is a flowchart of a semiconductor structure manufacturing method according to an embodiment of this disclosure. Figure 11-14 The diagram shown is an intermediate structure diagram of a semiconductor structure provided in an embodiment of this disclosure during the manufacturing process. Figure 10 As shown, a semiconductor structure manufacturing method provided in one embodiment of this disclosure includes the following steps:

[0056] Step S1: Provide a substrate and grow a multi-channel heterojunction layer on the substrate. The multi-channel heterojunction layer is the 1st, 2nd, ..., nth heterojunction layer in the direction away from the substrate, where n≥2. Each heterojunction layer includes a channel layer and a barrier layer.

[0057] Specifically, such as Figure 11As shown, a substrate 10 is provided, and a multi-channel heterojunction layer 20 is grown on the substrate 10. The multi-channel heterojunction layer 20 is a first, second, ..., nth heterojunction layer in the direction away from the substrate 10, where n ≥ 2. Each heterojunction layer includes a channel layer 21 and a barrier layer 22. The material of the substrate 10 includes any one or more combinations of Si, Al2O3, GaN, SiC, or AlN. The method for growing the multi-channel heterojunction layer 20 on the substrate 10 can be in-situ growth, or it can be prepared by atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), or a combination thereof.

[0058] Step S2: Etch multiple grooves at one end of the multi-channel heterojunction layer. The bottom surface of at least one groove is located in the channel layer of the first heterojunction layer. The multiple grooves are spaced apart along the first direction, and each groove extends along a second direction that is perpendicular to the first direction and parallel to the plane of the substrate.

[0059] Specifically, such as Figure 12 As shown, multiple grooves 201 are etched at one end of the multi-channel heterojunction layer 20. The bottom surface of at least one groove 201 is located in the channel layer 21 of the first heterojunction layer. The multiple grooves 201 are spaced apart along a first direction, and each groove 201 extends along a second direction perpendicular to the first direction and parallel to the plane of the substrate 10. By controlling the shape and spacing of the grooves 201, the shape and spacing of the first P-type region 31 grown in the grooves 201 can be controlled.

[0060] Step S3: Extend the first P-type region twice in the groove.

[0061] Specifically, such as Figure 13 As shown, a first P-type region 31 is epitaxially grown in the groove 201. By controlling the shape and spacing of the first P-type region 31 grown in the groove 201, the channel shape and depletion layer width of the semiconductor structure can be adjusted, the electron movement path and peak electric field can be modified, thereby reducing the on-state resistance and increasing the breakdown voltage.

[0062] Step S4: Continue to extend the first P-type region to form a healed second P-type layer.

[0063] Specifically, such as Figure 14 As shown, a healed second P-type layer 32 is formed by epitaxy on the first P-type region 31. The first P-type region 31 and the second P-type layer 32 can work together to redistribute the surface electric field of the heterojunction structure between the subsequently formed anode 41 and cathode 42, which can improve the electric field distribution at the electrode edge, prevent avalanche breakdown, further improve the device breakdown voltage and reduce the reverse leakage current.

[0064] Step S5: Etch the two ends of the multi-channel heterojunction layer to form an anode region and a cathode region. The anode region is in contact with the first P-type region and is located at the same end of the multi-channel heterojunction layer. An anode is set in the anode region and a cathode is set in the cathode region.

[0065] Specifically, the two ends of the etched multi-channel heterojunction layer 20 form an anode region and a cathode region. The anode region is in contact with the first P-type region 31 and is located at the same end of the multi-channel heterojunction layer 20. An anode 41 is disposed in the anode region, and a cathode 42 is disposed in the cathode region, forming a structure as shown in the image. Figure 2 The semiconductor structure shown is used to fabricate a junction barrier Schottky diode, which can reduce the reverse leakage current of the junction barrier Schottky diode and fully utilize the structural advantages of the junction barrier Schottky diode.

[0066] This disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate and a multi-channel heterojunction layer stacked together. The multi-channel heterojunction layer is a first, second, ..., n heterojunction layer in the direction away from the substrate, where n ≥ 2. Each heterojunction layer includes a channel layer and a barrier layer. The multi-channel heterojunction layer has a plurality of grooves. The bottom surface of at least one groove is located in the channel layer of the first heterojunction layer. The plurality of grooves are located at one end of the multi-channel heterojunction layer and are spaced apart along a first direction. Each groove extends along a second direction perpendicular to the first direction and parallel to the plane of the substrate. A P-type epitaxial layer is also provided, which includes a plurality of first P-type regions that fill the grooves.

[0067] This disclosure utilizes a first P-type region to form a lateral PN junction with a two-dimensional electron gas in the heterojunction. Under reverse bias, the depletion region of the PN junction widens, effectively pinching off the current path and shielding the low-barrier-height Schottky junction. This suppresses the Schottky barrier reduction effect and controls reverse leakage current, increasing the breakdown voltage while maintaining a low turn-on voltage. Simultaneously, the stacking of multiple heterojunctions between the anode and cathode forms multiple parallel two-dimensional electron gas pathways, significantly reducing the diode's on-resistance and compensating for the depletion of the two-dimensional electron gas by the first P-type region, ensuring a large forward current. The first P-type region and the second P-type layer work synergistically to redistribute the surface electric field of the heterojunction structure between the anode and cathode, improving the electric field distribution at the anode edge, preventing avalanche breakdown, further increasing the device's breakdown voltage, and reducing reverse leakage current.

[0068] It should be understood that the term "comprising" and its variations as used in this disclosure are open-ended, meaning "including but not limited to". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment". In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0069] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications or equivalent substitutions made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: A substrate (10) and a multi-channel heterojunction layer (20) are stacked together. The multi-channel heterojunction layer (20) is the first, second, ..., nth heterojunction layer in the direction away from the substrate (10), where n≥2. Each heterojunction layer includes a channel layer (21) and a barrier layer (22). The multi-channel heterojunction layer (20) has a plurality of grooves (201). The bottom surface of at least one groove (201) is located in the channel layer (21) of the first heterojunction layer. The plurality of grooves (201) are located at one end of the multi-channel heterojunction layer (20) and are spaced apart along a first direction. Each groove (201) extends along a second direction that is perpendicular to the first direction and parallel to the plane of the substrate (10). P-type epitaxial layer (30), the P-type epitaxial layer (30) includes a plurality of first P-type regions (31) filling the grooves (201), wherein the contact interface between the channel layer (21) and the barrier layer (22) in each heterojunction layer has a two-dimensional electron gas, and each first P-type region (31) satisfies one of the following relationships: Each of the first P-type regions (31) increases uniformly or in a stepped manner along the second direction in a direction away from the substrate (10); or Each of the first P-type regions (31) increases in length along the first direction uniformly or in a stepped manner in the direction away from the substrate (10).

2. The semiconductor structure according to claim 1, characterized in that, The bottom surface of the groove (201) has a (1-100) crystal plane or a (11-20) crystal plane.

3. The semiconductor structure according to claim 1, characterized in that, The P-type epitaxial layer (30) further includes a second P-type layer (32) located on the multi-channel heterojunction layer (20) and the plurality of first P-type regions (31), the second P-type layer (32) being connected to the plurality of first P-type regions (31).

4. The semiconductor structure according to claim 3, characterized in that, The length of the second P-type layer (32) along the second direction is greater than or equal to the length of the first P-type region (31) along the second direction.

5. The semiconductor structure according to claim 4, characterized in that, The second P-type layer (32) covers the entire surface of the multi-channel heterojunction layer (20).

6. The semiconductor structure according to claim 1, characterized in that, At least two of the first P-type regions (31) have different spacing along the first direction.

7. The semiconductor structure according to claim 1, characterized in that, The material of the P-type epitaxial layer (30) includes a P-type gallium nitride-based material.

8. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes: The anode (41) and cathode (42) are located at both ends of the multi-channel heterojunction layer (20), with the anode (41) in contact with the first P-type region (31) and located at the same end of the multi-channel heterojunction layer (20).

9. The semiconductor structure according to claim 8, characterized in that, At least one of the first P-type regions (31) has a pointed end near the cathode (42).

10. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: A passivation layer (43) covers the entire surface of the multi-channel heterojunction layer (20) and the P-type epitaxial layer (30).

11. A method for manufacturing a semiconductor structure, characterized in that, Includes the following steps: S1. Provide a substrate (10) and grow a multi-channel heterojunction layer (20) on the substrate (10). The multi-channel heterojunction layer (20) is the first, second, ..., nth heterojunction layer in the direction away from the substrate (10), where n≥2. Each heterojunction layer includes a channel layer (21) and a barrier layer (22). S2. A plurality of grooves (201) are etched at one end of the multi-channel heterojunction layer (20), at least one of the grooves (201) is located in the channel layer (21) of the first heterojunction layer, the plurality of grooves (201) are spaced apart along a first direction, and each groove (201) extends along a second direction that is perpendicular to the first direction and parallel to the plane of the substrate (10); S3. A first P-type region (31) is epitaxially extended in the groove (201), wherein the contact interface between the channel layer (21) and the barrier layer (22) in each heterojunction layer has a two-dimensional electron gas, and each first P-type region (31) satisfies one of the following relationships: Each of the first P-type regions (31) increases uniformly or in a stepped manner along the second direction in a direction away from the substrate (10); or Each of the first P-type regions (31) increases in length along the first direction uniformly or in a stepped manner in the direction away from the substrate (10).

12. The method for manufacturing a semiconductor structure according to claim 11, characterized in that, The method for manufacturing the semiconductor structure further includes: S4. Continue to extend the first P-type region (31) to form a healed second P-type layer (32).

13. The method for manufacturing a semiconductor structure according to claim 11, characterized in that, The method for manufacturing the semiconductor structure further includes: S5. Etch the two ends of the multi-channel heterojunction layer (20) to form an anode region and a cathode region. The anode region is in contact with the first P-type region (31) and is located at the same end of the multi-channel heterojunction layer (20). An anode (41) is provided in the anode region and a cathode (42) is provided in the cathode region.

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