Composite semiconductor device and preparation method thereof
By synchronously performing multiple N-type ion dopings with different energies, the drift region of the composite semiconductor device is formed, and the problems of complex process and high cost in the prior art are solved, and the effects of reducing on-internal resistance and increasing breakdown voltage are achieved.
Patent Information
- Application Number
- CN202510238175.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-28
- Publication Date
- 2025-06-03
AI Technical Summary
When the existing composite semiconductor devices form the drift region of the LDMOS device part and the N well of the CMOS structure of different functional devices, the process is complex and requires multiple mask plates and multiple N-type ion implantation, resulting in high costs and many process steps.
By synchronously performing multiple N-type ion dopings of different energies, a drift region of the LDMOS device is formed, specifically including synchronously performing the first N-type ion doping on the high-voltage N-well region of the flash memory and the first doping region of the LDMOS device, synchronously performing the second N-type ion doping on the N-well region of the input and output device and the second doping region of the LDMOS device, and performing the third N-type ion doping on the third doping region of the LDMOS device, forming a drift region to reduce the concentration gradient from the drain to the source.
The overall concentration of LDMOS devices is increased, effectively reducing on-internal resistance, increasing the breakdown voltage of the device, while reducing the cost of the mask and reducing the ion doping process steps.
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Figure CN120091579A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a compound semiconductor device and a preparation method thereof. Background Art
[0002] The compound semiconductor device adopts a flash memory combined with a BCD process platform, and integrates an LDMOS device part and a CMOS structure of different functional devices on the same substrate. The LDMOS device part adopts a lateral variable doping technology and requires three ion implantations to form an N-type drift region; the N-well of the CMOS structure of different functional devices also requires ion implantation. At present, in order to form the drift region of the LDMOS device part and the N-well of the CMOS structure of different functional devices, multiple mask plates and multiple N-type ion implantation processes are required, and the process is complex and the mask cost is high. Summary of the Invention
[0003] The purpose of the present invention is to provide a compound semiconductor device and a preparation method thereof, which can increase the overall concentration of the LDMOS device, effectively reduce the on-resistance, improve the breakdown voltage of the device, while reducing the photomask cost and reducing the ion doping process steps.
[0004] The present invention provides a preparation method of a compound semiconductor device, including:
[0005] Providing a substrate for integrating a flash memory, an input / output device and an LDMOS device;
[0006] Synchronously performing a first N-type ion doping on the high-voltage N-well region of the flash memory and the first doping region of the LDMOS device;
[0007] Synchronously performing a second N-type ion doping on the N-well region of the input / output device and the second doping region of the LDMOS device;
[0008] Performing a third N-type ion doping on the third doping region of the LDMOS device; wherein, the first doping region, the second doping region and the third doping region together form the drift region of the LDMOS device, and the concentration gradient of the drift region decreases from the drain to the source of the LDMOS device.
[0009] Further, the first N-type ion doping is performed by three N-type ion implantations with different energies to form an inverted doping well, and the energy ranges of the three times are 200 Kev to 300 Kev, 300 Kev to 400 Kev, and 650 Kev to 750 Kev respectively, and the first N-type ion implantation dose is 3E12 / cm 2 ~7E12 / cm 2 .
[0010] Further, the second N-type ion doping is formed by three N-type ion implantations with different energies. The energy ranges of the three times are 200 Kev to 300 Kev, 400 Kev to 500 Kev, and 750 Kev to 850 Kev respectively. The second N-type ion implantation dose is 1E12 / cm 2 ~4E12 / cm 2 .
[0011] Further, the third N-type ion doping is formed by three N-type ion implantations with different energies. The energy ranges of the three times are 50 Kev to 90 Kev, 200 Kev to 300 Kev, and 500 Kev to 550 Kev respectively. The third N-type ion implantation dose is 1E12 / cm 2 ~5E12 / cm 2 .
[0012] Further, the input / output device is a CMOS device, and the drain voltage of the CMOS device is 5V.
[0013] Further, the first N-type ion doping dopes the high-voltage N-well region in at least one of the high-voltage CMOS devices used in the signal amplification circuit, address selection circuit, charge pump circuit, and encoding and decoding circuit in the peripheral unit of the flash memory.
[0014] Further, the previous step or the next step of performing the second N-type ion doping is: performing P-type ion doping on the P-well region of the input / output device.
[0015] Further, the previous step or the next step of performing the first N-type ion doping is: performing P-type ion doping on the high-voltage P-well region of the flash memory.
[0016] The present invention also provides a compound semiconductor device, including:
[0017] A substrate, on which a flash memory, an input / output device, and an LDMOS device are integrated;
[0018] The N-type ion doping concentrations of the high-voltage N-well region of the flash memory and the first doping region of the LDMOS device are the same;
[0019] The N-type ion doping concentrations of the N-well region of the input / output device and the second doping region of the LDMOS device are the same;
[0020] The third doping region of the LDMOS device is doped with N-type ions; wherein, the first doping region, the second doping region, and the third doping region together form the drift region of the LDMOS device, and the concentration gradient of the drift region decreases from the drain to the source of the LDMOS device.
[0021] Further, the input / output device is a CMOS device, and the drain voltage of the CMOS device is 5V; the high-voltage N-well region is the N-well region of the high-voltage CMOS device used in at least one of the signal amplification circuit, address selection circuit, charge pump circuit, and encoding and decoding circuit in the peripheral unit of the flash memory.
[0022] Compared with the prior art, the present invention has the following beneficial effects:
[0023] The present invention provides a compound semiconductor device and a preparation method thereof, including: providing a substrate for integrating a flash memory, an input / output device, and an LDMOS device; synchronously performing first N-type ion doping on the high-voltage N-well region of the flash memory and the first doping region of the LDMOS device; synchronously performing second N-type ion doping on the N-well region of the input / output device and the second doping region of the LDMOS device; performing third N-type ion doping on the third doping region of the LDMOS device; wherein, the first doping region, the second doping region, and the third doping region together form the drift region of the LDMOS device, and the concentration gradient of the drift region from the drain to the source of the LDMOS device decreases. By increasing the overall concentration of the LDMOS device, the on-resistance is effectively reduced, the breakdown voltage of the device is improved, while the mask cost is reduced and the ion doping process steps are reduced. Description of the Drawings
[0024] Figure 1 It is a schematic flow chart of a preparation method of a compound semiconductor device according to an embodiment of the present invention.
[0025] Figure 2 It is a partial schematic diagram of an input / output device in a compound semiconductor device according to an embodiment of the present invention.
[0026] Figure 3 It is a partial schematic diagram of a flash memory in a compound semiconductor device according to an embodiment of the present invention.
[0027] Figure 4 It is a simplified partial schematic diagram of an LDMOS device in a compound semiconductor device according to an embodiment of the present invention.
[0028] Figure 5 It is a detailed partial schematic diagram of an LDMOS device in a compound semiconductor device according to an embodiment of the present invention.
[0029] Figure 6 It is Figure 4 a partial size schematic diagram of the LDMOS device in
[0030] Figure 7 It is an electric field distribution diagram of the drift region of an LDMOS device in a compound semiconductor device according to an embodiment of the present invention.
[0031] Among them, the reference numerals are as follows:
[0032] 10 - Substrate; 11 - Input / output device; 12 - Flash memory; 13 - LDMOS device; 131 - Drift region; 132 - P-type body region; 133 - Shallow trench isolation; 134 - Polysilicon layer; N1 - First doping region; N2 - Second doping region; N3 - Third doping region. Detailed implementation manners
[0033] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the purpose of the embodiments of the present invention.
[0034] For ease of description, some embodiments of the present application may use spatial relative terms such as "above", "below", "top", "bottom", etc. to describe the relationship between one element or component and another (or other) element or component as shown in the respective drawings of the embodiments. It should be understood that in addition to the orientations described in the drawings, the spatial relative terms are also intended to include different orientations of the device during use or operation. For example, if the device in the drawing is flipped, the element or component described as "below" or "beneath" other elements or components will subsequently be positioned "above" or "on top of" other elements or components. The terms "first", "second", etc. in the following are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that these terms may be replaced where appropriate.
[0035] Embodiments of the present invention provide a method for manufacturing a compound semiconductor device, as Figure 1 shown, including:
[0036] S1. Provide a substrate for integrating a flash memory, an input / output device, and an LDMOS device;
[0037] S2. Synchronously perform first N-type ion doping on the high-voltage N-well region of the flash memory and the first doping region of the LDMOS device;
[0038] S3. Synchronously perform second N-type ion doping on the N-well region of the input / output device and the second doping region of the LDMOS device;
[0039] S4. Perform third N-type ion doping on the third doping region of the LDMOS device; wherein, the first doping region, the second doping region, and the third doping region together constitute the drift region of the LDMOS device, and the concentration gradient of the drift region decreases from the drain to the source of the LDMOS device.
[0040] Next, in conjunction with Figures 2 to 5Describe in detail each step of the preparation method of the composite semiconductor device according to the embodiments of the present invention. Figure 2 It is a schematic diagram of a part of the input / output device 11 in a composite semiconductor device according to an embodiment of the present invention. Figure 3 It is a schematic diagram of a part of the flash memory 12 in a composite semiconductor device according to an embodiment of the present invention. Figure 4 It is a simplified schematic diagram of a part of the LDMOS device 13 in a composite semiconductor device according to an embodiment of the present invention. Figure 5 It is a detailed schematic diagram of a part of the LDMOS device 13 in a composite semiconductor device according to an embodiment of the present invention.
[0041] As shown, in step S1, a substrate 10 is provided, and subsequent processes integrate a flash memory 12, an input / output device 11, and an LDMOS device 13 on the same substrate 10. Among them, the substrate 10 can be any suitable substrate material known in the art. For example, it can be at least one of the materials mentioned below: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, and also includes multi-layer structures composed of these semiconductors, etc., or is silicon on insulator (SOI), silicon-on-insulator stacked silicon (SSOI), silicon germanium-on-insulator stacked silicon (S-SiGeOI), silicon germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or can also be a double-sided polished silicon wafer. Exemplarily, the substrate in this embodiment is a silicon wafer.
[0042] Step S2, as Figure 3 and Figure 4 shown, the first N-type ion doping is synchronously performed on the high-voltage N-well region (HV N-Well) of the flash memory 12 and the first doping region N1 of the LDMOS device 13. Exemplarily, the first N-type ion doping is formed by three N-type ion implantations with different energies to form an inverted doped well. The energy ranges of the three times are 200 Kev to 300 Kev, 300 Kev to 400 Kev, and 650 Kev to 750 Kev respectively. The first N-type ion implantation dose is 3E12 / cm 2 ~7E12 / cm 2 . The high-voltage N-well region (HV N-Well) of the flash memory 12 and the first doping region N1 of the LDMOS device 13 share the same photomask and the same ion doping process, reducing the cost of one photomask and the ion doping process.
[0043] The first N-type ion doping is performed on the high-voltage N-well region (HV N-Well) of the high-voltage CMOS devices used in at least one of the signal amplification circuit, address selection circuit, charge pump circuit, and encoding and decoding circuit in the peripheral units of the flash memory 12. The previous step or the subsequent step of performing the first N-type ion doping is: performing P-type ion doping on the high-voltage P-well region (HV P-Well) of the flash memory 12.
[0044] Step S3, as Figure 2 and Figure 4 shown, the second N-type ion doping is synchronously performed on the N-well region (N-Well) of the input / output device 11 and the second doping region N2 of the LDMOS device. Exemplarily, the second N-type ion doping is formed by three N-type ion implantations with different energies, and the three energy ranges are 200 Kev to 300 Kev, 400 Kev to 500 Kev, and 750 Kev to 850 Kev respectively. The second N-type ion implantation dose is 1E12 / cm 2 ~4E12 / cm 2 . The N-well region (N-Well) of the input / output device 11 and the second doping region N2 of the LDMOS device share the same mask and the same ion doping process, reducing the cost of one mask and the ion doping process.
[0045] The input / output device 11 is a CMOS device, and the drain voltage of the CMOS device is 5V. The previous step or the subsequent step of performing the second N-type ion doping can be: performing P-type ion doping on the P-well region (P-Well) of the input / output device 11.
[0046] Step S4, as Figure 4 and Figure 5 shown, the third N-type ion doping is performed on the third doping region N3 of the LDMOS device 13. Exemplarily, the third N-type ion doping is formed by three N-type ion implantations with different energies, and the three energy ranges are 50 Kev to 90 Kev, 200 Kev to 300 Kev, and 500 Kev to 550 Kev respectively. The third N-type ion implantation dose is 1E12 / cm 2 ~5E12 / cm 2 .
[0047] Figure 6 is Figure 4 a partial dimension schematic diagram of the LDMOS device in Figure 6As shown, taking the case where the lateral width dimension of the drift region of the 50V switching LDMOS is 4.7 μm as an example, there are sufficient critical dimensions to synchronously perform the first N-type ion doping on the high-voltage N-well region of the flash memory 12 and the first doped region N1 of the LDMOS device 13. The second N-type ion doping is synchronously performed on the N-well region 11 of the input / output device and the second doped region N2 of the LDMOS device. The N-type ion-doped region N+ in the upper region of the drift region is the drain. The abscissa of the left boundary of the drain is defined as 0, and the abscissa at the junction of the right side of the drain and the shallow trench isolation (i.e., STI2) 133 is X1. The abscissa of the right boundary of the third doped region N3 is X2. X2 is determined by the voltage requirements of the LDMOS. For a 50V switching LDMOS, it is usually between 3.5 μm and 6.5 μm. The abscissa interval of the first doped region N1 is [0.2, X1]; the range of the abscissa of the right boundary of the second doped region N2 is [X1 + 0.2 μm, X2 - 0.4 μm].
[0048] The first doped region N1, the second doped region N2, and the third doped region N3 together constitute the drift region 131 of the LDMOS device. In the LDMOS device 13, the N-type ion-doped region N+ in the upper region of the P-type body region 132 is the source, and the N-type ion-doped region N+ in the upper region of the drift region 131 is the drain. The concentration gradient of the drift region 131 from the drain to the source of the LDMOS device 13 decreases, realizing lateral variable doping. As Figure 4 and Figure 7 shown, the laterally variably doped drift region 131 of the present invention adopts a form of doping that changes with the length. A mask template with a series of different width windows is used for ion implantation, and then a high-temperature annealing is utilized to obtain a drift region 131 with a gradually changing impurity concentration. Since a new electric field peak is introduced at the junction of the concentration partitions, the electric field of the drift region is optimized, and the breakdown voltage of the LDMOS device 13 is improved.
[0049] As Figure 5 shown, in the LDMOS device 13 part, an N-type buried layer NBL and a P-type epitaxial layer P-epi are sequentially formed on the substrate 10. A drift region 131 and a P-type body region 132 are formed in the upper region of the P-type epitaxial layer P-epi. A shallow trench isolation (i.e., STI2) 133 is formed on the side of the drift region 131 away from the P-type body region 132, and a shallow trench isolation 133 is also formed in the upper region inside the drift region 131. A polysilicon layer 134 is formed above the substrate 10, and the polysilicon layer 134 serves as the gate of the LDMOS device 13.
[0050] The lateral variable-doping LDMOS realizes a gradient reduction in the concentration of the drain-to-source drift region through three ion implantations to achieve an overall increase in concentration, effectively reducing the on-resistance, and at the same time can effectively improve the breakdown voltage of the device. The composite semiconductor device of the present invention adopts a flash memory combined with a BCD process platform, and integrates an LDMOS device part, a flash memory part, and an input / output device part on the same substrate. The N-well implantation of the flash high-voltage CMOS structure and the 5V input / output device is close to the implantation conditions of the drift region in terms of both implantation depth and doping concentration. N1 / N2 / N3 is not fixed according to Figure 7 the combination, and only requires meeting the gradient reduction in the concentration of the drain-to-source drift region.
[0051] The present invention also provides a composite semiconductor device, including:
[0052] a substrate 10, on which a flash memory 12, an input / output device 11, and an LDMOS device 13 are integrated;
[0053] The N-type ion doping concentration of the high-voltage N-well region of the flash memory is the same as that of the first doping region N1 of the LDMOS device 13;
[0054] The N-type ion doping concentration of the N-well region of the input / output device is the same as that of the second doping region N2 of the LDMOS device;
[0055] The third doping region N3 of the LDMOS device is doped with N-type ions; wherein, the first doping region N1, the second doping region N2, and the third doping region N3 together form the drift region 131 of the LDMOS device, and the concentration gradient from the drain to the source of the LDMOS device decreases.
[0056] The input / output device 11 is a CMOS device, and the drain terminal voltage of the CMOS device is 5V. The high-voltage N-well region is the N-well region in the high-voltage CMOS device used in at least one of the signal amplification circuit, the address selection circuit, the charge pump circuit, and the encoding and decoding circuit in the peripheral unit of the flash memory 12.
[0057] In summary, the present invention provides a compound semiconductor device and a method for manufacturing the same, including: providing a substrate for integrating a flash memory, input / output devices, and an LDMOS device; synchronously performing first N-type ion doping on the high-voltage N-well region of the flash memory and the first doping region of the LDMOS device; synchronously performing second N-type ion doping on the N-well region of the input / output devices and the second doping region of the LDMOS device; performing third N-type ion doping on the third doping region of the LDMOS device; wherein the first doping region, the second doping region, and the third doping region together form the drift region of the LDMOS device, and the concentration gradient of the drift region from the drain to the source of the LDMOS device decreases. The overall concentration of the LDMOS device is increased, effectively reducing the on-resistance, improving the breakdown voltage of the device, while reducing the mask cost and reducing the number of ion doping process steps.
[0058] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other. For the methods disclosed in the embodiments, since they correspond to the devices disclosed in the embodiments, the description is relatively simple. For the relevant parts, refer to the description in the method section.
[0059] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the rights of the present invention in any way. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes, and decorations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention all belong to the protection scope of the technical solutions of the present invention.
Claims
1. A method for preparing a composite semiconductor device, characterized in that: include: Providing a substrate, wherein the substrate is used to integrate a flash memory, an input-output device, and an LDMOS device; Synchronously performing a first N-type ion doping on the high-voltage N-well region of the flash memory and the first doping region of the LDMOS device; Synchronously performing a second N-type ion doping on the N-well region of the input-output device and the second doping region of the LDMOS device; A third N-type ion doping is performed on the third doping region of the LDMOS device; wherein the first doping region, the second doping region and the third doping region together constitute a drift region of the LDMOS device, and a concentration gradient of the drift region decreases from the drain to the source of the LDMOS device.
2. The method for preparing a composite semiconductor device according to claim 1, wherein: The first N-type ion doping is performed by three N-type ion implantations with different energies to form a reverse doped well. The energy ranges of the three times are 200Kev to 300Kev, 300Kev to 400Kev, and 650Kev to 750Kev, respectively. The first N-type ion implantation dose is 3E12 / cm 2 ~7E12 / cm 2 .
3. The method for preparing a composite semiconductor device according to claim 1, wherein: The second N-type ion doping is formed by three N-type ion implantations with different energies, the energy ranges of the three times are 200Kev-300Kev, 400Kev-500Kev, 750Kev-850Kev, and the second N-type ion implantation dose is 1E12 / cm 2 ~4E12 / cm 2 .
4. The method for preparing a composite semiconductor device according to claim 1, wherein: The third N-type ion doping is formed by three N-type ion implantations with different energies, the energy ranges of the three times are 50Kev~90Kev, 200Kev~300Kev, 500Kev~550Kev respectively, and the third N-type ion implantation dose is 1E12 / cm 2 ~5E12 / cm 2 .
5. The method for preparing a composite semiconductor device according to claim 1, wherein: The input-output device is a CMOS device, and the drain voltage of the CMOS device is 5V.
6. The method for preparing a composite semiconductor device according to claim 1, wherein: The first N-type ion doping is used to dope the high-voltage N-well region in the high-voltage CMOS device used in at least one of the signal amplification circuit, the address selection circuit, the charge pump circuit, and the encoding and decoding circuit in the peripheral unit of the flash memory.
7. The method for preparing a composite semiconductor device according to claim 1, wherein: The step before or after performing the second N-type ion doping is: performing P-type ion doping on the P-well region of the input-output device.
8. The method for preparing a composite semiconductor device according to claim 1, wherein: The step before or after performing the first N-type ion doping is: performing P-type ion doping on the high-voltage P-well region of the flash memory.
9. A composite semiconductor device, characterized in that: The composite semiconductor device is formed by the method according to any one of claims 1 to 8, and the composite semiconductor device comprises: A substrate, on which a flash memory, an input-output device and an LDMOS device are integrated; The N-type ion doping concentration of the high-voltage N-well region of the flash memory and the first doping region of the LDMOS device is the same; The N-type ion doping concentration of the N-well region of the input-output device and the second doping region of the LDMOS device is the same; The third doping region of the LDMOS device is doped with N-type ions; wherein the first doping region, the second doping region and the third doping region together constitute a drift region of the LDMOS device, and a concentration gradient of the drift region decreases from the drain to the source of the LDMOS device.
10. The composite semiconductor device according to claim 9, wherein: The input-output device is a CMOS device, and the drain voltage of the CMOS device is 5V; the high-voltage N-well region is the N-well region in the high-voltage CMOS device used in at least one of the signal amplification circuit, address selection circuit, charge pump circuit and encoding and decoding circuit in the peripheral unit of the flash memory.