Vertical device epitaxial body and preparation method thereof

Abstract

The invention relates to a vertical device epitaxial body and a preparation method thereof, and the method comprises the steps: growing a first semiconductor layer from a vertical interface under a first growth condition, and enabling the lattice of the vertical interface to have hexagonal symmetry; the width of the first semiconductor layer is not less than half of the width of a preset epitaxial body; growing a second semiconductor layer from the outer surface of the first semiconductor layer under a second growth condition; wherein the thickness of the second semiconductor layer growing from the longitudinal side surface of the first semiconductor layer meets the first thickness requirement; growing a third semiconductor layer from the outer surface of the second semiconductor layer; the polar surface of the longitudinal side surface of the second semiconductor layer provides vertical two-dimensional electron gas or vertical two-dimensional hole gas; a first V / III flow ratio of the group V element source and the group III metal element source in the first growth condition is different from a second V / III flow ratio in the second growth condition. According to the invention, the high-quality epitaxial body can be directly grown, the preparation process is reduced, and the device performance is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a vertical device epitaxial body and a preparation method thereof. Background Art

[0002] Group III nitrides such as GaN, InN, AlN, and ternary or quaternary compounds formed by them are the core of the third-generation semiconductor technology, and have advantages such as a large bandgap, high temperature and high pressure resistance, and high electron saturation velocity. High electron mobility transistors (HEMTs) prepared by using the spontaneous polarization and piezoelectric polarization effects of these materials have great application advantages in fields such as high-frequency power devices and wireless communication.

[0003] At present, the HEMT device structures mainly based on GaN are mainly divided into two categories: horizontal and vertical. Horizontal devices have many advantages, including low manufacturing cost, good CMOS process compatibility, and mature packaging technology, which have enabled them to be widely used in many fields. However, since the source, gate, and drain electrodes of the device are all located on the same plane, the electric field distribution between the high-voltage drain and the low-voltage source and gate is uneven, which easily generates a high electric field in a local area, resulting in device failure. In order to meet the requirements of high power and safety, it is usually necessary to increase the device area, thus limiting the miniaturization and integration of horizontal devices. In vertical devices, the low-voltage source and gate electrodes and the high-voltage drain electrode are located on the upper and lower sides of the device respectively, and the current of the device also flows vertically in the longitudinal direction. This design overcomes the breakdown voltage and current limitations of the horizontal structure and has better heat dissipation performance.

[0004] Referring to the Chinese patent application with the publication number CN110224019A and the invention name "A Semiconductor Device and a Manufacturing Method Thereof", it discloses a GaN-based semiconductor device with a vertical structure. The Chinese patent application with the publication number CN111816706A and the invention name "A Fin-shaped Semiconductor Device, a Manufacturing Method Thereof, and an Application Thereof" also discloses a GaN-based semiconductor device with a vertical structure. The semiconductor devices disclosed in these two patent applications are both vertical devices, and their preparation processes generally include the following steps:

[0005] First, trenches are prepared on the substrate; then, a nucleation layer, an epitaxial layer (such as a GaN channel layer and an AlGaN barrier layer), and a dielectric layer (such as an SiN x layer) and other semiconductor layers are grown layer by layer; then, the top material is removed by etching or polishing; finally, source, gate, and drain electrodes are fabricated to form devices such as HEMT or HHMT.

[0006] Among them, for normally-on devices, refer to Figure 1 andFigure 2 , Figure 1 is an ideal structural schematic diagram of the epitaxial cylinder of a normally-open device in the prior art, Figure 2 and Figure 1 is a longitudinal sectional schematic diagram of the epitaxial cylinder in

[0007] . For normally-off devices, see Figure 3 , Figure 3 which is a longitudinal sectional schematic diagram of the ideal structure of the epitaxial cylinder of a normally-off device in the prior art. The epitaxial cylinder has a cuboid structure and consists of different semiconductor layers from bottom to top. For example, the inner channel layer from bottom to top is successively an n-GaN layer, a UID (Unintentionally Doped) layer or a c-GaN layer, a p-GaN layer and an n-GaN layer. The outer layer of the channel layer is an AlGaN barrier layer, and the outer layer of the AlGaN barrier layer is a dielectric layer. The laterally perpendicular 2DEG is depleted in the p-GaN layer, so that a normally-off device can be fabricated.

[0008] Figures 1 to 3 The structural schematic diagrams in Figure 4 are all ideal structures. However, in the actual scenario of growing each semiconductor layer, in addition to growing in the vertical direction (the Z direction in the figure), each semiconductor layer will also grow a thin layer on the side of the lower semiconductor layer (the ±X direction in the figure). For normally-off devices, see Figure 4 which is a schematic diagram of the actual structural principle of the epitaxial cylinder of a normally-off device in the prior art during preparation. The c-GaN layer grown on the side will cause problems in the connectivity between the bottom electrode and the 2DEG; the p-GaN layer grown on the side will cause a decrease in the 2DEG concentration on the side and may even be depleted, which is not conducive to device conduction. For the top n-GaN layer, lateral growth is sometimes necessary because it needs to be used as a channel, but the thickness needs to be strictly controlled. If the thickness is too large, the p-GaN layer cannot deplete all the carriers in the n-GaN layer corresponding to its sidewall, resulting in the device being unable to achieve the normally-off function. For normally-open devices, there are also problems with the connectivity between the bottom electrode and the 2DEG, and if the growth rates in all directions are not properly controlled, the epitaxial layer cannot form a uniform and specific-sized columnar structure, which will also pose great challenges to subsequent processing technologies.

[0009] Since it is impossible to obtain an ideal columnar structure through growth, in the prior art, an ideal columnar structure is mainly obtained by etching away the semiconductor layer on the sidewalls of the epitaxial column. However, the sidewall etching process is difficult and it is not easy to control the etching accuracy. In addition, when etching the epitaxial column, lattice damage will be caused. For example, high-energy ions will cause lattice displacement, dislocation, and defects during bombardment. The destruction of the lattice structure will affect the electrical properties of the material. Moreover, etching will increase the surface roughness, and such a rough surface will also have a potential adverse impact on the electrical properties of the device (such as leakage current, interface state density, etc.). Summary of the Invention

[0010] In view of the technical problems existing in the prior art, the present invention proposes a vertical device epitaxial body and a preparation method thereof, which can directly grow a high-quality epitaxial body and improve the device performance.

[0011] To solve the above technical problems, according to one aspect of the present invention, the present invention provides a method for preparing a vertical device epitaxial body, including the following steps:

[0012] Under the first growth conditions, a first semiconductor layer is grown from a vertical interface, and the lattice of the vertical interface has hexagonal symmetry; the width of the first semiconductor layer is not less than half of the preset width of the epitaxial body;

[0013] Under the second growth conditions, a second semiconductor layer is grown from the outer surface of the first semiconductor layer; wherein, the thickness of the second semiconductor layer grown from the longitudinal side surface of the first semiconductor layer meets the first thickness requirement;

[0014] A third semiconductor layer is grown from the outer surface of the second semiconductor layer; wherein, the thickness of the third semiconductor layer grown from the longitudinal side surface of the second semiconductor layer meets the second thickness requirement;

[0015] Among the longitudinal side surfaces of the second semiconductor layer, there is a polar plane parallel to the vertical interface adjacent to the interface of the third semiconductor layer, and the polar plane provides a vertical two-dimensional electron gas or a vertical two-dimensional hole gas;

[0016] The first V / III flow ratio of the group V element source and the group III metal element source used for growing the first semiconductor layer in the first growth conditions is different from the second V / III flow ratio of the group V element source and the group III metal element source used for growing the second semiconductor layer in the second growth conditions.

[0017] Optionally, under the first growth conditions, the first semiconductor layer is grown in stages. According to the growth order, the flow rates of the group V element source and the group III metal element source in each growth stage are controlled such that the lateral growth rate in the current growth stage is greater than that in the next growth stage, and the vertical growth rate in the current growth stage is less than that in the next growth stage; or the lateral growth rate in the current growth stage is less than that in the next growth stage, and the vertical growth rate in the current growth stage is greater than that in the next growth stage.

[0018] Optionally, according to the growth order of the first semiconductor layer, the respective first V / III flow ratios of multiple growth stages increase or decrease in sequence.

[0019] Optionally, when the first semiconductor layer is grown in two stages under the first growth conditions, in the first growth stage, the first semiconductor layer is grown according to the first V / III flow ratio of the first aspect ratio. When the first semiconductor layer reaches the second preset width, the first V / III flow ratio is increased, and the first semiconductor layer is continuously grown according to the first V / III flow ratio of the second aspect ratio until the first semiconductor layer reaches the first preset width; wherein, the first aspect ratio is less than the second aspect ratio;

[0020] Or, in the first growth stage, the first semiconductor layer is grown according to the first V / III flow ratio of the second aspect ratio. When the first semiconductor layer reaches the first preset height, the first V / III flow ratio is decreased, and the first semiconductor layer is continuously grown according to the first V / III flow ratio of the first aspect ratio until the first semiconductor layer reaches the first preset width.

[0021] Optionally, the first V / III flow ratio is increased by reducing the flow rate of the group III metal element source in the second growth stage and / or increasing the flow rate of the group V element source in the second growth stage; the first V / III flow ratio is decreased by increasing the flow rate of the group III metal element source in the second growth stage and / or reducing the flow rate of the group V element source in the second growth stage.

[0022] Optionally, when the difference between the flow rate of the group III metal element source in the first growth stage and that in the second growth stage is less than the threshold, the flow rate of the group V element source in the second growth stage is 1 - 3 times that in the first growth stage.

[0023] Optionally, the second semiconductor layer includes multiple semiconductor sub - layers. When the first semiconductor sub - layer of the second semiconductor layer is grown epitaxially in the vertical direction under the second growth conditions, the first semiconductor sub - layer substantially does not grow on the side of the underlying semiconductor layer.

[0024] Optionally, a second semiconductor sub-layer grown by longitudinal epitaxy is further included under the first semiconductor sub-layer, and the thickness of the second semiconductor sub-layer grown on the side of the lower semiconductor layer is not greater than a thickness threshold.

[0025] Optionally, a third semiconductor sub-layer grown by longitudinal epitaxy is further included above the first semiconductor sub-layer, and the third semiconductor sub-layer does not substantially grow on the side of the lower semiconductor layer.

[0026] Optionally, the longitudinal sides of the plurality of semiconductor sub-layers of the second semiconductor layer respectively include polar planes parallel to the vertical interface adjacent to the interface of the third semiconductor layer, and the polar planes provide a vertical two-dimensional electron gas or a vertical two-dimensional hole gas.

[0027] Optionally, the longitudinal sides of the third semiconductor sub-layer and the second semiconductor sub-layer respectively include polar planes parallel to the vertical interface adjacent to the interface of the third semiconductor layer, and the polar planes provide a vertical two-dimensional electron gas or a vertical two-dimensional hole gas; the region adjacent to the interface of the third semiconductor layer in the longitudinal side of the first semiconductor sub-layer forms a depletion region for the two-dimensional electron gas or the two-dimensional hole gas.

[0028] Optionally, a third semiconductor sub-layer grown by longitudinal epitaxy is further included above the first semiconductor sub-layer, and the thickness of the third semiconductor sub-layer on the side of the lower semiconductor layer is not greater than a thickness threshold; the region adjacent to the interface of the third semiconductor layer in the side of the first semiconductor sub-layer forms a depletion region for the two-dimensional electron gas or the two-dimensional hole gas; the vertical two-dimensional electron gas or the vertical two-dimensional hole gas provided in the longitudinal polar plane of the third semiconductor sub-layer is interrupted in the region corresponding to the depletion region.

[0029] Optionally, the method for preparing the vertical device epitaxial structure further includes: under a third growth condition, growing one or more fourth semiconductor layers by epitaxy on the top of the first semiconductor layer, and the one or more fourth semiconductor layers do not substantially grow on the side of the lower semiconductor layer. Correspondingly, under a second growth condition, growing a second semiconductor layer from the outer surface of the epitaxial body composed of the first semiconductor layer and the fourth semiconductor layer.

[0030] Optionally, when growing the plurality of semiconductor sub-layers of the second semiconductor layer, the second V / III flow ratio of the group V element source and the group III metal element source for growing each semiconductor sub-layer shows an overall upward trend.

[0031] Optionally, the second V / III flow ratio of the group V element source and the group III metal element source for growing the first semiconductor sub-layer is the largest.

[0032] Optionally, a second V / III flow ratio of a group V element source and a group III metal element source for growing the first semiconductor sublayer is 2-6 times that of the V / III flow ratio for growing the underlying semiconductor sublayer.

[0033] Optionally, the growth conditions further include temperature and / or gas pressure. When growing a target semiconductor layer at a preset V / III flow ratio, adjust the temperature and / or gas pressure to assist in adjusting the thickness of the target semiconductor layer growing on the longitudinal side of the underlying semiconductor layer; wherein, the preset V / III flow ratio is different from the V / III flow ratio for growing the underlying semiconductor layer; when the target semiconductor layer is the second semiconductor layer, the corresponding underlying semiconductor layer is the first semiconductor layer or the fourth semiconductor layer, and when the underlying semiconductor layer is the fourth semiconductor layer, the corresponding underlying semiconductor layer is the first semiconductor layer or another layer of the fourth semiconductor layer; the growth conditions are the first growth conditions or the second growth conditions, and the preset V / III flow ratio is the first V / III flow ratio or the second V / III flow ratio.

[0034] Optionally, when the first semiconductor layer and / or the second semiconductor layer is a doped semiconductor layer, a doping source gas is introduced during the corresponding growth process.

[0035] Optionally, during the growth process of the target semiconductor layer, based on the relationship that the width of the growth space where the vertical interface is located is negatively correlated with the aspect ratio of the semiconductor layer, determine a matching aspect ratio based on the width of the current growth space, and determine the V / III flow ratio for growing the target semiconductor layer according to the aspect ratio. When the target semiconductor layer is the first semiconductor layer, the V / III flow ratio is the first V / III flow ratio, and when the target semiconductor layer is the second semiconductor layer, the V / III flow ratio is the second V / III flow ratio.

[0036] Optionally, during the growth process of the target semiconductor layer, based on the relationship that the width of the growth space where the vertical interface is located is positively correlated with the growth thickness of the upper semiconductor layer on the longitudinal side of the lower semiconductor layer, determine the V / III flow ratio for growing the target semiconductor layer according to the width of the current growth space and the required side growth thickness. The target semiconductor layer is the second semiconductor layer or a semiconductor sublayer.

[0037] Optionally, the method for preparing the vertical device epitaxial system further includes: the step of providing a vertical interface with a hexagonal symmetry lattice.

[0038] Optionally, the step of providing a vertical interface with a hexagonal symmetry lattice includes:

[0039] Provide a substrate and form the vertical interface with a hexagonal symmetry lattice on the substrate.

[0040] Optionally, the step of forming the vertical interface on the substrate includes:

[0041] Forming a first region and a second region with different heights on the substrate, and a vertical connection surface between the lower second region and the higher first region constitutes the vertical interface.

[0042] Optionally, the method for preparing the vertical device epitaxial body further includes: growing a nucleation layer on the vertical connection surface between the lower second region and the higher first region, and a longitudinal side surface of the nucleation layer constitutes the vertical interface; or

[0043] Growing a nucleation layer on the vertical connection surface between the lower second region and the higher first region;

[0044] Growing a buffer layer from the nucleation layer, and a longitudinal side surface of the buffer layer constitutes the vertical interface.

[0045] Optionally, when the third semiconductor layer serves as a barrier layer, it further includes: growing a dielectric layer with a preset thickness from an outer surface of the barrier layer.

[0046] According to another aspect of the present invention, the present invention also provides a vertical device epitaxial body prepared based on the foregoing method, which includes:

[0047] A first semiconductor layer, which is grown from a vertical interface having a hexagonal symmetry lattice under a first growth condition, and a width of the first semiconductor layer is not less than half of a preset epitaxial body width;

[0048] A second semiconductor layer, which is grown from an outer surface of the first semiconductor layer under a second growth condition, wherein a thickness of the second semiconductor layer grown from a longitudinal side surface of the first semiconductor layer meets a first thickness requirement; and

[0049] A third semiconductor layer, which is grown from an outer surface of the second semiconductor layer; wherein a thickness of the third semiconductor layer grown from a longitudinal side surface of the second semiconductor layer meets a second thickness requirement;

[0050] A longitudinal side surface of the second semiconductor layer includes a polar plane parallel to the vertical interface adjacent to an interface with the third semiconductor layer, and the polar plane provides a vertical two-dimensional electron gas or a vertical two-dimensional hole gas; a first V / III flow ratio of a group V element source and a group III metal element source for growing the first semiconductor layer in the first growth condition is different from a second V / III flow ratio of a group V element source and a group III metal element source for growing the second semiconductor layer in the second growth condition.

[0051] Optionally, the second semiconductor layer includes a plurality of semiconductor sub-layers, and a first semiconductor sub-layer among them does not substantially grow on a side surface of a lower semiconductor layer.

[0052] Optionally, a second semiconductor sub-layer is further included under the first semiconductor sub-layer, and the thickness of the second semiconductor sub-layer grown on the side of the lower semiconductor layer is not greater than a thickness threshold.

[0053] Optionally, a third semiconductor sub-layer grown by longitudinal epitaxy is further included above the first semiconductor sub-layer, and the third semiconductor sub-layer substantially does not grow on the side of the lower semiconductor layer.

[0054] Optionally, the longitudinal sides of multiple semiconductor sub-layers of the second semiconductor layer respectively include polar planes parallel to the vertical interface adjacent to the interface of the third semiconductor layer, and the polar planes provide a vertical two-dimensional electron gas or a vertical two-dimensional hole gas; or

[0055] The longitudinal side of the first semiconductor sub-layer adjacent to the interface of the third semiconductor layer forms a depletion region for the two-dimensional electron gas or the two-dimensional hole gas.

[0056] Optionally, a third semiconductor sub-layer grown by longitudinal epitaxy is further included above the first semiconductor sub-layer, and the thickness of the third semiconductor sub-layer on the side of the lower semiconductor layer is not greater than a thickness threshold; the region adjacent to the interface of the third semiconductor layer in the side of the first semiconductor sub-layer forms a depletion region for the two-dimensional electron gas or the two-dimensional hole gas; the vertical two-dimensional electron gas or the vertical two-dimensional hole gas provided in the longitudinal polar plane of the third semiconductor sub-layer is interrupted in the region corresponding to the depletion region.

[0057] Optionally, one or more fourth semiconductor layers are further included between the first semiconductor layer and the second semiconductor layer, and the one or more fourth semiconductor layers substantially do not grow on the side of the lower semiconductor layer.

[0058] Optionally, the vertical device epitaxial body further includes a substrate, and the substrate provides the vertical interface with a hexagonal symmetry lattice.

[0059] Optionally, the substrate includes a first region and a second region with different heights, and the vertical connection surface between the lower second region and the higher first region constitutes the vertical interface; or

[0060] A nucleation layer grown on the vertical connection surface between the lower second region and the higher first region is further included, and the longitudinal side of the nucleation layer constitutes the vertical interface; or

[0061] A buffer layer grown from the nucleation layer is further included, and the longitudinal side of the buffer layer constitutes the vertical interface.

[0062] Optionally, the vertical device epitaxial body further includes a dielectric layer with a preset thickness grown from the longitudinal outer surface of the third semiconductor layer.

[0063] By controlling the growth conditions of different semiconductor layers, the present invention can inhibit or regulate the thickness of the semiconductor layer grown on the side of the underlying semiconductor layer, thereby precisely controlling the growth morphology of the vertical epitaxial column. The obtained column has high quality, reducing the etching process and the preparation process during device fabrication, thus improving the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Next, the preferred embodiments of the present invention will be further described in detail with reference to the accompanying drawings, where:

[0065] Figure 1 is a schematic diagram of the ideal structure of the epitaxial column of a normally open device in the prior art;

[0066] Figure 2 is Figure 1 a schematic longitudinal cross-sectional view of the epitaxial column in

[0067] Figure 3 is a schematic longitudinal cross-sectional view of the ideal structure of the epitaxial column of a normally off device in the prior art;

[0068] Figure 4 is a schematic diagram of the actual structural principle of the epitaxial column of a normally off device in the prior art during preparation;

[0069] Figure 5 is a flowchart of a method for preparing a vertical device epitaxial body according to an embodiment of the present invention;

[0070] Figure 6 is a schematic diagram of a plurality of trenches prepared on a substrate according to an embodiment of the present invention;

[0071] Figure 7 is a schematic SEM image of a semiconductor layer when the trench width is about 3.62 μm according to an embodiment of the present invention;

[0072] Figure 8 is a schematic SEM image of a semiconductor layer when the trench width is about 6.74 μm according to another embodiment of the present invention;

[0073] Figure 9 is a schematic SEM image of a semiconductor layer when the trench width is about 19.8 μm according to an embodiment of the present invention;

[0074] Figure 10 is Figure 9 an enlarged schematic diagram of the square box in

[0075] Figure 11 is a schematic diagram showing the relationship between the trench parameter value and the thickness of the upper semiconductor layer grown on the side of the lower semiconductor layer according to an embodiment of the present invention;

[0076] Figure 12 It is a flowchart of the preparation method of the first semiconductor layer in the epitaxial body according to Embodiment 1 of the present invention;

[0077] Figure 13 It is a schematic diagram of the atomic distribution principle after the decomposition of trimethylgallium and ammonia gas on the substrate;

[0078] Figure 14 It is a schematic diagram of the SEM image of the GaN layer grown under the conditions shown in Table 2 of Embodiment 1;

[0079] Figure 15 It is a schematic diagram of the SEM image of the GaN layer grown by the traditional growth method;

[0080] Figure 16 It is a schematic diagram of the partial epitaxial body structure of the n-GaN layer and the c-GaN layer grown from the nucleation layer on the sidewall of the self-substrate trench according to Embodiment 2 of the present invention;

[0081] Figure 17 It is a schematic diagram of the SEM image of the partial epitaxial body of the n-GaN layer and the c-GaN layer grown from the nucleation layer on the sidewall of the self-substrate trench according to Embodiment 2 of the present invention;

[0082] Figure 18 It is a schematic diagram of the partial epitaxial body structure of the n-GaN layer, the c-GaN layer and the p-GaN layer grown from the nucleation layer on the sidewall of the self-substrate trench according to Embodiment 2 of the present invention;

[0083] Figure 19 It is a schematic diagram of the partial epitaxial body structure of the n-GaN layer, the c-GaN layer, the p-GaN layer and the n-GaN layer grown from the nucleation layer on the sidewall of the self-substrate trench according to Embodiment 2 of the present invention;

[0084] Figure 20 It is a schematic diagram of the SEM image of the epitaxial body of the n-GaN layer, the c-GaN layer, the p-GaN layer and the n-GaN layer grown from the nucleation layer on the sidewall of the self-substrate trench according to Embodiment 2 of the present invention;

[0085] Figure 21 It is a schematic diagram of the epitaxial body structure after etching the top material according to Embodiment 2 of the present invention;

[0086] Figure 22 It is a flowchart of the preparation method of the vertical device epitaxial body according to Embodiment 3 of the present invention;

[0087] Figure 23 It is a schematic diagram of the partial epitaxial body structure according to Embodiment 3 of the present invention;

[0088] Figure 24Schematic diagram of the epitaxial structure after etching the top material according to Embodiment 3 of the present invention; and

[0089] Figure 25 Schematic diagram of the epitaxial structure after etching the top material according to Embodiment 4 of the present invention. Detailed implementation manners

[0090] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0091] In the following detailed description, reference may be made to the accompanying drawings that form a part hereof and that show, by way of illustration, specific embodiments in which the application may be practiced. In the drawings, like reference numerals generally refer to like components in different figures. The specific embodiments of the present application have been described in sufficient detail below to enable those of ordinary skill in the art with relevant knowledge and technology to implement the technical solutions of the present application. It should be understood that other embodiments may be utilized or structural, logical, or electrical changes may be made to the embodiments of the present application. Additionally, the "first", "second", etc. in this embodiment do not denote an order, but are only used to distinguish different technical features with the same name.

[0092] See Figure 4 and Figure 2 or Figure 3 , the longitudinal side of the vertical device epitaxial body includes two polar planes, such as the (0001) plane and (000-1) plane of GaN shown in the figure. In the following description, the vertical side of the epitaxial body far from the substrate vertical interface where the epitaxial body is grown is referred to as the first polar plane, such as Figure 4 the (0001) plane in Figure 4 ; the vertical side of the epitaxial body close to the substrate vertical interface is referred to as the second polar plane, such as

[0093] the (000-1) plane in

[0093] . According to the specific structure of the device, only the first polar plane may be utilized during device fabrication, or both the first polar plane and the second polar plane may be utilized. Figure 5 Figure 5 ,

[0094] Flowchart of a method for preparing a vertical device epitaxial body according to an embodiment of the present invention. In this embodiment, the method includes:

[0094] Step S1, grow a first semiconductor layer from a vertical interface under a first growth condition, where the lattice of the vertical interface has hexagonal symmetry; the width of the first semiconductor layer is not less than half of the preset epitaxial body width. Here, the width of the epitaxial body varies according to different actual growth conditions and process capabilities. In one embodiment, the minimum preset width of the epitaxial body is 1 μm, so the width of the first semiconductor layer is not less than 500 nm.

[0095] Step S2, grow a second semiconductor layer from the outer surface of the first semiconductor layer under a second growth condition; among them, the thickness of the second semiconductor layer grown from the longitudinal side surface of the first semiconductor layer meets the first thickness requirement.

[0096] Step S3, grow a third semiconductor layer from the outer surface of the second semiconductor layer; among them, the thickness of the third semiconductor layer grown from the longitudinal side surface of the second semiconductor layer meets the second thickness requirement.

[0097] The vertical device epitaxial body obtained through the above steps includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. The first semiconductor layer is grown from a vertical interface with a hexagonal symmetry lattice, and the width of the first semiconductor layer is not less than half of the epitaxial body width; the thickness of the second semiconductor layer grown from the longitudinal side surface of the first semiconductor layer meets the first thickness requirement; the thickness of the third semiconductor layer grown from the longitudinal side surface of the second semiconductor layer meets the second thickness requirement; among the longitudinal side surfaces of the second semiconductor layer, there is a polar plane parallel to the vertical interface adjacent to the interface of the third semiconductor layer, and the polar plane provides a vertical two-dimensional electron gas or a vertical two-dimensional hole gas.

[0098] Among them, the vertical interface in step S11 can be the side wall of the substrate, or the longitudinal side surface of the nucleation layer or the longitudinal side surface of the buffer layer grown from the nucleation layer. When using the side wall of the substrate as the vertical interface in step S11, a first region and a second region with different heights are formed on the substrate, and the vertical connection surface between the lower second region and the higher first region constitutes the vertical interface. The substrate in the present invention can be a silicon (Si) substrate, a sapphire (Al 2 O 3 ) substrate, a silicon carbide (SiC) substrate, or a gallium nitride (GaN) intrinsic substrate. The lattice of the vertical surface of the substrate has hexagonal symmetry so that nitride semiconductor crystals can be epitaxially grown subsequently. For example, the exposed vertical interface of the substrate can be the Si(111) plane, Al 2 O 3The (0001) plane of [substrate material], the (0001) plane of 4H-SiC, the (0001) plane of GaN, etc. In a specific embodiment, the first region and the second region are formed by etching grooves arranged at intervals downward on the upper surface of the substrate. Among them, the top of the groove is the first region, the bottom of the groove is the second region, the side wall of the groove is the vertical interface of the substrate, and the internal space of the groove constitutes a growth space. The distance between the two side walls of the groove is called the groove width, which serves as the width of the growth space. Refer to Figure 6 , Figure 6 is a schematic diagram of preparing multiple grooves on a substrate according to an embodiment of the present invention. In Figure 6 , the groove width w1 is the same as the groove pitch s. The multiple grooves on the substrate are arranged in parallel, which is convenient for operation and improves the utilization rate of the substrate. When only using the side surface of the epitaxial body on the inner side of the groove as the functional surface for making electrodes during device fabrication, the groove width w1 is not greater than 20 μm, and the groove pitch s is not limited. However, in order to improve the utilization rate of the substrate, the groove pitch s can be minimized as much as possible, and the minimum groove pitch s should be such that it does not affect the growth of the first epitaxial body and the barrier layer. When simultaneously using the side surface of the epitaxial body on the inner side of the groove and the opposite side surface as the functional surface to fabricate a device, the corresponding groove parameters include the groove width w1 and the groove pitch s, and the requirement for the groove pitch s is the same as that for the groove width w1, that is, not greater than 20 μm. In an embodiment, the groove pitch s is less than the groove width w1. Preferably, the groove pitch s is less than or equal to the distance between the two epitaxial bodies grown on the inner side wall of the groove after the epitaxial growth is completed. From the perspective of device density, when the groove width and the groove pitch (that is, one period) are smaller, the number of epitaxial columns per unit area is more, that is, the number of device channels is more, which is more conducive to improving the current density of the device.

[0099] In the present invention, for the sake of distinction, the ratio of the flow rate of the group V element source to the flow rate of the group III metal element source applied for growing the first semiconductor layer is called the first V / III flow ratio, and the ratio of the flow rate of the group V element source to the flow rate of the group III metal element source applied for growing the second semiconductor layer is called the second V / III flow ratio. Additionally, it should be noted that the group V element sources applied for the first semiconductor layer and the second semiconductor layer can be the same or different. The present invention does not exclude the case where the group V element sources are different. Additionally, the group III metal element source applied for the third semiconductor layer can be multiple. For the sake of simplicity in description, they are collectively referred to as the second group III metal element source here. During growth, usually through a carrier gas, such as hydrogen (H 2 ) or nitrogen (N 2 ), the group III metal element and the group V element are introduced into the growth reaction chamber respectively. In the following description, for the sake of simplicity, the carrier gas is not emphasized anymore, and the carrier gas carrying the group III metal element is directly called the group III metal element source gas, and the carrier gas carrying the group V element is called the group V element source gas.

[0100] Each semiconductor layer in the present invention is grown in stages by a selected group-V element source and a group-III metal element source under certain growth conditions. Among them, the first semiconductor layer serves as the substrate of the epitaxial body, and its width needs to be not less than half of the preset epitaxial body width. The first semiconductor layer and the second semiconductor layer can jointly serve as the channel layer providing vertical two-dimensional electron gas or vertical two-dimensional hole gas, or the second semiconductor layer alone serves as the channel layer. As required, the thickness of the second semiconductor layer grown from the longitudinal side of the first semiconductor layer meets the first thickness requirement. For example, when the first semiconductor layer and the second semiconductor layer jointly serve as the channel layer, the thickness of the second semiconductor layer on the side of the first semiconductor layer should be close to 0, that is to say, the second semiconductor layer does not substantially grow on the side of the underlying first semiconductor layer. When the second semiconductor layer alone serves as the channel layer, the thickness of the second semiconductor layer on the side of the underlying first semiconductor layer has an appropriate thickness to generate carriers, that is, vertical two-dimensional electron gas or vertical two-dimensional hole gas. In addition, when preparing the epitaxial body of a normally-off device, the thickness of the second semiconductor layer grown from the longitudinal side of the first semiconductor layer should enable the depletion layer (such as the p-GaN layer in HEMT or the n-GaN layer in HHMT) to deplete all the carriers corresponding to its sidewalls.

[0101] The second thickness requirement is to satisfy that the third semiconductor layer grown from the longitudinal side of the second semiconductor layer can generate sufficient and effective carriers with the longitudinal side of the second semiconductor layer.

[0102] The thickness of the second semiconductor layer grown from the longitudinal side of the first semiconductor layer and the thickness of the third semiconductor layer grown from the longitudinal side of the second semiconductor layer can be determined according to their respective semiconductor materials. Taking the second semiconductor layer as GaN and the third semiconductor layer as AlGaN as an example, the thickness of the GaN layer cannot be too thin. If the GaN layer is too thin, the quality of 2DEG will be reduced. The GaN layer needs to be thick enough, for example, greater than 1 μm, to avoid the direct transfer of stress to the substrate (such as the first semiconductor layer or the substrate), and at the same time ensure that electrons can be freely distributed without being scattered by the substrate.

[0103] The thickness of the AlGaN layer cannot be less than the critical thickness value, such as 3 - 5 nm. Only when this critical thickness value is exceeded can 2DEG be generated at the interface with the GaN layer. However, the thickness of the AlGaN layer cannot exceed the critical strain thickness value, which is about 30 - 40 nm for example. Exceeding the critical strain thickness will cause stress release, triggering crystal defects (such as dislocations or cracks), thereby reducing the density and mobility of 2DEG. In addition, the aforementioned critical thickness value and critical strain thickness value are also affected by the Al content in the AlGaN layer. The higher the Al content, the stronger the polarization effect and the lower the critical thickness.

[0104] The second semiconductor layer in the present invention can be a single layer or multiple layers. For the sake of distinction, the multiple semiconductor layers constituting the second semiconductor layer are respectively called semiconductor sub-layers.

[0105] The first V / III flow ratio of the group V element source and the group III metal element source used to grow the first semiconductor layer in the first growth condition of the present invention is different from the second V / III flow ratio of the group V element source and the group III metal element source used to grow the second semiconductor layer in the second growth condition. By adjusting the V / III flow ratio used to grow the target semiconductor layer in the current growth stage, the target semiconductor layer can meet the corresponding thickness requirements. The target semiconductor layer described here is, for example, a single-layer second semiconductor layer or a certain sub-semiconductor layer in the multiple-layer second semiconductor layer.

[0106] Among them, during the growth process of the semiconductor layer, the longitudinal growth rate and the lateral growth rate in the growth process can be adjusted by controlling the V / III flow ratio. From the growth results, when the V / III flow ratio is fixed, the obtained semiconductor layer has a corresponding aspect ratio. Therefore, during the growth process of the semiconductor layer, the height and width of the semiconductor layer can be controlled by adjusting the V / III flow ratio, so as to achieve the purpose of controlling the thickness of the growth on the side of the underlying semiconductor layer.

[0107] On the other hand, the width of the growth space where the vertical interface is located is negatively correlated with the aspect ratio of the semiconductor layer, that is, as the width of the growth space increases, the aspect ratio of the semiconductor layer decreases. Therefore, during the growth process of the target semiconductor layer, a matching aspect ratio is determined according to the width of the current growth space and the required growth thickness, and the V / III flow ratio for growing the target semiconductor layer is determined according to the aspect ratio. The target semiconductor layer described here is, for example, a single-layer second semiconductor layer or a certain sub-semiconductor layer in the multiple-layer second semiconductor layer.

[0108] Referring to the following embodiments, for the sake of simplicity in explaining the relationship between the aspect ratio of a semiconductor layer and the width of the growth space, the growth space in this embodiment takes the trench on a silicon substrate as an example. The data of growing GaN layers in trenches with different widths under the same growth conditions are shown in Table 1 below:

[0109] Table 1

[0110] Slot width (μm) Channel layer height (μm) Channel layer width (μm) Height-width ratio 3 2.65 0.94 2.81 6 μm 2.95 1.52 1.94 18 μm 3.38 1.96 1.72

[0111] The values of the trench widths in the table are approximate numbers, and the corresponding growth conditions are: the temperature range is 1070 - 1080 °C, the pressure range is 50 - 100 Torr, and the group V element hydride (such as ammonia gas NH 3) has a flow rate range of 2000 - 3000 mmol / min, the flow rate range of group III metal element source (such as trimethylgallium TMGa) is 300 - 500 μmol / min, and the V / III ratio range is 5000 - 7500.

[0112] In a specific embodiment, the temperature is 1075 °C, the gas pressure is 70 Torr, the flow rate of group V element hydride (such as ammonia gas NH 3 ) is 2634 mmol / min, the flow rate of group III metal element source (such as trimethylgallium TMGa) is 426 μmol / min, and the V / III ratio is 6183.

[0113] See Figures 7 to 10 , Figure 7 is a schematic SEM picture of the semiconductor layer when the groove width is about 3.62 μm, Figure 8 is a schematic SEM picture of the semiconductor layer when the groove width is about 6.74 μm, Figure 9 is a schematic SEM picture of the semiconductor layer when the groove width is about 19.8 μm, Figure 10 is Figure 9 an enlarged schematic diagram of the square box in. It can be seen from the measured dimensions marked in the figure and the approximate data in Table 1 that both the height and width of the semiconductor layer increase with the increase of the groove width, but the height-width ratio decreases with the increase of the groove width, that is, the groove width has a positive correlation with both the growth height and width of the semiconductor layer, and a negative correlation with the height-width ratio. In addition, it can be seen that Figure 7 and Figure 8 the morphology of the semiconductor layer obtained with a small groove width shown is better than that of the semiconductor layer obtained when the groove width is large as shown in Figure 9 .

[0114] In addition, the width of the growth space where the vertical interface is located has a positive correlation with the growth thickness of the upper semiconductor layer on the longitudinal side of the lower semiconductor layer, that is, as the width of the growth space increases, the growth thickness of the upper semiconductor layer on the longitudinal side of the lower semiconductor layer also increases. Therefore, during the growth process of the target semiconductor layer, based on the positive correlation between the width of the growth space where the vertical interface is located and the growth thickness of the upper semiconductor layer on the longitudinal side of the lower semiconductor layer, the V / III flow ratio for growing the target semiconductor layer is determined according to the width of the current growth space and the requirements for the side growth thickness. The target semiconductor layer mentioned here is, for example, a single-layer second semiconductor layer, or a certain sub-semiconductor layer in a multi-layer second semiconductor layer.

[0115] See Figure 11 , Figure 11It is a schematic diagram showing the relationship between the trench width and the growth thickness of the upper semiconductor layer relative to the side of the lower semiconductor layer according to an embodiment of the present invention. In this embodiment, the substrate is silicon, the upper semiconductor layer is GaN, and the lower semiconductor layer is undoped GaN. Under the same conditions such as temperature, gas pressure, V / III flow ratio, etc., as the trench width increases, the thickness of the upper GaN grown on the sidewalls of the lower undoped GaN is greater.

[0116] In addition, for the flow rate of the group V element source, the flow rate of the group III metal element source, and the flow rate ratio (abbreviated as V / III ratio) applied when growing each semiconductor layer, there is also a positive correlation with the V / III ratio for obtaining the same semiconductor layer as the width of the growth space (such as the trench on the substrate) increases. When the width of the growth space is determined, according to the growth order of the semiconductor layers, the V / III flow rate ratio for growing each semiconductor layer shows an upward trend.

[0117] The present invention will be described in detail below through specific embodiments.

[0118] Embodiment 1

[0119] Figure 12 It is a flowchart of the preparation method of the first semiconductor layer in the epitaxial body according to Embodiment 1 of the present invention. The first semiconductor layer can be either the first semiconductor layer in the normally-on vertical device epitaxial body or the first semiconductor layer in the normally-off vertical device epitaxial body. In this embodiment, the n-GaN layer is used as the first semiconductor layer.

[0120] Step S21, provide a silicon substrate and prepare a plurality of trenches on the substrate. Among them, the trench width and the trench pitch are 3 μm respectively. The trench sidewalls serve as the vertical interface of the substrate, and its lattice has hexagonal symmetry.

[0121] Step S22, prepare a mask at the bottom of the trench and on the top between adjacent trenches, exposing the trench sidewalls serving as the vertical interface of the substrate. The mask in this embodiment is, for example, silicon oxide SiO 2 .

[0122] Step S23, grow a nucleation layer on the trench sidewalls. Such as aluminum nitride AlN, aluminum gallium nitride AlGaN or gallium nitride GaN, with a thickness range of 50 - 150 nm.

[0123] Step S24, grow the GaN layer in two periods. In this embodiment, ammonia NH 3 is used as the group V element source, and trimethylgallium TMGa is used as the group III metal element source. Specifically, in the first growth stage, ammonia NH 3The flow rate is 500 - 700 mmol / min, the flow rate of trimethylgallium (TMGa) is 700 - 900 μmol / min, and the V / III ratio is 700 - 1000. For other growth conditions, such as the temperature is 1070 - 1080 °C and the gas pressure is 50 - 100 Torr. Since the GaN layer in this embodiment needs to be doped n-type GaN, a doping gas is also introduced simultaneously, such as silane (SiH 4 (also known as silane or monosilane), and the flow rate of the doping gas is, for example, 70 - 90 μmol / min. Among them, the ratio of SiH 4 to the carrier gas (hydrogen gas H 2 ) is 2:200 ppm. Then in the second growth stage, the flow rate range of ammonia (NH 3 ) is changed to 1500 - 2000 mmol / min, the flow rate range of trimethylgallium (TMGa) remains 700 - 900 μmol / min, and the V / III ratio range is 2000 - 3000. Other conditions remain unchanged or the differences are negligible. Based on the growth method in time segments, a uniform columnar structure semiconductor layer can be grown on the sidewalls of the trenches.

[0124] When transporting trimethylgallium (TMGa) and ammonia (NH 3 ) to a high-temperature substrate, both decompose and undergo a chemical reaction, and the reaction formula is as follows:

[0125] Ga(CH 3 ) 3 +NH 3 →GaN + 3CH 4

[0126] As the source of group V elements, the decomposition of ammonia requires a relatively high temperature (usually above 700 °C). Therefore, in the growth environment, ammonia decomposes into nitrogen atoms (N) and hydrogen gas (H 2 ) molecules in the high-temperature region near the substrate. The hydrogen gas molecules are lighter and will diffuse upward, while the nitrogen atoms are heavier and accumulate on the substrate surface.

[0127] Trimethylgallium (Ga(CH 3 ) 3 ) as the source of group III metal elements can decompose into gallium atoms (Ga) and methyl groups (CH 3 ) at a relatively low temperature. Therefore, in the same growth environment as ammonia, trimethylgallium starts to decompose above the ammonia decomposition region. The heavier gallium atoms diffuse downward, and the lighter methyl groups (CH 3 ) diffuse upward. During the downward diffusion process, the gallium atoms combine with nitrogen atoms to form gallium nitride (GaN) on the sidewalls of the trenches. The methyl groups (CH 3 ) react with hydrogen gas (H 2 ) to form methane (CH4 ), methane, and hydrogen (H 2 ), etc., are light gases. Because they are light and highly volatile, they are mainly distributed in the upper space of the growth environment (such as a reactor). As Figure 13 shown, Figure 13 is a schematic diagram of the atomic distribution principle after the decomposition of trimethylgallium and ammonia on the substrate. Since the bottom and top of the substrate trench are covered by a mask and a nucleation layer grows on the sidewall, most of the nitrogen atoms and gallium atoms are distributed near the sidewall of the nucleation layer inside the substrate trench, thereby generating GaN on the side of the nucleation layer.

[0128] GaN grows longitudinally and laterally on the sidewall of the nucleation layer, thereby obtaining a column with a cross-section similar to a rectangle. As the column grows, the lateral thickness becomes larger and the space between the GaN columns on the two sidewalls becomes smaller, resulting in a decrease in the amount of reaction gases TMGa and NH 3 entering the region between the two columns, while the amount of reaction gases at the top of the column relatively increases. Then, the nitrogen atoms and gallium atoms inside the trench are reduced compared to those at the top of the column, and the decomposed nitrogen atoms and gallium atoms at the top of the column increase, thereby causing the lateral growth rate of the column to decrease and the longitudinal growth rate to increase. As the height of the column increases, the lateral growth rate of the epitaxial layer further decreases and the longitudinal growth rate further increases.

[0129] When the V / III flow ratio is low, it is beneficial to the diffusion of gallium atoms Ga on the material surface, and the lateral growth rate of the semiconductor layer (GaN layer in this embodiment) is relatively high. Therefore, in this embodiment, in the first growth stage, a lower V / III flow ratio can effectively make the lateral thickness of the epitaxial layer column on the sidewall reach a preset thickness, and then increase the V / III flow ratio. Since the concentration of nitrogen atoms increases, the surface diffusion length of gallium atoms Ga becomes shorter, inhibiting the lateral growth of the GaN layer and promoting the longitudinal growth of GaN at the same time.

[0130] In the present invention, in order to inhibit unnecessary lateral growth, the width w1 or pitch s of the trench on the substrate is reduced, thereby inhibiting the reaction gases from entering the inside of the trench and reducing the growth on the sidewall; moreover, by reducing the trench width and pitch, the area efficiency of the device can be further improved, which is in line with the trend of device miniaturization.

[0131] In this embodiment, the flow rate of the group-III metal element source in the second growth stage is at the same level as that in the first growth stage. By increasing the flow rate of the group-V element, the surface diffusion length of Ga atoms is further shortened, thereby realizing the growth of a semiconductor layer with a specific size and high quality. Since increasing the flow rate of the group-V element source will increase the process cost and affect the growth rate when nitrogen atoms are in excess, the flow rate of the group-V element source in the second control period is not higher than 5000 mmol / min, and the highest is 2000 mmol / min in this embodiment, so the cost is relatively low.

[0132] In a specific embodiment, a GaN layer with a width of 740 nm and a height of 1.43 μm is obtained under the growth conditions shown in Table 2.

[0133] Table 2

[0134]

[0135]

[0136] See Figure 14 , Figure 14 FIG. is a schematic SEM picture of the GaN layer grown under the conditions shown in Table 2 of Example 1.

[0137] In this embodiment, in the first growth stage, ammonia gas NH 3 and trimethylgallium TMGa are transported to the substrate at a relatively low V / III ratio shown in Table 2. Due to the low V / III ratio, the lateral growth rate is fast and the preset width can be quickly reached. In the second growth stage, the flow rate of ammonia gas NH 3 is increased to increase the V / III ratio. Compared with the first growth stage, the longitudinal growth rate becomes faster and faster, and the lateral growth rate becomes slower and slower until the preset height and width are reached. The epitaxial structure obtained in Example 1 of the present invention is the same as the original structure shown in the first figure in Figure 4 . Its SEM picture is as shown in Figure 14 . As can be seen from the figure, the n-type GaN layer is an ideal columnar structure, with uniform columns and a smooth surface.

[0138] As a comparative example, see Table 3. Table 3 shows the growth condition data of the traditional non-segmented flow rate ratio. When using this growth condition, the column height obtained in the same time is 1.5 μm and the width is 500 nm.

[0139] Table 3

[0140]

[0141] Comparing with this embodiment, when a fixed V / III ratio is adopted, the longitudinal and lateral growth rates mainly depend on the chemical reactions during the growth process, and the semiconductor width that can be obtained under the basic process conditions is about 500 nm. When the two time periods described in the present invention are adopted and the V / III ratios of the two growth stages differ by 1 to 3 integer multiples, under the same conditions, the semiconductor width can be increased to 700 nm to 1 μm.

[0142] When the longitudinal and lateral growth rates of the semiconductor layer are not controlled, defects are likely to occur Figure 15 as shown. Figure 15 It is a schematic SEM picture of a GaN layer grown by a traditional growth method. During the growth process, when the longitudinal growth rate and the lateral growth rate are not effectively controlled and their ratio is inconsistent, other non-polar planes will appear, resulting in defects such as the pits circled in the figure on the column, which is not conducive to the growth of the subsequent semiconductor layer and the application of the device.

[0143] Example Two

[0144] In this embodiment, taking the first semiconductor layer in Example One as the foundation of the epitaxial body, three semiconductor sub-layers are continuously grown thereon as the second semiconductor layer. The three semiconductor sub-layers are a c-GaN layer (GaN doped with carbon element), a p-GaN layer, and an n-GaN layer. Then, AlGaN is grown on the outer surface of the foregoing multi-layer second semiconductor layer as the barrier layer, thereby obtaining an epitaxial body for manufacturing a vertical normally-off device. Among them, the first semiconductor layer in this embodiment serves as the supporting foundation in the epitaxial body and needs to grow to a certain width to play a supporting role. The c-GaN layer, p-GaN layer, and n-GaN layer constitute the second semiconductor layer and serve as the channel layer of the epitaxial body.

[0145] The growth condition data of the first semiconductor layer and the three sub-layers in the second semiconductor layer in this embodiment are shown in Table 4 below. To be concise and highlight the important data in the present invention, the doping composition data are omitted in Table 4. Specifically, for n-type GaN, silane SiH 4 in Example One can be doped, and the flow rate is, for example, 70 - 90 μmol / min. For p-type GaN, bis(cyclopentadienyl)magnesium (CP 2 Mg) can be doped, and its flow rate can be determined according to the doping concentration, for example, 1000 - 2500 sccm. The trench width and trench pitch in this embodiment are 3 μm respectively.

[0146] Table 4

[0147]

[0148] In this embodiment, multiple semiconductor layers are grown separately according to the time sequence in Table 4 under the aforementioned conditions. Among them, the first layer is an n-GaN layer, which serves as the foundation and support layer of the device. An n-type GaN layer with a width of 740 nm and a height of 1.43 μm is obtained through two growth stages. In the second growth stage, by slightly reducing the temperature, such as 1070 °C, the growth quality of the material can be optimized and the defect density can be reduced.

[0149] Then, the flow rate of TMGa and NH 3 flow rate are changed to grow the c-GaN layer at a new V / III ratio. Among them, the TMGa flow rate can be 500 - 700 μmol / min, and the NH 3 flow rate is 2000 - 2500 mmol / min. Compared with the flow rate conditions of the first semiconductor layer, by reducing the TMGa flow rate and / or increasing the NH 3 flow rate, the V / III ratio is increased to 3000 - 5000, thereby increasing the longitudinal growth rate and suppressing the lateral growth rate. In this embodiment, when the n-GaN layer reaches a width of 740 nm and a height of 1.43 μm, the TMGa flow rate is reduced, such as 550 - 650 μmol / min, while the NH 3 flow rate is increased, such as to 2000 - 2010 mmol / min, to grow the c-GaN layer at a V / III ratio of 3290 - 3310. The c-GaN layer grows upward from the top of the n-GaN layer of the first layer at a relatively fast longitudinal growth rate, and also grows from the side of the n-GaN layer at a relatively low lateral growth rate. When it reaches the preset height, such as about 2.5 μm from the bottom of the groove, the TMGa flow rate and NH 3 flow rate are changed to grow the next p-GaN layer. When growing the c-GaN layer, through a suitable combination of V / III ratio, gas pressure, and temperature conditions, its longitudinal growth rate is much greater than the lateral growth rate, and combined with the relatively narrow column spacing at this time, the growth on the sidewall of the lower semiconductor layer can be effectively suppressed. In addition, the c-GaN layer in this embodiment is located in the middle of the epitaxial body as a voltage-resistant layer, improving the quality of the epitaxial body. It can be known that the middle voltage-resistant layer can also be an undoped uid-GaN layer, which is specifically determined flexibly according to the application field of the device.

[0150] Embodiment 2

[0151] See Figure 16 , Figure 16 is a schematic structural principle diagram of the n-GaN layer and the c-GaN layer obtained by growing the nucleation layer on the sidewall of the self-substrate groove according to Embodiment 2 of the present invention. Figure 17SEM picture schematic of the n-GaN layer and c-GaN layer grown from the self-substrate trench sidewall nucleation layer according to Embodiment 2 of the present invention. In this embodiment, in addition to increasing the V / III ratio to increase the longitudinal growth rate of the semiconductor layer, the gas pressure can also be assisted to increase to help increase the longitudinal growth rate of the semiconductor layer. Therefore, in the specific data conditions of this embodiment, the TMGa flow rate is reduced from 700-850 μmol / min in the second growth stage to 550-650 μmol / min, and the NH 3 flow rate is increased to 2000-2010 mmol / min, and the gas pressure is increased to 150-160 Torr. Among them, the gas pressure range is 100-400 Torr. The height of the c-GaN layer is as Figure 17 shown, 2.51 μm high from the bottom of the groove, and the width is 1.05 μm.

[0152] For the p-GaN layer, the TMGa flow rate can be 300-500 μmol / min, the NH 3 flow rate is greater than 3000 mmol / min, and the V / III ratio is greater than 7000. Specifically as shown in Table 4, compared with the third period, in the fourth period, the TMGa flow rate is further reduced from 550-650 μmol / min to 310-330 μmol / min, and at the same time the NH 3 flow rate is further increased from 2000-2010 mmol / min to 3000-3010 mmol / min, and the V / III ratio at this time is 9350-9380. Since the growth of the pGaN layer on the side has the most serious impact on the device performance, the lateral growth is suppressed by increasing the V / III ratio. When the height of the p-GaN layer reaches the preset height, the top n-GaN layer is grown by changing each flow rate. See Figure 18 , Figure 18 is a schematic diagram of the structural principle of the n-GaN layer, c-GaN layer and p-GaN layer grown from the side of the self-nucleation layer according to Embodiment 2 of the present invention. In this embodiment, the V / III ratio is further increased, so the longitudinal growth rate of the p-GaN layer is further increased. At this time, since the gap between the two opposite sidewalls of the self-trench becomes narrow and deep, the lateral growth of the p-GaN layer is effectively suppressed. Therefore, the height of the p-GaN layer in this embodiment grows by 200 nm, and the thickness on the side is almost 0, that is, the p-GaN layer does not substantially grow on the side of the lower semiconductor layer.

[0153] Since the vertical growth rate and the lateral growth rate of the p-GaN layer can almost grow upward from the top layer of the lower semiconductor layer without growing laterally on the side of the lower layer, the growth conditions of the topmost n-GaN layer can be maintained to be roughly the same as those of the p-GaN layer, that is, the TMGa flow rate is 300-500 μmol / min, NH 3 flow rate is greater than 3000 mmol / min, and the V / III ratio is greater than 7000. In this embodiment, compared with the fourth growth stage, the TMGa flow rate is slightly increased, from 310-330 μmol / min in the fourth growth stage to 390-410 μmol / min, NH 3 flow rate is slightly increased, from 3000-3010 mmol / min in the fourth growth stage to 3190-3210 mmol / min. Correspondingly, the V / III ratio is 7990-8010. Under the condition of only growing longitudinally, by increasing TMGa to increase the concentration of Ga atoms, the growth rate of GaN is further increased. Refer to Figure 19 , Figure 19 FIG. is a schematic structural principle diagram of an n-GaN layer, a c-GaN layer, a p-GaN layer, and an n-GaN layer grown from the side of the self-nucleation layer according to Embodiment 2 of the present invention, Figure 20 FIG. is a schematic SEM picture diagram of an n-GaN layer, a c-GaN layer, a p-GaN layer, and an n-GaN layer grown from the side of the self-nucleation layer according to Embodiment 2 of the present invention. The n-G layer in the figure represents the n-GaN layer, and the p-G layer represents the p-GaN layer. In this embodiment, the top n-GaN layer has grown 730 nm upward from the top of the p-GaN layer. Currently, the width of the obtained epitaxial body still remains at about 1.05 μm and is overall uniform.

[0154] Another set of growth data is shown in Table 5: In this embodiment, the doping gas introduced is silane SiH 4 , and the flow rate is, for example, 240 μmol / min.

[0155] Table 5

[0156]

[0157] As can be seen from Table 5, starting from the first sub-guide uid-GaN layer in the second semiconductor layer, almost all grow only longitudinally without sidewall growth. Thus, it can be seen that by selecting a flow rate ratio matching the trench width, adjusting the flow rate and flow rate ratio of the growth conditions in different time periods, and then cooperating with appropriate temperature and pressure, the growth quality of the epitaxial body can be effectively and synergistically optimized.

[0158] As can be seen from the foregoing Example 1 and Example 2, the channel layer can be a single-layer semiconductor layer or a multi-layer semiconductor layer. The growth process of the first semiconductor layer grown from the bottom of the trench includes two growth stages. By controlling the molar flow rates of the group-V element source and the group-III metal element source in each of the two growth stages during the growth process of the first semiconductor layer, the lateral growth rate in the first growth stage can be made greater than that in the second growth stage, and the vertical growth rate in the second growth stage can be made greater than that in the first growth stage, so as to achieve the purpose of increasing the width of the first semiconductor layer. Specific control means, for example, making the molar flow rate of the group-III metal element source in the first growth stage greater than that of the group-III metal element source in the second growth stage. At the same time, making the molar flow rate of the group-V element source in the second growth stage greater than that of the group-V element source in the first growth stage.

[0159] Alternatively, when the difference between the molar flow rate of the group-III metal element source in the first growth stage and the molar flow rate of the first group-III metal element source in the second growth stage is less than a threshold value (such as 100 μmol / min), the molar flow rate of the group-V element source in the second growth stage is 1-3 times that of the group-V element source in the first growth stage. This solution is suitable for the case where the trench parameters are small.

[0160] When the trench parameters are large, it is also possible to make the vertical growth rate in the first growth stage greater than that in the second growth stage, and the lateral growth rate in the second growth stage greater than that in the first growth stage, that is, to first satisfy rapid growth in the vertical direction and then increase the lateral growth rate, which can also achieve the purpose of increasing the width of the first semiconductor layer.

[0161] In this embodiment, the growth conditions of the AlGaN barrier layer are, for example: under the conditions of a temperature of about 1050 °C and a pressure range of 50-100 Torr, trimethylgallium TMGa, trimethylaluminum TMAl and ammonia NH 3 are introduced, and the flow rates of the three are about 550 μmol / min, about 190 μmol / min and 2000-2500 mmol / min in sequence.

[0162] Further, a layer of silicon nitride SiN can be continuously grown on the outer surface of the AlGaN barrier layer x , for example, under the conditions of a temperature of about 1010 °C and a pressure range of 50-100 Torr, ammonia NH 3 and silane SiH 4 are introduced, and the flow rates of the two are about 2300 mmol / min and 3000-5000 mmol / min in sequence.

[0163] Finally, the top AlGaN and SiN are removed by etching or CMP (chemical mechanical polishing) to expose the n-GaN layer, facilitating the subsequent fabrication of electrodes. See x the materials, exposing the n-GaN layer for subsequent electrode fabrication. Refer to Figure 21 , Figure 21 which is a schematic diagram of the epitaxial structure principle after etching the top materials according to Embodiment 2 of the present invention. In this embodiment, the prepared epitaxial body includes a first epitaxial body 20, a barrier layer 30, and a dielectric layer 40. Among them, a nucleation layer is grown on the sidewalls of the trenches of the substrate 10, an n-GaN layer for support is grown from the nucleation layer, and then a c-GaN layer, a p-GaN layer, and an n-GaN layer are sequentially grown. The c-GaN layer, the p-GaN layer, and the n-GaN layer constitute the channel layer. A mask 12 is grown on the bottom and top surfaces of the substrate 10. The polar plane (0001) plane of the channel layer serves as the functional plane of the device, and the region adjacent to the barrier layer 30 is a two-dimensional electron gas (2DEG) 51, and the 2DEG 51 is depleted in the p-GaN layer. Therefore, the epitaxial body provided in this embodiment can be used to fabricate normally-off devices. As can be seen from Tables 4 and 5, the V / III ratio of the p-GaN layer for depleting the two-dimensional electron gas is the largest, and it only grows longitudinally without sidewall growth. Therefore, it can be used as the epitaxial body of a normally-off device.

[0164] When fabricating electrodes using the Figure 21 epitaxial body shown, in one embodiment, the substrate 10 is removed, and electrodes such as the drain are fabricated on the bottom of the epitaxial body. The bottom n-GaN layer in the epitaxial body can conveniently form an ohmic contact with the electrode, thus effectively improving the connectivity of the electrode. The middle p-GaN layer does not grow on the sidewalls of the c-GaN layer and does not affect the carrier density on the sidewalls. Therefore, the normally-off performance of the device is good.

[0165] Embodiment 3

[0166] Refer to Figure 22 , Figure 22 which is a flowchart of the preparation method of the normally-on vertical device epitaxial body according to Embodiment 3 of the present invention. In this embodiment, the epitaxial body includes a bottom n-GaN layer, a c-GaN layer as a buffer layer or a breakdown voltage layer, a single-channel layer uid-GaN layer, and a barrier layer. Among them, the bottom n-GaN layer serves as the first semiconductor layer, the channel layer uid-GaN layer serves as the second semiconductor layer, and the c-GaN layer serves as the fourth semiconductor layer. The fourth semiconductor layer substantially does not grow on the side of the lower semiconductor layer. The specific preparation method of this embodiment includes the following steps:

[0167] Step S31: Provide a silicon substrate and fabricate a plurality of trenches on the substrate. Among them, the trench width and trench pitch are 3 - 18 μm respectively. The sidewalls of the trenches serve as the vertical interfaces of the substrate, and their lattices have hexagonal symmetry.

[0168] Step S32: Fabricate a mask at the bottom of the trenches and on the top between adjacent trenches, exposing the sidewalls of the trenches that serve as the vertical interfaces of the substrate. The mask is, for example, silicon oxide SiO 2 .

[0169] Step S33: Grow a nucleation layer on the sidewalls of the trenches. Such as aluminum nitride AlN.

[0170] Step S34: Prepare the bottom n-GaN layer according to a preset V / III ratio. Among them, the temperature range is 1070 - 1080 °C, the pressure range is 50 - 100 Torr, the flow rate range of TMGa is 500 - 800 μmol / min, and the flow rate range of ammonia gas NH 3 is 1500 - 3000 mmol / min, and the V / III ratio range is 2000 - 5000.

[0171] Step S35: Determine whether the bottom n-GaN layer reaches the preset width and height. If the bottom n-GaN layer reaches the preset width and height, then in Step S36, adjust the V / III flow rate to prepare the c-GaN layer with a new V / III ratio for the breakdown voltage layer. If the bottom n-GaN layer does not reach the preset width and height, then continue to execute Step S34. Among them, when preparing the c-GaN layer for the breakdown voltage layer, the temperature range remains unchanged, still 1070 - 1080 °C, the pressure range remains unchanged, still 50 - 100 Torr, reduce the flow rate of TMGa, and its flow rate range is 300 - 500 μmol / min, increase the flow rate of ammonia gas NH 3 and its flow rate range is 2000 - 3000 mmol / min, thus increasing the V / III ratio, and the V / III ratio range is greater than 4000.

[0172] Step S37: Determine whether the c-GaN layer reaches the preset height. If the c-GaN layer reaches the preset height, then in Step S38, adjust the V / III flow rate to prepare the top uid-GaN layer with a new V / III ratio. If the c-GaN layer does not reach the preset height, then continue to execute Step S36. Among them, when preparing the top uid-GaN layer, the temperature range remains unchanged, still 1070 - 1080 °C, the pressure range remains unchanged, still 50 - 100 Torr, the flow rate of TMGa can remain unchanged or remain within a variable range, and the flow rate range is still 500 - 800 μmol / min, and the flow rate of ammonia gas NH 3The variation in the flow rate corresponds to the flow rate of TMGa. To increase the V / III ratio and make its range greater than 6000. Ammonia NH 3 has a flow rate range of 2000 - 3000 mmol / min.

[0173] Step S39: Determine whether the uid-GaN layer has reached the preset height and width. If the uid-GaN layer has reached the preset height and width, then in step S3910, prepare an AlGaN layer as the barrier layer. If the uid-GaN layer has not reached the preset height and width, then continue to execute step S38. Among them, when preparing the AlGaN layer, introduce TMGa with a flow rate range of 400 - 600 μmol / min, ammonia NH 3 with a flow rate range of 500 - 2500 mmol / min and TMAl with a flow rate range of 50 - 200 μmol / min into the reactor.

[0174] Step S311: Determine whether the thickness of the AlGaN layer has reached the preset requirement. If the thickness of the AlGaN layer has reached the preset requirement, then prepare a dielectric layer in step S312. If the thickness of the AlGaN layer has not reached the preset requirement, then continue to execute step S310. Among them, when preparing the dielectric layer, introduce ammonia NH 3 with a flow rate range of 2000 - 3000 mmol / min and silane SiH 4 .

[0175] Step S313: Determine whether the dielectric layer has reached the preset thickness. If the dielectric layer has reached the preset thickness, then in step S314, etch or polish the top dielectric layer and AlGaN layer to expose the top uid-GaN layer, and then end the process.

[0176] The growth period of each semiconductor layer in this embodiment adopts a fixed V / III ratio. After the current semiconductor layer meets the requirements, adjust the V / III ratio based on the trench width according to the matching relationship, and grow the next semiconductor layer with the new V / III ratio. Among them, after the bottom n-GaN layer reaches the preset width, the upper semiconductor layer grows upward from its top, and it does not substantially grow on the side of the lower semiconductor layer, that is, the thickness of the growth on the side of the lower semiconductor layer is close to zero. For the top uid-GaN layer, as the channel layer, it requires a certain thickness on the side, so the thickness of its growth from the lower semiconductor layer needs to meet this thickness requirement.

[0177] When adjusting the V / III ratio of each semiconductor layer, since the narrower the trench, the greater the aspect ratio of the semiconductor layer grown under the growth conditions of the same V / III ratio, in order to maintain a large aspect ratio, the wider the trench, the greater the flow rate of TMGa and NH 3 flow rate needs to be adjusted to increase the V / III ratio; under the same trench parameters, the V / III ratios of multiple semiconductor layers should show an overall upward trend in the growth order.

[0178] For example, when the substrate is silicon, the bottom layer is an n-GaN layer, the intermediate voltage-resistant layer is a c-GaN layer, the channel layer is a uid-GaN layer, the barrier layer is an AlGaN layer, the trench width is 3 μm, and the trench pitch is 3 μm, the growth parameters of each semiconductor layer are shown in Table 6:

[0179] Table 6

[0180]

[0181] As can be seen from Table 6, the V / III ratios of the 3 semiconductor layers increase in sequence according to the growth order. When growing the bottom n-GaN layer, a relatively high flow rate of TMGa is used to make the lateral growth rate of the n-GaN layer relatively large. When the height reaches the preset height, the width can also meet the requirements. Then, when growing the c-GaN layer, the V / III ratio is increased by reducing the flow rate of TMGa and simultaneously increasing the NH 3 flow rate and the longitudinal growth rate of the c-GaN layer is increased by increasing the gas pressure. Also, since the trench width in this embodiment is relatively narrow, the c-GaN layer can only grow upward from the top of the n-GaN layer, and the lateral growth rate is almost 0.

[0182] In this embodiment, since the uid-GaN layer is used as the channel layer, a certain thickness of the uid-GaN layer needs to grow on the side of the lower semiconductor layer. Therefore, the flow rates of TMGa and NH 3 are further adjusted, and the V / III ratio is further increased to increase the longitudinal growth rate, enabling the uid-GaN layer to grow rapidly upward from the top of the c-GaN layer to the preset height. In order to obtain a relatively small lateral growth rate, the temperature is reduced in the third growth stage, so that while growing longitudinally, it can grow from the side of the lower semiconductor layer at a relatively low lateral growth rate, resulting in a certain thickness of the uid-GaN layer growing on the side of the lower semiconductor layer. Refer to Figure 23 , Figure 23 which is a schematic diagram of the partial epitaxial structure principle in Embodiment 3 of the present invention. Figure 24Schematic diagram of the epitaxial structure after etching the top material according to Embodiment 3 of the present invention. In this embodiment, the prepared epitaxial body sequentially includes an n-GaN layer grown from the sidewall of the trench of the substrate 10, a c-GaN layer of the pressure-resistant layer, and a uid-GaN layer, an AlGaN layer, and a dielectric layer SiN of the top layer from bottom to top. A mask 12 is grown on the bottom and top surfaces of the trench of the substrate 10. The c-GaN layer of the pressure-resistant layer grows upward from the top of the n-GaN layer, and the side thickness is almost 0, while the uid-GaN layer grows upward from the top of the c-GaN layer and also grows from the side of the lower semiconductor, such as Figure 23 the thickness t therein. The structure after growing the AlGaN layer and the dielectric layer SiN and removing the top AlGaN layer and the dielectric layer SiN is as shown in Figure 24 . The prepared epitaxial body includes a first epitaxial body 20 (the outermost layer is the channel layer uid-GaN layer), a barrier layer 30, and a dielectric layer 40. In the region adjacent to the barrier layer 30 on the polar plane (0001) of the uid-GaN layer, there is a continuous two-dimensional electron gas (2DEG) 51. In the region adjacent to the barrier layer 30 on the polar plane (000-1) of the uid-GaN layer, there is a two-dimensional hole gas (2DHG) 52. Therefore, the epitaxial body provided in this embodiment can be used to manufacture normally-on devices.

[0183] When electrodes are prepared using the Figure 24 shown epitaxial structure, in one embodiment, the substrate 10 is removed, and an electrode, such as a drain electrode, is fabricated at the bottom of the epitaxial body. The bottom n-GaN layer in the epitaxial body can easily form an ohmic contact with the electrode, thus effectively improving the connectivity of the bottom electrode. Since the intermediate c-GaN layer does not grow on the sidewall of the n-GaN layer, the parasitic resistance generated by the c-GaN layer on the sidewall of the n-GaN layer is avoided; in addition, the uid-GaN in this embodiment can provide a high electron mobility, thereby improving the device performance.

[0184] In another embodiment, when the trench width is 6 μm and the trench pitch is 6 μm, the growth parameters of each semiconductor layer are shown in Table 7:

[0185] Table 7

[0186]

[0187] Comparing the first layer in Table 6 and Table 7, when the trench parameters increase, in order to obtain a sufficient aspect ratio, it is necessary to increase the V / III ratio. Then, comparing the second semiconductor layer, when the trench parameters increase, in order to increase the longitudinal growth rate and suppress the lateral growth rate, it is necessary to increase the V / III ratio by a large proportion, from about 4200 originally to about 6180, an increase of nearly 1.5 times. In addition, another reason for increasing the V / III ratio by a large proportion is the influence of the gas pressure. In this embodiment, the gas pressure values in the three growth stages remain the same, that is, when growing the second semiconductor layer, the longitudinal growth rate is not increased by adjusting the gas pressure, but by increasing the V / III ratio. That is to say, adjusting the gas pressure can also adjust the longitudinal growth rate, but it only serves as an auxiliary means. In this embodiment, the difference in the V / III ratio between the second and third semiconductor layers is not large, and the difference between the two is less than 1000.

[0188] In another embodiment, when the groove width is 18 μm and the groove pitch is 18 μm, the growth parameters of each semiconductor layer are shown in Table 8:

[0189] Table 8

[0190]

[0191] Comparing Table 6, Table 7 and Table 8, as the trench parameters increase, the V / III ratios of the second and third semiconductor layers further increase. Referring to Table 6 and Table 7, the V / III ratios of each semiconductor layer show an upward trend. Referring to Table 8, the difference in the V / III ratio between the second and third semiconductor layers is less than 1000.

[0192] As can be seen from the foregoing embodiments, when adjusting according to the matching relationship of the trench parameter value (i.e., the growth space width value), the V / III ratio in the same growth stage and the V / III ratio in adjacent growth stages during the growth processes of the first semiconductor layer and the second semiconductor layer, the longitudinal growth rate and the lateral growth rate of the target semiconductor layer can be effectively controlled, so that the grown epitaxial body is a high-quality and uniform columnar structure, and no side etching is required when manufacturing the device.

[0193] Embodiment 4

[0194] In this embodiment, the fabricated epitaxial body is used for normally-off devices, and the second semiconductor layer serves as the channel layer and is composed of three sub-layers. During the preparation, the substrate trench width value is 3 - 18 μm, the trench pitch is 3 - 18 μm, the group III metal element source is TMGa, and the group V element source is NH 3 . The growth parameters of each semiconductor layer are shown in Table 9:

[0195] Table 9

[0196]

[0197] Referring to the parameters in Table 9 above, it can be seen that the V / III ratio shows an upward trend in adjacent growth stages, and the TMGa flow rate shows a downward trend. When adjusting the flow rate, the morphology of the grown epitaxial layer can also be assisted in adjustment by adjusting the temperature and / or the air pressure.

[0198] Referring to Table 10, Table 10 is a data table of the specific growth condition parameter values of each semiconductor layer when preparing an epitaxial layer with a trench parameter value of 6 μm.

[0199] Table 10

[0200]

[0201]

[0202] Comparing Table 10 with Table 4 or Table 5, it can be seen that when the trench parameter value increases, since the trench parameter value is negatively correlated with the aspect ratio of the semiconductor layer, therefore, in order to obtain a large enough width, the height of the first semiconductor layer increases with the increase of the trench parameter value. Refer to Figure 25 , Figure 25 is a schematic structural diagram of an epitaxial layer obtained based on the growth conditions shown in Table 10 in the fourth embodiment of the present invention. In this embodiment, it can be seen from Table 10 that even without adjusting the air pressure and temperature, the p-GaN layer can grow only longitudinally by appropriately adjusting the flow rate of the group V element source gas and the flow rate of the group III metal element source. For the top n-GaN layer, when the air pressure and temperature are not adjusted, about 17.2 nm grows on the side walls of the lower semiconductor. The side of the top n-GaN layer adjacent to the barrier layer forms a polar plane, in which 2DEG is formed, and the 2DEG 51 in the region corresponding to the p-GaN layer in the polar plane is depleted, so that this epitaxial layer can be used to prepare normally-off vertical devices.

[0203] It can be known that the channel layer for a normally-off device can also be of the PNP type. The adjustment methods for the trench parameters, the molar flow rate of the group III metal element in the growth conditions, the molar flow rate of the group V element source, and the V / III ratio in the preparation process are the same as those in the foregoing embodiments. Referring to Table 11, Table 11 is a data table of the growth parameters of a PNP-type channel layer:

[0204] Table 11

[0205]

[0206] According to the parameters shown in Table 11, an epitaxial layer with an ideal columnar structure can be obtained.

[0207] In summary, the present invention controls the local growth gas distribution by regulating the growth space such as the width and spacing of the periodically arranged grooves on the substrate, thereby enabling the control of the morphology of the vertical epitaxial columns. By adjusting the flow rates of the group-V element source, the group-III metal element source, and the V / III ratio of different semiconductor layers based on the flow matching relationship between the grooves and the growth gas, the growth on the sidewalls of the underlying semiconductor can be inhibited and regulated during the growth process of the subsequent semiconductor layers, so that the growth morphology of the vertical epitaxial columns can be precisely regulated according to the device performance requirements.

[0208] The above embodiments are only for illustrating the present invention and are not intended to limit the present invention. Those of ordinary skill in the relevant technical fields can make various changes and modifications without departing from the scope of the present invention. Therefore, all equivalent technical solutions should also fall within the scope of the disclosure of the present invention.

Claims

1. A method for preparing a vertical device epitaxial body, characterized in that: include: Under the first growth condition, a first semiconductor layer is grown from a vertical interface, the lattice of the vertical interface has hexagonal symmetry; the width of the first semiconductor layer is not less than half of the width of the preset epitaxial body; Under a second growth condition, growing a second semiconductor layer from the outer surface of the first semiconductor layer; wherein the thickness of the second semiconductor layer grown from the longitudinal side of the first semiconductor layer meets the first thickness requirement; Growing a third semiconductor layer from the outer surface of the second semiconductor layer; wherein the thickness of the third semiconductor layer grown from the longitudinal side of the second semiconductor layer meets the second thickness requirement; Wherein, the longitudinal side surface of the second semiconductor layer includes a polar surface parallel to the vertical interface and adjacent to the interface of the third semiconductor layer, and the polar surface provides a vertical two-dimensional electron gas or a vertical two-dimensional hole gas; A first V / III flow ratio of the group V element source and the group III metal element source for growing the first semiconductor layer in the first growth condition is different from a second V / III flow ratio of the group V element source and the group III metal element source for growing the second semiconductor layer in the second growth condition.

2. The method for preparing a vertical device epitaxial body according to claim 1, characterized in that: Under the first growth condition, the first semiconductor layer is grown in stages, and the respective group V element source flow rates and group III metal element source flow rates in each growth stage are controlled according to the growth sequence, so that the lateral growth rate of the current growth stage is greater than the lateral growth rate of the next growth stage, and the longitudinal growth rate of the current growth stage is less than the longitudinal growth rate of the next growth stage; or the lateral growth rate of the current growth stage is less than the lateral growth rate of the next growth stage, and the longitudinal growth rate of the current growth stage is greater than the longitudinal growth rate of the next growth stage.

3. The method for preparing a vertical device epitaxial body according to claim 2, characterized in that: According to the growth sequence of the first semiconductor layer, the first V / III flow ratios of the plurality of growth stages are sequentially increased or decreased.

4. The method for preparing a vertical device epitaxial body according to claim 3, characterized in that: When growing the first semiconductor layer in two stages under the first growth condition, the first semiconductor layer is grown according to a first V / III flow ratio of a first aspect ratio in the first growth stage, and when the first semiconductor layer reaches a second preset width, the first V / III flow ratio is increased, and the first semiconductor layer is continued to grow according to the first V / III flow ratio of a second aspect ratio until the first semiconductor layer reaches the first preset width; wherein the first aspect ratio is smaller than the second aspect ratio; Alternatively, in the first growth stage, the first semiconductor layer is grown according to the first V / III flow ratio of the second aspect ratio, the first V / III flow ratio is reduced when the first semiconductor layer reaches the first preset height, and the first semiconductor layer is continued to grow at the first V / III flow ratio of the first aspect ratio until the first semiconductor layer reaches the first preset width.

5. The method for preparing a vertical device epitaxial body according to claim 4, characterized in that: The first V / III flow ratio is increased by reducing the flow rate of the group III metal element source in the second growth stage and / or increasing the flow rate of the group V element source in the second growth stage; the first V / III flow ratio is reduced by increasing the flow rate of the group III metal element source in the second growth stage and / or reducing the flow rate of the group V element source in the second growth stage.

6. The method for preparing a vertical device epitaxial body according to claim 4, characterized in that: When the difference between the group III metal element source flow rate in the first growth stage and the group III metal element source flow rate in the second growth stage is less than a threshold, the group V element source flow rate in the second growth stage is 1-3 times that of the group V element source flow rate in the first growth stage.

7. The method for preparing a vertical device epitaxial body according to claim 1, characterized in that: The second semiconductor layer includes a plurality of semiconductor sublayers. When a first semiconductor sublayer of the second semiconductor layer is longitudinally epitaxially grown under a second growth condition, the first semiconductor sublayer is substantially not grown on a side surface of a lower semiconductor layer.

8. The method for preparing a vertical device epitaxial body according to claim 7, characterized in that: A second semiconductor sublayer is also included below the first semiconductor sublayer by longitudinal epitaxial growth, and the thickness of the second semiconductor sublayer grown on the side of the lower semiconductor layer is not greater than a thickness threshold.

9. The method for preparing a vertical device epitaxial body according to claim 8, characterized in that: A third semiconductor sublayer is also included above the first semiconductor sublayer and is grown epitaxially in the longitudinal direction. The third semiconductor sublayer is not substantially grown on the side of the lower semiconductor layer.

10. The method for preparing a vertical device epitaxial body according to claim 9, characterized in that: The longitudinal side surfaces of the plurality of semiconductor sublayers of the second semiconductor layer respectively include polar surfaces parallel to the vertical interface and adjacent to the interface of the third semiconductor layer, and the polar surfaces provide vertical two-dimensional electron gas or vertical two-dimensional hole gas.

11. The method for preparing a vertical device epitaxial body according to claim 9, characterized in that: The longitudinal sides of the third semiconductor sublayer and the second semiconductor sublayer respectively include polar surfaces parallel to the vertical interface and adjacent to the interface of the third semiconductor layer, and the polar surfaces provide vertical two-dimensional electron gas or vertical two-dimensional hole gas; the region adjacent to the interface of the third semiconductor layer in the longitudinal side of the first semiconductor sublayer forms a depletion region for the two-dimensional electron gas or the two-dimensional hole gas.

12. The method for preparing a vertical device epitaxial body according to claim 7, characterized in that: A third semiconductor sublayer is also included above the first semiconductor sublayer, which is grown by longitudinal epitaxial growth. The thickness of the third semiconductor sublayer on the side of the lower semiconductor layer is not greater than a thickness threshold. A region of the side of the first semiconductor sublayer adjacent to the interface of the third semiconductor layer forms a depletion region for two-dimensional electron gas or two-dimensional hole gas. The vertical two-dimensional electron gas or the vertical two-dimensional hole gas provided in the longitudinal polar plane of the third semiconductor sublayer is interrupted in a region corresponding to the depletion region.

13. The method for preparing a vertical device epitaxial body according to claim 1, characterized in that: Further including: Under the third growth condition, one or more fourth semiconductor layers are epitaxially grown on top of the first semiconductor layer, and the one or more fourth semiconductor layers do not substantially grow on the side of the underlying semiconductor layer. Correspondingly, under the second growth condition, a second semiconductor layer is grown from the outer surface of the epitaxial body formed by the first semiconductor layer and the fourth semiconductor layer.

14. The method for preparing a vertical device epitaxial body according to claim 8 or 9 or 10 or 11 or 12, characterized in that: When epitaxially growing a plurality of semiconductor sublayers of the second semiconductor layer, a second V / III flow ratio of a group V element source and a group III metal element source used to grow each semiconductor sublayer shows an overall upward trend.

15. The method for preparing a vertical device epitaxial body according to claim 11 or 12, characterized in that: A second V / III flow ratio of the group V element source and the group III metal element source for growing the first semiconductor sublayer is the largest.

16. The method for preparing a vertical device epitaxial body according to claim 11 or 12, characterized in that: A second V / III flow ratio of the group V element source and the group III metal element source for growing the first semiconductor sublayer is 2-6 times the V / III flow ratio for growing the lower semiconductor sublayer.

17. The method for preparing a vertical device epitaxial body according to claim 1 or 13, characterized in that: The growth conditions also include temperature and / or gas pressure. When growing the target semiconductor layer with a preset V / III flow ratio, the temperature and / or gas pressure are adjusted to assist in adjusting the thickness of the target semiconductor layer grown from the longitudinal side of the lower semiconductor layer; wherein the preset V / III flow ratio is different from the V / III flow ratio for growing the lower semiconductor layer; when the target semiconductor layer is the second semiconductor layer, the corresponding lower semiconductor layer is the first semiconductor layer or the fourth semiconductor layer, and when the lower semiconductor layer is the fourth semiconductor layer, the corresponding lower semiconductor layer is the first semiconductor layer or another fourth semiconductor layer; the growth conditions are the first growth conditions or the second growth conditions, and the preset V / III flow ratio is the first V / III flow ratio or the second V / III flow ratio.

18. The method for preparing a vertical device epitaxial body according to claim 1, characterized in that: When the first semiconductor layer and / or the second semiconductor layer is a doped semiconductor layer, a doping source gas is introduced during the corresponding growth process.

19. The method for preparing a vertical device epitaxial body according to claim 1, characterized in that: During the growth process of the target semiconductor layer, based on the negative correlation between the width of the growth space where the vertical interface is located and the aspect ratio of the semiconductor layer, the matching aspect ratio is determined according to the width of the current growth space, and the V / III flow ratio of the growing target semiconductor layer is determined according to the aspect ratio. When the target semiconductor layer is the first semiconductor layer, the V / III flow ratio is the first V / III flow ratio, and when the target semiconductor layer is the second semiconductor layer, the V / III flow ratio is the second V / III flow ratio.

20. The method for preparing a vertical device epitaxial body according to claim 1 or 7, characterized in that: During the growth process of the target semiconductor layer, based on the positive correlation between the width of the growth space where the vertical interface is located and the growth thickness of the upper semiconductor layer on the longitudinal side of the lower semiconductor layer, the V / III flow ratio of the growth target semiconductor layer is determined according to the current width of the growth space and the side growth thickness requirements. The target semiconductor layer is the second semiconductor layer or semiconductor sublayer.

21. The method for preparing a vertical device epitaxial body according to claim 1, 19 or 20, characterized in that: Further including: The step of providing a vertical interface having a lattice with hexagonal symmetry.

22. The method for preparing a vertical device epitaxial body according to claim 21, characterized in that: The step of providing a vertical interface having a hexagonal symmetry lattice comprises: A substrate is provided, on which the vertical interface having a hexagonal symmetry lattice is formed.

23. The method for preparing a vertical device epitaxial body according to claim 22, characterized in that: The step of forming the vertical interface having a hexagonal symmetry lattice on the substrate comprises: A first region and a second region of different heights are formed on the substrate, and a vertical connection surface between the lower second region and the higher first region constitutes the vertical interface having a hexagonal symmetric lattice.

24. The method for preparing a vertical device epitaxial body according to claim 23, characterized in that: Further including: A nucleation layer is grown on a vertical connection surface between the second region at a lower position and the first region at a higher position, wherein the longitudinal side surface of the nucleation layer constitutes the vertical interface; or A core layer grows on a vertical connection surface between the second region at a lower position and the first region at a higher position; A buffer layer is grown from the nucleation layer, and the longitudinal side surfaces of the buffer layer constitute the vertical interface.

25. The method for preparing a vertical device epitaxial body according to claim 1, characterized in that: The third semiconductor layer serves as a barrier layer, and further comprises: a dielectric layer with a preset thickness is grown from the outer surface of the barrier layer.

26. A vertical device epitaxial body prepared by the method according to any one of claims 1 to 25, characterized in that: include: A first semiconductor layer, which is grown from a vertical interface having a hexagonal symmetry lattice under a first growth condition, wherein the width of the first semiconductor layer is not less than half of the width of the preset epitaxial body; A second semiconductor layer, which is grown from the outer surface of the first semiconductor layer under a second growth condition, wherein the thickness of the second semiconductor layer grown from the longitudinal side of the first semiconductor layer meets the first thickness requirement; and A third semiconductor layer is grown from the outer surface of the second semiconductor layer; wherein the thickness of the third semiconductor layer grown from the longitudinal side of the second semiconductor layer meets the second thickness requirement; The longitudinal side surface of the second semiconductor layer includes a polar surface parallel to the vertical interface and adjacent to the interface with the third semiconductor layer, and the polar surface provides a vertical two-dimensional electron gas or a vertical two-dimensional hole gas.

27. The vertical device epitaxial body according to claim 26, characterized in that: The second semiconductor layer includes a plurality of semiconductor sub-layers, wherein a first semiconductor sub-layer is not substantially grown on a side surface of a lower semiconductor layer.

28. The vertical device epitaxial body according to claim 27, characterized in that: A second semiconductor sublayer is also included below the first semiconductor sublayer. The thickness of the second semiconductor sublayer grown on the side of the lower semiconductor layer is not greater than a thickness threshold.

29. The vertical device epitaxial body according to claim 28, characterized in that: A third semiconductor sublayer is also included above the first semiconductor sublayer and is grown epitaxially in the longitudinal direction. The third semiconductor sublayer is not substantially grown on the side of the lower semiconductor layer.

30. The vertical device epitaxial body according to claim 28, characterized in that: The longitudinal side surfaces of the plurality of semiconductor sublayers of the second semiconductor layer respectively include polar surfaces parallel to the vertical interface and adjacent to the interface of the third semiconductor layer, and the polar surfaces provide a vertical two-dimensional electron gas or a vertical two-dimensional hole gas; or A longitudinal side surface of the first semiconductor sublayer adjacent to the interface with the third semiconductor layer forms a depletion region for the two-dimensional electron gas or the two-dimensional hole gas.

31. The vertical device epitaxial body according to claim 28, characterized in that: A third semiconductor sublayer is also included above the first semiconductor sublayer, which is grown by longitudinal epitaxial growth. The thickness of the third semiconductor sublayer on the side of the lower semiconductor layer is not greater than a thickness threshold. A region of the side of the first semiconductor sublayer adjacent to the interface of the third semiconductor layer forms a depletion region for two-dimensional electron gas or two-dimensional hole gas. The vertical two-dimensional electron gas or the vertical two-dimensional hole gas provided in the longitudinal polar plane of the third semiconductor sublayer is interrupted in a region corresponding to the depletion region.

32. The vertical device epitaxial body according to claim 26, characterized in that: One or more fourth semiconductor layers are included between the first semiconductor layer and the second semiconductor layer. The one or more fourth semiconductor layers are not substantially grown on the side of the lower semiconductor layer.

33. The vertical device epitaxial body according to claim 26, characterized in that: Further included is a substrate, wherein the substrate provides a vertical interface of the lattice having hexagonal symmetry.

34. The vertical device epitaxial body according to claim 33, characterized in that: The substrate comprises a first region and a second region of different heights, and a vertical connection surface between the second region at the lower position and the first region at the higher position constitutes the vertical interface; or It further comprises a nucleation layer grown on a vertical connection surface between the second region at a lower position and the first region at a higher position, wherein a longitudinal side surface of the nucleation layer constitutes the vertical interface; or The method further includes a buffer layer grown from the nucleation layer, wherein the longitudinal side surfaces of the buffer layer constitute the vertical interface.

35. The vertical device epitaxial body according to claim 26, characterized in that: The method further includes growing a dielectric layer with a preset thickness from the longitudinal outer surface of the third semiconductor layer.

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