A semiconductor structure and its manufacturing method

Abstract

This disclosure provides a semiconductor structure and its manufacturing method. The semiconductor structure includes a substrate, a buffer layer, a first channel layer, an etch mask layer, a first barrier layer, a second channel layer, and a second barrier layer stacked sequentially. The etch mask layer comprises multiple strip-shaped structures, with a strip-shaped groove between adjacent strip-shaped structures. The extension direction of the strip-shaped groove is a first direction, penetrating the etch mask layer and partially penetrating the first channel layer. The first barrier layer is conformally disposed in the strip-shaped grooves and on the etch mask layer, and includes a second groove corresponding to each strip-shaped groove. This disclosure simultaneously designs vertical and lateral multi-channel structures, increasing the two-dimensional electron gas concentration, reducing channel on-resistance, and achieving relative stability of transconductance within a large gate-source bias range, thereby increasing breakdown voltage, improving dynamic characteristics, and ultimately improving device linearity.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and specifically to a semiconductor structure and its manufacturing method. Background Technology

[0002] High electron mobility transistors (HEMTs) are a type of field-effect transistor that uses two materials with different band gaps to form a heterostructure, resulting in a strong two-dimensional electron gas (2DEG). They can operate at high frequencies and are therefore widely used in mobile phones, satellite television, and radar.

[0003] Compared to single-channel heterostructures, multi-channel heterostructures exhibit greater advantages. However, high electron mobility transistors with multi-channel heterostructures currently suffer from short transconductance stability and poor linearity. Therefore, improving transconductance stability and linearity is a problem that urgently needs to be solved by researchers in this field. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, to improve the linearity of high electron mobility transistors with multi-channel heterostructures.

[0005] According to one aspect of this disclosure, an embodiment of this disclosure provides a semiconductor structure, characterized in that it includes:

[0006] A substrate, a buffer layer, a first channel layer, an etching mask layer, a first barrier layer, a second channel layer, and a second barrier layer are stacked sequentially.

[0007] The etching mask layer comprises multiple strip-shaped structures, with a strip-shaped groove between two adjacent strip-shaped structures. The extension direction of the strip-shaped groove is a first direction. The strip-shaped groove penetrates the etching mask layer and partially penetrates the first channel layer. The first barrier layer is conformally disposed in the strip-shaped groove and on the etching mask layer. The first barrier layer includes a second groove corresponding to the strip-shaped groove.

[0008] As an optional embodiment, the bandgap width of the first barrier layer is greater than the bandgap width of the etch mask layer, and the bandgap width of the etch mask layer is greater than the bandgap width of the first channel layer.

[0009] As an optional embodiment, the material of the first barrier layer includes AlN, the material of the etching mask layer includes AlGaN, and the material of the first channel layer includes GaN.

[0010] As an optional embodiment, at least one of the strip structures of the etching mask layer has an Al composition different from that of the strip structures of the other etching mask layers.

[0011] As an optional embodiment, the surface of the second channel layer on the side away from the first barrier layer is planar.

[0012] As an optional embodiment, the second channel layer is conformally disposed on the first barrier layer, and the second channel layer includes a third groove corresponding to the second groove.

[0013] As an optional embodiment, the second barrier layer is conformally disposed on the second channel layer, and the second barrier layer includes a fourth groove corresponding to the third groove.

[0014] As an optional embodiment, in a plane perpendicular to the first direction, the cross-section of the strip-shaped groove is rectangular, trapezoidal, V-shaped, or bowl-shaped.

[0015] As an optional embodiment, at least one of the strip grooves has a different aspect ratio than the other strip grooves.

[0016] As an optional embodiment, the depth of the strip-shaped groove is constant while the width of the strip-shaped groove varies; or

[0017] The depth of the strip-shaped groove varies while the width of the strip-shaped groove remains constant; or

[0018] The depth and width of the strip-shaped groove change proportionally; or

[0019] The depth and width of the strip-shaped groove change inversely proportionally.

[0020] As an optional embodiment, the semiconductor structure further includes:

[0021] The source and drain are located on the second barrier layer, and the direction from the source to the drain is parallel to the first direction;

[0022] A gate is located on the second barrier layer and between the source and the drain;

[0023] A dielectric layer is located on the side of the gate near the second barrier layer.

[0024] As an optional embodiment, the second channel layer, the second barrier layer, the dielectric layer and the gate are conformally disposed on the first barrier layer in sequence, and the gate has a fifth groove corresponding to the second groove.

[0025] As an optional embodiment, the semiconductor structure further includes:

[0026] The anode and cathode are located on the buffer layer and on both sides of the first channel layer, the etching mask layer, the first barrier layer, the second channel layer, and the second barrier layer. The direction of the anode pointing to the cathode is parallel to the first direction.

[0027] According to another aspect of this disclosure, one embodiment of this disclosure provides a method for manufacturing a semiconductor structure, characterized by comprising the following steps:

[0028] S1. A substrate is provided, on which a buffer layer, a first channel layer and a plurality of strip-shaped etching mask layers are sequentially stacked;

[0029] S2. Etch the first channel layer exposed by the etching mask layer, with the etching depth being less than the thickness of the first channel layer, to form a plurality of strip-shaped grooves, wherein the extension direction of the strip-shaped grooves is a first direction;

[0030] S3. A first barrier layer is conformally disposed in the strip-shaped groove and on the etching mask layer, wherein the first barrier layer includes a second groove corresponding to the strip-shaped groove;

[0031] S4. A second channel layer is formed on the first barrier layer;

[0032] S5. A second barrier layer is provided on the second channel layer.

[0033] As an optional embodiment, the surface of the second channel layer on the side away from the first barrier layer is planar.

[0034] As an optional embodiment, the second channel layer is conformally disposed on the first barrier layer, and the second channel layer includes a third groove corresponding to the second groove.

[0035] As an optional embodiment, the second barrier layer is conformally disposed on the second channel layer, and the second barrier layer includes a fourth groove corresponding to the third groove.

[0036] As an optional embodiment, in a plane perpendicular to the first direction, the cross-section of the strip-shaped groove is rectangular, trapezoidal, V-shaped, or bowl-shaped.

[0037] As an optional embodiment, at least one of the strip-shaped grooves has a different aspect ratio than the other strip-shaped grooves.

[0038] This disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate, a buffer layer, a first channel layer, an etch mask layer, a first barrier layer, a second channel layer, and a second barrier layer stacked sequentially. The etch mask layer comprises multiple strip-shaped structures, with a strip-shaped groove between two adjacent strip-shaped structures. The extension direction of the strip-shaped groove is a first direction. The strip-shaped groove penetrates the etch mask layer and partially penetrates the first channel layer. The first barrier layer is conformally disposed in the strip-shaped groove and on the etch mask layer. The first barrier layer includes a second groove corresponding to the strip-shaped groove.

[0039] This disclosure designs multiple strip-shaped grooves in the first channel layer. The heterojunction interface between the first barrier layer and the first channel layer on the sidewall of the strip-shaped groove is approximately parallel to the polarization axis, resulting in virtually no polarization effect and no carrier generation. Therefore, the two-dimensional electron gas in the first channel layer can be confined to the bottom surface of the groove and the top surface between adjacent grooves, allowing the two-dimensional electron gas in the heterojunction structure to exhibit an approximately one-dimensional transport mode during migration, which can improve carrier mobility. At the same time, the lateral multi-channel design is equivalent to multiple heterojunction structures connected in parallel between the source and drain electrodes. Compared with planar heterojunction structures, this is beneficial for achieving mutual compensation of different transconductances in the device, achieving relative stability of transconductance within a large gate-source bias range, which is beneficial for improving breakdown voltage, improving dynamic characteristics, and thus improving device linearity.

[0040] The heterojunction between the second channel layer and the second barrier layer of this disclosure can generate a high-concentration and high-mobility two-dimensional electron gas. The heterojunctions between the first channel layer and the etch mask layer, between the etch mask layer and the first barrier layer, and between the first channel layer and the first barrier layer can replenish charge carriers, further increasing the two-dimensional electron gas concentration and reducing the channel on-resistance. The vertical multi-channel design, while increasing the two-dimensional electron gas concentration and carrier mobility, can also disperse the electric field lines and weaken the electric field strength, thereby increasing the breakdown voltage of the semiconductor structure. Attached Figure Description

[0041] Figure 1 The diagram shown is a schematic diagram of a semiconductor structure provided in an embodiment of this disclosure.

[0042] Figures 2a to 2c The diagram shown is a schematic diagram of a semiconductor structure provided in an embodiment of this disclosure.

[0043] Figures 3a to 3d The diagram shown is a schematic diagram of a semiconductor structure provided in an embodiment of this disclosure.

[0044] Figures 4a to 4d The diagram shown is a schematic diagram of a semiconductor structure provided in an embodiment of this disclosure.

[0045] Figure 5The diagram shown is a schematic diagram of a semiconductor structure provided in an embodiment of this disclosure.

[0046] Figure 6 The diagram shown is a flowchart of a semiconductor structure manufacturing method according to an embodiment of this disclosure.

[0047] Figure 7-12 The diagram shown is an exploded view of the semiconductor structure provided in an embodiment of this disclosure during the manufacturing process. Detailed Implementation

[0048] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0049] To improve the linearity of high electron mobility transistors with multi-channel heterostructures, this disclosure provides a semiconductor structure and its manufacturing method. The semiconductor structure includes a substrate, a buffer layer, a first channel layer, an etch mask layer, a first barrier layer, a second channel layer, and a second barrier layer stacked sequentially. The etch mask layer comprises multiple strip-shaped structures, with a strip-shaped groove between adjacent strip-shaped structures. The extension direction of the strip-shaped groove is a first direction, penetrating the etch mask layer and partially penetrating the first channel layer. The first barrier layer is conformally disposed in the strip-shaped grooves and on the etch mask layer, and includes a second groove corresponding to the strip-shaped groove. This disclosure simultaneously designs vertical and horizontal multi-channel structures, increasing the two-dimensional electron gas concentration, reducing channel on-resistance, and achieving relative stability of transconductance within a large gate-source bias range, thereby increasing breakdown voltage, improving dynamic characteristics, and ultimately improving device linearity.

[0050] The following is combined with Figures 1 to 12 A further example illustrates a semiconductor structure and its manufacturing method mentioned in this disclosure.

[0051] Figure 1 The diagram shown is a schematic representation of a semiconductor structure provided in an embodiment of this disclosure. Figure 1As shown, the semiconductor structure includes a substrate 10, a buffer layer 20, a first channel layer 30, an etching mask layer 40, a first barrier layer 50, a second channel layer 60, and a second barrier layer 70, which are sequentially stacked. The etching mask layer 40 comprises multiple strip-shaped structures, with a strip-shaped groove 31 between adjacent strip-shaped structures. The extension direction of the strip-shaped groove 31 is a first direction. The strip-shaped groove 31 penetrates the etching mask layer 40 and partially penetrates the first channel layer 30. The first barrier layer 50 is conformally disposed in the strip-shaped groove 31 and on the etching mask layer 40, and the first barrier layer 50 includes a second groove 51 corresponding to the strip-shaped groove 31. Figure 1 As shown, the semiconductor structure further includes: a source 81 and a drain 82, located on the second barrier layer 70, with the direction of the source 81 pointing towards the drain 82 parallel to the first direction; a gate 83, located on the second barrier layer 70 and between the source 81 and the drain 82; and a dielectric layer 84, located on the side of the gate 83 near the second barrier layer 70. The material of the dielectric layer 84 includes at least one of aluminum oxide, aluminum nitride, and aluminum oxynitride. The material of the dielectric layer 84 has a strong charge binding ability, and in the formed external electric field, the charge is not easily polarized, resulting in fewer polarized charges and a weaker polarization electric field, effectively avoiding the short-channel effect of the semiconductor structure. By setting the dielectric layer 84 to form a MIS gate structure, the gate leakage current can be effectively reduced, the gate voltage swing and drain current swing can be increased, and the device performance can be further improved.

[0052] In this embodiment, the bandgap of the first barrier layer 50 is greater than the bandgap of the etching mask layer 40, and the bandgap of the etching mask layer 40 is greater than the bandgap of the first channel layer 30. For example, in one embodiment, the material of the first barrier layer 50 includes AlN, the material of the etching mask layer 40 includes AlGaN, and the material of the first channel layer 30 includes GaN. Since the bandgap of the first barrier layer 50 is greater than the bandgap of the etching mask layer 40, and the bandgap of the etching mask layer 40 is greater than the bandgap of the first channel layer 30, a two-dimensional electron gas can be generated at the heterojunction interface of the first barrier layer 50 and the etching mask layer 40, and a two-dimensional electron gas can also be generated at the heterojunction interface of the etching mask layer 40 and the first channel layer 30, which can increase the two-dimensional electron gas concentration of the semiconductor structure and reduce the channel on-resistance.

[0053] In one embodiment, at least one strip structure of the etch mask layer 40 has an Al composition different from the strip structures of other etch mask layers 40. Increasing the Al composition in the etch mask layer 40 can increase the two-dimensional electron gas density, thereby increasing the saturation current of the device. By changing the Al composition in the etch mask layer 40 at different locations, the saturation current at different locations of the semiconductor structure can be adjusted, thereby making the transconductance peak values ​​of the heterojunction structure of the first barrier layer 50 and the etch mask layer 40, and the heterojunction structure of the etch mask layer 40 and the first channel layer 30 tend to be more uniform. The semiconductor structure of this disclosure can be regarded as a parallel connection of several devices with different transconductance distributions. Through this parallel structure, mutual compensation of the different transconductances of the devices is achieved, thereby achieving relative stability of the transconductance value within a large gate-source bias range, resulting in good linearity of the semiconductor structure.

[0054] Figures 2a to 2c The diagram shown is a schematic representation of a semiconductor structure provided in an embodiment of this disclosure. In one embodiment, as... Figure 1 As shown, the surface of the second channel layer 60 away from the first barrier layer 50 can be planar, so the two-dimensional electron gas generated at the heterojunction interface between the second channel layer 60 and the second barrier layer 70 is located on the same horizontal plane. In another embodiment, as... Figure 2a As shown, the second channel layer 60 is conformally disposed on the first barrier layer 50. The second channel layer 60 includes a third groove 61 corresponding to the second groove 51. Therefore, the two-dimensional electron gas generated at the heterojunction interface between the second channel layer 60 and the second barrier layer 70 is not on the same horizontal plane, further forming a lateral multi-channel structure. This facilitates mutual compensation of different transconductances in the device, achieving relative stability of the transconductance within a large gate-source bias range, which is beneficial for improving the breakdown voltage, enhancing dynamic characteristics, and thus improving the device linearity. In another embodiment, as... Figure 2b As shown, while the second channel layer 60 is conformally disposed on the first barrier layer 50, the second barrier layer 70 is also conformally disposed on the second channel layer 60. The second barrier layer 70 includes a fourth groove 71 corresponding to the third groove 61. Therefore, the two-dimensional electron gas generated at the heterojunction interface between the second channel layer 60 and the second barrier layer 70 is not on the same horizontal plane, and the gate 83 fills the fourth groove 71 in the second barrier layer 70. Besides further forming a lateral multi-channel structure, this significantly improves the gate 83's control over charge carriers, thus greatly increasing the device's breakdown voltage and reducing leakage current, and improving the efficiency and linearity of the RF device. In other embodiments, such as... Figure 2c As shown, the second channel layer 60, the second barrier layer 70, the dielectric layer 84 and the gate 83 are conformally disposed on the first barrier layer 50 in sequence. The gate 83 has a fifth groove 85 corresponding to the second groove 51, which can further improve the gate 83's control capability over charge carriers and further improve the device linearity.

[0055] Figures 3a to 3d The diagram shown is a schematic representation of a semiconductor structure according to an embodiment of this disclosure. In one embodiment, the cross-section of the strip-shaped groove 31 is rectangular in a plane perpendicular to the first direction (e.g., ...). Figure 3a (as shown), trapezoidal (as shown) Figure 3b As shown), V-shaped (as shown) Figure 3c (as shown) or bowl-shaped (such as) Figure 3d (As shown). This disclosure does not impose specific limitations on the cross-sectional shape of the strip groove 31. Changing the shape of the strip groove 31 can change the shape of the first barrier layer 50 in the strip groove 31, thereby modulating the generated two-dimensional electron gas and further improving the linearity of the semiconductor structure.

[0056] Figures 4a to 4d The diagram shown is a schematic representation of a semiconductor structure according to an embodiment of this disclosure. In one embodiment, at least one strip-shaped groove 31 has a different aspect ratio than the other strip-shaped grooves 31. Figure 4a As shown, the depth of the strip-shaped groove 31 is constant while the width of the strip-shaped groove 31 varies; or as... Figure 4b As shown, the depth of the strip-shaped groove 31 varies while the width of the strip-shaped groove 31 remains constant; or as... Figure 4c As shown, the depth and width of the strip-shaped groove 31 vary proportionally; or as... Figure 4d As shown, the depth and width of the strip groove 31 change inversely. By changing the depth and / or width of the strip groove 31, the transconductance peak value of the heterojunction structure at different locations can be changed, the threshold voltage of the heterojunction structure at different locations can be changed, and the linear operating characteristics of the device can be improved by superimposing multiple heterojunction structures.

[0057] Figure 5 The diagram shown is a schematic representation of a semiconductor structure according to an embodiment of this disclosure. In one embodiment, the semiconductor structure can be used to fabricate a diode, such as... Figure 5 As shown, the semiconductor structure further includes an anode 91 and a cathode 92, located on the buffer layer 20 and on both sides of the first channel layer 30, the etch mask layer 40, the first barrier layer 50, the second channel layer 60, and the second barrier layer 70. The direction of the anode 91 toward the cathode 92 is parallel to the first direction. Diode devices fabricated using the semiconductor structure of this disclosure can also improve breakdown voltage, enhance dynamic characteristics, and improve device linearity.

[0058] According to another aspect of this disclosure, Figure 6 The diagram shown is a flowchart of a semiconductor structure manufacturing method according to an embodiment of this disclosure. Figure 7-12 The diagram shown is an exploded view of the semiconductor structure provided in an embodiment of this disclosure during the manufacturing process. Figure 6 As shown, a semiconductor structure manufacturing method provided in one embodiment of this disclosure includes the following steps:

[0059] like Figure 7 As shown, step S1: A substrate is provided, and a buffer layer, a first channel layer and a plurality of strip-shaped etching mask layers are sequentially stacked on the substrate.

[0060] Specifically, the substrate 10 is made of any one or more combinations of Si, Al2O3, GaN, SiC, or AlN. The buffer layer 20 is made of a group III nitride material, which may include one or more of GaN, AlGaN, and AlInGaN, but is not limited thereto. The band gap of the etching mask layer 40 is larger than the band gap of the first channel layer 30. For example, the etching mask layer 40 may be made of AlGaN, and the first channel layer 30 may be made of GaN. A two-dimensional electron gas can be generated at the heterojunction interface between the etching mask layer 40 and the first channel layer 30.

[0061] In this embodiment, the fabrication method of the multiple strip-shaped etching mask layers 40 can be as follows: first, a film layer covering the entire surface is grown, and then a portion of the etching mask layer 40 is etched away using photolithography to form multiple strip-shaped etching mask layers 40; alternatively, the fabrication method of the multiple strip-shaped etching mask layers 40 can be as follows: first, multiple strip-shaped photoresist layers are formed, and then the strip-shaped etching mask layers 40 are grown between the photoresist layers, followed by the striping of the photoresist layers. This disclosure does not impose specific limitations on the fabrication method of the multiple strip-shaped etching mask layers 40.

[0062] like Figure 8 As shown, step S2: Etch the first channel layer exposed by the etching mask layer. The etching depth is less than the thickness of the first channel layer to form multiple strip-shaped grooves. The extension direction of the strip-shaped grooves is the first direction.

[0063] Specifically, the first channel layer 30 exposed by the etching mask layer 40 is etched, and the etching depth is less than the thickness of the first channel layer 30 to form multiple strip-shaped grooves 31, the extension direction of the strip-shaped grooves 31 being the first direction.

[0064] like Figure 9 As shown, step S3: a first barrier layer is conformally disposed in the strip-shaped groove and on the etching mask layer, the first barrier layer including a second groove corresponding to the strip-shaped groove.

[0065] Specifically, a first barrier layer 50 is conformally disposed in the strip groove 31 and on the etch mask layer 40. The first barrier layer 50 includes a second groove 51 corresponding to the strip groove 31. The band gap of the first barrier layer 50 is greater than the band gap of the etch mask layer 40. A two-dimensional electron gas can be generated at the heterojunction interface between the first barrier layer 50 and the etch mask layer 40.

[0066] like Figure 10 As shown, step S4: A second channel layer is formed on the first barrier layer. (As illustrated...) Figure 11 As shown, step S5: Set a second barrier layer on the second channel layer.

[0067] Specifically, a second channel layer 60 is disposed on the first barrier layer 50, and a second barrier layer 70 is disposed on the second channel layer 60. The band gap of the second barrier layer 70 is greater than the band gap of the second channel layer 60, and the heterojunction structure between the second barrier layer 70 and the second channel layer 60 can generate a high concentration of two-dimensional electron gas.

[0068] Step S6: Form a dielectric layer, a source and a drain on the second barrier layer, and a gate on the dielectric layer between the source and the drain, wherein the direction from the source to the drain is parallel to the first direction.

[0069] Specifically, a dielectric layer 84, a source 81, and a drain 82 are formed on the second barrier layer 70, and a gate 83 is formed on the dielectric layer 84 and located between the source 81 and the drain 82. The direction from the source 81 to the drain 82 is parallel to the first direction, forming a structure as shown in the diagram. Figure 1 The semiconductor structure shown is a dielectric layer 84 made of at least one of aluminum oxide, aluminum nitride, and aluminum oxynitride. The dielectric layer 84 has a strong charge-binding capability, making it less prone to charge polarization in the formed external electric field, resulting in fewer polarized charges and a weaker polarization electric field, effectively avoiding the short-channel effect in the semiconductor structure. By setting the dielectric layer 84 to form a MIS gate structure, the gate leakage current can be effectively reduced, and the gate voltage swing and drain current swing can be increased, further improving device performance.

[0070] In one embodiment, the grown second channel layer 60 completely fills the groove of the first barrier layer 50 and is flat, that is, the surface of the second channel layer 60 away from the first barrier layer 50 is planar, such as... Figure 1 As shown, the two-dimensional electron gas generated at the heterojunction interface between the second channel layer 60 and the second barrier layer 70 is located on the same horizontal plane. In another embodiment, the grown second channel layer 60 can be conformally disposed on the first barrier layer 50, and the second channel layer 60 includes a third groove 61 corresponding to the second groove 51, such as... Figure 2a As shown, the two-dimensional electron gas generated at the heterojunction interface between the second channel layer 60 and the second barrier layer 70 is not on the same horizontal plane, further forming a lateral multi-channel structure. This is beneficial for achieving mutual compensation of different transconductances in the device, realizing relative stability of transconductance within a large gate-source bias range, which is beneficial for improving breakdown voltage, improving dynamic characteristics, and thus improving device linearity. In another embodiment, while the grown second channel layer 60 is conformally disposed on the first barrier layer 50, the grown second barrier layer 70 is also conformally disposed on the second channel layer 60. The second barrier layer 70 includes a fourth groove 71 corresponding to the third groove 61, and the gate 83 fills the fourth groove 71 in the second barrier layer 70, as shown. Figure 2bAs shown, the two-dimensional electron gas generated at the heterojunction interface between the second channel layer 60 and the second barrier layer 70 is also not on the same horizontal plane. Besides further forming a lateral multi-channel structure, this significantly improves the gate 83's control over charge carriers, thus greatly increasing the device's breakdown voltage and reducing leakage current, and improving the efficiency and linearity of the RF device. In other embodiments, such as... Figure 2c As shown, the second channel layer 60, the second barrier layer 70, the dielectric layer 84 and the gate 83 are conformally disposed on the first barrier layer 50 in sequence. The gate 83 has a fifth groove 85 corresponding to the second groove 51, which can further improve the gate 83's control capability over charge carriers and further improve the device linearity.

[0071] In one embodiment, in a plane perpendicular to the first direction, the cross-section of the strip-shaped groove 31 is rectangular (e.g., ...). Figure 3a (as shown), trapezoidal (as shown) Figure 3b As shown), V-shaped (as shown) Figure 3c (as shown) or bowl-shaped (such as) Figure 3d (As shown). This disclosure does not impose specific limitations on the cross-sectional shape of the strip groove 31. Changing the shape of the strip groove 31 can change the shape of the first barrier layer 50 subsequently grown in the strip groove 31, thereby modulating the generated two-dimensional electron gas and further improving the linearity of the semiconductor structure.

[0072] In one embodiment, the etched grooves 31 have different dimensions, and at least one groove 31 has a different aspect ratio than the other grooves 31. For example... Figure 4a As shown, the depth of the strip-shaped groove 31 is constant while the width of the strip-shaped groove 31 varies; or as... Figure 4b As shown, the depth of the strip-shaped groove 31 varies while the width of the strip-shaped groove 31 remains constant; or as... Figure 4c As shown, the depth and width of the strip-shaped groove 31 vary proportionally; or as... Figure 4d As shown, the depth and width of the strip groove 31 change inversely. By changing the depth and / or width of the strip groove 31, the transconductance peak value of the heterojunction structure at different locations during subsequent growth can be changed, as can the threshold voltage of the heterojunction structure at different locations. Through the superposition of multiple heterojunction structures, the linear operating characteristics of the device can be improved.

[0073] In one embodiment, the semiconductor structure can be used to fabricate a diode. The semiconductor structure manufacturing method further includes step S7 after step S5: etching the second barrier layer, the second channel layer, the first barrier layer, the etching mask layer, and the first channel layer to the exposure buffer layer in the anode and cathode regions; setting an anode in the anode region and a cathode in the cathode region; the direction from the anode to the cathode is parallel to a first direction. Specifically, as shown... Figure 12As shown, the second barrier layer 70, the second channel layer 60, the first barrier layer 50, the etching mask layer 40, and the first channel layer 30 are etched to the exposure buffer layer 20 in the anode and cathode regions. An anode 91 is provided in the anode region and a cathode 92 is provided in the cathode region. The direction of the anode 91 pointing to the cathode 92 is parallel to the first direction, forming a structure as shown in the diagram. Figure 5 The diode structure shown is illustrated. Diode devices fabricated using the semiconductor structure disclosed herein can also improve breakdown voltage, dynamic characteristics, and device linearity.

[0074] This disclosure provides a semiconductor structure and its manufacturing method. The semiconductor structure includes a substrate, a buffer layer, a first channel layer, an etch mask layer, a first barrier layer, a second channel layer, and a second barrier layer stacked sequentially. The etch mask layer comprises multiple strip-shaped structures, with a strip-shaped groove between adjacent strip-shaped structures. The extension direction of the strip-shaped groove is a first direction, penetrating the etch mask layer and partially penetrating the first channel layer. The first barrier layer is conformally disposed in the strip-shaped grooves and on the etch mask layer, and includes a second groove corresponding to each strip-shaped groove. This disclosure simultaneously designs vertical and lateral multi-channel structures, increasing the two-dimensional electron gas concentration, reducing channel on-resistance, and achieving relative stability of transconductance within a large gate-source bias range, thereby increasing breakdown voltage, improving dynamic characteristics, and ultimately improving device linearity.

[0075] It should be understood that the term "comprising" and its variations as used in this disclosure are open-ended, meaning "including but not limited to". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment". In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0076] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications or equivalent substitutions made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: A substrate (10), a buffer layer (20), a first channel layer (30), an etching mask layer (40), a first barrier layer (50), a second channel layer (60), and a second barrier layer (70) are stacked sequentially. The etching mask layer (40) comprises multiple strip structures, with a strip groove (31) between two adjacent strip structures. The extension direction of the strip groove (31) is a first direction. The strip groove (31) penetrates the etching mask layer (40) and partially penetrates the first channel layer (30). The first barrier layer (50) is conformally disposed in the strip groove (31) and on the etching mask layer (40). The first barrier layer (50) includes a second groove (51) corresponding to the strip groove (31). The band gap of the first barrier layer (50) is greater than the band gap of the etching mask layer (40), and the band gap of the etching mask layer (40) is greater than the band gap of the first channel layer (30). The material of the etching mask layer (40) includes AlGaN.

2. The semiconductor structure according to claim 1, characterized in that, The material of the first barrier layer (50) includes AlN, and the material of the first channel layer (30) includes GaN.

3. The semiconductor structure according to claim 2, characterized in that, At least one of the strip structures of the etching mask layer (40) has an Al composition different from that of the strip structures of the other etching mask layers (40).

4. The semiconductor structure according to claim 1, characterized in that, The surface of the second channel layer (60) on the side away from the first barrier layer (50) is planar.

5. The semiconductor structure according to claim 1, characterized in that, The second channel layer (60) is conformally disposed on the first barrier layer (50), and the second channel layer (60) includes a third groove (61) corresponding to the second groove (51).

6. The semiconductor structure according to claim 5, characterized in that, The second barrier layer (70) is conformally disposed on the second channel layer (60), and the second barrier layer (70) includes a fourth groove (71) corresponding to the third groove (61).

7. The semiconductor structure according to claim 1, characterized in that, In a plane perpendicular to the first direction, the cross-section of the strip groove (31) is rectangular, trapezoidal, V-shaped or bowl-shaped.

8. The semiconductor structure according to claim 1, characterized in that, At least one of the strip grooves (31) has a different aspect ratio than the other strip grooves (31).

9. The semiconductor structure according to claim 8, characterized in that, The depth of the strip-shaped groove (31) is constant and the width of the strip-shaped groove (31) varies; or The depth of the strip-shaped groove (31) varies while the width of the strip-shaped groove (31) remains constant; or The depth and width of the strip-shaped groove (31) vary proportionally; or The depth and width of the strip groove (31) change inversely proportionally.

10. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes: The source (81) and drain (82) are located on the second barrier layer (70), and the direction of the source (81) pointing to the drain (82) is parallel to the first direction; The gate (83) is located on the second barrier layer (70) and between the source (81) and the drain (82); A dielectric layer (84) is located on the side of the gate (83) near the second barrier layer (70).

11. The semiconductor structure according to claim 10, characterized in that, The second channel layer (60), the second barrier layer (70), the dielectric layer (84) and the gate (83) are conformally disposed on the first barrier layer (50) in sequence, and the gate (83) has a fifth groove (85) corresponding to the second groove (51).

12. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes: The anode (91) and cathode (92) are located on the buffer layer (20) and on both sides of the first channel layer (30), the etching mask layer (40), the first barrier layer (50), the second channel layer (60) and the second barrier layer (70), with the anode (91) pointing towards the cathode (92) in a direction parallel to the first direction.

13. A method for manufacturing a semiconductor structure, characterized in that, Includes the following steps: S1. Provide a substrate (10), on which a buffer layer (20), a first channel layer (30) and a plurality of strip-shaped etching mask layers (40) are sequentially stacked. S2. The first channel layer (30) exposed by the etching mask layer (40) is etched, and the etching depth is less than the thickness of the first channel layer (30) to form a plurality of strip grooves (31), wherein the extension direction of the strip grooves (31) is the first direction; S3. A first barrier layer (50) is conformally disposed in the strip groove (31) and on the etching mask layer (40), the first barrier layer (50) including a second groove (51) corresponding to the strip groove (31). S4. A second channel layer (60) is provided on the first barrier layer (50). S5. A second barrier layer (70) is provided on the second channel layer (60), wherein the band gap of the first barrier layer (50) is greater than the band gap of the etching mask layer (40) and the band gap of the etching mask layer (40) is greater than the band gap of the first channel layer (30), and the material of the etching mask layer (40) includes AlGaN.

14. The method for manufacturing a semiconductor structure according to claim 13, characterized in that, The surface of the second channel layer (60) on the side away from the first barrier layer (50) is planar.

15. The method for manufacturing a semiconductor structure according to claim 13, characterized in that, The second channel layer (60) is conformally disposed on the first barrier layer (50), and the second channel layer (60) includes a third groove (61) corresponding to the second groove (51).

16. The method for manufacturing a semiconductor structure according to claim 15, characterized in that, The second barrier layer (70) is conformally disposed on the second channel layer (60), and the second barrier layer (70) includes a fourth groove (71) corresponding to the third groove (61).

17. The method for manufacturing a semiconductor structure according to claim 13, characterized in that, In a plane perpendicular to the first direction, the cross-section of the strip groove (31) is rectangular, trapezoidal, V-shaped or bowl-shaped.

18. The method for manufacturing a semiconductor structure according to claim 13, characterized in that, At least one of the strip grooves (31) has a different aspect ratio than the other strip grooves (31).

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