Trench gate device and manufacturing method thereof

Abstract

The invention relates to a trench gate device and a manufacturing method thereof. The trench gate device comprises a source region; a first doped region; the source electrode is arranged above the source electrode region and is electrically connected with the source electrode region and the first doped region; the enclosing wall structure comprises a trench gate, the trench gate comprises a gate dielectric layer located on the inner surface of the trench and a gate electrode located in the trench, and the periphery and the bottom of the gate electrode are surrounded by the gate dielectric layer; the enclosing wall structure separates the source region from the first doped region; the current blocking structure is located at the bottom of the enclosing wall structure and connected with the enclosing wall structure to form a surrounding structure, and the first doping region is located in the surrounding structure; the second doped region is located in the surrounding structure; the gate electrode is positioned above the trench gate and is electrically connected with the gate electrode and the second doped region; and the third doped region is located in the surrounding structure, and the first doped region and the second doped region are separated by the third doped region. According to the invention, bidirectional ESD protection can be obtained between the gate and the source of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and particularly to a trench gate device and a manufacturing method thereof. Background Art

[0002] ESD (Electro-Static Discharge) protection is an important part in IC (Integrated Circuit) design. For trench gate devices, there is also a need for gate ESD protection. Summary of the Invention

[0003] Based on this, it is necessary to provide a trench gate device with gate ESD protection ability and a manufacturing method thereof.

[0004] A trench gate device includes: a source region having a first conductivity type; a first doped region having a second conductivity type; the first conductivity type and the second conductivity type being opposite conductivity types; a source electrode disposed above the source region and electrically connected to the source region and the first doped region; a fence structure including a trench gate, the trench gate including a gate dielectric layer on the inner surface of the trench and a gate electrode located in the trench and surrounded by the gate dielectric layer on all sides and at the bottom; the fence structure separating the source region from the first doped region; a current blocking structure located at the bottom of the fence structure and connected to the fence structure to form an enclosed structure, the first doped region being located within the enclosed structure; a second doped region having a second conductivity type and located within the enclosed structure; a gate electrode located above the trench gate and electrically connected to the gate electrode and the second doped region; the trench gate extending from below the gate electrode to a position adjacent to the source region; a third doped region having a first conductivity type and located within the enclosed structure and separating the first doped region and the second doped region.

[0005] In the above trench gate device, when an ESD stress is applied between the gate and the source / between the source and the gate, the PN junction formed by the first doped region and the third doped region / the PN junction formed by the second doped region and the third doped region will undergo avalanche breakdown prior to the gate dielectric layer, and the ESD current is conducted away along the path of gate electrode - second doped region - third doped region - first doped region - source electrode / source electrode - first doped region - third doped region - second doped region - gate electrode, and the device obtains the characteristic of bidirectional ESD protection between the gate and the source.

[0006] In one embodiment, the current blocking structure is a buried region of the second conductivity type.

[0007] In one embodiment, the third doped region separates the current blocking structure from the second doped region.

[0008] In one embodiment, the spacing between the bottom of the second doped region and the top of the current blocking structure is ≥ 0.2 micrometers.

[0009] In one embodiment, the current blocking structure and the first doped region are separated by the third doped region.

[0010] In one embodiment, the trench gate device further includes: a first body region, having a second conductivity type, disposed adjacent to the first doped region, the first body region and the first doped region being separated by the enclosure structure, and the source region being located in the first body region.

[0011] In one embodiment, the trench gate device further includes: a second body region, having a second conductivity type, disposed adjacent to the second doped region, and the second body region and the second doped region being separated by the enclosure structure.

[0012] In one embodiment, the side surface of the trench gate is in direct contact with the second doped region and the second body region.

[0013] In one embodiment, the bottom depth of the trench gate is greater than the bottom depths of the second doped region and the second body region.

[0014] In one embodiment, the side surface of the trench gate is in direct contact with the first doped region and the first body region.

[0015] In one embodiment, the bottom depth of the trench gate is greater than the bottom depths of the first doped region and the first body region.

[0016] In one embodiment, the trench gate device further includes a first conductivity type region, the bottoms of the first body region, the second body region, and the current blocking structure being in direct contact with the first conductivity type region, and the bottom of the trench gate extending into the first conductivity type region.

[0017] In one embodiment, the trench gate device is a vertical device.

[0018] In one embodiment, the trench gate device is a vertical double-diffused metal oxide semiconductor field effect transistor or an insulated gate bipolar transistor.

[0019] A manufacturing method of a trench gate device, comprising: forming a current blocking structure in a first conductivity type region; forming a second conductivity type region and a surrounding wall structure in the first conductivity type region; the first conductivity type and the second conductivity type are opposite conductivity types; the surrounding wall structure includes a trench gate, the trench gate includes a gate dielectric layer located on the inner surface of the trench, and a gate electrode located in the trench and surrounded by the gate dielectric layer on all sides and at the bottom; the bottom of the surrounding wall structure extends to the current blocking structure, and the surrounding wall structure and the current blocking structure form an enclosing structure; the second conductivity type region includes a first doping region and a second doping region, the first doping region and the second doping region are located within the enclosing structure, and the first doping region and the second doping region are separated by the first conductivity type region inside the enclosing structure; forming a source region of the first conductivity type outside the enclosing structure; forming a first contact hole, a second contact hole, a third contact hole, a fourth contact hole, a source electrode and a gate electrode, the source electrode is formed above the source region, and the gate electrode is formed above the gate electrode; the source electrode is electrically connected to the source region through the conductive material in the first contact hole and electrically connected to the first doping region through the conductive material in the second contact hole, and the gate electrode is electrically connected to the second doping region through the conductive material in the third contact hole and electrically connected to the gate electrode through the conductive material in the fourth contact hole.

[0020] In the manufacturing method of the above trench gate device, when an ESD stress is applied between the gate and the source / between the source and the gate, the PN junction formed by the first doping region and the first conductivity type region in the enclosing structure / the PN junction formed by the second doping region and the first conductivity type region in the enclosing structure will undergo avalanche breakdown prior to the gate dielectric layer, and the ESD current is conducted away along the path of the gate electrode - the second doping region - the first conductivity type region - the first doping region - the source electrode / the source electrode - the first doping region - the first conductivity type region - the second doping region - the gate electrode, and the device obtains the characteristic of bidirectional ESD protection between the gate and the source. And the additional process steps required to form the ESD protection structure are less and simpler, so the additional manufacturing cost is less.

[0021] In one embodiment, the second conductivity type region further includes a first body region and a second body region, the first body region and the first doping region are separated by the surrounding wall structure, the second body region and the second doping region are separated by the surrounding wall structure, and the source region is located in the first body region.

[0022] In one embodiment, the current blocking structure is a second conductivity type buried region.

[0023] In one embodiment, the current blocking structure and the second doping region are separated by a third doping region.

[0024] In one embodiment, the trench gate device is a vertical device.

[0025] In one embodiment, the trench gate device is a vertical double-diffused metal oxide semiconductor field effect transistor or an insulated gate bipolar transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] To better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more of the accompanying drawings. Additional details or examples used to describe the drawings should not be construed as limiting the scope of any of the disclosed inventions, the presently described embodiments and / or examples, and the presently understood best mode of these inventions.

[0027] Figure 1 is a schematic structural diagram of a trench gate device in an embodiment of the present application;

[0028] Figure 2 is a flowchart of a manufacturing method of a trench gate device in an embodiment of the present application;

[0029] Figure 3 is a flowchart of sub-steps of forming a trench gate in an embodiment of the present application;

[0030] Figure 4 is in an embodiment of the present application Figure 2 a flowchart of sub-steps of step S240 shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present invention is thorough and comprehensive.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this invention belongs. The terms used in the description of the present invention herein are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0033] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Thus, a first element, component, region, layer or portion discussed below may be denoted as a second element, component, region, layer or portion without departing from the teachings of the present invention.

[0034] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature to another element or feature shown in the figures. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0035] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0036] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the invention. As such, variations from the shapes as shown are to be expected, for example, due to manufacturing techniques and / or tolerances. Accordingly, embodiments of the invention should not be limited to the particular shapes of regions shown herein, but include shape deviations resulting, for example, from manufacturing. For example, an implanted region shown as rectangular will typically have rounded or curved features at its edges and / or an implantation concentration gradient, rather than a binary change from the implanted region to the non-implanted region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the invention.

[0037] The semiconductor field terms used herein are common technical terms for those skilled in the art. For example, for P-type and N-type impurities, to distinguish the doping concentrations, simply the P+ type represents the P-type with a high doping concentration, the P type represents the P-type with a medium doping concentration, the P- type represents the P-type with a low doping concentration, the N+ type represents the N-type with a high doping concentration, the N type represents the N-type with a medium doping concentration, and the N- type represents the N-type with a low doping concentration.

[0038] Exemplary vertical-conduction power semiconductor devices (such as VDMOS, IGBT, etc.) achieve ESD protection for the device by fabricating a PN junction series structure in polysilicon on a substrate. Specifically, a polysilicon PN junction series structure on a thick dielectric is added in the region between the gate metal and the source metal, and the current discharge of the instantaneous high voltage between the gate and the source is achieved by relying on the series connection of multiple polysilicon PN junctions. To implement this structure, generally two photolithographies need to be added, namely, an etching mask for polysilicon and the thick dielectric below it, and an N-type doping implantation mask for the PN junction on the polysilicon. Since polysilicon has more defects and poorer breakdown voltage resistance, generally multiple PN junctions need to be connected in series to achieve the required breakdown voltage capability. This structure belongs to the ESD structure on the device surface, so the leakage between the gate and the source of the device is relatively large.

[0039] Figure 1 It is a schematic structural diagram of a trench gate device in an embodiment of the present application, including a first doping region 44, a second doping region 46, a third doping region 14, a current blocking structure 12, a trench gate 30, a source region 16, a source electrode (i.e., source metal) 72, and a gate electrode (i.e., gate metal) 74.

[0040] The source region 16 has a first conduction type. The first doped region 44 has a second conduction type and is disposed adjacent to the source region 16. The source electrode 72 is disposed above the source region 16 and is electrically connected to the source region 16 and the first doped region 44. The trench gate 30 includes a gate dielectric layer 32 located on the inner surface of the second trench, and a gate electrode 34 located within the second trench and surrounded by the gate dielectric layer 32 on all sides and at the bottom. The trench gate 30 extends from a position adjacent to the source region 16 to below the gate electrode 74, and the trench gate 30 controls the channel to turn on through the portion adjacent to the source region 16. In one embodiment of the present application, the trench gate 30 forms a wall structure that is a closed structure in a plane; in other embodiments, the wall structure may also be composed of the trench gate 30 and an isolation structure connected to the trench gate 30. The wall structure separates the source region 16 from the first doped region 44. The current blocking structure 12 is located at the bottom of the wall structure and is connected to the wall structure to form an enclosing structure that surrounds all sides and the bottom. The first doped region 44, the second doped region 46, and the third doped region 14 are located within the enclosing structure. The second doped region 46 has a second conduction type. The gate electrode 74 is located above the trench gate 30 and is electrically connected to the gate electrode 34 and the second doped region 46. The third doped region 14 has a first conduction type and is located within the enclosing structure and between the first doped region 44 and the second doped region 46, and is separated by the first doped region 44 and the second doped region 46. In Figure 1 In the illustrated embodiment, the first conduction type is N-type and the second conduction type is P-type. In other embodiments, the first conduction type may also be P-type and the second conduction type may be N-type.

[0041] In the above trench gate device, the first doped region 44, the second doped region 46, and the third doped region 14 within the enclosing structure form an ESD protection structure inside the device. When an ESD stress is applied between the gate and the source / between the source and the gate, the PN junction formed by the first doped region 44 and the third doped region 14 / the PN junction formed by the second doped region 46 and the third doped region 14 will undergo avalanche breakdown (reverse breakdown) prior to the gate dielectric layer 32, and the ESD current is conducted away along the path of the gate electrode 74 - the second doped region 46 - the third doped region 14 - the first doped region 44 - the source electrode 72 / the source electrode 72 - the first doped region 44 - the third doped region 14 - the second doped region 46 - the gate electrode 74, and the device obtains the characteristic of bidirectional ESD protection between the gate and the source. The enclosing structure can limit the current flow direction inside the ESD protection structure and prevent current leakage outside the enclosing structure. And since this ESD protection structure is made of bulk silicon, it has the advantage of lower leakage compared to the device surface ESD structure made of polysilicon, and is also not easily affected by the surface charges of the device.

[0042] See Figure 1, by reasonably setting the distance D between the first doping region 44 and the second doping region 46, the breakdown voltage of the ESD protection structure can be adjusted. It can be understood that the breakdown voltage of the ESD protection structure should be lower than the actual breakdown voltage of the gate dielectric layer 32 - that is, the voltage between the gate electrode 74 and the source electrode 72 at the moment when the gate dielectric layer 32 breaks down. Further, in order to suppress the leakage between the gate and the source during normal operation of the device, the breakdown voltage of the ESD protection structure can be adjusted to be not less than the rated anti-gate breakdown voltage, that is, the guaranteed value of the gate-source breakdown voltage marked in the device datasheet. This value means that when a given gate-source voltage is applied, the leakage between the gate and the source needs to be less than the set specification value, and this given gate-source voltage is the rated anti-gate breakdown voltage, which can also be called the basic gate breakdown voltage requirement.

[0043] In an embodiment of the present application, the trench-gate device is a vertical device, such as a vertical double-diffused metal oxide semiconductor field effect transistor (VDMOSFET) or an insulated gate bipolar transistor (IGBT). Correspondingly, the drain of the device is arranged on the back side of the wafer.

[0044] In an embodiment of the present application, the trench-gate device further includes a first body region 42. The first body region 42 has a second conductivity type and is disposed close to the first doping region 44. The first body region 42 and the first doping region 44 are separated by a wall structure, and the source region 16 is located in the first body region 42. In Figure 1 the illustrated embodiment, the first body region 42 and the first doping region 44 are separated by the trench gate 30.

[0045] In an embodiment of the present application, the trench-gate device further includes a second body region 48. The second body region 48 has a second conductivity type and is disposed close to the second doping region 46, and the second body region 48 and the second doping region 46 are separated by a wall structure. In Figure 1 the illustrated embodiment, the second body region 48 and the second doping region 46 are separated by the trench gate 30.

[0046] In an embodiment of the present application, the current blocking structure 12 is a buried region of the second conductivity type and withstands voltage by forming a PN junction with the third doping region 14. In Figure 1 the illustrated embodiment, the current blocking structure 12 is a P-buried layer, and its doping concentration is controlled at a low level to reduce the leakage during normal operation of the device. In other embodiments, the current blocking structure 12 can also be other isolation structures, such as an insulating layer, or a structure with a conductive material inside and wrapped by an insulating layer outside, etc.

[0047] In an embodiment of the present application, the current blocking structure 12 and the second doping region 46 are separated by the third doping region 14, that is, the distance between the bottom of the second doping region 46 and the top of the current blocking structure 12 is H, see Figure 1。In an embodiment where the current blocking structure 12 is a buried region of the second conductivity type, by reasonably setting the value of H, the reverse breakdown voltage of the PN junction formed by the third doped region 14 and the buried region of the second conductivity type can be adjusted. By reasonably setting the value of the reverse breakdown voltage, ESD protection can also be obtained between the gate and the drain of the device. In an embodiment of the present application, the interval H is greater than or equal to 0.2 micrometers.

[0048] In an embodiment of the present application, the current blocking structure 12 is separated from the first doped region 44 by the third doped region 14.

[0049] In an embodiment of the present application, the side surface of the trench gate 30 is in direct contact with the second doped region 46 and the second body region 48. In an embodiment of the present application, the bottom depth of the trench gate 30 is greater than the bottom depths of the second doped region 46 and the second body region 48.

[0050] In an embodiment of the present application, the side surface of the trench gate 30 is in direct contact with the first doped region 44 and the first body region 42. In an embodiment of the present application, the bottom depth of the trench gate 30 is greater than the bottom depths of the first doped region 44 and the first body region 42.

[0051] In Figure 1 In the embodiment shown, the trench gate device further includes a first conductivity type region 10. The bottoms of the first body region 42, the second body region 48, and the current blocking structure 12 are in direct contact with the first conductivity type region 10, and the bottom of the trench gate 30 extends into the first conductivity type region 10. The first conductivity type region 10 can serve as the drift region of the device.

[0052] In an embodiment of the present application, the gate layer 34 is made of polysilicon material. In other embodiments, metals, metal nitrides, metal silicides, or similar compounds can also be used as the material of the gate 34.

[0053] In one embodiment, the gate dielectric layer 32 can include conventional dielectric materials such as oxides, nitrides, and oxynitrides of silicon having a dielectric constant ranging from about 4 to about 20 (measured in a vacuum), or the gate dielectric layer 32 can include dielectric materials having a generally higher dielectric constant ranging from about 20 to at least about 100. Such higher dielectric constant dielectric materials can include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).

[0054] In an embodiment of the present application, the source electrode 72 is electrically connected to the source region 16 and the first body region 42 through the conductive material in the first contact hole 62, and is electrically connected to the first doped region 44 through the conductive material in the second contact hole 64. The gate electrode 74 is electrically connected to the second doped region 46 through the conductive material in the third contact hole 66, and is electrically connected to the gate 34 through the conductive material in the fourth contact hole 68.

[0055] In an embodiment of the present application, the trench gate device further includes an interlayer dielectric (ILD) layer 50. The first contact hole 62, the second contact hole 64, the third contact hole 66, and the fourth contact hole 68 penetrate through the interlayer dielectric layer 50.

[0056] The present application correspondingly provides a manufacturing method for a trench gate device. Figure 2 FIG. is a flowchart of a manufacturing method for a trench gate device in an embodiment of the present application, including the following steps:

[0057] S210, forming a current blocking structure in the first conductivity type region.

[0058] In an embodiment of the present application, the current blocking structure 12 is a second conductivity type buried region, which is formed in the first conductivity type region of the wafer by patterning (such as lithography) and ion implantation (implanting second conductivity type ions). In other embodiments, the current blocking structure 12 can also be other isolation structures, such as an insulating layer, or a structure with a conductive material inside and wrapped by an insulating layer outside, etc.

[0059] S220, forming a second conductivity type region and a surrounding wall structure in the first conductivity type region.

[0060] The surrounding wall structure is a closed structure in the plane. The surrounding wall structure includes the trench gate 30. The trench gate 30 includes a gate dielectric layer 32 on the inner surface of the trench, and a gate 34 located inside the trench and surrounded by the gate dielectric layer 32 on all sides and at the bottom. The bottom of the surrounding wall structure extends to the current blocking structure 12. The surrounding wall structure and the current blocking structure 12 form an enclosure structure. The second conductivity type region includes a first region and a second region, and the first region and the second region are separated by the first conductivity type region (i.e., the third doped region 14) inside the enclosure structure. The first region is separated by the surrounding wall structure into a first doped region 44 (located inside the enclosure structure) and a first body region 42 (located outside the enclosure structure), and the second region is separated by the surrounding wall structure into a second doped region 46 (located inside the enclosure structure) and a second body region 48 (located outside the enclosure structure). The second conductivity type region can be formed by patterning (such as lithography) and ion implantation (implanting second conductivity type ions). In an embodiment of the present application, the first conductivity type is N type and the second conductivity type is P type. In other embodiments, it can also be that the first conductivity type is P type and the second conductivity type is N type.

[0061] In one embodiment of the present application, the second conductivity type region may be formed in the first conductivity type region by patterning (e.g., lithography) and ion implantation (implanting ions of the second conductivity type).

[0062] See Figure 3 , in one embodiment of the present application, forming the trench gate 30 specifically includes the following steps:

[0063] S222, forming a trench.

[0064] In one embodiment of the present application, a trench is formed in the first conductivity type region by patterning (e.g., lithography) and etching.

[0065] S224, forming a gate dielectric layer in the trench.

[0066] In one embodiment of the present application, the gate dielectric layer 32 may be formed by thermal oxidation.

[0067] S226, filling polysilicon into the trench.

[0068] Polysilicon is deposited on the front side of the wafer, and the gate 34 is formed in the trench. After deposition, the excess polysilicon on the wafer surface can be removed by chemical mechanical planarization (CMP).

[0069] Thus far, the fabrication of the trench gate 30 is completed.

[0070] S230, forming a source region of the first conductivity type.

[0071] A source region 16 is formed outside the surrounding structure. In one embodiment of the present application, the source region 16 of the first conductivity type is formed in the first body region 42. In one embodiment of the present application, the source region 16 is formed by patterning (e.g., lithography) and ion implantation (implanting ions of the first conductivity type).

[0072] S240, forming a first contact hole, a second contact hole, a third contact hole, a fourth contact hole, a source electrode, and a gate electrode.

[0073] The source electrode 72 is formed above the source region 16, and the gate electrode 74 is formed above the gate 34. The source electrode 72 is electrically connected to the source region 16 through the conductive material in the first contact hole 62 and is electrically connected to the first doped region 44 through the conductive material in the second contact hole 64. The gate electrode 74 is electrically connected to the second doped region 46 through the conductive material in the third contact hole 66 and is electrically connected to the gate 34 through the conductive material in the fourth contact hole 68.

[0074] In one embodiment of the present application, step S240 includes the following steps:

[0075] S242, forming an interlayer dielectric layer 50.

[0076] The interlayer dielectric (ILD) can be a silicon oxide layer, such as a doped or undoped silicon oxide material layer formed by a thermal chemical vapor deposition (thermal CVD) manufacturing process or a high density plasma chemical vapor deposition (HDPCVD) manufacturing process. Specifically, it can be undoped silicon glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric can also be spin-on-glass (SOG) doped with boron or phosphorus, tetraethoxysilane doped with phosphorus (PTEOS), tetraethoxysilane doped with boron (BTEOS), etc.

[0077] S244, form contact holes penetrating the interlayer dielectric layer.

[0078] In an embodiment of the present application, the first contact hole 62, the second contact hole 64, the third contact hole 66, the fourth contact hole 68, etc. can be formed by photolithography and etching the interlayer dielectric layer 50. The lower part of the first contact hole 62 extends to the source region 16 and the first body region 42 near the source region 16. The bottom of the second contact hole 64 extends to the first doped region 44. The bottom of the third contact hole 66 extends to the second doped region 46. The bottom of the fourth contact hole 68 extends to the gate 34.

[0079] S246, fill the conductive material in each contact hole.

[0080] Fill metal and / or alloy as the conductive material in the first contact hole 62, the second contact hole 64, the third contact hole 66, the fourth contact hole 68, etc. Among them, the metal material can include one or several of Ag, Au, Cu, Pd, Pt, Cr, Mo, Ti, Ta, W, and Al.

[0081] S248, form the source electrode and the gate electrode.

[0082] Form the source electrode 72 and the gate electrode 74 on the interlayer dielectric layer 50.

[0083] For the manufacturing method of the trench gate device described above, when the gate-source or source-gate is subjected to ESD stress, the PN junction formed by the first doped region 44 and the first conductivity type region in the surrounding structure / the PN junction formed by the second doped region 46 and the first conductivity type region in the surrounding structure will undergo avalanche breakdown prior to the gate dielectric layer 32. The ESD current is conducted away along the path of gate electrode 74 - second doped region 46 - first conductivity type region - first doped region 44 - source electrode 72 / source electrode 72 - first doped region 44 - first conductivity type region - second doped region 46 - gate electrode 74, and the device obtains the characteristic of bidirectional ESD protection between the gate and the source. Since in the process architectures of some devices, the lithography and ion implantation of the second conductivity type region in step S220 already exist, the ESD protection structure only needs to add the process step of forming the current blocking structure 12, and the added process steps are fewer and simpler, so the increased manufacturing cost is less.

[0084] The manufacturing method of the trench gate device of the present application and the trench gate device are based on the same inventive concept. For the content not specifically described in the manufacturing method of the trench gate device, reference can be made to the introduction of the trench gate device above.

[0085] It should be understood that although the steps in the flowchart of the present application are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the present application may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0086] In the description of this specification, the description with reference to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or features described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0087] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0088] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patented application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A trench gate device, characterized in that, comprising: a source region having a first conductivity type; a first doped region having a second conductivity type; the first conductivity type and the second conductivity type are opposite conductivity types; a source electrode disposed above the source region and electrically connected to the source region and the first doped region; a surrounding structure including a trench gate, the trench gate including a gate dielectric layer on the inner surface of the trench and a gate electrode located within the trench and surrounded by the gate dielectric layer on all sides and at the bottom; the surrounding structure separates the source region from the first doped region; a current blocking structure located at the bottom of the surrounding structure and connected to the surrounding structure to form an enclosed structure, and the first doped region is located within the enclosed structure; a second doped region having a second conductivity type, located within the enclosed structure; a gate electrode located above the trench gate and electrically connected to the gate electrode and the second doped region; the trench gate extends from below the gate electrode to a position adjacent to the source region; a third doped region having a first conductivity type, located within the enclosed structure and separating the first doped region and the second doped region.

2. The trench gate device according to claim 1, characterized in that, the current blocking structure is a buried region of the second conductivity type.

3. The trench gate device according to claim 2, characterized in that, the third doped region separates the current blocking structure from the second doped region.

4. The trench gate device according to claim 1, characterized in that, further comprising: a first body region having a second conductivity type, disposed adjacent to the first doped region, separated from the first doped region by the surrounding structure, and the source region is located within the first body region; a second body region having a second conductivity type, disposed adjacent to the second doped region, and separated from the second doped region by the surrounding structure.

5. The trench gate device according to claim 4, characterized in that, the side surface of the trench gate is in direct contact with the second doped region and the second body region, and the bottom depth of the trench gate is greater than the bottom depths of the second doped region and the second body region; and / or the side surface of the trench gate is in direct contact with the first doped region and the first body region, and the bottom depth of the trench gate is greater than the bottom depths of the first doped region and the first body region.

6. The trench gate device according to claim 4, characterized in that, further comprising a region of the first conductivity type, the bottom of the first body region, the bottom of the second body region and the current blocking structure are in direct contact with the region of the first conductivity type, and the bottom of the trench gate extends into the region of the first conductivity type.

7. The trench gate device according to any one of claims 1-3, characterized in that, the trench gate device is a vertical device.

8. The trench gate device according to claim 7, characterized in that, the trench gate device is a vertical double-diffused metal oxide semiconductor field effect transistor or an insulated gate bipolar transistor.

9. A method for manufacturing a trench gate device, comprising: forming a current blocking structure in a region of the first conductivity type; A second conductivity type region and a surrounding wall structure are formed in the first conductivity type region; The first conductivity type and the second conductivity type are opposite conductivity types; the surrounding wall structure includes a trench gate, the trench gate includes a gate dielectric layer located on the inner surface of the trench, and a gate electrode located in the trench and surrounded by the gate dielectric layer on all sides and at the bottom; the bottom of the surrounding wall structure extends to the current blocking structure, and the surrounding wall structure and the current blocking structure form an enclosing structure; the second conductivity type region includes a first doping region and a second doping region, the first doping region and the second doping region are located within the enclosing structure, and the first doping region and the second doping region are separated by the first conductivity type region inside the enclosing structure; A source region of the first conductivity type is formed outside the enclosing structure; A first contact hole, a second contact hole, a third contact hole, a fourth contact hole, a source electrode, and a gate electrode are formed. The source electrode is formed above the source region, and the gate electrode is formed above the gate electrode; the source electrode is electrically connected to the source region through the conductive material in the first contact hole and is electrically connected to the first doping region through the conductive material in the second contact hole. The gate electrode is electrically connected to the second doping region through the conductive material in the third contact hole and is electrically connected to the gate electrode through the conductive material in the fourth contact hole.

10. The manufacturing method of the trench gate device according to claim 9, characterized in that, The second conductivity type region further includes a first body region and a second body region. The first body region and the first doping region are separated by the surrounding wall structure, the second body region and the second doping region are separated by the surrounding wall structure, and the source region is located in the first body region.

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