Groove type silicon carbide MOSFET device and preparation method thereof

Abstract

The invention provides a trench-type silicon carbide MOSFET device and a preparation method thereof, the trench-type silicon carbide MOSFET device comprises drain electrode metal and an N-type drain electrode, an N-type epitaxial layer and a P-type body region are sequentially arranged on the upper surface of the N-type drain electrode, an N-type source electrode and a P-type source electrode are further arranged on the surface of the P-type body region, a longitudinal trench is arranged on the surface of one end, away from the N-type drain electrode, of the N-type epitaxial layer, polycrystalline silicon is arranged in the longitudinal trench, and the polycrystalline silicon is arranged in the longitudinal trench. The periphery of the polycrystalline silicon is wrapped by the gate oxide layer; a first P-type doped region is arranged in the lower area of the bottom of the longitudinal groove, a second P-type doped region is arranged in the lower area of the P-type body region, the first P-type doped region and the second P-type doped region extend in the direction close to the N-type drain electrode and are connected through a transverse P-type doped region, and source electrode metal and dielectric layers are arranged on the surface of the N-type source electrode and the surface of the P-type source electrode. The gate oxide layer of the device can be comprehensively protected, meanwhile, the current path is matched with the electric field direction when the structure is conducted, and the on resistance of the device can be greatly reduced.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a trench-type silicon carbide MOSFET device and a manufacturing method thereof. Background Art

[0002] As one of the representatives of the third-generation wide bandgap semiconductor materials, silicon carbide (SiC) material has advantages such as wide bandgap, high critical breakdown electric field, high thermal conductivity, and high saturation drift velocity compared with the existing silicon materials. The MOSFET device prepared with SiC material has advantages such as low on-resistance, small size, and fast switching speed compared with the silicon-based MOSFET with the same breakdown voltage level, making it have broad application prospects in the fields of high-power, high-temperature, and high-frequency power electronics. There are two typical gate structures for SiC MOSFET devices: planar gate and trench gate. Among them, SiC trench MOSFET has become one of the research hotspots due to its advantages such as low on-resistance and small chip area. Compared with the planar gate type SiC MOSFET device, the trench-type SiC MOSFET device forms a channel on the sidewall of the trench, which not only improves the channel mobility but also eliminates the JFET effect, significantly reduces the on-resistance of the device, and at the same time reduces the cell size and increases the power density.

[0003] During the traditional gate oxide preparation process of SiC trench MOSFET, since the oxidation rate at the bottom of the trench is much lower than that at the sidewall of the trench, the quality of the gate oxide at the bottom of the trench is poor, and electric field concentration is likely to occur at the trench corner, deteriorating the breakdown characteristics of the device. The current traditional trench-type silicon carbide MOSFET device structure is as Figure 2 shown. Generally, a P-type doping region is implanted at the bottom of the trench to relieve the electric field concentration problem at the trench corner and improve the breakdown characteristics of the device. However, other performances of the device cannot be well improved. In addition, this method also increases the process production cost. Summary of the Invention

[0004] The object of the present invention is to overcome the deficiencies existing in the prior art and provide a trench-type silicon carbide MOSFET device and a manufacturing method thereof. The present invention can provide a relatively comprehensive protection for the gate oxide layer of the device. At the same time, the current path during the conduction of the structure matches the electric field direction, which can greatly reduce the on-resistance of the device. In addition, the structure of the laterally arranged P-type doping regions at intervals in the present invention can achieve a good pinch-off effect, suppress the saturation current of the device, and improve the short-circuit and avalanche capabilities of the device. Moreover, the formation of the first P-type doping region does not require a mask plate, improving the accuracy of the production process and reducing the process production cost.

[0005] To achieve the above technical objectives, the technical solution adopted in the embodiment of the present invention is: In a first aspect, an embodiment of the present invention provides a trench-type silicon carbide MOSFET device, including a drain metal and an N-type drain located on its upper surface. An N-type epitaxial layer is provided on the upper surface of the N-type drain as the drift region of the MOSFET. A P-type body region is provided on the upper surface of the N-type epitaxial layer. An N-type source and a P-type source are also provided on the surface of the P-type body region. A longitudinal trench is provided on the surface of the N-type epitaxial layer at an end far from the N-type drain. Polysilicon is provided inside the longitudinal trench as the gate of the MOSFET, and the periphery of the polysilicon is wrapped by a gate oxide layer; The implantation depth of the P-type body region in the N-type epitaxial layer is less than the depth of the longitudinal trench. A first P-type doped region is provided in the region below the bottom of the longitudinal trench. A second P-type doped region is provided in the region below the P-type body region. The first P-type doped region and the second P-type doped region extend towards the N-type drain and are connected by a lateral P-type doped region. Source metals for connecting source signals are provided on the surfaces of the N-type source and the high-concentration P-type source. A dielectric layer is provided on other regions of the surface of the N-type epitaxial layer except for the source metals.

[0006] Further, the N-type source is located on both sides of the longitudinal trench, and the P-type source is interspersed between adjacent two N-type sources at intervals.

[0007] Further, the doping concentrations of the first P-type doped region, the second P-type doped region, and the lateral P-type doped region are all higher than the doping concentration of the P-type body region.

[0008] Preferably, the doping concentrations of the first P-type doped region, the second P-type doped region, and the lateral P-type doped region are 1e17 cm -3 ~1e21 cm -3 , and the doping concentration range of the P-type body region is 1e13 cm -3 ~1e17 cm -3 , and the doping concentrations of the first P-type doped region, the second P-type doped region, and the lateral P-type doped region are higher than the doping concentration of the P-type body region.

[0009] Further, the first P-type doped region is provided below the longitudinal trench. The upper surface of the first P-type doped region overlaps with the longitudinal trench, and the width of the first P-type doped region is less than the width of the longitudinal trench.

[0010] Further, the second P-type doped region is provided below the P-type body region. The upper surface of the second P-type doped region overlaps with the P-type body region, and the width of the P-type doped region is less than the width of the P-type body region.

[0011] Further, the bottoms of the first P-type doped region and the second P-type doped region are connected by a lateral P-type doped region, and the lateral P-type doped regions are arranged at intervals in a direction perpendicular to the longitudinal trench.

[0012] Further, the doping concentrations of the N-type drain, the N-type source, and the P-type source are all higher than the doping concentration of the N-type epitaxial layer.

[0013] In a second aspect, an embodiment of the present invention provides a method for manufacturing the trench-type silicon carbide MOSFET device described in the first aspect, including the following steps: Step S1: Select an N-type substrate material as the N-type drain of the device, and epitaxially grow an N-type epitaxial layer on the upper surface of the N-type drain once; Step S2: Use a mask for the lateral P-type doped region to implant acceptor ions on the surface of the N-type epitaxial layer by high-energy ion implantation to form a lateral P-type doped region; Step S3: Use a mask for the P-type doped region to implant acceptor ions on the surface of the N-type epitaxial layer by high-energy ion implantation to form a first P-type doped region and a second P-type doped region; Step S4: Inject acceptor ions on the surface of the N-type epitaxial layer to form a P-type body region, and then inject donor ions on the surface of the N-type epitaxial layer to form an N-type source; Step S5: Deposit a first barrier layer on the N-type epitaxial layer, use a mask to remove the first barrier layer in the region where the longitudinal trench is located, and further form a longitudinal trench; Step S6: Grow a gate oxide layer in the longitudinal trench, then deposit polysilicon in the longitudinal trench to form a gate, and remove the gate oxide layer and polysilicon on the surface of the N-type epitaxial layer; Step S7: Deposit a dielectric layer on the N-type epitaxial layer, use a mask for the P-type source to etch down the dielectric layer, and implant acceptor ions on the surface of the N-type epitaxial layer to form a P-type source; Step S8: Deposit metal on the upper surface of the N-type epitaxial layer and the lower surface of the N-type drain respectively and anneal to form a source metal and a drain metal.

[0014] In a third aspect, an embodiment of the present invention provides a method for manufacturing the trench-type silicon carbide MOSFET device described in the first aspect, where the P-type doped region is formed by multiple epitaxies, including the following steps: Step 1: Select an N-type substrate material as the N-type drain of the device, epitaxially grow an N-type epitaxial layer for the first time, and use a mask for the lateral P-type doped region to implant acceptor ions on the surface of the N-type epitaxial layer to form a lateral P-type doped region; Step 2: Grow an N-type epitaxial layer for the second time, use masks for the first P-type doped region and the second P-type doped region to implant acceptor ions on the surface of the N-type epitaxial layer to form a first P-type doped region and a second P-type doped region, and then grow a third layer of N-type epitaxial layer; Step 3: Inject acceptor ions onto the surface of the N-type epitaxial layer to form a P-type body region, and then inject donor ions onto the surface of the N-type epitaxial layer to form an N-type source electrode; Step 4: Deposit a first barrier layer on the N-type epitaxial layer, then use a mask plate to remove the first barrier layer in the region where the longitudinal trench is located, and further form a longitudinal trench; Step 5: Grow a gate oxide layer in the longitudinal trench, then deposit polysilicon in the longitudinal trench to form a gate electrode, and remove the gate oxide layer and polysilicon on the surface of the N-type epitaxial layer; Step 6: Deposit a dielectric layer on the N-type epitaxial layer, use a P-type source electrode mask plate to etch the dielectric layer downward, and inject acceptor ions onto the surface of the N-type epitaxial layer to form a P-type source electrode; Step 7: Deposit metal on the upper surface of the N-type epitaxial layer and the lower surface of the N-type drain respectively and anneal to form a source electrode metal and a drain electrode metal.

[0015] Fourthly, an embodiment of the present invention provides a preparation method of the trench-type silicon carbide MOSFET device described in the first aspect. The lateral P-type doping region and the second P-type doping region are formed together, and the first P-type doping region is formed by a self-alignment process, including the following steps: Step St1: Select an N-type substrate material as the N-type drain of the device, and epitaxially grow an N-type epitaxial layer once; Step St2: Use a mask plate for the lateral P-type doping region and the second P-type doping region to inject acceptor ions onto the surface of the N-type epitaxial layer to form a lateral P-type doping region and a second P-type doping region respectively; Step St3: Inject acceptor ions onto the surface of the N-type epitaxial layer to form a P-type body region, and then inject donor ions onto the surface of the N-type epitaxial layer to form an N-type source electrode; Step St4: Deposit a first barrier layer on the N-type epitaxial layer, then use a mask plate to remove the first barrier layer in the region where the longitudinal trench is located, and further form a longitudinal trench; Step St5: Deposit a second barrier layer on the surface of the N-type epitaxial layer, then etch the second barrier layer, etch off the second barrier layer at the bottom of the longitudinal trench, and retain the second barrier layer on the sidewall of the longitudinal trench; Step St6: Use an ion implantation method to inject acceptor ions onto the surface of the N-type epitaxial layer to form a first P-type doping region; Step St7: Etch off the remaining first barrier layer and second barrier layer on the surface of the N-type epitaxial layer, and then perform high-temperature annealing; Step St8: Grow a gate oxide layer in the longitudinal trench, then deposit polysilicon in the longitudinal trench to form a gate electrode, and remove the gate oxide layer and polysilicon on the surface of the N-type epitaxial layer; Step St9: Deposit a dielectric layer on the N-type epitaxial layer, etch away the dielectric layer downward using a P-type source mask, and implant acceptor ions on the surface of the N-type epitaxial layer to form a P-type source. Step St10: Deposit metal on the upper surface of the N-type epitaxial layer and the lower surface of the N-type drain and anneal to form source metal and drain metal.

[0016] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects: (1) The trench-type silicon carbide MOSFET device provided by the present invention has a relatively deep first P-type doping region at the bottom of the trench gate. The first P-type doping region is connected to the second P-type doping region to the device source through a lateral P-type doping region, which can effectively reduce the electric field strength at the gate oxide interface and improve the device reliability.

[0017] (2) The width of the P-type doping region at the bottom of the longitudinal trench of the trench-type silicon carbide MOSFET device provided by the present invention is smaller than the width of the longitudinal trench. In the on state, the current path of this device structure matches the direction of the electric field, which can greatly reduce the on-resistance of the device.

[0018] (3) The trench-type silicon carbide MOSFET device provided by the present invention has a relatively deep lateral P-type doping region at the bottom of the longitudinal trench connecting the first P-type doping region and the second P-type doping region. The lateral P-type doping regions are arranged at intervals in the direction perpendicular to the longitudinal trench. In the on state, it has a good pinch-off effect, suppresses the saturation current of the device, and improves the short-circuit ability and avalanche ability of the device.

[0019] (4) When preparing the first P-type doping region of the trench-type silicon carbide MOSFET device provided by the present invention, deposit a second barrier layer on the surface of the N-type epitaxial layer, then etch the second barrier layer, etch away the second barrier layer at the bottom of the longitudinal trench, and retain the second barrier layer on the sidewalls of the longitudinal trench; use the ion implantation method to implant acceptor ions on the surface of the N-type epitaxial layer to form a first P-type doping region with a width less than or equal to the width of the longitudinal trench; that is, the present invention provides a self-aligned process method. Without the aid of a mask, this method can accurately form the first P-type doping region at the bottom of the longitudinal trench, improve the accuracy of the production process, and reduce the production cost at the same time. Description of the Drawings

[0020] Figure 1 It is a schematic cross-sectional structure diagram of the trench-type silicon carbide MOSFET device in Embodiment 1.

[0021] Figure 2 It is a schematic cross-sectional structure diagram of a traditional trench-type silicon carbide MOSFET device.

[0022] Figure 3Schematic cross-sectional structure diagram after forming the N-type epitaxial layer in Embodiment 1 of the present invention.

[0023] Figure 4 Schematic cross-sectional structure diagram for forming the lateral P-type doped region in Embodiment 1 of the present invention.

[0024] Figure 5 Schematic cross-sectional structure diagram for forming the first P-type doped region and the second P-type doped region in Embodiment 1 of the present invention.

[0025] Figure 6 Schematic cross-sectional structure diagram for forming the P-type body region and the N-type source in Embodiment 1 of the present invention.

[0026] Figure 7 Schematic cross-sectional structure diagram after completing the longitudinal trench etching in Embodiment 1 of the present invention.

[0027] Figure 8 Schematic cross-sectional structure diagram after completing the growth of the gate oxide layer and the polysilicon filling in Embodiment 1 of the present invention.

[0028] Figure 9 Schematic cross-sectional structure diagram after forming the dielectric layer and the P-type source in Embodiment 1 of the present invention.

[0029] Figure 10 Schematic cross-sectional structure diagram for forming the lateral P-type doped region after the first epitaxy in Embodiment 2 of the present invention.

[0030] Figure 11 Schematic cross-sectional structure diagram for forming the first P-type doped region and the second P-type doped region after the second epitaxy, and the profile after growing the third epitaxy in Embodiment 2 of the present invention.

[0031] Figure 12 Schematic cross-sectional structure diagram for forming the lateral P-type doped region and the second P-type doped region in Embodiment 3 of the present invention.

[0032] Figure 13 Schematic cross-sectional structure diagram after depositing the first barrier layer and etching the longitudinal trench in Embodiment 3 of the present invention.

[0033] Figure 14 Schematic cross-sectional structure diagram after completing the deposition of the second barrier layer in Embodiment 3 of the present invention.

[0034] Figure 15 Schematic cross-sectional structure diagram after completing the etching of the second barrier layer in Embodiment 3 of the present invention.

[0035] Figure 16 Schematic cross-sectional structure diagram for forming the first P-type doped region in Embodiment 3 of the present invention.

[0036] Explanation of the reference numerals: 01—source metal; 02a—dielectric layer; 02b—gate oxide layer; 03—N-type source; 04—P-type body region; 05—polysilicon; 06—vertical groove; 07—P-type source; 07a—first P-type doped region; 07b—second P-type doped region; 07c—lateral P-type doped region; 08—N-type epitaxial layer; 09—N-type drain; 10—drain metal; 11—first barrier layer; 12—second barrier layer. DETAILED DESCRIPTION

[0037] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0038] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of the present invention.

[0039] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the present invention described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0040] Comparative Example The cross-section of a conventional trench SiC MOSFET device is shown below: Figure 2As shown in the figure, it includes an N-type drain 09 and a drain metal 10 located on the lower surface of the N-type drain 09. An N-type epitaxial layer 08 is provided on the upper surface of the N-type drain 09 as the drift region of the MOSFET. A P-type body region 04 is provided on the upper surface of the N-type epitaxial layer 08. An N-type source 03 and a P-type source 07 are also provided on the upper surface of the P-type body region 04. A longitudinal trench 06 is provided on the surface of the N-type epitaxial layer 08 far from the N-type drain 09. Polysilicon 05 is provided inside the longitudinal trench 06 as the gate of the MOSFET, and the periphery of the polysilicon 05 is wrapped by a gate oxide layer 02b. The implantation depth of the P-type body region 04 in the N-type epitaxial layer 08 is less than the depth of the longitudinal trench 06. A first P-type doped region 07a and a second P-type doped region 07b are respectively provided in the N-type epitaxial layer in the region below the bottom of the longitudinal trench 06 and in the region below the P-type body region 04. The first P-type doped region 07a wraps the entire bottom of the longitudinal trench 06. The first P-type doped region 07a and the second P-type doped region 07b extend towards the N-type drain 09. Source metals 01 for connecting source signals are also provided on the surfaces of the N-type source 03 and the P-type source 07. A dielectric layer 02a is provided on the surface of the N-type epitaxial layer 08 except for the source metals 01.

[0041] The doping concentrations of the N-type drain 09, the N-type source 03, and the P-type source 07 are all higher than the doping concentration of the N-type epitaxial layer 08.

[0042] The most important problem of the trench-type silicon carbide trench MOSFET is the high electric field strength problem of the gate oxide under the reverse breakdown voltage state. In order to maintain the long-term reliability of the silicon carbide MOSFET device, the maximum electric field strength of the gate oxide needs to be limited below 3 MV / cm when the device is under reverse breakdown voltage. The gate oxide field strength of the trench-type silicon carbide MOSFET without a protection structure often reaches above 8 MV / cm under the reverse breakdown voltage state, far higher than the requirement of the working reliability of the electric field strength. Setting a P-type shielding region structure connected to the source potential at the bottom and side walls of the longitudinal trench can effectively relieve the electric field strength in the gate oxide layer 02b and ensure the reliability of the device.

[0043] Example 1 As Figure 1As shown, a trench-type silicon carbide MOSFET device includes an N-type drain 09 and a drain metal 10 on the lower surface of the N-type drain 09. An N-type epitaxial layer 08 is provided on the upper surface of the N-type drain 09 as the drift region of the MOSFET. A P-type body region 04 is provided on the upper surface of the N-type epitaxial layer 08. An N-type source 03 and a P-type source 07 are also provided on the upper surface of the P-type body region 04. A longitudinal trench 06 is provided on the surface of the N-type epitaxial layer 08 away from the N-type drain 09. Polysilicon 05 is provided inside the longitudinal trench 06 as the gate of the MOSFET, and the polysilicon 05 is surrounded by a gate oxide layer 02b. The polysilicon 05 is connected to the longitudinal trench 06 through the gate oxide layer 02b. The implantation depth of the P-type body region 04 in the N-type epitaxial layer 08 is less than the depth of the longitudinal trench 06. Two first P-type doped regions 07a and second P-type doped regions 07b are respectively provided in the N-type epitaxial layer in the region below the bottom of the longitudinal trench 06 and in the region below the P-type body region 04. The first P-type doped region 07a and the second P-type doped region 07b extend in the direction close to the N-type drain 09 and are connected to each other through a lateral P-type doped region 07c. A source metal 01 for connecting the source signal is also provided on the surfaces of the N-type source 03 and the P-type source 07. A dielectric layer 02a is provided on the surface of the N-type epitaxial layer 08 except for the source metal 01.

[0044] The N-type source 03 is located on both sides of the longitudinal trench 06, and the P-type source 07 is interspersed between adjacent two N-type sources 03 at intervals.

[0045] The first P-type doped region 07a is provided below the longitudinal trench 06. The upper surface of the first P-type doped region 07a overlaps with the longitudinal trench 06. The width of the first P-type doped region 07a is less than the width of the longitudinal trench 06. The first P-type doped region 07a can be located directly below, diagonally below to the left or diagonally below to the right of the longitudinal trench 06, not limited to directly below as shown in the figure.

[0046] The second P-type doped region 07b is provided below the P-type body region 04. The upper surface of the second P-type doped region 07b overlaps with the P-type body region 04. The width of the P-type doped region 07b is less than the width of the P-type body region 04. The second P-type doped region 07b can be located directly below, diagonally below to the left or diagonally below to the right of the P-type body region 04, not limited to directly below as shown in the figure.

[0047] The bottoms of the first P-type doped region 07a and the second P-type doped region 07b are connected by a lateral P-type doped region 07c, and the lateral P-type doped regions 07c are arranged at intervals in a direction perpendicular to the longitudinal trench 06. The doping concentrations of the first P-type doped region 07a, the second P-type doped region 07b, and the lateral P-type doped region 07c are all higher than the doping concentration of the P-type body region 04. Among them, the doping concentrations of the first P-type doped region 07a, the second P-type doped region 07b, and the lateral P-type doped region 07c are 1e17 cm -3 ~1e21 cm -3 , and the doping concentration range of the P-type body region 04 is 1e13 cm -3 ~1e17 cm -3 .

[0048] The doping concentrations of the N-type drain 09, the N-type source 03, and the P-type source 07 are all higher than the doping concentration of the N-type epitaxial layer 08.

[0049] The concentration range of the N-type drain 09 is 7.5e 18 cm -3 ~1.5e 19 cm -3 , the concentration range of the N-type source 03 is 1.5e 19 cm -3 ~1.5e 20 cm -3 , the concentration range of the P-type source 07 is 1.5e 19 cm -3 ~1.5e 20 cm -3 , and the doping concentration of the N-type epitaxial layer 08 is 1e 15 cm -3 ~5e 16 cm -3 .

[0050] Example 2 The preparation method of the trench-type silicon carbide MOSFET device in Example 1 includes the following steps: Step S1: Select an N-type substrate material as the N-type drain 09 of the device, then epitaxially grow an N-type epitaxial layer 08 on the upper surface of the N-type drain 09 once, and then clean the epitaxial wafer to obtain the device structure as Figure 3 shown; Among them, the N-type substrate material is 4H-SiC, 6H-SiC or 3C-SiC, preferably 4H-SiC; Step S2: Use a mask plate to expose the region where the lateral P-type doped region 07c is located in the N-type epitaxial layer 08 through photolithography, form the lateral P-type doped region 07c by high-energy ion implantation of acceptor ions, and obtain the device structure as Figure 4 shown after removing the mask plate; Step S3: Using a mask plate, the areas in the N-type epitaxial layer 08 that need to form P-type doped regions are exposed through photolithography. Acceptor ions are implanted into the surface of the N-type epitaxial layer 08 at high energy to form a first P-type doped region 07a and a second P-type doped region 07b. The bottoms of the first P-type doped region 07a and the second P-type doped region 07b are connected by a lateral P-type doped region 07c, obtaining the device structure as shown in Figure 5 the figure; Step S4: Acceptor ions are implanted into the surface of the N-type epitaxial layer 08 to form a P-type body region 04, and then donor ions are implanted into the surface of the N-type epitaxial layer 08 to form an N-type source electrode 03, obtaining the device structure as shown in Figure 6 the figure; Step S5: A first barrier layer 11 is deposited on the N-type epitaxial layer 08. Then, using a mask plate, the areas on the surface of the N-type epitaxial layer 08 that need to form the vertical trench 06 are exposed through photolithography. The first barrier layer 11 in the area where the vertical trench 06 is located is removed, and the silicon carbide is further etched to form the vertical trench 06, obtaining the device structure as shown in Figure 7 the figure; The first barrier layer 11 is made of a material including silicon nitride, silicon oxide compound, or polysilicon; Step S6: A gate oxide layer 02b is grown in the vertical trench 06, and polysilicon 05 is deposited in the vertical trench 06 to form a gate. Then, the redundant gate oxide layer and polysilicon on the surface of the N-type source electrode 03 are removed, obtaining the device structure as shown in Figure 8 the figure; When forming the gate, polysilicon with a relatively high doping concentration is used, and the doping concentration range is 5.0×10 19 cm -3 ~1.0×10 21 cm -3 , aiming to facilitate obtaining a lower gate resistance; Step S7: A dielectric layer 02a is deposited on the upper surface of the N-type source electrode 03. Then, using a P-type source electrode 07 mask plate, the dielectric layer 02a is etched downward to form a contact hole. Acceptor ions are implanted into the surface of the N-type epitaxial layer 08 to form a P-type source electrode 07, obtaining the device structure as shown in Figure 9 the figure; The dielectric layer 02a is made of one of silicon oxide, nitrogen oxide, and polyimide; Step S8: Metals are deposited on the upper surface of the N-type epitaxial layer 08 and the lower surface of the N-type drain 09 respectively and annealed to form a source electrode metal 01 and a drain electrode metal 10 for ohmic contact, obtaining the final Figure 1 device structure shown in the figure.

[0051] Example 3 The preparation method of the trench-type silicon carbide MOSFET device in Embodiment 1, where the P-type doped region is formed by multiple epitaxial growths, includes the following steps: Step 1: Select an N-type substrate material as the N-type drain 09 of the device. After the first growth of the N-type epitaxial layer 08, use a mask to expose the area on the epitaxial layer where the lateral P-type doped region 07c needs to be formed through photolithography. Then, implant acceptor ions on the surface of the N-type epitaxial layer 08 to form the lateral P-type doped region 07c, obtaining the device structure as shown in Figure 10 the figure; Step 2: After the second growth of the N-type epitaxial layer, use the masks of the first P-type doped region 07a and the second P-type doped region 07b to implant acceptor ions on the surface of the N-type epitaxial layer 08 to form the first P-type doped region 07a and the second P-type doped region 07b. The bottoms of the first P-type doped region 07a and the second P-type doped region 07b are connected by the lateral P-type doped region 07c. Then, grow the third epitaxial layer to obtain the device structure as shown in Figure 11 the figure; Step 3: Implant acceptor ions on the surface of the N-type epitaxial layer 08 to form the P-type body region 04, and then implant donor ions on the surface of the P-type body region 04 to form the N-type source 03, obtaining the device structure as shown in Figure 6 the figure; Step 4: Deposit the first barrier layer 11 on the N-type epitaxial layer 08. Then, use a mask to expose the area on the surface of the N-type epitaxial layer 08 where the vertical trench 06 needs to be formed through photolithography. Remove the first barrier layer 11 in the area where the vertical trench 06 is located, and further etch the silicon carbide to form the vertical trench 06, obtaining the device structure as shown in Figure 7 the figure; The first barrier layer 11 is made of a material including silicon nitride, silicon oxide compound, or polysilicon; Step 5: Grow the gate oxide layer 02b in the vertical trench 06. Then, deposit polysilicon 05 in the vertical trench 06 to form the gate. Next, remove the excess gate oxide layer and polysilicon on the surface of the N-type epitaxial layer 08, obtaining the device structure as shown in Figure 8 the figure; When forming the gate, polysilicon with a relatively high doping concentration is used, and the doping concentration range is 5.0×10 19 cm -3 ~1.0×10 21 cm -3 , aiming to facilitate obtaining a lower gate resistance; Step 6: Deposit the dielectric layer 02a on the upper surface of the N-type source 03. Then, use the mask of the P-type source 07 to etch the dielectric layer 02a downward to form a contact hole. Implant acceptor ions on the surface of the N-type epitaxial layer 08 to form the P-type source 07, obtaining the device structure as shown in Figure 9 the figure; The dielectric layer 02a is made of one of silicon oxide, nitrogen oxide, and polyimide; Step 7: Deposit metal on the upper surface of the N-type epitaxial layer 08 and the lower surface of the N-type drain 09 respectively and anneal to form the source metal 01 and drain metal 10 for ohmic contact, obtaining the final Figure 1 device structure as shown.

[0052] The process method provided by the present invention forms a P-type doped region through multiple epitaxial ion implantations. Therefore, compared with the high-energy ion implantation under single-layer epitaxial conditions, this method has lower requirements for equipment and can reduce the production cost of the device.

[0053] Example 4 A preparation method for a trench-type silicon carbide MOSFET device in Example 1 includes the following steps: (1) Select an N-type substrate material as the N-type drain 09 of the device, with a concentration range of 7.5e 18 cm -3 ~1.5e 19 cm -3 , epitaxially grow an N-type epitaxial layer 08 on the upper surface of the N-type drain 09 once, and then clean the epitaxial wafer to obtain the Figure 3 device structure as shown. The N-type substrate material is 4H-SiC, 6H-SiC, or 3C-SiC, and 4H-SiC material is preferred; (2) Use a mask plate to expose the region where the lateral P-type doped region 07c in the N-type epitaxial layer 08 is located through photolithography, form the lateral P-type doped region 07c by high-energy ion implantation of acceptor ions, and then use the mask plate to expose the region of the P-type doped region 07b in the N-type epitaxial layer 08 through photolithography, form the second P-type doped region 07b by high-energy ion implantation of acceptor ions, and obtain the Figure 12 device structure as shown after removing the mask plate; (3) Inject acceptor ions on the surface of the N-type epitaxial layer 08 to form a P-type body region 04, then inject donor ions on the surface of the N-type epitaxial layer 08 to form an N-type source 03, then deposit a first barrier layer 11 on the N-type source 03, and then use a mask plate to remove the first barrier layer 11 in the region where the vertical trench 06 is located, and further etch the silicon carbide downward to form the vertical trench 06, obtaining the Figure 13 device structure as shown. (4) Deposit a second barrier layer 12 on the surface of the N-type epitaxial layer 08. The second barrier layer 12 is made of materials such as silicon nitride, silicon oxide, or polysilicon, obtaining the Figure 14 device structure as shown. (5) The second barrier layer 12 is etched on the surface of the N-type epitaxial layer 08 by an isotropic etching method. Since it is etched isotropically downward, generally a dry etching technique is used, that is, the wafer surface is bombarded with plasma to remove the material with a specified thickness on the surface. Therefore, only a part of the outermost surface of the barrier layer on the sidewall of the trench will be etched due to its relatively thick thickness, and the barrier layer at the bottom is basically completely etched, as Figure 15 shown; (6) An acceptor ion is implanted on the surface of the N-type epitaxial layer 08 by ion implantation to form a first P-type doping region 07a, and the device structure as shown in Figure 16 is obtained; (7) The remaining first barrier layer 11 and second barrier layer 12 on the surface of the N-type epitaxial layer 08 are removed; (8) After removing the first barrier layer 11, a gate oxide layer 02b is grown in the longitudinal trench 06, then polysilicon 05 is deposited in the trench to form a gate, and then the excess oxide layer and polysilicon on the surface of the N-type epitaxial layer 08 are removed, and the device structure as shown in Figure 8 is obtained; When forming the gate, polysilicon with a relatively high doping concentration is used, and the doping concentration range is 5.0×10 19 cm -3 ~1.0×10 21 cm -3 , and the purpose is to facilitate obtaining a lower gate resistance; (9) A dielectric layer 02a is deposited on the upper surface of the N-type source 03, and then the dielectric layer 02a is etched downward using a P-type source 07 mask to form a contact hole. An acceptor ion is implanted on the surface of the N-type epitaxial layer 08 to form a P-type source 07, and the device structure as shown in Figure 9 is obtained; The dielectric layer 02a is made of one of silicon oxide, nitrogen oxide, and polyimide; (10) Metals are deposited on the upper surface of the N-type epitaxial layer 08 and the lower surface of the N-type drain 09 and annealed to form a source metal 01 and a drain metal 10 for ohmic contact, and the final device structure as shown in Figure 1 is obtained.

[0054] In this embodiment, the lateral P-type doping region and the second P-type doping region are formed together, and there is no need to use a mask to define the pattern of the first P-type doping region, and self-aligned implantation of the first P-type doping region can be realized during the process. Therefore, there is no need to consider the exposure accuracy of the photolithography mask during preparation, which effectively saves the number of photolithography masks, improves the production yield, and reduces the production cost of the device.

[0055] The present invention can provide relatively comprehensive protection for the gate oxide layer of the device. At the same time, the current path during the conduction of the structure is matched with the electric field direction, which can greatly reduce the on-resistance of the device. In addition, the structure of the laterally arranged P-type doping regions with intervals in the invention can achieve a good pinch-off effect, suppress the saturation current of the device, and improve the short-circuit and avalanche capabilities of the device. Moreover, the formation of the first P-type doping region does not require a mask, which improves the precision of the production process and reduces the process production cost.

[0056] The above describes the present invention and its implementation manners. The description is not restrictive. Only two implementation manners of the present invention are shown in the drawings, and the actual structure is not limited thereto. Generally speaking, if those of ordinary skill in the art are inspired by it and design similar structural manners and embodiments to the technical solution without creative efforts without departing from the purpose of the present invention, they shall fall within the protection scope of the present invention.

Claims

1. A trench silicon carbide MOSFET device, comprising a drain metal (10) and an N-type drain (09) located on the upper surface thereof, an N-type epitaxial layer (08) being provided on the upper surface of the N-type drain (09) as a drift region of the MOSFET, a P-type body region (04) being provided on the upper surface of the N-type epitaxial layer (08), and an N-type source (03) and a P-type source (07) being provided on the surface of the P-type body region (04), characterized in that: A longitudinal groove (06) is provided on the surface of one end of the N-type epitaxial layer (08) away from the N-type drain (09), polysilicon (05) is provided inside the longitudinal groove (06) as a gate of the MOSFET, and the periphery of the polysilicon (05) is wrapped by a gate oxide layer (02b); The implantation depth of the P-type body region (04) in the N-type epitaxial layer (08) is less than the depth of the longitudinal groove (06); a first P-type doping region (07a) is provided in the lower region of the bottom of the longitudinal groove (06); a second P-type doping region (07b) is provided in the lower region of the P-type body region (04); the first P-type doping region (07a) and the second P-type doping region (07b) extend in a direction close to the N-type drain (09) and are connected via a lateral P-type doping region (07c); source metal (01) for connecting a source signal is provided on the surfaces of the N-type source (03) and the high-concentration P-type source (07); and a dielectric layer (02a) is provided on the surface of the N-type epitaxial layer (08) except for the source metal (01).

2. The trench silicon carbide MOSFET device according to claim 1, characterized in that: The N-type source (03) is located on both sides of the longitudinal groove (06), and the P-type source (07) is interspersed between two adjacent N-type source electrodes (03).

3. The trench silicon carbide MOSFET device according to claim 1, characterized in that: The doping concentrations of the first P-type doping region (07a), the second P-type doping region (07b) and the lateral P-type doping region (07c) are all higher than the doping concentration of the P-type body region (04).

4. The trench silicon carbide MOSFET device according to claim 1, characterized in that: The first P-type doping region (07a) is arranged below the longitudinal groove (06), the upper surface of the first P-type doping region (07a) overlaps with the longitudinal groove (06), and the width of the first P-type doping region (07a) is smaller than the width of the longitudinal groove (06).

5. The trench silicon carbide MOSFET device according to claim 1, characterized in that: The second P-type doping region (07b) is arranged below the P-type body region (04), the upper surface of the second P-type doping region (07b) overlaps with the P-type body region (04), and the width of the second P-type doping region (07b) is smaller than the width of the P-type body region (04).

6. The trench silicon carbide MOSFET device according to claim 1, characterized in that: The bottoms of the first P-type doping region (07a) and the second P-type doping region (07b) are connected via a lateral P-type doping region (07c), and the lateral P-type doping regions (07c) are arranged at intervals in a direction perpendicular to the longitudinal groove (06).

7. The trench silicon carbide MOSFET device according to claim 1, characterized in that: The doping concentrations of the N-type drain (09), the N-type source (03) and the P-type source (07) are all higher than the doping concentration of the N-type epitaxial layer (08).

8. The method for preparing a trench silicon carbide MOSFET device according to any one of claims 1 to 7, characterized in that: The steps include: Step S1, selecting an N-type substrate material as an N-type drain (09) of the device, and performing single epitaxial growth of an N-type epitaxial layer (08) on the upper surface of the N-type drain (09); Step S2, using a mask of the lateral P-type doping region (07c), high-energy ion implantation of acceptor ions on the surface of the N-type epitaxial layer (08) forms a lateral P-type doping region (07c); Step S3, using a mask of a P-type doping region, high-energy ion implantation of acceptor ions on the surface of the N-type epitaxial layer (08) forms a first P-type doping region (07a) and a second P-type doping region (07b); Step S4, injecting acceptor ions into the surface of the N-type epitaxial layer (08) to form a P-type body region (04), and then injecting donor ions into the surface of the N-type epitaxial layer (08) to form an N-type source (03); Step S5, depositing a first barrier layer (11) on the N-type epitaxial layer (08), and then using a mask to remove the first barrier layer (11) in the area where the longitudinal groove (06) is located, and further forming the longitudinal groove (06); Step S6, growing a gate oxide layer (02b) in the longitudinal groove (06), then depositing polysilicon (05) in the longitudinal groove (06) to form a gate, and removing the oxide layer and polysilicon on the surface of the N-type epitaxial layer (08); Step S7, depositing a dielectric layer (02a) on the N-type epitaxial layer (08), etching downwards the dielectric layer (02a) using a P-type source (07) mask, and injecting acceptor ions into the surface of the N-type epitaxial layer (08) to form a P-type source (07); Step S8, depositing metals on the upper surface of the N-type epitaxial layer (08) and the lower surface of the N-type drain (09), respectively, and annealing to form a source metal (01) and a drain metal (10).

9. The method for preparing a trench silicon carbide MOSFET device according to any one of claims 1 to 7, characterized in that: The P-type doped region is formed by multiple epitaxy steps, including the following steps: Step 1: Select an N-type substrate material as the N-type drain (09) of the device, epitaxially grow an N-type epitaxial layer (08) for the first time, and use a mask of a lateral P-type doped region (07c) to inject acceptor ions on the surface of the N-type epitaxial layer (08) to form a lateral P-type doped region (07c); Step 2: growing the N-type epitaxial layer (08) for the second time, using the mask of the first P-type doping region (07a) and the second P-type doping region (07b), injecting acceptor ions on the surface of the N-type epitaxial layer (08) to form the first P-type doping region (07a) and the second P-type doping region (07b), and then growing the third N-type epitaxial layer (08); Step 3: injecting acceptor ions into the surface of the N-type epitaxial layer (08) to form a P-type body region (04), and then injecting donor ions into the surface of the N-type epitaxial layer (08) to form an N-type source (03); Step 4: depositing a first barrier layer (11) on the N-type epitaxial layer (08), and then using a mask to remove the first barrier layer (11) in the area where the longitudinal groove (06) is located, and further forming the longitudinal groove (06); Step 5: growing a gate oxide layer (02b) in the longitudinal groove (06), then depositing polysilicon (05) in the longitudinal groove (06) to form a gate, and removing the gate oxide layer and polysilicon on the surface of the N-type epitaxial layer (08); Step six, depositing a dielectric layer (02a) on the N-type epitaxial layer (08), etching downwards the dielectric layer (02a) using a P-type source (07) mask, and injecting acceptor ions on the surface of the N-type epitaxial layer (08) to form a P-type source (07); Step seven: depositing metals on the upper surface of the N-type epitaxial layer (08) and the lower surface of the N-type drain (09) respectively and annealing them to form a source metal (01) and a drain metal (10).

10. The method for preparing a trench silicon carbide MOSFET device according to any one of claims 1 to 7, characterized in that: The lateral P-type doping region (07c) and the second P-type doping region (07b) are formed together, and the first P-type doping region (07a) is formed by a self-alignment process, comprising the following steps: Step St1, selecting an N-type substrate material as the N-type drain of the device (09), and performing single epitaxial growth of an N-type epitaxial layer (08); Step St2, using the lateral P-type doping region (07c) and the second P-type doping region (07b) mask plates, injecting acceptor ions into the surface of the N-type epitaxial layer (08) to form the lateral P-type doping region (07c) and the second P-type doping region (07b), respectively; Step St3, injecting acceptor ions into the surface of the N-type epitaxial layer (08) to form a P-type body region (04), and then injecting donor ions into the surface of the N-type epitaxial layer (08) to form an N-type source (03); Step St4, depositing a first barrier layer (11) on the N-type epitaxial layer (08), and then using a mask to remove the first barrier layer (11) in the area where the longitudinal groove (06) is located, and further forming the longitudinal groove (06); Step St5, depositing a second barrier layer (12) on the surface of the N-type epitaxial layer (08), then etching the second barrier layer (12), etching away the second barrier layer (12) at the bottom of the longitudinal groove (06), and retaining the second barrier layer (12) on the side wall of the longitudinal groove (06); Step St6, using an ion implantation method to implant acceptor ions on the surface of the N-type epitaxial layer (08) to form a first P-type doping region (07a); Step St7, etching away the remaining first barrier layer (11) and second barrier layer (12) on the surface of the N-type epitaxial layer, and then performing high temperature annealing; Step St8, growing a gate oxide layer (02b) in the longitudinal groove (06), then depositing polysilicon (05) in the longitudinal groove (06) to form a gate, and removing the gate oxide layer and polysilicon on the surface of the N-type epitaxial layer (08); Step St9, depositing a dielectric layer (02a) on the N-type epitaxial layer (08), etching downwards the dielectric layer (02a) using a P-type source (07) mask, and injecting acceptor ions on the surface of the N-type epitaxial layer (08) to form a P-type source (07); Step St10: depositing metals on the upper surface of the N-type epitaxial layer (08) and the lower surface of the N-type drain (09) respectively and annealing them to form a source metal (01) and a drain metal (10).

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