Electrostatic protection structure and method of forming the same

Abstract

An electrostatic protection structure and a forming method thereof, the structure comprising: a substrate with a deep N-type well region; a first isolation structure located in the deep N-type well region of a PMOS region and an NMOS region and spaced apart; a P-type well region and an N-type well region located in the deep N-type well region and in the same MOS region, the P-type well region and the N-type well region being spaced apart, the N-type well region and the P-type well region of adjacent MOS regions being oppositely arranged; a gate structure located on the P-type well region and close to one side of the N-type well region of the same MOS region; a P-type source region located in the P-type well region of the PMOS region and on the side of the gate structure away from the N-type well region of the PMOS region; a P-type drain region located in the N-type well region of the PMOS region; an N-type source region located in the P-type well region of the NMOS region and on the side of the gate structure away from the N-type well region of the NMOS region; and an N-type drain region located in the N-type well region of the NMOS region. The electrostatic protection structure realizes bidirectional protection and forms a thyristor device, and the electrostatic protection performance is improved.

Description

Technical Field

[0001] This invention relates to the field of electrostatic discharge (ESD) protection manufacturing, and more particularly to an ESD protection structure and a method for forming the same. Background Technology

[0002] Since integrated circuits are susceptible to damage from static electricity, electrostatic discharge (ESD) protection circuits are commonly used in existing chip designs to reduce chip damage.

[0003] However, with the rapid growth of the integrated circuit (IC) industry, semiconductor technology, driven by Moore's Law, continues to advance towards smaller process nodes, making integrated circuits smaller, more precise, and more complex.

[0004] Therefore, the performance of existing electrostatic protection structures needs to be improved. Summary of the Invention

[0005] The problem addressed by the embodiments of the present invention is to provide an electrostatic protection structure and a method for forming the same, so as to improve the performance of the electrostatic protection structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide an electrostatic discharge (ESD) protection structure, comprising: a substrate including adjacent PMOS and NMOS regions, wherein deep N-type well regions are formed in the substrates of the PMOS and NMOS regions; a first isolation structure located in the deep N-type well regions of the PMOS and NMOS regions, and spaced apart; a P-type well region located in the deep N-type well regions of the PMOS and NMOS regions, and located on a first side of the first isolation structure, wherein the P-type well regions in the PMOS and NMOS regions are spaced apart; and an N-type well region located in the deep N-type well regions of the PMOS and NMOS regions, and located on a second side of the first isolation structure. In the adjacent PMOS and NMOS regions, the N-type well region of the PMOS region is disposed opposite to the P-type well region of the NMOS region; the gate structure is located on the P-type well regions of the PMOS and NMOS regions respectively, and is located on the side of the P-type well region that is close to the N-type well region of the same MOS region; the P-type source region is located in the P-type well region of the PMOS region, and is located on the side of the gate structure that is away from the N-type well region of the PMOS region; the P-type drain region is located in the N-type well region of the PMOS region; the N-type source region is located in the P-type well region of the NMOS region, and is located on the side of the gate structure that is away from the N-type well region of the NMOS region; the N-type drain region is located in the N-type well region of the NMOS region.

[0007] Optionally, in the adjacent PMOS and NMOS regions, the N-type well sidewall of the PMOS region is in contact with the P-type well sidewall of the NMOS region.

[0008] Optionally, the gate structure may also extend to cover the top of the adjacent first isolation structure.

[0009] Optionally, the electrostatic protection structure further includes a body region located in the deep N-type well region and surrounding the outermost periphery of the P-type well region and the N-type well region.

[0010] Optionally, the electrostatic protection structure further includes a second isolation structure located in a deep N-type well region between the body region and the adjacent well region.

[0011] Optionally, the material of the first isolation structure includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0012] Optionally, the electrostatic protection structure further includes an interconnect structure, which is electrically connected to the gate structure, the P-type source region, the P-type drain region, the N-type source region, and the N-type drain region, and applies electrical signals to each of them.

[0013] Optionally, the interconnect structure electrically connecting the P-type drain region is used to apply a negative potential, the interconnect structure electrically connecting the N-type drain region is used to apply a positive potential, and the interconnect structure electrically connecting the gate structure, the P-type source region, and the N-type source region is used to apply a zero potential.

[0014] Optionally, the interconnect structure electrically connecting the gate structure, the P-type source region, and the N-type source region is shorted.

[0015] Accordingly, embodiments of the present invention also provide a method for forming an electrostatic discharge (ESD) protection structure, comprising: providing a substrate, the substrate including adjacent PMOS regions and NMOS regions, wherein deep N-type well regions are formed in the substrate of the PMOS regions and NMOS regions; forming a first isolation structure spaced apart in the deep N-type well regions of the PMOS regions and NMOS regions; forming a P-type well region in the deep N-type well region on a first side of the first isolation structure, wherein the P-type well regions in the PMOS regions and NMOS regions are spaced apart; forming an N-type well region in the deep N-type well region on a second side of the first isolation structure, wherein in the adjacent PMOS regions and NMOS regions, the N-type well regions of the PMOS regions are disposed opposite to the P-type well regions of the NMOS regions; and forming a first isolation structure spaced apart in the deep N-type well regions of the PMOS regions and NMOS regions. Gate structures are formed on the P-type well regions of the NMOS region, and the gate structures are located on the side of the P-type well region close to the N-type well region in the same MOS region; a P-type source region is formed in the P-type well region of the PMOS region, and the sidewall of the P-type source region is spaced from the sidewall of the P-type well region in which it is located; a P-type drain region is formed in the N-type well region of the PMOS region; an N-type source region is formed in the P-type well region of the NMOS region, and the sidewall of the N-type source region is spaced from the sidewall of the P-type well region in which it is located; an N-type drain region is formed in the N-type well region of the NMOS region; wherein the P-type source region and the P-type drain region are located on both sides of the gate structure in the PMOS region, and the N-type source region and the N-type drain region are located on both sides of the gate structure in the NMOS region.

[0016] Optionally, in the step of forming the P-type well region and the N-type well region, in the adjacent PMOS region and NMOS region, the sidewall of the N-type well region of the PMOS region is in contact with the sidewall of the P-type well region of the NMOS region.

[0017] Optionally, in the step of forming the gate structure, the gate structure further extends to cover the top of the adjacent first isolation structure.

[0018] Optionally, in the step of forming the P-type source region and the P-type drain region, a body region is formed in the deep N-type well region, and the body region surrounds the outermost periphery of the P-type well region and the N-type well region.

[0019] Optionally, in the step of forming the first isolation structure, a second isolation structure spaced apart from the first isolation structure in the deep N-type well regions of the PMOS and NMOS regions is formed respectively. In the same MOS region, the second isolation structure is located on the side of the first isolation structure facing away from the other MOS region. In the step of forming the P-type well region and the N-type well region, the P-type well region and the N-type well region in the same MOS region are both located on the side of the second isolation structure facing the other MOS region. In the step of forming the P-type drain region, the P-type source region, the N-type drain region, the N-type source region, and the body region, the P-type drain region and the P-type source region are both located on the side of the second isolation structure of the PMOS region facing the NMOS region, the body region of the PMOS region is located on the other side of the second isolation structure of the PMOS region, the N-type drain region and the N-type source region are both located on the side of the second isolation structure of the NMOS region facing the PMOS region, and the body region of the NMOS region is located on the other side of the second isolation structure of the NMOS region.

[0020] Optionally, after forming the gate structure, P-type source region, P-type drain region, N-type source region, and N-type drain region, the forming method further includes: forming interconnect structures that are electrically connected to the gate structure, P-type source region, P-type drain region, N-type source region, and N-type drain region respectively and to which electrical signals are applied respectively.

[0021] Optionally, in the step of forming the interconnect structure, the interconnect structure electrically connecting the gate structure, the P-type source region, and the N-type source region is shorted.

[0022] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0023] The electrostatic discharge protection structure provided in this embodiment of the invention includes a substrate, which includes adjacent PMOS and NMOS regions. Deep N-type well regions are formed in the substrates of the PMOS and NMOS regions. P-type well regions are located in the deep N-type well regions of the PMOS and NMOS regions and are spaced apart. N-type well regions are located in the deep N-type well regions on the sides of the P-type well regions of the PMOS and NMOS regions. In the adjacent PMOS and NMOS regions, the N-type well regions of the PMOS region and the P-type well regions of the NMOS region are positioned opposite each other. A P-type source region is located in the P-type well region of the PMOS region. A P-type drain region is located in the N-type well region of the PMOS region. An N-type source region is located in the P-type well region of the NMOS region. An N-type drain region is located in the P-type well region of the NMOS region. Because the PMOS and NMOS regions have different conductive channel types, they also have different conduction characteristics. This allows the electrostatic discharge (ESD) protection structure of this embodiment to achieve bidirectional protection, thereby improving its protection capability and performance. Furthermore, in the adjacent PMOS and NMOS regions, the N-type well region of the PMOS region is positioned opposite to the P-type well region of the NMOS region. This allows the P-type drain region, the N-type well region of the PMOS region, the deep N-type well region, the P-type well region of the NMOS region, and the N-type source region to form a silicon controlled rectifier (SCR) device. When the PN junction of the deep N-type well region and the P-type well region breaks down under reverse bias, an avalanche current is generated, creating a voltage drop in the P-type well region. This causes the parasitic bipolar junction transistor (BJT) to conduct, increasing the current discharge path and thus improving the secondary breakdown current (It2) of the ESD protection structure, thereby enhancing its performance.

[0024] The method for forming an electrostatic discharge (ESD) protection structure provided in this embodiment of the invention includes a substrate comprising adjacent PMOS and NMOS regions. A deep N-type well region is formed in the substrate of the PMOS and NMOS regions. A P-type well region is formed in the deep N-type well region on a first side of the first isolation structure. The P-type well regions in the PMOS and NMOS regions are spaced apart. An N-type well region is formed in the deep N-type well region on a second side of the first isolation structure. In the adjacent PMOS and NMOS regions, the N-type well region of the PMOS region is positioned opposite to the P-type well region of the NMOS region. A P-type source region is formed in the P-type well region of the PMOS region, a P-type drain region is formed in the N-type well region of the PMOS region, an N-type source region is formed in the P-type well region of the NMOS region, and an N-type drain region is formed in the N-type well region of the NMOS region. Because the PMOS and NMOS regions have different conductive channel types, they also have different conduction characteristics. This allows the electrostatic discharge (ESD) protection structure of this embodiment to achieve bidirectional protection, thereby improving its protection capability and performance. Furthermore, in the adjacent PMOS and NMOS regions, the N-type well region of the PMOS region is positioned opposite to the P-type well region of the NMOS region. This allows the P-type drain region, the N-type well region of the PMOS region, the deep N-type well region, the P-type well region of the NMOS region, and the N-type source region to form a silicon controlled resonant device (SCR). When the PN junction of the deep N-type well region and the P-type well region breaks down under reverse bias, an avalanche current is generated, creating a voltage drop in the P-type well region. This causes the parasitic bipolar junction transistor to conduct, increasing the current discharge path and thus improving the secondary breakdown current of the ESD protection structure, thereby enhancing its performance. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of an embodiment of the electrostatic protection structure of the present invention;

[0026] Figures 2 to 6 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming the electrostatic protection structure of the present invention. Detailed Implementation

[0027] As can be seen from the background technology, the performance of current electrostatic protection structures needs to be improved.

[0028] To address the aforementioned technical problems, embodiments of the present invention provide an electrostatic discharge (ESD) protection structure, comprising: a substrate including adjacent PMOS and NMOS regions, wherein deep N-type well regions are formed in the substrate of the PMOS and NMOS regions; a first isolation structure located in the deep N-type well regions of the PMOS and NMOS regions, and spaced apart; P-type well regions located in the deep N-type well regions of the PMOS and NMOS regions, and located on a first side of the first isolation structure, wherein the P-type well regions in the PMOS and NMOS regions are spaced apart; and N-type well regions located in the deep N-type well regions of the PMOS and NMOS regions, and located on a second side of the first isolation structure. In the adjacent PMOS and NMOS regions, the N-type well region of the PMOS region is positioned opposite to the P-type well region of the NMOS region; the gate structure is located on the P-type well regions of the PMOS and NMOS regions respectively, and is located on the side of the P-type well region closer to the N-type well region of the same MOS region; the P-type source region is located in the P-type well region of the PMOS region, and is located on the side of the gate structure facing away from the N-type well region of the PMOS region; the P-type drain region is located in the N-type well region of the PMOS region; the N-type source region is located in the P-type well region of the NMOS region, and is located on the side of the gate structure facing away from the N-type well region of the NMOS region; the N-type drain region is located in the N-type well region of the NMOS region.

[0029] The electrostatic discharge protection structure provided in this embodiment of the invention includes a substrate, which includes adjacent PMOS and NMOS regions. Deep N-type well regions are formed in the substrates of the PMOS and NMOS regions. P-type well regions are located in the deep N-type well regions of the PMOS and NMOS regions and are spaced apart. N-type well regions are located in the deep N-type well regions on the sides of the P-type well regions of the PMOS and NMOS regions. In the adjacent PMOS and NMOS regions, the N-type well regions of the PMOS region and the P-type well regions of the NMOS region are positioned opposite each other. A P-type source region is located in the P-type well region of the PMOS region. A P-type drain region is located in the N-type well region of the PMOS region. An N-type source region is located in the P-type well region of the NMOS region. An N-type drain region is located in the P-type well region of the NMOS region. Because the PMOS and NMOS regions have different conductive channel types, they also have different conduction characteristics. This allows the electrostatic discharge (ESD) protection structure of this embodiment to achieve bidirectional protection, thereby improving its protection capability and performance. Furthermore, in the adjacent PMOS and NMOS regions, the N-type well region of the PMOS region is positioned opposite to the P-type well region of the NMOS region. This allows the P-type drain region, the N-type well region of the PMOS region, the deep N-type well region, the P-type well region of the NMOS region, and the N-type source region to form a silicon controlled resonant device (SCR). When the PN junction of the deep N-type well region and the P-type well region breaks down under reverse bias, an avalanche current is generated, creating a voltage drop in the P-type well region. This causes the parasitic bipolar junction transistor to conduct, increasing the current discharge path and thus improving the secondary breakdown current of the ESD protection structure, thereby enhancing its performance.

[0030] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0031] Figure 1 This is a schematic diagram of an embodiment of the electrostatic protection structure of the present invention.

[0032] refer to Figure 1In this embodiment, the electrostatic discharge (ESD) protection structure includes: a substrate 100, which includes adjacent PMOS regions 11 and NMOS regions 12, with deep N-type well regions 110 formed in the substrate 100 of the PMOS regions 11 and NMOS regions 12; a first isolation structure 111, located in the deep N-type well regions 110 of the PMOS regions 11 and NMOS regions 12, and spaced apart; a P-type well region 121, located in the PMOS regions 11 and NMOS regions 12, and located in the deep N-type well region 110 on the first side of the first isolation structure 111, with the P-type well regions 121 in the PMOS regions 11 and NMOS regions 12 spaced apart; and an N-type well region 122, located in the deep N-type well region 110 on the second side of the first isolation structure 111, and located in the adjacent PMOS regions 11 and NMOS regions 12. In regions 11 and 12, the N-type well region 122 of the PMOS region 11 is disposed opposite to the P-type well region 121 of the NMOS region 12; the gate structure 140 is located on the P-type well regions 121 of the PMOS region 11 and the NMOS region 12, respectively, and is located on the side of the P-type well region close to the N-type well region 122 of the same MOS region; the P-type source region 131 is located in the P-type well region 121 of the PMOS region 11, and is located on the side of the gate structure 140 facing away from the N-type well region 122 of the PMOS region 11; the P-type drain region 132 is located in the N-type well region 122 of the PMOS region 11; the N-type source region 135 is located in the P-type well region 121 of the NMOS region 12, and is located on the side of the gate structure 140 facing away from the N-type well region 122 of the NMOS region 12; the N-type drain region 136 is located in the N-type well region 122 of the NMOS region 12.

[0033] The substrate 100 is used to provide a process platform for the formation of electrostatic discharge protection structures.

[0034] In this embodiment, the substrate 100 is used to form a laterally diffused metal oxide semiconductor (LDMOS) transistor. Specifically, the PMOS region 11 is used to form a PLDMOS, and the NMOS region 12 is used to form an NLDMOS.

[0035] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, etc., and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc.

[0036] In this embodiment, the substrate 100 is a P-type substrate (P-sub), that is, the substrate 100 is doped with P-type ions, including B ions, Ga ions or In ions.

[0037] The deep N-well (DNW) 110 is used to isolate the P-type well 121 from the P-type substrate, and also to isolate the N-type well 122 from the P-type substrate, thereby reducing the coupling noise of the substrate 100.

[0038] The first isolation structure 111 results in a larger lateral resistance between the source and drain regions, which forces the current to move longitudinally, increases the current transmission path between the source and drain regions, and further increases the resistance between the source and drain regions, thereby reducing the discharge current and increasing the protection capability.

[0039] Here, the lateral direction refers to the direction perpendicular to the sidewall of the gate structure 140, and the longitudinal direction refers to the normal direction of the top surface of the substrate 100.

[0040] Specifically, the material of the first isolation structure 111 includes silicon oxide.

[0041] Silicon oxide is a commonly used material in semiconductor manufacturing, exhibiting high process compatibility, which helps reduce the difficulty and cost of forming the first isolation structure 111. Furthermore, silicon oxide has a low dielectric constant, resulting in better current flow along the vertical direction. In other embodiments, the material of the first isolation structure can also be other types of dielectric materials such as silicon nitride and silicon oxynitride.

[0042] In PMOS region 11, P-type well region 121 is used to withstand a large voltage division, and N-type well region 122 is used as a lateral diffusion region to form a channel with a concentration gradient. In NMOS region 12, P-type well region 121 is used as a lateral diffusion region to form a channel with a concentration gradient, and N-type well region 122 is used to withstand a large voltage division. The large voltage division of PMOS region 11's P-type well region 121 is beneficial to improving the breakdown voltage between P-type source region 131 and P-type drain region 132. Similarly, the large voltage division of NMOS region 12's N-type well region 122 is beneficial to improving the breakdown voltage between N-type source region 135 and N-type drain region 136.

[0043] In other words, the P-type well region 121 of PMOS region 11 and the N-type well region 122 of NMOS region 12 are high-resistivity regions. Moreover, typically, the P-type well region 121 of PMOS region 11 and the P-type well region 121 of NMOS region 12 are formed in the same step, and the N-type well region 122 of PMOS region 11 and the N-type well region 122 of NMOS region 12 are formed in the same step. Therefore, the doping ion concentrations of P-type well region 121 and N-type well region 122 are small. The ion doping concentration of P-type well region 121 is less than that of P-type drain region 132, and the ion doping concentration of N-type well region 122 is less than that of N-type drain region 136.

[0044] It is understood that the doped ions in the P-type well region 121 are P-type ions, such as B ions, Ga ions or In ions; and the doped ions in the N-type well region 122 are N-type ions, such as P ions, As ions or Sb ions.

[0045] P-type well region 121 is located on the first side of the first isolation structure 111, and N-type well region 122 is located on the second side of the first isolation structure 111. That is, there is a gap between N-type well region 122 and P-type well region 121 in the same MOS region.

[0046] It should be noted that the P-type well region 121 also has a first side and a second side, and the first side of the P-type well region 121 is disposed opposite to the first side of the first isolation structure 111. The N-type well region 122 also has a first side and a second side, and the second side of the N-type well region 122 is disposed opposite to the second side of the first isolation structure 111. In the adjacent PMOS region and NMOS region, the N-type well region of the PMOS region is disposed opposite to the P-type well region of the NMOS region. It can be understood that in the adjacent PMOS region and NMOS region, the first side of the N-type well region 122 is disposed opposite to the second side of the P-type well region 121.

[0047] In this embodiment, in the adjacent PMOS region 11 and NMOS region 12, the sidewall of the N-type well region 122 of the PMOS region 11 is in contact with the sidewall of the P-type well region 121 of the NMOS region 12.

[0048] The sidewall of the N-type well region 122 of the PMOS region 11 is in contact with the sidewall of the P-type well region 121 of the NMOS region 12, which helps to reduce the area of ​​the substrate 100 occupied by the PMOS region 11 and the NMOS region 12, thereby saving chip area.

[0049] The gate structure 140 is used to control the opening and closing of the channel.

[0050] The gate structures are located on the P-type well regions 121 of PMOS region 11 and NMOS region 12, respectively, so that the drain region and the gate structure 140 of the same MOS region are separated by a certain lateral distance to improve the voltage withstand performance of LDMOS transistor.

[0051] The gate structure 140 includes a gate dielectric layer (not shown) and a gate layer (not shown) covering the gate dielectric layer. In this embodiment, the gate structure 140 is a polysilicon gate structure, the gate dielectric layer is made of silicon oxide, and the gate layer is made of polysilicon. In other embodiments, the gate structure can also be a metal gate structure, the gate dielectric layer can be made of a high-k gate dielectric material, such as HfO2 or Al2O3, and the gate layer can be made of a metal, such as copper, aluminum, or tungsten.

[0052] In this embodiment, the gate structure 140 also extends to cover the top of the adjacent first isolation structure 111.

[0053] The gate structure 140 also extends to cover the top of the adjacent first isolation structure 111, which facilitates increasing the process window for forming the gate structure 140, reducing the difficulty of forming the gate structure 140, and also helps to weaken the electric field strength at the bottom corner of the gate structure 140, thereby helping to improve the breakdown voltage of the LDMOS transistor.

[0054] In this embodiment, the semiconductor structure further includes a sidewall (not shown) located on the sidewall of the gate structure 140.

[0055] The sidewalls protect the sidewalls of the gate structure 140.

[0056] It should be noted that the sidewall material can be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride.

[0057] It should also be noted that the sidewall can be a single-layer structure or a multi-layer structure.

[0058] The P-type source region 131 is used as the source terminal of the PLDMOS transistor, and the P-type drain region 132 is used as the drain terminal of the PLDMOS transistor. Accordingly, the P-type source region 131 and the P-type drain region 132 have P-type ions.

[0059] The N-type source region 135 is used as the source terminal of the NLDMOS transistor, and the N-type drain region 136 is used as the drain terminal of the NLDMOS transistor. Accordingly, the N-type source region 135 and the N-type drain region 136 have N-type ions.

[0060] In this embodiment, the electrostatic protection structure further includes a body region 133, located in the deep N-type well region 110, and surrounding the outermost periphery of the P-type well region 121 and the N-type well region 122.

[0061] The deep N-type well region 110 is externally connected via a body region 133. The ion doping type of the body region 133 is the same as that of the substrate 100. Therefore, as an example, the body region 133 is doped with P-type ions. Furthermore, the doping concentration of the body region 133 is greater than that of the deep N-type well region 110, so that the resistance of the body region 133 is lower.

[0062] In other embodiments, the body region may also be located only in the deep N-type well region, which is the outermost part of the P-type well region and the N-type well region.

[0063] In this embodiment, the electrostatic protection structure further includes a second isolation structure 112, located in a deep N-shaped well region 110 between the body region 133 and the adjacent well region.

[0064] The second isolation structure 112 is used to isolate the body region 133 from the adjacent source or drain region and to block ion diffusion.

[0065] It is understood that, within the same MOS region, both the P-type well region 121 and the N-type well region 122 are located on the side of the second isolation structure 112 facing away from the body region 133. That is, within the same MOS region, either the P-type well region 121 or the N-type well region 122 is located between the second isolation structure 112 and the first isolation structure 111. Correspondingly, the second isolation structure 112 is spaced apart from the adjacent first isolation structure 111.

[0066] Typically, the second isolation structure 112 is formed in the same step as the first isolation structure 111. Forming the second isolation structure 112 and the first isolation structure 111 in the same step helps to simplify the process flow and improve process efficiency.

[0067] Accordingly, the material of the second isolation structure 112 is the same as that of the first isolation structure 111.

[0068] In this embodiment, the electrostatic protection structure further includes an interconnect structure (not shown), which is electrically connected to the gate structure 140, the P-type source region 131, the P-type drain region 132, the N-type source region 135, and the N-type drain region 136, and applies electrical signals to them respectively.

[0069] The interconnect structure is electrically connected to the gate structure 140, the P-type source region 131, the P-type drain region 132, the N-type source region 135, and the N-type drain region 136, respectively, so as to apply electrical signals to the gate structure 140, the P-type source region 131, the P-type drain region 132, the N-type source region 135, and the N-type drain region through the interconnect structure.

[0070] It should be noted that the interconnect structure electrically connecting the P-type drain region 132 is used to apply a negative potential, the interconnect structure electrically connecting the N-type drain region 136 is used to apply a positive potential, and the interconnect structure electrically connecting the gate structure 140, the P-type source region 131, and the N-type source region 135 is used to apply a zero potential.

[0071] In other words, the interconnect structure electrically connected to the P-type source region 131 is used as the anode of the PMOS region 11, and the interconnect structure electrically connected to the P-type drain region 132 is used as the cathode of the PMOS region 11; the interconnect structure electrically connected to the N-type drain region 136 is used as the anode of the NMOS region 12, and the interconnect structure electrically connected to the N-type source region 135 is used as the cathode of the NMOS region 12.

[0072] Depending on the application, a zero potential can be applied to the gate structure 140 of the PMOS region 11 and NMOS region 12, or a non-zero potential can be applied to the gate structure 140 of the PMOS region 11 and NMOS region 12.

[0073] It should also be noted that the interconnect structure electrically connecting the gate structure 140, the P-type source region 131, and the N-type source region 135 is shorted.

[0074] Shorting the interconnect structure that electrically connects the gate structure 140, the P-type source region 131, and the N-type source region 135 makes it easier to increase the process window of the interconnect structure that electrically connects the gate structure 140, the P-type source region 131, and the N-type source region 135, thus reducing the process difficulty.

[0075] Specifically, the interconnect structure is made of a conductive material, such as copper.

[0076] In this embodiment, the electrostatic protection structure further includes: plugs (not shown), which are electrically connected to the gate structure 140, the P-type source region 131, the P-type drain region 132, the N-type source region 135, and the N-type drain region 136, respectively, so that each of the interconnect structures is electrically connected to the gate structure 140, the P-type source region 131, the P-type drain region 132, the N-type source region 135, and the N-type drain region 136 through the plugs.

[0077] Specifically, the plug is also made of a conductive material, such as tungsten, cobalt, ruthenium, etc.

[0078] Accordingly, the present invention also provides a method for forming an electrostatic protection structure. Figures 2 to 6 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming the electrostatic protection structure of the present invention.

[0079] refer to Figure 2 A substrate 500 is provided, the substrate 500 including a PMOS region 51 and an NMOS region 52 disposed adjacently, and a deep N-type well region 510 is formed in the substrate 500 of the PMOS region 51 and the NMOS region 52.

[0080] The substrate 500 is used to provide a process platform for the formation of electrostatic discharge protection structures.

[0081] In this embodiment, the substrate 500 is used to form a laterally diffused metal-oxide-semiconductor transistor. Specifically, the PMOS region 51 is used to form a PLDMOS, and the NMOS region 52 is used to form an NLDMOS.

[0082] In this embodiment, the substrate 500 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, etc., and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc.

[0083] In this embodiment, the substrate 500 is a P-type substrate, that is, the substrate 500 is doped with P-type ions, including B ions, Ga ions or In ions.

[0084] The deep N-type well region 510 is used to isolate the P-type well region from the P-type substrate, and also to isolate the N-type well region from the P-type substrate, thereby reducing the coupling noise of the substrate 500.

[0085] refer to Figure 3 A first isolation structure 511 is formed in the deep N-type well region 510 of the PMOS region 51 and the NMOS region 52, with spacing provided.

[0086] In the subsequent steps of forming the P-type well region and the N-type well region, in the same MOS region, the adjacent P-type well regions and N-type well regions are located on both sides of the same first isolation structure 511, which results in a larger lateral resistance between the subsequently formed source region and drain region. This forces the current to move vertically, increases the current transmission path between the source region and drain region, and further increases the resistance between the source region and drain region, thereby reducing the discharge current and increasing the protection capability.

[0087] Here, the horizontal direction refers to the direction perpendicular to the sidewall of the gate structure, and the vertical direction refers to the normal direction of the top surface of the substrate 500.

[0088] In this embodiment, a first isolation structure 511 is formed before the P-type well region and the N-type well region are formed, thereby facilitating the definition of the positions of the P-type well region and the N-type well region. In other embodiments, the first isolation structure may also be formed after the P-type well region and the N-type well region are formed.

[0089] Specifically, the material of the first isolation structure 511 includes silicon oxide.

[0090] Silicon oxide is a commonly used material in semiconductor manufacturing, exhibiting high process compatibility, which helps reduce the difficulty and cost of forming the first isolation structure 511. Furthermore, silicon oxide has a low dielectric constant, resulting in better current flow along the vertical direction. In other embodiments, the material of the first isolation structure can also be other types of dielectric materials such as silicon nitride and silicon oxynitride.

[0091] In this embodiment, during the step of forming the first isolation structure 511, a second isolation structure 512 is formed in the deep N-type well region 510 of the PMOS region 51 and the NMOS region 52, respectively, which is spaced apart from the first isolation structure 511 in the same MOS region. In the same MOS region, the second isolation structure 512 is located on the side of the first isolation structure 511 facing away from the other MOS region.

[0092] The second isolation structure 512 is used to isolate the subsequently formed body region from the adjacent source or drain region and to block ion diffusion.

[0093] In the subsequent steps of forming the P-type well region and the N-type well region, within the same MOS region, both the P-type well region and the N-type well region are located on the side of the second isolation structure 512 facing away from the body region. That is, the P-type well region and the N-type well region of the same MOS region are both located in the deep N-type well region of the second isolation structure 512 facing the other MOS region. Furthermore, a P-type well region is subsequently formed on the first side of the first isolation structure 511, and an N-type well region is formed on the second side of the first isolation structure 511. In other words, within the same MOS region, either the P-type well region or the N-type well region is located between the second isolation structure 512 and the first isolation structure 511. Correspondingly, in the step of forming the second isolation structure 512, within the same MOS region, the second isolation structure 512 is spaced apart from the adjacent first isolation structure 511.

[0094] The second isolation structure 512 is formed in the same step as the first isolation structure 511, which helps to simplify the process flow and improve process efficiency.

[0095] Accordingly, the material of the second isolation structure 512 is the same as that of the first isolation structure 511.

[0096] In other embodiments, the second isolation structure may also be formed in a different step from the first isolation structure.

[0097] refer to Figure 4 A P-type well region 521 is formed in the deep N-type well region 510 on the first side of the first isolation structure 511, and the P-type well regions 521 in the PMOS region 51 and the NMOS region 52 are spaced apart; an N-type well region 522 is formed in the deep N-type well region 510 on the second side of the first isolation structure 511, and in the adjacent PMOS region 51 and NMOS region 52, the N-type well region 522 of the PMOS region 51 is arranged opposite to the P-type well region 521 of the NMOS region 52.

[0098] In PMOS region 51, P-type well region 521 is used to withstand a large voltage division, and N-type well region 522 is used as a lateral diffusion region to form a channel with a concentration gradient. In NMOS region 52, P-type well region 521 is used as a lateral diffusion region to form a channel with a concentration gradient, and N-type well region 522 is used to withstand a large voltage division. The large voltage division of PMOS region 51's P-type well region 521 is beneficial to improving the breakdown voltage between the subsequently formed P-type source and P-type drain regions. Similarly, the large voltage division of NMOS region 52's N-type well region 522 is beneficial to improving the breakdown voltage between the subsequently formed N-type source and N-type drain regions.

[0099] In other words, the P-type well region 521 of PMOS region 51 and the N-type well region 522 of NMOS region 52 are high-resistivity regions. Moreover, in the same step, the P-type well region 521 of PMOS region 51 and the P-type well region 521 of NMOS region 52 are formed, and in the same step, the N-type well region 522 of PMOS region 51 and the N-type well region 522 of NMOS region 52 are formed. Therefore, the doping ion concentrations of P-type well region 521 and N-type well region 522 are small. The ion doping concentration of P-type well region 521 is less than the doping ion concentration of the subsequently formed P-type drain region, and the ion doping concentration of N-type well region 522 is less than the doping ion concentration of the subsequently formed N-type drain region.

[0100] It is understandable that the doped ions in the P-type well region 521 are P-type ions, such as B ions, Ga ions or In ions; and the doped ions in the N-type well region 522 are N-type ions, such as P ions, As ions or Sb ions.

[0101] The P-type well region 521 is located on the first side of the first isolation structure 511, and the N-type well region 522 is located on the second side of the first isolation structure 511. That is, there is a gap between the N-type well region 522 and the P-type well region 521 in the same MOS region.

[0102] It should be noted that the P-type well region 521 also has a first side and a second side. The first side of the P-type well region 521 is disposed opposite to the first side of the first isolation structure 511. The N-type well region 522 also has a first side and a second side. The second side of the N-type well region 522 is disposed opposite to the second side of the first isolation structure 511. In the adjacent PMOS region and NMOS region, the N-type well region of the PMOS region is disposed opposite to the P-type well region of the NMOS region. It can be understood that in the adjacent PMOS region and NMOS region, the first side of the N-type well region 522 is disposed opposite to the second side of the P-type well region 521.

[0103] Specifically, using a photomask and different ion implantation processes, the deep N-type well region 510 in a specific area is doped to form the P-type well region 521 and the N-type well region 522 in the deep N-type well region 510 of the PMOS region 51, and the P-type well region 521 and the N-type well region 522 in the deep N-type well region 510 of the NMOS region 52.

[0104] Alternatively, the P-type well region 521 can be formed first, followed by the N-type well region 522; or the N-type well region 522 can be formed first, followed by the P-type well region 521.

[0105] In this embodiment, during the steps of the P-type well region 521 and the N-type well region 522, in the adjacent PMOS region 51 and NMOS region 52, the sidewall of the N-type well region 522 of the PMOS region 51 is in contact with the sidewall of the P-type well region 521 of the NMOS region 52.

[0106] The sidewall of the N-type well region 522 of the PMOS region 51 is in contact with the sidewall of the P-type well region 521 of the NMOS region 52, which helps to reduce the area of ​​the substrate 500 occupied by the PMOS region 51 and the NMOS region 52, thereby saving chip area.

[0107] Accordingly, in this embodiment, during the steps of forming the P-type well region 521 and the N-type well region 522, the P-type well region 521 and the N-type well region 522 of the same MOS region are both located on the side of the second isolation structure 512 facing the other MOS region.

[0108] refer to Figure 5 Gate structures 540 are formed on the P-type well regions 521 of the PMOS region 51 and the NMOS region 52, respectively, and the gate structures 540 are located on the side of the P-type well region 521 close to the N-type well region 522 in the same MOS region.

[0109] The gate structure 540 is used to control the opening and closing of the channel.

[0110] Gate structures 540 are formed on the P-type well regions 521 of the PMOS region 51 and NMOS region 52, respectively, so that the drain region formed subsequently and the gate structure 540 of the same MOS region are separated by a certain lateral distance to improve the voltage withstand performance of the LDMOS transistor.

[0111] It should be noted that the P-type source region, P-type drain region, N-type source region, and N-type drain region can be formed after the gate structure 540 is formed; or the gate structure 540 can be formed after the P-type source region, P-type drain region, N-type source region, and N-type drain region are formed.

[0112] The gate structure 540 includes a gate dielectric layer (not shown) and a gate layer (not shown) covering the gate dielectric layer. In this embodiment, the gate structure 540 is a polysilicon gate structure, the gate dielectric layer is made of silicon oxide, and the gate layer is made of polysilicon. In other embodiments, the gate structure can also be a metal gate structure, the gate dielectric layer can be made of a high-k gate dielectric material, such as HfO2 or Al2O3, and the gate layer can be made of a metal, such as copper, aluminum, or tungsten.

[0113] In this embodiment, during the step of forming the gate structure 540, the gate structure 540 further extends to cover the top of the adjacent first isolation structure 511.

[0114] The gate structure 540 also extends and covers the top of the adjacent first isolation structure 511, which facilitates increasing the process window for forming the gate structure 540, reducing the difficulty of forming the gate structure 540, and also helps to weaken the electric field strength at the bottom corner of the gate structure 540, thereby helping to improve the breakdown voltage of the LDMOS transistor.

[0115] In this embodiment, after forming the gate structure 540, the method further includes forming a sidewall (not shown) on the sidewall of the gate structure 540.

[0116] The sidewalls protect the sidewalls of the gate structure 540.

[0117] It should be noted that the sidewall material can be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride.

[0118] It should also be noted that the sidewall can be a single-layer structure or a multi-layer structure.

[0119] refer to Figure 6A P-type source region 531 is formed in the P-type well region 521 of the PMOS region 51, and there is a gap between the sidewall of the P-type source region 531 and the sidewall of the P-type well region 521. A P-type drain region 532 is formed in the N-type well region 522 of the PMOS region 51. An N-type source region 535 is formed in the P-type well region 521 of the NMOS region 52, and there is a gap between the sidewall of the N-type source region 535 and the sidewall of the P-type well region 521. An N-type drain region 536 is formed in the N-type well region 522 of the NMOS region 52.

[0120] The P-type source region 531 is used as the source terminal of the PLDMOS transistor, and the P-type drain region 532 is used as the drain terminal of the PLDMOS transistor. Accordingly, the P-type source region 531 and the P-type drain region 532 have P-type ions.

[0121] The N-type source region 535 is used as the source terminal of the NLDMOS transistor, and the N-type drain region 536 is used as the drain terminal of the NLDMOS transistor. Accordingly, the N-type source region 535 and the N-type drain region 536 have N-type ions.

[0122] The gate structure 540 is located on the P-type well region 521 of the PMOS region 51 and the NMOS region 52, respectively, which makes it easy for the sidewall of the P-type source region 531 to be spaced with the sidewall of the P-type well region 521, and the sidewall of the N-type source region 535 to be spaced with the sidewall of the P-type well region 521.

[0123] Specifically, using a photomask and employing an ion implantation process, the P-type well region 521 and N-type well region 522 of the PMOS region 51, and the P-type well region 521 and N-type well region 522 of the NMOS region 52 are doped to form the P-type source region 531, P-type drain region 532, N-type source region 535, and N-type drain region 536.

[0124] It should be noted that the P-type source region 531 and P-type drain region 532 can be formed first, and then the N-type source region 535 and N-type drain region 536 can be formed; or the N-type source region 535 and N-type drain region 536 can be formed first, and then the P-type source region 531 and P-type drain region 532 can be formed.

[0125] In this embodiment, during the steps of forming the P-type source region 531 and the P-type drain region, a body region 533 is formed in the deep N-type well region 510, and the body region 533 surrounds the outermost periphery of the P-type well region and the N-type well region.

[0126] The deep N-type well region 510 is externally connected via a body region 533. The ion doping type of the body region 533 is the same as that of the substrate 500. Therefore, as an example, the body region 533 is doped with P-type ions. Furthermore, the doping concentration of the body region 533 is greater than that of the deep N-type well region 510, so as to reduce the resistance of the body region 533.

[0127] In other embodiments, the body region may also be located only in the deep N-type well region, which is the outermost part of the P-type well region and the N-type well region.

[0128] Correspondingly, a photomask is used to dope the deep N-type well region 510 by ion implantation to form the body region 533.

[0129] In other embodiments, the body region 533 may also be formed by a separate step.

[0130] Accordingly, in this embodiment, in the steps of forming the P-type drain region 532, P-type source region 531, N-type drain region 536, N-type source region 535 and body region 533, the P-type drain region 532 and P-type source region 531 are both located on the side of the second isolation structure 512 of the PMOS region 51 facing the NMOS region 52, the body region 533 of the PMOS region 51 is located on the other side of the second isolation structure 512 of the PMOS region 51, the N-type drain region 536 and N-type source region 535 are both located on the side of the second isolation structure 512 of the NMOS region 52 facing the PMOS region 51, and the body region 533 of the NMOS region 52 is located on the other side of the second isolation structure 512 of the NMOS region 52.

[0131] In this embodiment, after forming the gate structure 540, P-type source region 531, P-type drain region 532, N-type source region 535, and N-type drain region 536, the forming method further includes: forming interconnect structures (not shown) that are electrically connected to the gate structure 540, P-type source region 531, P-type drain region 532, N-type source region 535, and N-type drain region 536 respectively and to which electrical signals are applied respectively.

[0132] The interconnect structure is electrically connected to the gate structure 540, the P-type source region 531, the P-type drain region 532, the N-type source region 535, and the N-type drain region 536, respectively, so as to facilitate the application of electrical signals to the gate structure 540, the P-type source region 531, the P-type drain region 532, the N-type source region 535, and the N-type drain region through the interconnect structure.

[0133] It should be noted that the interconnect structure electrically connecting the P-type drain region 532 is used to apply a negative potential, the interconnect structure electrically connecting the N-type drain region 536 is used to apply a positive potential, and the interconnect structure electrically connecting the gate structure 540, the P-type source region 531, and the N-type source region 535 is used to apply a zero potential.

[0134] In other words, the interconnect structure electrically connected to the P-type source region 531 is used as the anode of the PMOS region 51, and the interconnect structure electrically connected to the P-type drain region 532 is used as the cathode of the PMOS region 51; the interconnect structure electrically connected to the N-type drain region 536 is used as the anode of the NMOS region 52, and the interconnect structure electrically connected to the N-type source region 535 is used as the cathode of the NMOS region 52.

[0135] Depending on the application, a zero potential can be applied to the gate structure 540 of the PMOS region 51 and the NMOS region 52, or a non-zero potential can be applied to the gate structure 540 of the PMOS region 51 and the NMOS region 52.

[0136] It should also be noted that, in the step of forming the interconnect structure, the interconnect structure electrically connecting the gate structure 540, the P-type source region 531, and the N-type source region 535 is shorted.

[0137] Shorting the interconnect structure that electrically connects the gate structure 540, the P-type source region 531, and the N-type source region 535 makes it easier to increase the process window of the interconnect structure that electrically connects the gate structure 540, the P-type source region 531, and the N-type source region 535, thereby reducing the process difficulty.

[0138] Specifically, the interconnect structure is made of a conductive material, such as copper.

[0139] In this embodiment, after forming the gate structure 540 and before forming the interconnect structure, the method further includes: forming plugs (not shown) that are electrically connected to the gate structure 540, the P-type source region 531, the P-type drain region 532, the N-type source region 535, and the N-type drain region 536 respectively, and each of the interconnect structures is electrically connected to the gate structure 540, the P-type source region 531, the P-type drain region 532, the N-type source region 535, and the N-type drain region 536 respectively through each of the plugs.

[0140] Specifically, the plug is also made of a conductive material, such as tungsten, cobalt, ruthenium, etc.

[0141] It should be noted that the electrostatic protection structure can be formed using the forming method described in the foregoing embodiments, or it can be formed using other forming methods. For a detailed description of the electrostatic protection structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0142] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An electrostatic protection structure, characterized by, include: The substrate includes adjacent PMOS and NMOS regions, and deep N-type well regions are formed in the substrate of the PMOS and NMOS regions. The first isolation structure is located in the deep N-type well regions of the PMOS region and the NMOS region respectively, and is arranged at intervals; The P-type well regions are located in the PMOS region and the NMOS region respectively, and are located in the deep N-type well region on the first side of the first isolation structure. The P-type well regions in the PMOS region and the NMOS region are spaced apart. The N-type well region is located in the PMOS region and the NMOS region respectively, and is located in the deep N-type well region on the second side of the first isolation structure. In the adjacent PMOS region and NMOS region, the N-type well region of the PMOS region is arranged opposite to the P-type well region of the NMOS region. The gate structure is located on the P-type well regions of the PMOS region and the NMOS region, respectively, and is located on the side of the P-type well region that is close to the N-type well region of the same MOS region. The P-type source region is located in the P-type well region of the PMOS region and is located on the side of the gate structure opposite to the N-type well region of the PMOS region. The P-type drain region is located in the N-type well region of the PMOS region; The N-type source region is located in the P-type well region of the NMOS region and is located on the side of the gate structure opposite to the N-type well region of the NMOS region; The N-type drain region is located in the N-type well region of the NMOS region.

2. The electrostatic protection structure of claim 1, wherein, In the adjacent PMOS and NMOS regions, the sidewall of the N-type well region of the PMOS region is in contact with the sidewall of the P-type well region of the NMOS region.

3. The electrostatic protection structure of claim 1 or 2, wherein, The gate structure also extends to cover the top of the adjacent first isolation structure.

4. The electrostatic protection structure of claim 1, wherein, The electrostatic protection structure further includes a body region located within the deep N-type well region and surrounding the outermost periphery of the P-type well region and the N-type well region.

5. The electrostatic protection structure of claim 4, wherein, The electrostatic protection structure further includes a second isolation structure located in a deep N-type well region between the body region and the adjacent well region.

6. The electrostatic protection structure of claim 1, wherein, The material of the first isolation structure includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

7. The electrostatic protection structure of claim 1, wherein, The electrostatic protection structure further includes an interconnection structure, which is electrically connected to the gate structure, the P-type source region, the P-type drain region, the N-type source region, and the N-type drain region, and applies electrical signals to each of them.

8. The electrostatic protection structure of claim 7, wherein, An interconnect structure electrically connecting the P-type drain region is used to apply a negative potential, an interconnect structure electrically connecting the N-type drain region is used to apply a positive potential, and an interconnect structure electrically connecting the gate structure, the P-type source region, and the N-type source region is used to apply a zero potential.

9. The electrostatic protection structure of claim 8, wherein, The interconnect structure electrically connecting the gate structure, the P-type source region, and the N-type source region is shorted.

10. A method of forming an electrostatic protection structure, comprising: include: A substrate is provided, the substrate comprising a PMOS region and an NMOS region disposed adjacently, wherein a deep N-type well region is formed in the substrate of the PMOS region and the NMOS region; A first isolation structure is formed at intervals in the deep N-type well regions of the PMOS and NMOS regions; A P-type well region is formed in the deep N-type well region on the first side of the first isolation structure, and the P-type well regions in the PMOS region and the NMOS region are spaced apart; forming an N-type well region in a deep N-type well region on a second side of the first isolation structure, and the N-type well region of the PMOS region is located opposite to the P-type well region of the NMOS region; forming a gate structure on the P-type well region of the PMOS region and the NMOS region respectively, and the gate structure is located on a side of the P-type well region close to the N-type well region in the same MOS region; forming a P-type source region in the P-type well region of the PMOS region, and a space is formed between a side wall of the P-type source region and a side wall of the P-type well region where the P-type source region is located, and forming a P-type drain region in the N-type well region of the PMOS region; forming an N-type source region in the P-type well region of the NMOS region, and a space is formed between a side wall of the N-type source region and a side wall of the P-type well region where the N-type source region is located, and forming an N-type drain region in the N-type well region of the NMOS region; wherein the P-type source region and the P-type drain region are located on both sides of the gate structure in the PMOS region, and the N-type source region and the N-type drain region are located on both sides of the gate structure in the NMOS region.

11. The method for forming the electrostatic protection structure as described in claim 10, characterized in that, In the step of forming the P-type well region and the N-type well region, in the adjacently arranged PMOS region and NMOS region, the side wall of the N-type well region of the PMOS region is in contact with the side wall of the P-type well region of the NMOS region.

12. The method for forming the electrostatic protection structure as described in claim 10, characterized in that, In the step of forming the gate structure, the gate structure also extends to cover the top of the adjacent first isolation structure.

13. The method for forming the electrostatic protection structure as described in claim 10, characterized in that, In the step of forming the P-type source region and the P-type drain region, a body region is formed in the deep N-type well region, and the body region surrounds the outermost periphery of the P-type well region and the N-type well region.

14. The method for forming the electrostatic protection structure as described in claim 13, characterized in that, In the step of forming the first isolation structure, a second isolation structure is formed in the deep N-type well region of the PMOS region and the NMOS region respectively, and the second isolation structure has a space with the first isolation structure in the same MOS region, and in the same MOS region, the second isolation structure is located on a side of the first isolation structure away from the other MOS region; In the step of forming the P-type well region and the N-type well region, the P-type well region and the N-type well region of the same MOS region are both located on a side of the second isolation structure facing the other MOS region; In the step of forming the P-type drain region, the P-type source region, the N-type drain region, the N-type source region and the body region, the P-type drain region and the P-type source region are both located on a side of the second isolation structure of the PMOS region facing the NMOS region, the body region of the PMOS region is located on the other side of the second isolation structure of the PMOS region, the N-type drain region and the N-type source region are both located on a side of the second isolation structure of the NMOS region facing the PMOS region, and the body region of the NMOS region is located on the other side of the second isolation structure of the NMOS region.

15. The method for forming the electrostatic protection structure as described in claim 10, characterized in that, After the gate structure, the P-type source region, the P-type drain region, the N-type source region and the N-type drain region are formed, the forming method further comprises: forming an interconnection structure electrically connected with the gate structure, the P-type source region, the P-type drain region, the N-type source region and the N-type drain region respectively and applying an electrical signal to them respectively.

16. The method for forming the electrostatic protection structure as described in claim 15, characterized in that, In the step of forming the interconnection structure, the interconnection structure short-circuits the gate structure, the P-type source region, and the N-type source region electrically. In the step of forming the interconnection structure, the interconnection structure short-circuits the gate structure, the P-type source region, and the N-type source region electrically.

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