Back contact photovoltaic cell and method of making same, cell assembly

Abstract

The application discloses a back contact photovoltaic cell and a preparation method and a battery assembly thereof, and relates to the technical field of photovoltaic cells. The application discloses a back contact photovoltaic cell and a preparation method and a battery assembly thereof, and relates to the technical field of photovoltaic cells. The application discloses a back contact photovoltaic cell and a preparation method and a battery assembly thereof, and relates to the technical field of photovoltaic cells. The preparation method of the back contact photovoltaic cell comprises the following steps: a silicon base is used to prepare a first oxide layer, a first intrinsic crystalline silicon layer, a second oxide layer and a second intrinsic crystalline silicon layer which are arranged in a stack from inside to outside, and the first oxide layer is a tunneling oxide layer. The second intrinsic crystalline silicon layer is doped to form a first doped oxide layer. The first doped oxide layer of at least a second polarity region is removed by laser. The second intrinsic crystalline silicon layer and the second oxide layer of at least the second polarity region are removed. A first doped crystalline silicon layer is formed on the inner side of the first doped oxide layer in the first polarity region. A second doped oxide layer is prepared on the outer side of the first intrinsic crystalline silicon layer in the second polarity region, and a doping source of the second doped oxide layer is pushed into the first intrinsic crystalline silicon layer to form a second doped crystalline silicon layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of photovoltaic cells, in particular to a back contact photovoltaic cell and a preparation method and a cell module thereof. BACKGROUND

[0002] The back contact photovoltaic cell refers to a photovoltaic cell in which the emitter and the metal contact are both located on the back surface of the cell, and the front surface is not blocked by the metal electrode. Compared with the photovoltaic cell with a blocked front surface, the back contact photovoltaic cell has a larger light receiving area, thereby reducing light loss and improving photoelectric conversion efficiency.

[0003] However, due to the poor passivation contact performance of the back contact photovoltaic cell, the passivation contact performance of the back contact photovoltaic cell needs to be optimized by a tunnel oxide passivation contact technology to further improve the photoelectric conversion efficiency.

[0004] Therefore, due to the fact that the primary electrode and the secondary electrode are both located on the back surface of the cell, the back surface of the cell is alternately provided with two different types of doped regions, and the back surface of the cell is further provided with a complex structure such as a tunnel oxide layer, the preparation process of the back contact photovoltaic cell using the tunnel oxide passivation contact technology is relatively complex. SUMMARY

[0005] Therefore, the present application provides a back contact photovoltaic cell and a preparation method and a cell module thereof to solve the problem of complex preparation process of the back contact photovoltaic cell.

[0006] In a first aspect, the present application provides a preparation method of a back contact photovoltaic cell, comprising:

[0007] providing a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged oppositely, the first surface comprising a first polarity region and a second polarity region.

[0008] At least on the first surface, a first oxide layer, a first intrinsic crystalline silicon layer, a second oxide layer and a second intrinsic crystalline silicon layer are prepared from inside to outside, and the first oxide layer is a tunnel oxide layer.

[0009] The second intrinsic crystalline silicon layer of the first surface is doped, and a first doped oxide layer is formed outside the doped second intrinsic crystalline silicon layer.

[0010] The first doped oxide layer of at least the second polarity region is removed by laser.

[0011] The second intrinsic crystalline silicon layer and the second oxide layer of at least the second polarity region are removed.

[0012] The first doped silicon layer is formed on the inner side of the first doped oxide layer in the first polarity region. The second doped oxide layer is prepared on the outer side of the first intrinsic silicon layer in the second polarity region, and the doping source of the second doped oxide layer is pushed to the first intrinsic silicon layer to form the second doped silicon layer. The doping type of the first doped silicon layer is opposite to the doping type of the second doped silicon layer.

[0013] Beneficial effects: Through the above preparation steps, the photovoltaic cell structure including the tunneling oxide layer (i.e., the first oxide layer), the first doped silicon layer, and the second doped silicon layer can be formed on the first surface of the silicon substrate as the basic structure of the photovoltaic cell including the tunneling oxide layer passivation contact technology and the full back electrode contact technology. The ultra-thin oxide layer and the doped polysilicon layer can be deposited on the surface of the silicon wafer to achieve high-efficiency passivation, thereby significantly reducing the recombination of carriers on the surface, improving the open-circuit voltage and the fill factor. The front surface (i.e., the second surface) of the photovoltaic cell is not blocked by the electrode, thereby maximizing the use of the illumination area and reducing the optical loss. The photovoltaic cell has the advantages of high conversion efficiency, low temperature coefficient, long service life, and low attenuation.

[0014] Compared with the preparation steps in the related art, the second oxide layer and the second intrinsic silicon layer of the outer layer are at least partially used as a sacrificial layer, and the first doped oxide layer is used as an etching stop layer to realize the preparation of the first doped silicon layer and the second doped silicon layer by twice doping. In this way, the first oxide layer, the first intrinsic silicon layer, the second oxide layer, and the second intrinsic silicon layer can be formed only in the film layer deposition process, and the film layer deposition process for preparing the first doped silicon layer and the second doped silicon layer does not need to be performed in multiple steps. This is conducive to simplifying the preparation process of the overall process and shortening the overall process time, and can also avoid the problem of electric leakage caused by the secondary deposition and stacking of the film layer.

[0015] In a second aspect, the present application provides a back contact photovoltaic cell prepared by the preparation method in the first aspect.

[0016] Beneficial effects: Since the back contact photovoltaic cell in the second aspect is prepared by the preparation method of the back contact photovoltaic cell in the first aspect, the back contact photovoltaic cell has all the beneficial effects of the preparation method of the back contact photovoltaic cell, which will not be repeated here.

[0017] In a third aspect, the present application provides a cell assembly including a plurality of back contact photovoltaic cells in the second aspect, and the plurality of back contact photovoltaic cells are electrically connected.

[0018] Beneficial effects: Since the photovoltaic assembly in the third aspect includes the back contact photovoltaic cell in the second aspect, the photovoltaic assembly has all the beneficial effects of the back contact photovoltaic cell, which will not be repeated here. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the disclosed drawings without creative effort.

[0020] Figure 1 This is a first part of the flowchart of the method for preparing a back-contact photovoltaic cell provided in the embodiments of this application;

[0021] Figure 2 This is a partial structural cross-sectional schematic diagram of the fabrication process of the back-contact photovoltaic cell provided in the embodiments of this application;

[0022] Figure 3 This is a partial cross-sectional structural schematic diagram obtained after step S400 processing in the embodiments of this application;

[0023] Figure 4 This is a partial cross-sectional structural schematic diagram obtained after step S500 processing in the embodiments of this application;

[0024] Figure 5 A partial cross-sectional structural schematic diagram obtained after step S600 processing in the embodiments of this application;

[0025] Figure 6 This is a second part of the flowchart illustrating the method for preparing a back-contact photovoltaic cell according to an embodiment of this application.

[0026] Figure 7 This is a partial cross-sectional structural schematic diagram obtained after step S700 processing in the embodiments of this application;

[0027] Figure 8 A partial cross-sectional structural schematic diagram obtained after steps S810 to S830 in the embodiments of this application;

[0028] Figure 9 This is a partial cross-sectional structural schematic diagram obtained after step S910 processing in the embodiments of this application;

[0029] Figure 10 A partial cross-sectional structural schematic diagram obtained after step S920 processing in the embodiments of this application;

[0030] Figure 11 A partial cross-sectional structural schematic diagram obtained after step S300 processing in the embodiments of this application;

[0031] Figure 12A flow chart of step S600 of the method for manufacturing the back contact photovoltaic cell provided in the embodiments of the present application is shown in FIG. 6.

[0032] Figure 13 Another partial cross-sectional structure schematic diagram of the back contact photovoltaic cell provided in the embodiments of the present application after step S600 is shown in FIG. 7.

[0033] Figure 14 Another partial cross-sectional structure schematic diagram of the back contact photovoltaic cell provided in the embodiments of the present application after step S810 to step S830 is shown in FIG. 8.

[0034] Figure 15 Another partial cross-sectional structure schematic diagram of the back contact photovoltaic cell provided in the embodiments of the present application after step S920 is shown in FIG. 9.

[0035] Figure 16 A cross-sectional structure schematic diagram of the photovoltaic module provided in the embodiments of the present application is shown in FIG. 10.

[0036] Legend of reference signs:

[0037] 1000, photovoltaic module;

[0038] 100, back contact photovoltaic cell;

[0039] 1, silicon substrate; 2, first oxide layer; 3, first intrinsic crystalline silicon layer; 4, second oxide layer; 5, second intrinsic crystalline silicon layer; 6, first doped oxide layer; 7, second doped oxide layer; 8, first doped crystalline silicon layer; 9, second doped crystalline silicon layer; 10, passivation film; 11, anti-reflection film; 12, first electrode; 13, second electrode. DETAILED DESCRIPTION

[0040] In order to make the purpose and embodiments of the present application more clear, the following will combine the drawings in the exemplary embodiments of the present application to make a clear and complete description of the exemplary embodiments of the present application.

[0041] It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs.

[0042] It should be noted that the terms used herein are only for the purpose of describing the specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise, and furthermore, it should be understood that when the terms "comprise" and / or "include" are used in the specification, there is a presence of the features, steps, operations, devices, components and / or combinations thereof.

[0043] It should be noted that the terms "first", "second" and the like in the description and in the claims of the present application and the above-described accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular sequential or chronological order. It should be understood that the data thus used can be interchanged, where appropriate, to describe the embodiments of the present application described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or apparatus that includes a list of steps or units is not necessarily limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to such processes, methods, products or apparatuses.

[0044] It should be understood that when an element (such as a layer, film, region, or substrate) is described as "on" another element, it can be directly on the other element, or an intermediate element can also be present. Moreover, in the specification and claims, when an element is described as "connected" to another element, it can be "directly connected" to the other element, or "connected" to the other element through a third element.

[0045] At present, the preparation route of the back contact cell with the tunnel oxide passivation contact structure includes the process steps of low pressure chemical vapor deposition of amorphous silicon, boron diffusion, laser opening mold, wet etching and cleaning, low pressure chemical vapor deposition of amorphous silicon, phosphorus diffusion, laser opening mold, and wet etching and cleaning.

[0046] In the process of preparing the cell by the above process, two times of low pressure chemical vapor deposition of amorphous silicon and two times of diffusion (i.e. boron diffusion and phosphorus diffusion) are required, the process steps are complicated, thereby resulting in low preparation speed and low yield of the finished product of the cell.

[0047] In order to solve the problem that the preparation process of the back contact photovoltaic cell is relatively complex, the embodiments of the present application provide a back contact photovoltaic cell, a preparation method thereof, and a cell module.

[0048] The technical solutions in the embodiments of the present application will be clearly and completely described in the following with reference to the accompanying drawings of the embodiments of the present application. Figure 1 to the accompanying drawings of the embodiments of the present application. Figure 16 The technical solutions in the embodiments of the present application will be clearly and completely described in the following with reference to the accompanying drawings of the embodiments of the present application.

[0049] In a first aspect, the embodiments of the present application provide a preparation method of a back contact photovoltaic cell, Figure 1 The main flowchart schematic diagram of the preparation method of the back contact photovoltaic cell is shown. Figures 2 to 5 The main flowchart schematic diagram of the preparation method of the back contact photovoltaic cell is shown. Figure 1 As shown in the figure, the preparation method of the back contact photovoltaic cell includes the following steps:

[0050] Step S100: providing a silicon substrate 1 having a first surface and a second surface oppositely arranged, the first surface having a first polarity region and a second polarity region.

[0051] The silicon substrate can be a P-type silicon substrate or an N-type silicon substrate.

[0052] In step S100, as shown in FIG. 1, the first surface and the second surface of the silicon substrate 1 can also be polished to make the main surfaces of the silicon substrate 1 flat. Taking the first surface of the silicon substrate 1 as the back surface as an example, the first surface can be polished only, or both surfaces can be polished, which is not limited. Figure 2

[0053] The back surface (i.e. the first surface) of the silicon substrate 1 needs to be prepared with P+ crystalline silicon layers and N+ crystalline silicon layers in different regions, i.e. the P region and the N region of the photovoltaic cell are arranged on the first surface of the silicon substrate 1. The first polarity region and the second polarity region in the first surface are not originally separated regions, but are positions for arranging the P+ crystalline silicon layer (such as the P region) and the N+ crystalline silicon layer (such as the N region) in subsequent steps.

[0054] Step S200: at least on the first surface of the silicon substrate, a first oxide layer 2, a first intrinsic crystalline silicon layer 3, a second oxide layer 4 and a second intrinsic crystalline silicon layer 5 are prepared from inside to outside, and the first oxide layer 2 is a tunneling oxide layer.

[0055] In step S200, one or more deposition methods such as low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD) can be used to form the first oxide layer 2, the first intrinsic crystalline silicon layer 3, the second oxide layer 4 and the second intrinsic crystalline silicon layer 5 as shown in FIG. 2. Figure 2

[0056] The first oxide layer 2 deposited is a tunneling oxide layer to provide excellent surface passivation effect. The first oxide layer 2 can effectively reduce the defect state density on the surface of the silicon substrate 1 to reduce the recombination rate of carriers on the surface, thereby facilitating the improvement of the open circuit voltage and conversion efficiency of the cell. The first oxide layer 2 is generally a silicon oxide deposition layer.

[0057] ​​For example, the first oxide layer 2 is prepared by low pressure chemical vapor deposition. Oxygen is introduced at a high temperature of 600-700°C to oxidize the surface of the silicon substrate 1 and form the first oxide layer 2. The deposition thickness of the first oxide layer 2 can be 1-2 nm, such as 1 nm, 1.2 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.8 nm, or 2 nm, by controlling the reaction time to be 10-20 min.

[0058] The first intrinsic crystalline silicon layer 3 can be a polysilicon structure, or an amorphous silicon or microcrystalline silicon structure. For example, the first intrinsic crystalline silicon layer 3 is a polysilicon structure. In the process of preparing the first intrinsic crystalline silicon layer 3 by low pressure chemical vapor deposition, the deposition temperature is controlled to be 510-610°C, and the deposition time is controlled to be 1200-2400 s, so that the deposition thickness of the first intrinsic crystalline silicon layer 3 is 50-300 nm.

[0059] Similarly, the second oxide layer 4 is continuously deposited on the outer side of the first intrinsic crystalline silicon layer 3 away from the silicon substrate 1. The second oxide layer 4 can also be prepared by low pressure chemical vapor deposition. Only the oxidation temperature needs to be adjusted to 600-700°C, the thickness of the second oxide layer 4 is 1-5 nm, and the oxidation time is controlled to be 10-35 min, so that the deposition thickness of the second oxide layer 4 is 1-5 nm.

[0060] Correspondingly, the second intrinsic crystalline silicon layer 5 can be prepared by low pressure chemical vapor deposition on the outer side of the second oxide layer 4 away from the silicon substrate 1. The deposition temperature is controlled to be 600-700°C, and the deposition time is controlled to be 1200-2400 s, so that the deposition thickness of the second intrinsic crystalline silicon layer 5 is 50-200 nm.

[0061] It should be noted that in step S200, as shown in Figure 2 The first oxide layer 2, the first intrinsic crystalline silicon layer 3, the second oxide layer 4, and the second intrinsic crystalline silicon layer 5 can be prepared on the first and second surfaces of the silicon substrate 1 at the same time. For example, the first oxide layer 2, the first intrinsic crystalline silicon layer 3, the second oxide layer 4, and the second intrinsic crystalline silicon layer 5 are sequentially distributed from the inside to the outside of the first and second surfaces of the silicon substrate 1.

[0062] Alternatively, the first oxide layer 2, the first intrinsic crystalline silicon layer 3, the second oxide layer 4, and the second intrinsic crystalline silicon layer 5 can also be prepared on the first surface of the silicon substrate 1.

[0063] Step S300: Doping the second intrinsic crystalline silicon layer 5 on the first surface, and preparing a first doped oxide layer 6 on the outer side of the second intrinsic crystalline silicon layer 5 after doping.

[0064] In the embodiments of this application, the distinction between the inner and outer sides of the film layer refers to the fact that, along the stacking direction of the multiple film layers, the side closer to the silicon substrate 1 is the inner side, while the side farther away from the silicon substrate 1 is the outer side.

[0065] Among them, such as Figure 3 As shown, the doping source type of the first doped oxide layer 6 can be opposite to that of the silicon substrate 1. For example, if the silicon substrate 1 is an N-type substrate, then the doping source of the first doped oxide layer 6 is boron. This facilitates the formation of a PN junction, enabling efficient carrier separation and transport, reducing recombination losses, and optimizing the process flow.

[0066] For example, a patterned partial cutout CVD (Chemical Vapor Deposition) process can be used to boron-dopant the second intrinsic silicon layer 5 in the first polar region of the silicon wafer. This forms a first doped silicon layer (such as a boron-doped polycrystalline silicon layer) and a first doped oxide layer 6 (such as a borosilicate glass layer).

[0067] Alternatively, boron doping can be directly performed on the second intrinsic silicon layer 5 of the first surface. This only requires removing the first doped oxide layer 6, the second intrinsic silicon layer 5, and the second oxide layer 4 in steps S400 and S500. This simplifies the fabrication process in step S300.

[0068] In the process of preparing the first doped oxide layer 6 and the first doped crystalline silicon layer, a boron source with an appropriate flow rate is introduced and the preparation temperature is controlled at 840-850℃ to form a borosilicate glass layer (i.e., the first doped oxide layer 6).

[0069] After the first doped oxide layer 6 is formed, the propagation temperature can be controlled to be 880-920℃, and the propagation time of the dopant source in the first doped oxide layer 6 can be controlled to be 8-12 min, so as to dop the second intrinsic silicon layer 5 inside the first doped oxide layer 6, so as to form the first doped silicon layer outside the second oxide layer 4.

[0070] For example, the propagation temperature of the first doped silicon layer can be 900°C, and the propagation time can be 10 minutes.

[0071] It should be noted that the first doped silicon layer can be prepared in step S300 or in step S600. Alternatively, after preparing the first doped silicon layer in step S300, the doping degree and depth of the first doped silicon layer can be further increased in step S600; this is not limited.

[0072] Step S400: Remove the first doped oxide layer in at least the second polar region by laser.

[0073] The first polarity region and the second polarity region are used for preparing P region and N region of the back contact photovoltaic cell respectively. Taking the phosphorus element as the doping source of the first doped oxide layer 6 as an example, the first polarity region is used for forming a first doped crystalline silicon layer, i.e. the P region. The second polarity region is used for forming a second doped crystalline silicon layer, i.e. the N region.

[0074] As shown in FIG. 6, the first doped oxide layer 6 in the second polarity region can be removed by laser irradiation, so that the region where the first doped oxide layer 6 is removed serves as the second polarity region, and the region where the first doped oxide layer 6 is retained serves as the first polarity region. Figure 3

[0075] The first doped oxide layer 6 (i.e. borosilicate glass layer) in the second polarity region is removed by laser, which is beneficial to the cleaning treatment of the second intrinsic crystalline silicon layer and the second oxide layer inside the first doped oxide layer 6 in the subsequent step.

[0076] Step S500: removing the second intrinsic crystalline silicon layer and the second oxide layer in at least the second polarity region.

[0077] As shown in FIG. 6, the second intrinsic crystalline silicon layer 5 and the second oxide layer 4 can be removed by polishing with an alkali solution or laser removal, so as to facilitate the doping of the first intrinsic crystalline silicon layer 3 exposed by the second polarity region. The second intrinsic crystalline silicon layer partially doped in step S300 can also be regarded as a film layer part of the removed second intrinsic crystalline silicon layer 5. Figure 4 As shown in FIG. 6, if the second surface of the silicon substrate 1 has the first oxide layer 2, the first intrinsic crystalline silicon layer 3, the second oxide layer 4 and the second intrinsic crystalline silicon layer 5 deposited from inside to outside. In step S500, the first oxide layer 2, the first intrinsic crystalline silicon layer 3, the second oxide layer 4 and the second intrinsic crystalline silicon layer 5 at the second surface can be cleaned to remove the first oxide layer 2, the first intrinsic crystalline silicon layer 3, the second oxide layer 4 and the second intrinsic crystalline silicon layer 5 until the second surface of the silicon substrate 1 is exposed. The cleaning can be performed by polishing with an alkali solution or laser irradiation removal, etc.

[0078] Figure 2

[0079] Step S600: the first doped crystalline silicon layer 8 is formed inside the first doped oxide layer 6 in the first polarity region. The second doped oxide layer 7 is prepared outside the first intrinsic crystalline silicon layer 3 in the second polarity region, and the doping source of the second doped oxide layer 7 is pushed to the first intrinsic crystalline silicon layer 3 to form the second doped crystalline silicon layer 9. The doping type of the first doped crystalline silicon layer 8 is opposite to the doping type of the second doped crystalline silicon layer 9.

[0080] As shown in FIG. 6, the first doped oxide layer 6 in the second polarity region can be removed by laser irradiation, so that the region where the first doped oxide layer 6 is removed serves as the second polarity region, and the region where the first doped oxide layer 6 is retained serves as the first polarity region. Figure 4 ​​​As shown, the region where the second oxide layer 4, the second intrinsic crystalline silicon layer 5 and the first doped oxide layer 6 exist on the first surface of the silicon substrate 1 is the first polarity region. The region where the second oxide layer 4, the second intrinsic crystalline silicon layer 5 and the first doped oxide layer 6 are removed is the second polarity region.

[0081] The first polarity region and the second polarity region can be arranged in a finger-like cross manner so that the P region and the N region are arranged alternately on the first surface, thereby forming a cross-finger structure. Alternatively, the first polarity region and the second polarity region can also be arranged in other shapes, and the P region and the N region are arranged alternately on the first surface, which is not limited.

[0082] In combination Figure 4 and Figure 5 In the first polarity region, the advancement of the doping source in the first doped oxide layer 6 is controlled to form the first doped crystalline silicon layer 8 on the inner side of the first doped oxide layer 6. Taking the doping element of the first doped crystalline silicon layer 8 as boron element for example, Figure 5 The first doped crystalline silicon layer 8 shown is the P region, which is generally a boron-doped polysilicon layer.

[0083] The advancement of the doping source (such as boron element) in the first doped oxide layer 6 is controlled to form the first doped crystalline silicon layer 8, or to deepen the doping degree of the first doped crystalline silicon layer 8. This can be performed in at least one of the steps S300 and S600.

[0084] Then, the outer side of the first intrinsic crystalline silicon layer 3 exposed in the second polarity region is doped to form the second doped oxide layer 7. In this process, taking the doping source as phosphorus element for example, the phosphorus source with an appropriate flow is introduced, and the preparation temperature is controlled to be 830-850°C (such as 840°C) to form the second doped oxide layer 7 (i.e. phosphorus-silicon glass) on the outer side of the first intrinsic crystalline silicon layer 3.

[0085] Subsequently, the temperature is increased to make the advancement temperature 880-900°C, and the advancement time of the doping source in the second doped oxide layer 7 is controlled to be 15-25 min. The doping source (such as phosphorus element) in the second doped oxide layer 7 is advanced to the first intrinsic crystalline silicon layer 3 to form Figure 5 The second doped crystalline silicon layer 9 shown.

[0086] Taking the doping element of the second doped crystalline silicon layer 9 as phosphorus element for example, Figure 5 The second doped crystalline silicon layer 9 shown is the N region, which is generally a phosphorus-doped polysilicon layer.

[0087] Thus, in the fabrication method provided in this application, through the above-described fabrication steps, a photovoltaic cell structure comprising a tunneling oxide layer (i.e., the first oxide layer 2), a first doped crystalline silicon layer 8, and a second doped crystalline silicon layer 9 can be formed on the first surface of the silicon substrate 1. This serves as the basic structure for photovoltaic cells incorporating tunneling oxide layer passivation contact technology and full back electrode contact technology. It achieves efficient passivation by depositing an ultrathin oxide layer and a doped polycrystalline silicon layer on the silicon wafer surface, significantly reducing carrier recombination on the surface and thereby improving the open-circuit voltage and fill factor. Furthermore, it ensures that the front side (i.e., the second surface) of the photovoltaic cell is unobstructed by electrodes, maximizing the utilization of the light-emitting area and reducing optical losses. It possesses advantages such as high conversion efficiency, low temperature coefficient, long lifetime, and low degradation.

[0088] Compared to related technologies that involve two low-pressure chemical vapor depositions of amorphous silicon and two dopant source diffusions, the fabrication process in this application uses the outer second oxide layer 4 and the second intrinsic silicon layer 5 as sacrificial layers in steps S400 and S500, and the first doped oxide layer 6 as an etch barrier layer, to achieve two-stage doping of the first doped silicon layer 8 and the second doped silicon layer 9. Thus, only step S100 is needed to deposit the first oxide layer 2, the first intrinsic silicon layer 3, the second oxide layer 4, and the second intrinsic silicon layer 5, eliminating the need for multiple film deposition processes for the first doped silicon layer 8 and the second doped silicon layer 9. This simplifies the overall fabrication process, shortens the overall process time, and avoids problems such as leakage current caused by secondary deposition and stacking of the film layers.

[0089] like Figure 6 As shown, after step S600, the preparation method further includes:

[0090] Step S700: At least the second doped oxide layer 7 and the first doped oxide layer 6 of the electrical isolation region are removed by laser. The electrical isolation region is located between the first polarity region and the second polarity region.

[0091] Step S810: Remove the film layer of the electrical isolation area and clean it until the silicon substrate 1 is exposed.

[0092] Step S820: Remove the first doped oxide layer 6 and the second doped oxide layer 7 and clean.

[0093] Step S830: Prepare a textured structure on at least the second side of the silicon substrate.

[0094] The electrical isolation region is located between the first polarity region and the second polarity region, and is used to physically separate the first polarity region (e.g., the first doped silicon layer 8) and the second polarity region (e.g., the second doped silicon layer 9). While preventing short circuit, the electrical isolation region can reduce the recombination of carriers at the junction of the P region (e.g., the first polarity region) and the N region (e.g., the first polarity region), thereby improving the conversion efficiency of the cell.

[0095] As shown in Figure 7 and Figure 8 , since only the second doped oxide layer 7 and the first doped oxide layer 6 of the electrical isolation region are removed, the cleaning agent such as an alkali solution can avoid removing the film layers such as the first doped silicon layer 8 and the second doped silicon layer 9 of the first polarity region and the second polarity region during the cleaning process of step S810. Subsequently, step S820 further removes the remaining first doped oxide layer 6 and second doped oxide layer 7 by laser, so as to facilitate the subsequent deposition of the passivation film and the anti-reflection film outside the first doped silicon layer 8 and the second doped silicon layer 9. Finally, step S830 facilitates the reduction of the reflection of sunlight on the second surface of the photovoltaic cell by making a textured structure on the first surface of the silicon substrate 1.

[0096] Continuing to refer to Figure 6 , after step S830, the preparation method further comprises:

[0097] Step S910: preparing the passivation film 10 and the anti-reflection film 11 which are stacked on both sides of the silicon substrate 1.

[0098] Step S920: preparing the first electrode 12 connected to the first doped silicon layer 8 and the second electrode 13 connected to the second doped silicon layer 9.

[0099] As shown in Figure 9 , the combined use of the passivation film 10 and the anti-reflection film 11 can significantly improve the overall performance of the photovoltaic cell. The passivation film 10 can reduce the recombination loss of carriers, and the anti-reflection film 11 cooperates with the textured structure to further increase the light absorption efficiency, and the synergistic effect of the two makes the photovoltaic cell improve the conversion efficiency while maintaining high stability and reliability.

[0100] During the preparation of the passivation film 10 and the anti-reflection film 11 in step S910, the electrical isolation region is also formed with the passivation film 10 and the anti-reflection film 11 which are stacked from inside to outside, further improving the electrical isolation effect between the first polarity region and the second polarity region.

[0101] As shown in Figure 10As shown, the first electrode 12 and the second electrode 13 are prepared in the first surface by step S920, so that the first electrode 12 is connected with the first doped crystalline silicon layer 8, and the second electrode 13 is connected with the second doped crystalline silicon layer 9. Good ohmic contact can be achieved by setting the first electrode 12 and the second electrode 13 to form silver microcrystals in the passivation film 10. These silver microcrystals can penetrate the passivation film 10 to form stable contact while reducing contact resistance.

[0102] In some embodiments, step S300 further comprises:

[0103] The dopant source in the first doped oxide layer 6 is pushed to the second intrinsic crystalline silicon layer 5 to form the first doped crystalline silicon layer 8 outside the second oxide layer 4.

[0104] In combination with Figure 2 and Figure 11 After the first doped oxide layer 6 is formed, the dopant source in the first doped oxide layer 6 can be continuously pushed inward to form the first doped crystalline silicon layer 8 in the second intrinsic crystalline silicon layer 5 between the first doped oxide layer 6 and the second oxide layer 4.

[0105] After the first doped oxide layer 6 is formed, the dopant source in the first doped oxide layer 6 can be continuously pushed inward to form the first doped crystalline silicon layer 8 in the second intrinsic crystalline silicon layer 5 between the first doped oxide layer 6 and the second oxide layer 4.

[0106] Subsequently, in steps S400 and S500, the first doped oxide layer 6 and the first doped crystalline silicon layer 8 of the second polarity region can be removed to facilitate preparation of the second doped crystalline silicon layer in the polarity region.

[0107] Based on this, as shown in Figure 12 step S600 further comprises:

[0108] Step S610: The dopant source of the first doped oxide layer 6 is pushed at least to the second intrinsic crystalline silicon layer 5 to form the first doped crystalline silicon layer 8 at least outside the second oxide layer 4.

[0109] Taking the dopant source as boron element as an example, the second oxide layer 4 and the first doped crystalline silicon layer 8 are P region of the photovoltaic cell. The preparation thickness of the second oxide layer 4 can be 1-2 nm to ensure the tunneling efficiency. The thickness of the second intrinsic crystalline silicon layer 5 can be 100-200 nm, and the speed and deposition quality of the second intrinsic crystalline silicon layer 5 in the deposition process are controlled to make the formed first doped crystalline silicon layer 8 have better film quality.

[0110] Step S620: Preparing a second doped oxide layer 7 outside the first intrinsic silicon layer 3 of the second polar region, and pushing the doping source of the second doped oxide layer 7 to the first intrinsic silicon layer 3 to form a second doped silicon layer 9.

[0111] Thus, referring to Figure 5 , by step S610 and step S620, the basic structure of P region and N region can be prepared on the first surface of the photovoltaic cell.

[0112] In step S610, the pushing temperature can also be controlled to be 950-970℃, and the pushing time of the doping source in the first doped oxide layer 6 can be controlled to be 25-35min.

[0113] As by the above process, the first doping step S610 further comprises:

[0114] The doping source of the first doped oxide layer 6 is pushed to the second intrinsic silicon layer 5 and the first intrinsic silicon layer 3 to form two layers of first doped silicon layers 8 inside the first doped oxide layer 6.

[0115] For example, in combination with Figure 11 and Figure 13 , by a pushing temperature of 960℃ and a pushing time of 30min, the doping source in the first doped oxide layer 6 can be pushed deeply to the first intrinsic silicon layer 3, so as to form the first doped silicon layers 8 on the inside and outside of the second oxide layer 4, and the two layers of first doped silicon layers 8 have a better cell conversion efficiency by taking the second oxide layer 4 as a tunneling oxide layer.

[0116] Alternatively, after step S600, as shown in Figure 13 and Figure 14 , the first doped silicon layer 8 outside the second oxide layer 4 and the second oxide layer 4 can be taken as a sacrificial layer, and only the first doped silicon layer 8 inside the second oxide layer 4 and the first doped silicon layer 8 need to be reserved.

[0117] For example, step S820 can further comprise:

[0118] In the first polar region, the first doped silicon layer 8 outside the second oxide layer 4 and the second oxide layer 4 are removed and cleaned until the first doped silicon layer 8 formed by the first intrinsic silicon layer 3 is exposed.

[0119] Thus, by providing multiple preparation process directions, the flexibility of the preparation process can be adjusted.

[0120] When the first doped silicon layer 8 outside the second oxide layer 4 and the second oxide layer 4 are taken as a sacrificial layer, the thickness of the second oxide layer 4 can be flexibly adjusted. Correspondingly, the preparation process of the second intrinsic silicon layer 5 can be accelerated to reduce the production time of the overall process.

[0121] For example, the thickness of the second oxide layer 4 can be set to be greater than the thickness of the first oxide layer 2. In this case, the second oxide layer 4 serves as a sacrificial layer structure.

[0122] Correspondingly, the deposition temperature of the first intrinsic silicon layer 3 is lower than that of the second intrinsic silicon layer 5. This means that a higher deposition temperature is beneficial for increasing the deposition rate of the second intrinsic silicon layer 5, thereby reducing the overall process time. Furthermore, a lower deposition temperature and deposition rate are beneficial for improving the deposition uniformity and quality of the first intrinsic silicon layer 3.

[0123] Since the second intrinsic silicon layer 5, which serves as a sacrificial layer, does not require a large thickness, its deposition time can be further reduced. This makes the deposition time of the second intrinsic silicon layer 5 shorter than that of the first intrinsic silicon layer 3, thereby reducing the overall process time.

[0124] In some embodiments, step S830 further includes:

[0125] A textured structure is fabricated on a silicon substrate 1 in an electrically isolated region, and a textured structure is fabricated on a silicon substrate 1 with a second facet shape.

[0126] By fabricating a textured structure on the exposed silicon substrate 1 in the electrical isolation zone, the light reflection effect of the silicon substrate 1 can be improved, thereby increasing the efficiency of light utilization.

[0127] In some embodiments, step S810 further includes:

[0128] A portion of the silicon substrate 1 is removed in the electrical isolation area to form a groove structure on the silicon substrate 1.

[0129] That is, by setting the portion of the silicon substrate 1 exposed in the electrical isolation area as Figure 15 The groove structure shown. During the preparation of the passivation film 10 and the antireflection film 11 in step S910, the passivation film 10 and the antireflection film 11 can be extended along the inner wall of the groove structure, which helps to improve the creepage gap and creepage distance between the P-region and the N-region, thereby improving the electrical isolation effect within a limited space. Alternatively, based on the same electrical isolation effect, the groove structure can help to reduce the width gap of the electrical isolation area, thereby increasing the structural area ratio of the P-region and N-region in the photovoltaic cell.

[0130] Secondly, such as Figure 10 and Figure 15 As shown, this application embodiment also provides a back contact photovoltaic cell 100, which is prepared by the method described in the first aspect.

[0131] Beneficial effects: since the back contact photovoltaic cell 100 in the second aspect is prepared by the preparation method of the back contact photovoltaic cell in the first aspect, the back contact photovoltaic cell 100 has all the beneficial effects of the preparation method of the back contact photovoltaic cell, which will not be repeated here.

[0132] In a third aspect, as shown in Figure 16 The embodiments of the present application also provide a photovoltaic module 1000, which comprises the plurality of back contact photovoltaic cells 100 in the second aspect and the plurality of back contact photovoltaic cells 100 are electrically connected. The plurality of back contact photovoltaic cells 100 can be partially connected in series and partially connected in parallel, or the plurality of back contact photovoltaic cells 100 can be connected in series to output electric power under light.

[0133] Beneficial effects: since the photovoltaic module 1000 in the third aspect comprises the back contact photovoltaic cell 100 in the second aspect, the photovoltaic module 1000 has all the beneficial effects of the back contact photovoltaic cell 100, which will not be repeated here.

[0134] In the description of the present application, the description of the terms "embodiment", "example", "some embodiments", "exemplary", "for example", etc. means that the specific features, structures, shapes, positions, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present application, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0135] Although the embodiments of the present application have been shown and described, those skilled in the art can understand that various changes, modifications, replacements and variations can be made to the embodiments without departing from the principles and purposes of the present application, and the scope of the present application is defined by the claims and their equivalents.

Claims

1. A method of fabricating a back contact photovoltaic cell, characterized by, Comprising: Step S100: providing a silicon substrate, the silicon substrate comprising oppositely arranged first and second surfaces, the first surface comprising a first polarity region and a second polarity region; Step S200: preparing, at least on the first surface, a first oxide layer, a first intrinsic crystalline silicon layer, a second oxide layer and a second intrinsic crystalline silicon layer in a stacked arrangement from inside to outside, the first oxide layer being a tunnel oxide layer, wherein the first and second intrinsic crystalline silicon layers are prepared by deposition for a predetermined time, and the deposition time of the second intrinsic crystalline silicon layer is less than that of the first intrinsic crystalline silicon layer; Step S300: doping the second intrinsic crystalline silicon layer of the first surface, and forming a first doped oxide layer outside the doped second intrinsic crystalline silicon layer; Step S400: removing the first doped oxide layer at least in the second polarity region by laser; Step S500: removing the second intrinsic crystalline silicon layer and the second oxide layer at least in the second polarity region; Step S600: pushing a doping source of the first doped oxide layer to the second intrinsic crystalline silicon layer and the first intrinsic crystalline silicon layer to form two layers of first doped crystalline silicon layers inside the first doped oxide layer; preparing a second doped oxide layer outside the first intrinsic crystalline silicon layer in the second polarity region, and pushing a doping source of the second doped oxide layer to the first intrinsic crystalline silicon layer to form a second doped crystalline silicon layer; the doping type of the first doped crystalline silicon layer being opposite to that of the second doped crystalline silicon layer; After the step S600, the preparation method further comprises: In the first polarity region, removing the first doped crystalline silicon layer and the second oxide layer outside the second oxide layer and cleaning until the first doped crystalline silicon layer formed by the first intrinsic crystalline silicon layer is exposed.

2. The method of claim 1, wherein the back contact photovoltaic cell is prepared by a process comprising: After the step S600, the preparation method further comprises: Step S700: removing the second doped oxide layer and the first doped oxide layer at least in an electrical isolation region by laser, the electrical isolation region being located between the first polarity region and the second polarity region; Step S810: removing the film layer of the electrical isolation region and cleaning until the silicon substrate is exposed; Step S820: removing the first doped oxide layer and the second doped oxide layer and cleaning; Step S830: preparing a textured structure at least on the second surface of the silicon substrate.

3. The method of claim 2, wherein the back contact photovoltaic cell is prepared by a process comprising: In the step "pushing a doping source of the first doped oxide layer to the second intrinsic crystalline silicon layer and the first intrinsic crystalline silicon layer to form two layers of first doped crystalline silicon layers inside the first doped oxide layer", the pushing temperature is controlled to be 950-970°C, and the pushing time of the doping source in the first doped oxide layer is controlled to be 25-35 min.

4. The method of claim 2, wherein the back contact photovoltaic cell is formed by a process comprising: In the step "preparing the second doped oxide layer outside the first intrinsic crystalline silicon layer in the second polarity region, and pushing a doping source of the second doped oxide layer to the first intrinsic crystalline silicon layer to form the second doped crystalline silicon layer", the preparation temperature of the second doped oxide layer is 830-850°C; and / or, The pushing temperature is controlled at 880-900 ℃, and the pushing time of the doping source in the second doped oxide layer is controlled at 15-25 min.

5. The preparation method of the back contact photovoltaic cell according to any one of claims 1-4, characterized in that, The step S300 further comprises: The doping source in the first doped oxide layer is pushed to the second intrinsic crystalline silicon layer to form a first doped crystalline silicon layer outside the second oxide layer.

6. The method of claim 5, wherein the back contact photovoltaic cell is formed by a process comprising: In the step S300, the preparation temperature of the first doped oxide layer is 840-850 ℃; and / or, After the first doped oxide layer is formed, the pushing temperature is controlled at 880-920 ℃, and the pushing time of the doping source in the first doped oxide layer is controlled at 8-12 min.

7. The method of producing a back contact photovoltaic cell according to any one of claims 1 to 4, characterized in that, The oxidation temperature of the first oxide layer is 600-700 ℃, the thickness of the first oxide layer is 1-2 nm, and the oxidation time of the first oxide layer is 10-20 min; and / or, The deposition temperature of the first intrinsic crystalline silicon layer is 510-610 ℃, the thickness of the first intrinsic crystalline silicon layer is 50-300 nm, and the deposition time of the first intrinsic crystalline silicon layer is 1200-2400 s; and / or, The oxidation temperature of the second oxide layer is 600-700 ℃, the thickness of the second oxide layer is 1-5 nm, and the oxidation time of the second oxide layer is 10-35 min; and / or, The deposition temperature of the second intrinsic crystalline silicon layer is 600-700 ℃, the thickness of the second intrinsic crystalline silicon layer is 50-200 nm, and the deposition time of the second intrinsic crystalline silicon layer is 1200-1400 s.

8. The method for preparing a back-contact photovoltaic cell according to claim 2, characterized in that, The thickness of the second oxide layer is greater than the thickness of the first oxide layer; and / or, The deposition temperature of the first intrinsic crystalline silicon layer is less than the deposition temperature of the second intrinsic crystalline silicon layer.

9. The method of producing a back contact photovoltaic cell according to any one of claims 2 to 4, wherein The second oxide layer is a tunneling oxide layer.

10. The method of producing a back contact photovoltaic cell according to any one of claims 2 to 4 or 8, characterized in that, In the step S200, the first face and the second face of the silicon substrate form the first oxide layer, the first intrinsic crystalline silicon layer, the second oxide layer and the second intrinsic crystalline silicon layer; The step S500 further comprises: The second face of the silicon substrate is cleaned until the second face of the silicon substrate is exposed.

11. The method of producing a back contact photovoltaic cell according to any one of claims 2 to 4 or 8, characterized in that, The step S830 comprises: A textured structure is prepared at the silicon substrate of the electrical isolation region, and a textured structure is prepared at the second face of the silicon substrate.

12. The method of producing a back contact photovoltaic cell according to any one of claims 2 to 4 or 8, characterized in that, The step S810 further comprises: Part of the silicon substrate is removed at the electrical isolation region to form a groove structure on the silicon substrate.

13. The method of producing a back contact photovoltaic cell according to any one of claims 2 to 4 or 8, wherein After the step S830, the preparation method further comprises: Step S910: a passivation film and an anti-reflection film are prepared on both sides of the silicon substrate in a stacked manner; Step S920: a first electrode connected to the first doped crystalline silicon layer and a second electrode connected to the second doped crystalline silicon layer are prepared.

14. A back contact photovoltaic cell characterized in that, The back contact photovoltaic cell is prepared by the preparation method of any one of claims 1-13.

15. A photovoltaic module, characterized by The photovoltaic assembly comprises a plurality of back contact photovoltaic cells according to claim 14, and the plurality of back contact photovoltaic cells are electrically connected.

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