Estimating characteristics of semiconductor device using quantum computing device

Abstract

Methods and apparatus are provided for estimating characteristics of a semiconductor device using a quantum computing device. A method includes initializing a first system of equations based on one or more parameters associated with a spatially discretized representation of a semiconductor device; a loop reduction method is applied to the first equation set to obtain a second equation set, so that the calculation complexity of the method is reduced; and estimating a characteristic of the semiconductor device based on a solution of the second equation set. In one embodiment, a method includes determining an entry of a matrix B that is an inverse of a matrix A by expressing a quadratic unconstrained binary optimization (QUBO) problem with a formula, and performing the QUBO problem on a quantum computing device, where the entry of the matrix A represents interactions within a layer of a spatially discrete representation of a semiconductor device.

Description

Technical Field

[0001] Examples of the present disclosure relate to estimating characteristics of semiconductor devices. Examples of the present disclosure also relate to determining entries of an N×N matrix B, for example, using a method leveraging a quantum computing device, where matrix B is the inverse of an N×N matrix A. Background Art

[0002] The evolution of 5G towards enhanced connectivity, intelligent network platforms, and edge computing requires powerful computing capabilities in telecommunication infrastructure.

[0003] The transistor density on integrated chips doubles every two years (known as Moore's Law), combined with the improvement in individual transistor performance, leading to a huge development in the capabilities of electronic devices. New sub-10nm transistor technologies (such as fully depleted surround gate (GAA) 3nm transistors) can be used to meet the performance requirements of new applications, where the electrical, thermal, and switching characteristics of these transistors are dominated by quantum effects. Accurately modeling these quantum effects improves the integrity of circuit design in this field.

[0004] Traditionally, semiconductor device analysis has been performed by simulating electron transport using semi-classical methods based on the Boltzmann transport equation (BTE) or moments of the BTE (e.g., drift-diffusion models or hydrodynamic models). However, when semiconductor devices are scaled down to the point where the de Broglie wavelength of electrons is comparable to the size of the semiconductor device, the wave characteristics cannot be ignored. At this point, the semi-classical transport equations are no longer valid because they cannot accurately handle quantum effects. Therefore, semiconductor device simulation methods that can incorporate quantum effects to enable the discovery and development of modern nanoelectronic devices are needed.

[0005] There are models (known as quantum models) that can model these quantum effects, such as self-consistent solutions of the Schrödinger equation with open boundary conditions. Compared with drift-diffusion models, these models can more accurately simulate nano-scale devices, but at the cost of increased computational complexity. The computational complexity of quantum models reduces their usability. The simulation domain using these models is typically limited to two dimensions, while in reality, transistors are three-dimensional devices, and the simulation time of these models can be very long.

[0006] However, continuously improving supercomputers and quantum computers present new opportunities for simulating semiconductor devices using quantum models.

[0007] First, consider the macroscopic approach. As the size of semiconductor devices shrinks, there has been an ongoing effort to implement quantum effects in macroscopic device simulators. One approach is based on moment equations derived from the Wigner distribution function and is known as the density gradient (DG) method [2]. The Wigner distribution satisfies the microscopic transport equation derived from the quantum Liouville equation, with a quantum correction term added. Calculating the first moment of this transport equation yields the macroscopic current continuity equation used in the density gradient method. The DG method is embedded in the drift-diffusion model to account for statistical quantum effects [3].

[0008] For the microscopic approach, electrons are guided by both the classical electrostatic potential and the quantum potential, which can be implemented in Monte Carlo techniques. This approach can explain static quantum interference effects due to the non-local wave nature of particles. Depending on the assumptions and approximations used in its derivation, many different kinds of quantum potentials can be obtained, such as the DG method, the quantum moment method

[13] , and the smoothed effective potential

[14] . The quantum potential can be used to explain static quantum effects caused by the potential distribution within semiconductor devices. However, this approach assumes a closed system and thus is not easily able to explain dynamic quantum effects associated with phase-randomizing scattering processes.

[0009] To capture dynamic quantum effects, the quantum transport equation for the entire system and its environment (such as phonons) must be solved. Several techniques can handle dynamic quantum effects, such as the density matrix method (using the Wigner distribution for open systems but not for closed systems associated with the quantum potential), the master equation method, and the non-equilibrium Green's function method.

[0010] To capture random phase scattering in sub-10nm transistors, it has been proposed to replace the semiclassical BTE with a master equation based on a natural basis [6, 15, 16], where the natural basis consists of the eigenstates of the self-consistent Hartree potential in the Schrödinger equation within the density matrix. This approach assumes that the off-diagonal elements of the density matrix in the natural basis can be neglected. This means that the transitions of electron states are approximated as fully collisional and Markovian. Comparing the master equation method with the BTE, the deviations of electron transport characteristics (such as electron density, drift velocity, and average energy) are small.

[0011] The non-equilibrium Green's function (NEGF) method requires several Green's functions (appropriate correlation functions) in addition to the retarded Green's function and the advanced Green's function to describe non-equilibrium transport. The Green's functions satisfy the Dyson 2x2 matrix equation. This method introduces the self-energy function to capture the scattering process and the interaction with the semiconductor device environment. This method has been applied to simulate electron transport under high electric fields and quantum effects such as collision broadening and intra-collision effects. Due to the approximations (Born) in the scattering kernel, the importance of these quantum effects is not yet certain. This method has also been applied to nanostructure devices.

[0012] Note that specific prior arts for simulating semiconductor devices (such as the density matrix (Wigner distribution) method, the master equation method, and the non-equilibrium Green's function method) are computationally very complex. Therefore, these methods are limited to simulating one-dimensional structures (see [3] for example).

[0013] Microscopic methods recognize the drawbacks of the semiclassical BTE method and represent the basis for the next generation of simulators. However, since these methods involve much more content, they are also much more computationally complex.

[0014] Now consider the Schrödinger equation with open boundaries. The goal of solving the Schrödinger equation is to study the behavior of semiconductor devices under an applied bias (such as a drain-source voltage), where particles can be exchanged with the environment through contacts. To handle the interaction with the environment, the quantum transport boundary method (QTBM) is used. The source contact and the drain contact are idealized as infinite leads connected to the active region of the device. Then, electron waves are injected from the leads, and the distribution of the electron waves within the semiconductor device and the current entering the leads are calculated.

[0015] After discretizing the Schrödinger equation using the finite element method, by using rectangular grid cells and applying open boundary conditions with QTBM, the following sparse linear system of equations Hφ = b is obtained:

[0016]

[0017] where H D is the NxN Schrödinger Hamiltonian, I is the NxN identity matrix, B m is the Nx1 vector of the modes injected into the semiconductor device, and Σ L and Σ R are NxN matrices representing the self-energy (including reflected and transmitted waves (traveling and evanescent waves) entering and leaving the semiconductor device). QTBM is used to calculate Σ L and Σ R . The interface Γ o where no electrons are injected implements the zero-value Dirichlet boundary condition. Equation 1 is then solved to obtain the electron wave vectors for different injection energies traveling modes m, leads s, and conduction band valleys v The obtained electron wave vectors are then used to calculate the density of states [6].

[0018] To be able to utilize the parallel capabilities of supercomputers and / or quantum computers, the domain decomposition (DD) method can be utilized to solve the boundary value problem by the following operations: splitting the boundary value problem into smaller boundary value problems on subdomains and iterating to coordinate the solutions between adjacent subdomains.

[0019] Quantum computers are limited by the number of their logical qubits and thus cannot solve large problems. Since domain decomposition methods enable large problems to be reduced to a number of smaller sub-problems, domain decomposition methods enable these larger problems (e.g., solving the discretized Schrödinger equation for semiconductor devices) to be implemented on quantum computers according to current limitations.

[0020] Implementing the DD method as part of a method for simulating semiconductor devices thus enables improvement of the execution time of the simulation by enabling parallel computing to solve the sub-problems simultaneously and / or allowing the use of quantum computing devices to solve the sub-problems.

[0021] An example of a domain decomposition method is the block cyclic reduction (BCR) method [4], also known as "renormalization" [5].

[0022] The BCR method exploits the structure of the system of linear equations in order to then allow Gaussian elimination to be used to decouple the matrix blocks. In Equation 1, the matrix blocks correspond to different layers of a semiconductor device, where the layers of the semiconductor device are coupled to each other. Thus, by decoupling the matrix blocks, the BCR method enables the different layers of the semiconductor device to be decoupled until a system of linear equations is formed in which only the first and last layers are coupled.

[0023] In the BCR method, the layers i of the semiconductor device are decoupled by "renormalizing" the matrix blocks H i-1,i-1 、H i+1,i+1 、H i-1,i+1 and H i+1,i-1 as follows:

[0024]

[0025] where i-l and i+r are the indices of the semiconductor device layers that are currently coupled to layer I, denotes the matrix block H after renormalization.

[0026] These six operations suppress layer i in H. The BCR method can suppress all layers of the semiconductor device except the first and last layers in this way.

[0027] The BCR method can be divided into three stages:

[0028] In the first stage, the matrix blocks with even indices are decoupled (2, 4, 6,...), except for the last layer with an even index.

[0029] In the second stage, half of the matrix blocks with odd indices are decoupled (3, 7, 11,...). This includes the inversion and multiplication of real dense matrices.

[0030] In the third stage, the remaining half of the matrix blocks with odd indices are decoupled (5, 9, 13, …). All matrices in this stage are full rank. The process is then repeated until only the matrix blocks and

[0031] remain. After performing the BCR method, a system of linear equations is formed in which only the first and last layers are coupled (i.e., a 2n z × 2n z system of linear equations).

[0032] Therefore, the BCR method requires determining the solution of n z × n z inverses of size n x - 2 and a 2n z × 2n z system of linear equations, rather than an n x n z × n x n z system of linear equations (i.e., the initial system of equations).

[0033] The 2n z × 2n z system of linear equations is then solved to determine the entries Φ 1 and Φ nx of the solution vector Φ.

[0034] Then, for each entry Φ i , the remaining part of the solution vector Φ can be reconstructed using the following equation:

[0035] Φ i = -X i Φ i-l - Y i Φ i+r (2g)

[0036] where Φ i-l and Φ i+r are the entries of the solution vector corresponding to the layer to which layer i was previously coupled before being decoupled at layer i. That is, the entry Φ i is reconstructed based on the layer to which layer i was coupled before decoupling at layer i.

[0037] In this way, the complete solution Φ can be recursively reconstructed.

[0038] The BCR method has been applied to atomic simulations, where the system of linear equations used in the simulation includes diagonal matrix blocks that are themselves diagonal (see, for example, in

[10] Figure 1) Note that this makes the necessary calculations for the matrix inverse simpler. However, atomic simulations require determining solutions for several systems of linear equations.

[0039] Quantum annealers are a class of quantum computers and are rapidly becoming the target hardware platform for efficiently solving combinatorial optimization problems. Quantum annealers reduce these problems to energy minimization problems and implement a metaheuristic process called quantum annealing to find the low-energy states of the problem and thus find the optimal combination of variables that yields the global optimum of the objective function.

[0040] For a quantum system, the Hamiltonian is a function that maps specific states (called eigenstates) to corresponding eigenenergies. The set of these eigenenergies constitutes the eigen-spectrum. The Hamiltonian can be considered as the sum of two terms: (i) an initial Hamiltonian whose lowest energy state is when all qubits are in a superposition of 0 and 1; (ii) a final Hamiltonian or problem Hamiltonian whose lowest energy state is the solution of the problem being solved. The quantum annealing process initializes the system to the lowest energy eigenstate of the initial Hamiltonian. Then, it gradually increases the influence of the problem Hamiltonian (which includes qubit biases and the coupling strength between qubits) and slowly decreases the influence of the initial Hamiltonian. At the end of the quantum annealing process, the system will be in an eigenstate of the problem Hamiltonian. Ideally, the system remains in the minimum energy state throughout the quantum annealing process so that at the end of the process, the system is in the minimum energy state of the problem Hamiltonian and thus provides the solution to the problem. At the end of annealing, each qubit is a classical object.

[0041] Reference

[11] describes the QUBO formulation for computing the inverse of a matrix. The inverse of an N×N matrix A can be determined by solving the system of linear equations Ax = m, where m is a unit vector (e.g., m = e 1 = [1, 0, …, 0] T ). The solution to this system of linear equations (where the right-hand side m = e 1 ) will be the first column of A -1 . Thus, by solving this system of linear equations for all unit vectors, A -1 can be determined. However, this method requires the system of linear equations to be solved N times, each time determining N unknown variables.

[0042] As described above, for the method of simulating a semiconductor device by solving the discretized Schrödinger equation for the semiconductor device, the discretized Schrödinger equation is solved to obtain the electron wave vectors for different injection energies traveling modes m, leads s, and conduction band valleys v That is, as part of the simulation method, the discretized Schrödinger equation must be solved multiple times for many different device states and may thus represent a "bottleneck" in the execution time of the method. In addition, calculating the inverse matrices required to determine each of these different solutions of the discretized Schrödinger equation is computationally expensive and time-consuming. Although the BCR method can be used to reduce the computational burden of determining the solution of each discretized Schrödinger equation, the BCR method itself requires calculating inverse matrices. Also note that if the first and last entries of the solution vector (determined using the BCR method) are equal to zero, it is not possible to use the BCR method to determine a non-zero solution of the solution vector.

[0043] Accordingly, there is a need for improved methods of estimating the characteristics of semiconductor devices that are capable of more accurately estimating the characteristics of semiconductor devices and / or being executed more quickly and / or having a lower computational cost. SUMMARY OF THE INVENTION

[0044] A first aspect of the present disclosure provides a method of estimating the characteristics of a semiconductor device. The method includes:

[0045] forming a spatially discretized representation of the semiconductor device including n x layers;

[0046] initializing a first system of equations based on one or more parameters associated with the spatially discretized representation of the semiconductor device, wherein the first system of equations represents the characteristics of the semiconductor device, wherein each equation in the first system of equations represents layer i, where i = (1, 2,... n x-1 , n x ), and includes one or more matrix blocks H i,j , where j = (1, 2,... n x-1 , n x ), and wherein each matrix block represents any one of the following:

[0047] one or more interactions within layer i, or

[0048] one or more interactions between layer i and an adjacent layer to layer i in the spatially discretized representation;

[0049] applying cyclic reduction to the first system of equations to obtain a second system of equations;

[0050] determining the solution of the second system of equations; and

[0051] estimating the characteristics of the semiconductor device based on the solution of the second system of equations.

[0052] Another aspect of the present disclosure provides a method for determining entries of an N x N matrix B, where the matrix B is the inverse of an N x N matrix A. The method includes:

[0053] For each entry of B, form a representation of that entry of B that includes one or more binary variables;

[0054] Based on the representation of the entry of B, form N 2 linear equality constraints representing A·B = I, where I is an N x N identity matrix;

[0055] Based on the N 2 linear equality constraints, formulate a quadratic unconstrained binary optimization QUBO problem;

[0056] Execute the QUBO problem on a quantum computing device to obtain a set of values of the binary variables; and

[0057] Use the set of values of the binary variables to determine the entry of the matrix B.

[0058] Another aspect of the present disclosure provides a method for determining entries of an N x N matrix B for use in a method of estimating characteristics of a semiconductor device, where the matrix B is the inverse of an N x N matrix A, and where the entries of the matrix A represent interactions within a layer of a spatially discretized representation of the semiconductor device. The method includes:

[0059] For each entry of B, form a representation of that entry of B that includes one or more binary variables;

[0060] Based on the representation of the entry of B, form N 2 linear equality constraints representing A·B = I, where I is an N x N identity matrix;

[0061] Based on the N 2 linear equality constraints, formulate a quadratic unconstrained binary optimization QUBO problem;

[0062] Execute the QUBO problem on a quantum computing device to obtain a set of values of the binary variables; and

[0063] Use the set of values of the binary variables to determine the entry of the matrix B.

[0064] Yet another aspect of the present disclosure provides an apparatus for estimating characteristics of a semiconductor device. The apparatus is configured to:

[0065] Form a spatially discretized representation of the semiconductor device that includes n x layers;

[0066] Initialize a first system of equations based on one or more parameters related to the spatially discretized representation of the semiconductor device, where the first system of equations represents the characteristics of the semiconductor device, and where each equation in the first system of equations represents layer i, where i = (1, 2, … n x-1 , n x ), and includes one or more matrix blocks H i,j , where j = (1, 2, … n x-1 , n x ), and where each matrix block represents any one of the following:

[0067] One or more interactions within layer i, or

[0068] One or more interactions between layer i and the layer adjacent to layer i in the spatially discretized representation;

[0069] Apply cyclic reduction to the first system of equations to obtain a second system of equations;

[0070] Determine the solution of the second system of equations; and

[0071] Estimate the characteristics of the semiconductor device based on the solution of the second system of equations.

[0072] Another aspect of the present disclosure provides an apparatus for determining the entries of an N x N matrix B, where the matrix B is the inverse of an N x N matrix A. The apparatus is configured to:

[0073] For each entry of B, form a representation of that entry of B including one or more binary variables;

[0074] Based on the representation of the entry of B, form N 2 linear equality constraints representing A·B = I, where I is an NxN identity matrix;

[0075] Based on the N 2 linear equality constraints, formulate a quadratic unconstrained binary optimization (QUBO) problem;

[0076] Execute the QUBO problem on a quantum computing device to obtain a set of values of the binary variables; and

[0077] Use the set of values of the binary variables to determine the entry of matrix B.

[0078] Another aspect of the present disclosure provides a data processing apparatus for determining entries of an N×N matrix B for use in a method of estimating characteristics of a semiconductor device, where the matrix B is the inverse of an N×N matrix A, and where the entries of the matrix A represent interactions within a layer of a spatially discretized representation of the semiconductor device. The data processing apparatus is configured to:

[0079] For each entry of B, form a representation of that entry of B that includes one or more binary variables;

[0080] Based on the representation of the entry of B, form N 2 linear equality constraints representing A·B = I, where I is an N×N identity matrix;

[0081] Based on the N 2 linear equality constraints, formulate a quadratic unconstrained binary optimization (QUBO) problem;

[0082] Execute the QUBO problem on a quantum computing device to obtain a set of values of the binary variables; and

[0083] Use the set of values of the binary variables to determine the entries of the matrix B. BRIEF DESCRIPTION OF THE DRAWINGS

[0084] To better understand examples of the present disclosure and to more clearly show how these examples may be implemented, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0085] Figure 1 A method 100 of estimating characteristics of a semiconductor device is shown;

[0086] Figure 2 An example of a spatially discretized representation of a semiconductor device 200 including a plurality of layers 208a…208e is shown;

[0087] Figure 3a The matrix structure of a matrix H of Equation 3 is shown;

[0088] Figure 3b The matrix structure of the matrix H obtained after performing the first stage of the BCR method is shown;

[0089] Figure 3c The matrix structure of the matrix H obtained after performing the second stage of the BCR method is shown;

[0090] Figure 4 A method 400 of determining entries of an N×N matrix B, where the matrix B is the inverse of an N×N matrix A, is shown;

[0091] Figure 5Method 500 for determining entries of an N x N matrix B for use in a method of estimating characteristics of a semiconductor device is shown, where matrix B is the inverse of an N x N matrix A and where entries of matrix A represent interactions between coupled layers of a spatially discretized representation of the semiconductor device;

[0092] Figure 6 Method 600 for simulating a semiconductor device is shown;

[0093] Figure 7 An initial potential distribution of a resonant tunneling device is shown;

[0094] Figure 8a Root mean square errors of different types of 1 energy are shown;

[0095] Figure 8b Root mean square errors of different types of 2 energy are shown;

[0096] Figure 9a Wave functions of an RTD for a 10th type of 2 energy obtained using a linear equation solver are shown;

[0097] Figure 9b Wave functions of an RTD for a 10th type of 2 energy obtained using a conventional BCR method are shown;

[0098] Figure 9c Wave functions of an RTD for a 10th type of 2 energy obtained using an additional layer BCR method are shown;

[0099] Figure 10 Speed improvements of the full matrix method compared to the unit vector method are shown;

[0100] Figure 11 Embedding overheads of the full matrix method compared to the unit vector method are shown;

[0101] Figure 12 Qubit requirements for both the full matrix method and the unit vector method are shown;

[0102] Figure 13 Resource efficiencies of both the full matrix method and the unit vector method are shown;

[0103] Figure 14 A schematic diagram of an example of apparatus 1400 for estimating characteristics of a semiconductor device is shown;

[0104] Figure 15 A schematic diagram of an example of apparatus 1500 for entries of an N x N matrix B, where matrix B is the inverse of an N x N matrix A; and

[0105] Figure 16It is a schematic diagram of an example of a data processing apparatus 1600 for determining entries of an N×N matrix B for use in a method of estimating characteristics of a semiconductor device, where the matrix B is the inverse of an N×N matrix A and where the entries of the matrix A represent interactions within a layer of a spatially discretized representation of the semiconductor device. Detailed Description

[0106] For purposes of explanation and not limitation, specific details are set forth, such as specific embodiments or examples. Those skilled in the art will appreciate that other examples may be employed in addition to these specific details. In some instances, detailed descriptions of well-known methods, nodes, interfaces, circuits, and devices are omitted so as not to obscure the description with unnecessary detail. Those skilled in the art will appreciate that the described functionality may be implemented in one or more nodes using hardware circuits (e.g., analog and / or discrete logic gates interconnected to perform a dedicated function, ASICs, PLAs, etc.) and / or using software programs and data in conjunction with one or more digital microprocessors or general purpose computers. Nodes that communicate using an air interface also have appropriate radio communication circuitry. Additionally, in appropriate instances, the technology may additionally be considered to be fully contained in any form of computer-readable memory, such as solid-state memory, magnetic disk, or optical disk, that contains an appropriate set of computer instructions to cause a processor to perform the technology described herein.

[0107] Hardware implementations may include or incorporate, but are not limited to, digital signal processor (DSP) hardware; reduced instruction set processors; hardware (e.g., digital or analog) circuits, including but not limited to application specific integrated circuits (ASICs) and / or field programmable gate arrays (FPGAs); and (where appropriate) state machines capable of performing such functions.

[0108] Embodiments of the present disclosure relate to improved methods of estimating characteristics of semiconductor devices. Some embodiments herein are directed to more accurately estimating characteristics of semiconductor devices. Some embodiments herein are directed to reducing the execution time of estimating characteristics of semiconductor devices.

[0109] In particular, some embodiments relate to methods of estimating characteristics of semiconductor devices that employ cyclic reduction methods that select additional layers of the semiconductor device to remain coupled to a first layer and a last layer of the semiconductor device. This then enables reconstruction of a solution based on solutions determined for the additional layers of the semiconductor device and solutions determined for the first layer and the last layer, respectively, thereby improving the accuracy of the obtained solution.

[0110] In particular, some embodiments improve the accuracy of solutions obtained for discretized Schrödinger equations of semiconductor devices.

[0111] Some embodiments relate to methods of accelerating the use of a quantum computing device to determine the entries of an N x N matrix B, where matrix B is the inverse of an N x N matrix A. The speed at which these embodiments determine the inverse of an N x N matrix A can be approximately three times faster than prior art methods (see

[11] ).

[0112] These methods can be used as part of the methods described for estimating the characteristics of a semiconductor device. For example, these accelerated methods of determining the entries of an N x N matrix B (where matrix B is the inverse of an N x N matrix A) can be used as part of the cyclic reduction method in the method of estimating the characteristics of a semiconductor device.

[0113] Figure 1 Method 100 for estimating the characteristics of a semiconductor device is shown.

[0114] In step 102, method 100 includes: forming a spatial discretized representation of a semiconductor device including n x layers.

[0115] In some embodiments, each layer of the spatial discretized representation of the semiconductor device includes one or more nodes. An example of the spatial discretized representation of the semiconductor device is shown in Figure 2 .

[0116] In some embodiments, forming the spatial discretized representation of the semiconductor device includes: using the finite element method. In some embodiments, using the finite element method to form the spatial discretized representation of the semiconductor device includes: using rectangular grid cells, where each rectangular grid cell represents a spatial portion of the device.

[0117] In step 104, method 100 includes: initializing a first system of equations based on one or more parameters associated with the spatial discretized representation of the semiconductor device, where the first system of equations represents the characteristics of the semiconductor device, where each equation in the first system of equations represents layer i, where i = (1, 2,... n x-1 , n x ), and includes one or more matrix blocks H i,j , where j = (1, 2,... n x-1 , n x ), and where each matrix block represents any of the following:

[0118] · one or more interactions within layer i, or

[0119] · one or more interactions between layer i and an adjacent layer in the spatial discretized representation to layer i.

[0120] That is, the first system of equations represents each layer of the spatial discretized representation of the semiconductor device as being coupled to adjacent layers of that layer.

[0121] In some embodiments, the first set of equations includes the two-dimensional Schrödinger equation for the spatially discretized representation of a semiconductor device. In these embodiments, for a layer of the spatially discretized representation of the semiconductor device, the first set of equations includes the Schrödinger equation initialized for that layer. In these embodiments, the property may include the wave function in the semiconductor device.

[0122] For example, a first set of equations including the Schrödinger equation initialized for each layer in the spatially discretized representation of a semiconductor device may be represented as follows:

[0123]

[0124] In this example, each layer in the spatially discretized representation includes n z nodes. Thus, in this example, the elements in the matrix of Equation 3 are themselves matrices of size n z x n z (corresponding to the n z nodes included within each of these layers). In this example, each diagonal element in Equation 3 describes the interaction within a layer of the spatially discretized representation. For example, the element describes the interaction within layer 1 of the spatially discretized representation. In this example, each non-diagonal element in Equation 3 describes the interaction between adjacent layers of the spatially discretized representation. For example, the element describes the interaction between layer 1 and layer 2 of the spatially discretized representation.

[0125] In some embodiments, if the first set of equations includes the two-dimensional Schrödinger equation for the spatially discretized representation of a semiconductor device, then initializing the first set of equations based on one or more parameters related to the spatially discretized representation of the semiconductor device may include initializing the first set of equations based on one or more of the following: one or more modes injected into the device; the self-energy of the device.

[0126] In some embodiments, if the first set of equations includes the two-dimensional Schrödinger equation for the spatially discretized representation of a semiconductor device, then the property of the semiconductor device represented by the first set of equations includes the wave function of the semiconductor device.

[0127] For example, in Equation 3, the wave function of the semiconductor device is represented by the vector Φ. Each entry of the vector Φ then corresponds to the wave function of a particular layer of the semiconductor device (e.g., Φ 1 represents the wave function in layer 1 of the semiconductor device).

[0128] As described above, each equation in the first set of equations represents a layer of the spatially discretized representation of the semiconductor device. Thus, for each equation in the first set of equations, the equation is solved such that the characteristics in the corresponding layer of the semiconductor device can be determined.

[0129] In some embodiments, the first set of equations includes the two-dimensional Poisson equation for the spatially discretized representation of the semiconductor device. In these embodiments, for the layers of the spatially discretized representation of the semiconductor device, the first set of equations includes the Poisson equation initialized for that layer. In these embodiments, the characteristics of the semiconductor device may include the electrostatic potential in the semiconductor device.

[0130] In step 106, method 100 includes: applying the cyclic reduction method to the first set of equations to obtain a second set of equations.

[0131] In some embodiments, the cyclic reduction method may include the block cyclic reduction method.

[0132] As described above, applying the cyclic reduction method to the first set of equations reduces the first set of equations to a number of smaller sub-problems (the second set of equations). Then the solutions of these smaller sub-problems can be obtained, and then these solutions can be used to reconstruct the solution of the initial problem (represented by the first set of equations).

[0133] Therefore, applying the cyclic reduction method to the first set of equations to obtain the second set of equations reduces the computational complexity of method 100 and / or enables the use of parallel computing and / or quantum computing methods to obtain the solution of the first set of equations.

[0134] As described above, each layer of the spatially discretized representation of the semiconductor device is represented by the first set of equations as being coupled to the adjacent layers of that layer. For example, for the spatially discretized representation of a semiconductor device including 5 layers, the first set of equations may represent: layer 1 is coupled to layer 2; layer 2 is coupled to layer 1 and layer 3; layer 3 is coupled to layer 2 and layer 4; layer 4 is coupled to layer 3 and layer 5; and layer 5 is coupled to layer 4.

[0135] In some embodiments, applying the cyclic reduction method to the first set of equations decouples one or more layers of the spatially discretized representation of the semiconductor device to obtain the second set of equations. That is, the second set of equations represents only some of the layers of the spatially discretized representation of the semiconductor device that are coupled to each other.

[0136] For example, the second set of equations may represent the spatially discretized representation of the semiconductor device, where only the first layer and the last layer of the spatially discretized representation of the semiconductor device are coupled to each other. For example, considering the spatially discretized representation of a semiconductor device including 5 layers, the second set of equations may represent: layer 1 is coupled to layer 5; and layer 5 is coupled to layer 1.

[0137] In other words, applying the cyclic reduction method to the first set of equations allows obtaining a second set of equations, where the first set of equations represents each layer of the spatially discretized representation of the semiconductor device as being coupled to adjacent layers thereof, and where the second set of equations represents only some of the layers of the spatially discretized representation of the semiconductor device as being coupled to each other.

[0138] An example of applying the cyclic reduction method to the first set of equations to decouple one or more layers of the spatially discretized representation of the semiconductor device is described with reference to FIG. 3.

[0139] At step 108, method 100 includes: determining a solution to the second set of equations.

[0140] For example, determining a solution to the second set of equations may include: determining one or more entries of a solution vector of the first set of equations. The one or more entries of the solution vector correspond to layers of the semiconductor device that are represented as being coupled in the second set of equations.

[0141] At step 110, method 100 includes: estimating characteristics of the semiconductor device based on the solution to the second set of equations.

[0142] For example, estimating characteristics of the semiconductor device based on the solution to the second set of equations may include: reconstructing the remaining entries of the solution vector based on the one or more determined entries of the solution vector. In this example, the solution vector represents characteristics of the semiconductor device.

[0143] An example of reconstructing the remaining entries of the solution vector based on the one or more determined entries of the solution vector is described with reference to FIG. 3.

[0144] In some embodiments, method 100 further includes: using the estimated characteristics of the semiconductor device to estimate one or more other characteristics of the semiconductor device. For example, in embodiments where the wave function of the semiconductor device is estimated, the obtained wave function can then be used to estimate the electrostatic potential in the semiconductor device (as described in reference Figure 6 ).

[0145] In some embodiments, method 100 further includes: using the one or more other estimated characteristics of the semiconductor device to estimate one or more characteristics of a circuit including the semiconductor device. In some embodiments, method 100 further includes: using the estimated characteristics of the semiconductor device during a design process. For example, in some embodiments, using the estimated characteristics of the semiconductor device during a design process may include: adjusting the design of the semiconductor device and / or adjusting a circuit including the semiconductor device based on the estimated characteristics.

[0146] In some embodiments, characteristics of the semiconductor device are estimated in a method of simulating the semiconductor device and / or a circuit including the semiconductor device. That is, method 100 can be used in a simulation method (e.g., as described in referenceFigure 6 Estimate the characteristics of a semiconductor device in the described method 600).

[0147] Now describe an example method for initializing the first set of equations (i.e., an example implementation of step 104 of method 100).

[0148] Figure 2 An example of a spatially discretized representation of a semiconductor device 200 including multiple layers 208a…208e is shown.

[0149] The spatially discretized representation of semiconductor device 200 includes leads 202 and 204 respectively representing a source contact and a drain contact.

[0150] The spatially discretized representation of semiconductor device 200 includes multiple nodes (e.g., node 206a represented by index (1,1)), and these nodes are grouped to represent the layers 208a, 208b, 208c, 208d, 208e of the spatially discretized representation of semiconductor device 200.

[0151] In some embodiments described herein, the Schrödinger equation and / or Poisson equation are solved for each layer included within the spatially discretized representation of semiconductor device 200.

[0152] Taking the Schrödinger equation as an example, the two-dimensional Schrödinger equation for the spatially discretized representation of a semiconductor device can be expressed as the following first set of equations:

[0153]

[0154] This two-dimensional Schrödinger equation for the spatially discretized representation of a semiconductor device is obtained using rectangular grid cells and "vertical" ordering, as described in more detail below.

[0155] The elements in the matrix are themselves matrices of size n z x n z For each layer among layers 208a…208e of the spatially discretized representation of semiconductor device 200, these matrices correspond to the nodes included within that layer. These matrices are obtained using the finite element method with uniform rectangular grid cells.

[0156] The diagonal elements in Equation 3 describe the interactions within the layer of the spatially discretized representation of semiconductor device 200, while the off-diagonal elements describe the interactions between adjacent layers of the spatially discretized representation of semiconductor device 200. In this example, the diagonal elements in H have been denoted as H i,i (e.g., ), while the off-diagonal elements in H have been denoted as H i,±i (e.g., ).

[0157] The structure of Equation 3 can be obtained from Equation 1 as follows.

[0158] Except for the open boundary conditions Σ L and Σ R each row in H in Equation 1 has at most five non-zero elements, and it can be written in the following form

[0159] (Hφ) ij = a ij u ij - b ij u i-1j - c ij u i+1j - d ij u ij-1 - e ij u ij+1 (4)

[0160] where i = 1, …, n z and j = 1, …, n x represent two-dimensional spatial positions in the discretization (i.e., represent nodes), a ij describes the site energy at the corresponding node, b ij and c ij describe the interaction with adjacent sites in the z direction, while d ij and e ij describe the interaction with adjacent sites in the x direction.

[0161] The two-dimensional index ij is then mapped to a one-dimensional index i. Multiple different orderings (e.g., using natural ordering or using red-black ordering) can be used to map the index in this way. It will be understood that using different mappings will provide different structures for the matrix H in Equation 3.

[0162] In the example shown, the following ordering is adopted.

[0163] l(i,j) = i + (j - 1)·n z (5)

[0164] This mapping enables Equation 1 to be written in the block tri-diagonal form shown in Equation 3 and enables the block cyclic reduction method to be performed on the resulting block tri-diagonal matrix.

[0165] As described above, this ordering is a vertical ordering, mapping from the top to the bottom of each layer of the semiconductor device one layer at a time.

[0166] This ordering provides the following structure for the H matrix. Consider any row r(I,j)

[0167]

[0168] Among them, those corresponding to -d r , -b r , a r and e r have column indices r - n z , r - 1, r, r + 1, and r + n z respectively. In matrix format, ignoring any open boundary conditions, any row can be written as:

[0169]

[0170] This matrix is a block tridiagonal matrix and can be written as shown in Equation 3.

[0171] Therefore, the block matrix shown in Equation 3 will have the following structure:

[0172]

[0173]

[0174] Then, the system of equations is initialized as follows.

[0175] The values of the matrix elements are calculated using linear shape functions in the finite element method. The open boundary conditions Σ L and Σ R are also calculated according to the QTBM for the n z ×n z matrix.

[0176] When the wave function of the semiconductor device vanishes outside the semiconductor device, there is a Dirichlet boundary condition of 0 at the Γ o boundary (i.e., the boundary of the semiconductor device that does not contact any lead). To implement this boundary condition, the row r corresponding to the boundary can be set to zero, except for the diagonal elements, which are set to 1. Except for the indices related to the device - lead boundary, the injection vector B m will be zero at any position. This process results in inserting the trivial equation 1·Φ r = 0 at each boundary index into the system. However, these trivial equations are deleted before solving the system of equations to avoid unnecessary calculations and to maintain the matrix structure H as shown in Equation 3.

[0177] Now, an example method of applying the cyclic reduction method to the first system of equations to obtain a second system of equations will be described with reference to Figure 3. That is, an example implementation of step 106 of method 100 will be described with reference to Figure 3.

[0178] In this example, the cyclic reduction method is applied to the first system of equations, as shown in Equation 3.

[0179] Figure 3a Shows the matrix structure of matrix H of Equation 3. Figure 3b Shows the matrix structure of matrix H obtained after performing the first stage of the BCR method. Figure 3c Shows the matrix structure of matrix H obtained after performing the second stage of the BCR method. For Figures 3a - 3c each of, dots are used to indicate non-zero matrix elements.

[0180] In the first stage of the BCR method, layer 2 of the semiconductor device is decoupled as follows.

[0181] Since layer 1 and layer 3 are the layers of the semiconductor device to which layer 2 is currently coupled, the blocks H 1,1 、H 3,3 、H 3,1 and H 1,3 are "renormalized" as follows:

[0182]

[0183] Layer 4 of the semiconductor device is also decoupled in the first stage, as shown below.

[0184] Since layer 3 and layer 5 are the layers of the semiconductor device to which layer 4 is currently coupled, the blocks H 3,3 、H 5,5 、H 5,3 and H 3,5 are "renormalized" as follows:

[0185]

[0186] Thus, in some embodiments, applying the cyclic reduction method to the first set of equations to obtain a second set of equations includes:

[0187] For one or more layers represented by spatial discretization:

[0188] For layer i, where layer i is coupled to layer i-l and layer i+r:

[0189] Renormalize the matrix blocks H i-l,i 、H i+r,i 、H i,i-l and H i,i+r of the first set of equations.

[0190] In some embodiments, the steps of renormalizing the matrix blocks H i-l,i 、H i+r,i 、H i,i-l and H i,i+r include:

[0191] Determine the matrix block Hi,i the inverse matrix; and

[0192] Based on the determined one or more inverse matrices, for matrix blocks H i-l,i 、H i+r,i 、H i,i-l and H i,i+r perform re-normalization.

[0193] In this example, after performing the first stage of the BCR method, a system of equations (as shown in Figure 3b ) is obtained, which represents layers 1, 3, and 5 of the semiconductor device as being coupled to each other. In other words, after performing the first stage of the BCR method, layers 2 and 4 of the semiconductor device are decoupled from the other layers of the semiconductor device.

[0194] In this embodiment, the first stage only processes the inversion of sparse tridiagonal matrices. Since it is easier to invert sparse matrices compared to full-rank matrices (which are introduced in other decoupling stages, as shown in Figure 3b ), that is, decoupling the layers will introduce full-rank matrices in the layers that the decoupled layers were previously coupled to), it is desirable to decouple as many layers as possible in the first stage.

[0195] Therefore, in some embodiments, re-normalization of the matrix blocks for one or more layers is first performed for one or more even-indexed layers among the one or more layers represented by spatial discretization. This step can be performed in parallel for each of the one or more even-indexed layers because these layers are not connected to each other.

[0196] In the second stage of the BCR method, layer 3 of the semiconductor device is decoupled, as shown below.

[0197] Since layers 1 and 5 are the layers of the semiconductor device to which layer 3 is currently coupled, the blocks H 1,1 、H 5,5 、H 5,1 and H 1,5 are "re-normalized" as follows:

[0198]

[0199] In some embodiments, after re-normalizing the matrix blocks for one or more even-indexed layers, re-normalization of the matrix blocks for half of the odd-indexed layers among the one or more layers represented by spatial discretization is performed. This step can be performed in parallel for each of the half of the odd-indexed layers because these layers are not connected to each other.

[0200] In some embodiments, it includes: renormalizing matrix blocks of remaining layers in one or more layers for spatially discretized representation. That is, although stage 2 of FIG. 3 is the last stage of the BCR method described with reference to FIG. 3, for semiconductor devices including more layers, BCR can include a third stage. Note that this step cannot be executed in parallel for the remaining layers because the remaining layers are connected to each other.

[0201] In this example, after executing the second stage of the BCR method, a second set of equations (as Figure 3c shown) is obtained, which represents only layer 1 and layer 5 of the semiconductor device as being coupled to each other. In other words, after executing the second stage of the BCR method, layer 3 of the semiconductor device is decoupled from the other layers of the semiconductor device.

[0202] Therefore, in some embodiments, one or more layers of the spatially discretized representation include all layers of the spatially discretized representation except layer 1 and layer n x thereafter.

[0203] In some embodiments, determining one or more inverse matrices includes: determining one or more inverse matrices according to method 400 or method 500 described below.

[0204] In the illustrated embodiment, the first layer and the last layer are not decoupled. Note that Figure 3a the first matrix block and the last matrix block are the only full-rank complex blocks due to the open boundary conditions. Therefore, decoupling the first layer and the last layer in the early stage of the BCR method will introduce complex numbers during the decoupling process. Complex arithmetic is four times slower than real arithmetic. Therefore, by not decoupling the first layer and the last layer, complex arithmetic is not introduced in the BCR method, thus reducing the execution time of this method.

[0205] Also note that one of the first layer or the last layer will have a non-zero injection vector and should not be decoupled.

[0206] Considering Equation 3, one difference between the block cyclic reduction method described in [9] and the block cyclic reduction method described with reference to FIG. 3 is that these block cyclic reduction methods are applied to matrices with different structures.

[0207] In [9], the matrix to which the block cyclic reduction method is applied includes diagonal matrix blocks, where each of these matrix blocks is also diagonal (an example of this structure is shown in Figure 1

[10] ). This matrix structure is generated because the matrix in [9] does not include any elements representing the connections between sites (nodes) in each layer of the semiconductor device.

[0208] Therefore, in [9], X can be easily calculatedi and Y i matrices because they only require the calculation of the inverse of a diagonal matrix.

[0209] In contrast, for the rectangular grid discretization of the Schrödinger equation (e.g., Equation 3), the BCR method is applied to a sparse linear system where the diagonal matrix blocks are not diagonal, and thus, performing the BCR method requires the calculation of a computationally intensive matrix inverse.

[0210] As Figure 3a shown, the execution of the first step of the BCR method described herein requires the calculation of the inverse of a tridiagonal matrix. Also note that for the BCR method described herein, full-rank matrices are introduced in the calculations at all stages of the BCR method. In [9], matrices are only introduced in the calculations at the last stage of the BCR method.

[0211] As described above, after the execution of the second stage of the BCR method described herein, a 2n z × 2n z system of linear equations is obtained.

[0212] The 2n z × 2n z system of linear equations can then be solved to determine the entries Φ of the solution vector φ 1 and In this example, the 2n Figure 3c × 2n z × 2n z system of linear equations shown in

[0213] can then be solved to obtain the entries 1 and 5 of the solution vector. i The remaining part of the solution vector Φ can then be reconstructed for each entry Φ using the following equation:

[0214] Φ i = -X i Φ i-l - Y i Φ i+r (2g)

[0215] where Φ i-l and Φ i+r are the entries of the solution vector corresponding to the layer to which layer i was previously coupled before being decoupled at layer i. That is, the entry Φ i is reconstructed based on the layer to which layer i was coupled before decoupling layer i. For this example, the entry 3 of the solution vector will be reconstructed based on the entries 1 and 5 of the solution vector, the entry 2 of the solution vector will be reconstructed based on the entries 1 and 3 of the solution vector, and the entry 4 of the solution vector will be reconstructed based on the entries 3 and 5 of the solution vector.

[0216] Thus, in some embodiments, determining the solution of the second system of equations includes:

[0217] Solving the second system of equations to obtain the entry i = 1 of the solution vector and the entry i = n of the solution vector x , wherein the first system of equations includes the solution vector.

[0218] Thus, in some embodiments, determining the solution of the second system of equations further includes: reconstructing the remaining entries of the solution vector other than entries 1 and n x thereof.

[0219] However, note that in the reconstruction phase of the BCR method, if the solutions Φ 1 and in the first and last layers of the semiconductor device (i.e., the two layers where the re-coupling phase starts) are equal to zero, it is impossible to reconstruct a non-zero solution. Also note that if the solutions Φ 1 and in the first and last layers of the semiconductor device are much smaller than the remaining solutions (the solutions that the re-coupling phase aims to reconstruct), the accuracy of the BCR method may be affected.

[0220] Specific embodiments herein attempt to overcome these problems by utilizing the BCR method that obtains a second system of equations representing the first, last, and an additional layer of the semiconductor device as being coupled.

[0221] In other words, specific embodiments herein utilize the BCR method that retains the additional layer of the semiconductor device in the decoupling phase.

[0222] In some embodiments, the additional layer is selected based on the probability that the solution for the additional layer will be similar in magnitude to the solution for the semiconductor device. Since the solution for the device can then be reconstructed based on the solution for the additional layer, this improves the accuracy of the solution obtained for the device. Thus, in some embodiments, method 100 further includes: selecting another layer of the spatial discretization representation.

[0223] In some embodiments, the additional layer is selected from the final decoupling phase of the BCR method. For example, considering the example shown in FIG. 3, if layer 3 is selected as the additional layer, then phase 1 will become the last phase of the BCR method.

[0224] Thus, in some embodiments, determining the solution of the second system of equations includes:

[0225] Solving the second system of equations to obtain the entry i = 1 of the solution vector, the entry i = n of the solution vector x , and the entry of the solution vector having an index corresponding to the index of another layer, wherein the first system of equations includes the solution vector.

[0226] Thus, in some embodiments, determining the solution of the second set of equations further comprises: reconstructing the remaining entries of the solution vector except for entries 1 and n x and the entries of the solution vector having indices corresponding to the indices of another layer.

[0227] In embodiments where the first set of equations includes the two-dimensional Schrödinger equation for a spatially discretized representation of a semiconductor device, the additional layer can be selected based on the magnitude of the wave function in the additional layer of the semiconductor device. For example, the additional layer can be selected such that: the magnitude of the wave function of the additional layer is non-negligible, the magnitude of the wave function of the additional layer corresponds to the magnitude of the wave function of the semiconductor device, the wave function of the additional layer belongs to the mode of the wave function of the semiconductor device, and the magnitude of the wave function of the additional layer corresponds to the magnitude of one of the modes of the wave function of the semiconductor device.

[0228] Thus, in some embodiments, the step of selecting another layer comprises selecting another layer based on:

[0229] the magnitude of the wave function of the spatially discretized representation of the semiconductor device, and

[0230] the magnitude of the wave function of the other layer.

[0231] Note that for embodiments where the additional layer is retained during the decoupling phase, performing the final stage of the BCR method will result in obtaining a 3n z × 3n z system of linear equations, which can then be solved to determine the entries of the solution vector corresponding to the first layer, the last layer, and the additional layer of the semiconductor device.

[0232] As described above, the most time-consuming part of the BCR method is the inversion of the diagonal blocks.

[0233] Now a quantum method is described that attempts to accelerate the calculation of the inverse of a matrix.

[0234] Figure 4 A method 400 for determining the entries of an N x N matrix B is shown, where matrix B is the inverse of an N x N matrix A. Method 400 can be used to determine one or more inverse matrices according to the method described above with reference to FIG. 3 (i.e., according to the method implementing step 106 of method 100).

[0235] In some embodiments, method 400 utilizes an objective function based on the following expression (as will be explained in more detail below):

[0236] ‖A·B - I‖

[0237] where I is the identity matrix.

[0238] This expression can be written as:

[0239]

[0240] In step 402, method 400 includes: for each entry of B, forming a representation of that entry of B that includes one or more binary variables. That is, method 400 utilizes binary representations of many unknowns. For the accuracy of R qubits, a quantum computing device requires R·N 2 logical qubits to represent R·N 2 binary variables.

[0241] For example, in some embodiments, each representation of each entry b ij of B can include R binary variables as follows:

[0242]

[0243] In these embodiments, Equation 11a can then be expressed as follows:

[0245]

[0246] The binary expansion of the unknown value (in this case b) requires specifying the domain [-d, 2c - d). The smaller the domain, the more accurate the solution obtained using a smaller number of qubits. A very large domain can be specified, but at the expense of the accuracy of the solution. However, based on the solution obtained, a new smaller domain can be specified around the solution obtained. A new more accurate solution can then be calculated using this new domain. Thus, determining the solution in this iterative manner can enable a satisfactory solution to be obtained.

[0247] In some embodiments, the entries of matrix A represent interactions within a layer of a spatially discretized representation of a semiconductor device. For example, A can include the matrix block H of Equation 3 i,i .

[0248] In step 404, method 400 includes: based on the representations of the entries of B, forming N 2 linear equality constraints representing A·B = I, where I is the N x N identity matrix.

[0249] For example, in some embodiments, Equation 11c can be represented as N 2 linear equality constraints as follows:

[0250]

[0251] In step 406, method 400 includes: formulating a quadratic unconstrained binary optimization QUBO problem based on the N 2 linear equality constraints.

[0252] In some embodiments, based on N 2 linear equality constraints, formulating the quadratic unconstrained binary optimization (QUBO) problem using a formula includes: expressing the N 2 linear equality constraints in the form of Cx = b, where x is a binary decision vector including binary variables.

[0253] For example, in some embodiments, the above N 2 constraints can be expressed in the form of Cx = b, where C is a matrix of size N × R·N, and x is a binary decision vector of size R·N 2 as follows:

[0254]

[0255] In some embodiments, based on N 2 linear equality constraints, further formulating the QUBO problem using a formula includes:

[0256] formulating the QUBO matrix Q such that Q = C T C - 2b T C.

[0257] For example, in some embodiments, the QUBO matrix can be obtained as follows:

[0258] E = (Cx - b) 2

[0259] = x T C T Cx + b T b - 2b T Cx

[0260] Since b T b is the same for all combinations, it can be ignored so that:

[0261] E ≈ x T C T Cx - 2b T Cx

[0262] When x ∈ {0, 1}x 2 = x, then b T Cx = x T b T Cx:

[0263] E ≈ x T [C T C]x - x T 2b T Cx

[0264] E ≈ xT [C T C-2b T C]x

[0265] Thus, the QUBO is formulated as:

[0266] Q = C T C-2b T C (13)

[0267] That is, in some embodiments, the QUBO formulation for calculating the matrix inverse B using a quantum annealing process is obtained by the following operations: for each unit vector of the identity matrix I = A·B and the associated unknown column vector B of the inverse matrix B i the corresponding system of linear equations is converted into a block diagonal system of linear equations Cx = b by taking the direct sum, and the difference between the product of the block diagonal matrix C and its transpose and the product of b and the transpose of C is calculated.

[0268] At step 408, method 400 includes: performing a QUBO problem on a quantum computing device to obtain a set of values for the binary variables.

[0269] In some embodiments, performing a QUBO problem on a quantum computing device to obtain values for the binary variables includes:

[0270] manipulating the quantum states of the qubits of the quantum computing device based on the QUBO matrix Q;

[0271] obtaining a measurement for each of one or more qubits; and

[0272] determining a set of values for the binary variables based on the obtained measurements.

[0273] In some embodiments, the measured states of the qubits of the quantum computing device correspond to the solution of the binary decision vector x.

[0274] In some embodiments, performing a QUBO problem on a quantum computing device includes: performing a quantum annealing process. In other embodiments, performing a QUBO problem on a quantum computing device may include: performing a quantum approximate optimization algorithm on a gate model quantum computer.

[0275] At step 410, method 400 includes: using the set of values for the binary variables to determine the entries of matrix B.

[0276] For example, in some embodiments, the determined set of values for the binary variables is used to reconstruct the entries of matrix B based on the representation of the formed entries of B.

[0277] Thus, the method 400 can calculate the inverse of matrix A by embedding the above QUBO problem on a quantum computing device and performing one annealing process. In contrast, the method described in

[11] requires performing N annealing and embedding processes to determine the inverse of matrix A. Therefore, the method 400 is approximately three times faster than the prior art methods.

[0278] In some embodiments, the method 400 is used in a method for estimating characteristics of a semiconductor device (such as the method 100 described above). In some embodiments, the characteristics include a wave function in the semiconductor device. In some embodiments, the characteristics include an electrostatic potential in the semiconductor device.

[0279] In some embodiments, the method 400 is used in a method for simulating a semiconductor device and / or a circuit including the semiconductor device. For example, the method 400 can be used in the method 600 for simulating a semiconductor device described below.

[0280] In some embodiments, the method 400 is executed on a data processing device.

[0281] Figure 5 A method 500 for determining entries of an N×N matrix B for use in a method for estimating characteristics of a semiconductor device, which is executed on a data processing device, is shown, where matrix B is the inverse of the N×N matrix A, and where the entries of matrix A represent interactions within a coupling layer of a spatially discretized representation of the semiconductor device. The method 500 is an example of an embodiment of the method 400 described above.

[0282] In step 502, the method 500 includes: for each entry of B, forming a representation of that entry of B including one or more binary variables.

[0283] In step 504, the method 500 includes: based on the representation of the entries of B, forming N 2 linear equality constraints representing A·B = I, where I is the N×N identity matrix.

[0284] In step 506, the method 500 includes: formulating a quadratic unconstrained binary optimization QUBO problem based on the N 2 linear equality constraints.

[0285] In step 508, the method 500 includes: executing the QUBO problem on a quantum computing device to obtain a set of values of the binary variables.

[0286] In step 510, the method 500 includes: using the set of values of the binary variables to determine the entries of matrix B.

[0287] Thus, in some embodiments, the “quantum accelerated block cyclic reduction” method described herein (i.e., using Method 100 in combination with Method 400 or 500) can be utilized to estimate the wave function of a semiconductor device. The estimated wave function(s) can then be used to estimate the steady-state characteristics (e.g., current-voltage characteristics, charge density, current density) of a two-dimensional nanoscale semiconductor device, as referenced Figure 6 as described.

[0288] Figure 6 Method 600 for simulating a semiconductor device is shown. Method 600 can utilize Method 100 described above to estimate the characteristics of a semiconductor device, and can utilize Method 400 and 500 to determine the entries of an N x N matrix B, where matrix B is the inverse of an N x N array A.

[0289] In this embodiment, the simulation is performed in the two-dimensional x (transport)-z (confining) plane of the semiconductor device using the effective mass approximation, thereby restricting the calculation to the first conduction band of silicon, and using six equivalent elliptical valleys to approximate the (conduction) band minimum. A translational minimum is assumed in the y direction (out-of-plane) since this embodiment involves wide devices. For simplicity, ballistic transport is also assumed, and thus scattering is not considered. Ballistic transport can be considered an analysis of the “best case” of semiconductor device behavior.

[0290] In this embodiment, the Schrödinger equation and the Poisson equation are solved self-consistently to determine the electrical behavior of the device. Thus, performing Method 600 enables the estimation of one or more characteristics (e.g., charge distribution, current, wave function, electrostatic potential distribution) of a semiconductor device. The numerical scheme employed in this embodiment includes specific features described in [6, 7].

[0291] In step 602, Method 600 includes: initializing matrices for the Schrödinger equation discretized for the semiconductor device and the Poisson equation discretized for the semiconductor device.

[0292] In step 604, Method 600 includes: setting a new bias for the semiconductor device, and in step 606, Method 600 includes: updating the electric potential of the semiconductor device. For the first execution of this method, the initial electric potential distribution is used in step 606.

[0293] To determine the current-voltage (I-V) curve, Method 600 needs to be executed multiple times to determine the current generated for many applied biases.

[0294] This process can be accelerated through parallelization, thereby allowing the simultaneous calculation of the current generated from different bias points.

[0295] In step 608, Method 600 includes: calculating the energy spectrum of the semiconductor device. Note that the energy is a continuous energy spectrum and, in this embodiment, is discretized in step 608. In this embodiment, the energy is discretized according to the method outlined in [7]. is discretized.

[0296] In this embodiment, the energy spectrum is sampled by applying two different closed boundary conditions (zero-value Dirichlet or Neumann boundary conditions) of the Schrödinger equation at the device-lead interface, and thus the energy spectrum is double-sampled. Two resulting eigenvalue problems are solved, and the eigenvalues in the solutions constitute the injection energy of the open system. energy sampling. This energy spectrum improves the accuracy of the obtained density of states [6]. The eigenfunctions in the eigenvalue problem will have a "cosine-like" or "sine-like" behavior at the Γ s boundary, forming a complete orthonormal basis set spanning the Hilbert space of the physical solutions in the device and obeying the injection boundary conditions of the equilibrium open system. These properties are then utilized when calculating the injection mode vector B m [6].

[0297] In step 610, method 600 includes: calculating the wave vector of the semiconductor device. In this embodiment, using the equations described in [7], the mode energy E is obtained considering an infinite well. m The mode energy is in turn used to calculate the wave vector (for mode "m" in lead i).

[0298] In step 612, method 600 includes: calculating the open boundary conditions for the semiconductor device. For example, QTBM can be used to determine the open boundary conditions.

[0299] In step 614, method 600 includes: solving the discretized Schrödinger equation for the semiconductor device to obtain the wave function of the semiconductor device. In some embodiments, step 614 may include: performing method 600 to estimate the wave function of the semiconductor device. That is, the wave function in the semiconductor device can be obtained by solving the two-dimensional Schrödinger equation for the discretized semiconductor device using the block cyclic reduction method operating on individual layers.

[0300] In step 616, method 600 includes: determining whether the discretized Schrödinger equation for the semiconductor device has been solved for all energies. If the discretized Schrödinger equation for the semiconductor device has been solved for all energies, method 600 proceeds to step 618; otherwise, the method returns to step 610.

[0301] Thus, using the discretized energy spectrum obtained as described above, a wave function φ for the open system containing density of states (DOS) information can be obtained.

[0302] At step 618, method 600 includes: calculating the charge distribution and current of a semiconductor device. The charge distribution can be calculated using the equations provided in [6]. The current can be calculated using the equations provided in [7].

[0303] In this embodiment, after determining the wave function φ for an open system that includes density of states (DOS) information, the electron density n(x,z) and hole charge distribution p(x,z) can be determined according to the equations provided in [6].

[0304] At step 620, method 600 includes: solving the discretized Poisson equation for the semiconductor device to obtain the electrostatic potential distribution in the semiconductor device.

[0305] In this embodiment, after determining the distributions of electrons, holes, and ionized dopants (i.e., the distributions of all charge carriers), the Poisson equation is solved to find the electrostatic potential distribution V in the two-dimensional (x,z) cross-section of the device, which is given by:

[0306]

[0307] where ∈ is the dielectric constant, e is the electron charge, N A is the acceptor concentration, and N D is the donor concentration. The gate potential V GS is included by applying Dirichlet boundary conditions at the domain edges representing the oxide-metal interface. Zero normal derivatives are applied for all other boundaries [6]. This is a computationally less expensive method that addresses the problem of non-physical electron depletion or accumulation at the lead-device interface (which typically occurs at high V DS ).

[0308] For example, Equation 2 can be discretized using the finite element method, where the rectangular grid of the finite element method is the same as the rectangular grid of the two-dimensional Schrödinger equation used to form the spatial discretized representation of the semiconductor device.

[0309] Then a linear system of equations Lv = c can be obtained, where L is an N×N matrix representing the discretized Laplace operator, v is an N×1 column vector representing the unknown potential V, and c is an N×1 column vector representing the known charge ρ(x,z). L will have the same structure as the matrix in Equation 7 and is obtained according to a similar method. Then the elements in the matrix can be calculated using the equation with the dielectric constant replacing the reciprocal mass. In this example, the boundary condition is zero normal derivative, and thus no modification is required to incorporate these conditions. Then the solution of the linear system of equations can be determined using the cyclic reduction method described herein (e.g., method 100).

[0310] Thus, in some embodiments, step 120 may include: performing method 600 to estimate the electrostatic potential distribution in a semiconductor device.

[0311] At step 622, method 600 includes: determining whether convergence has been achieved. For example, if the error between the current potential and the previous potential is less than a predefined threshold, it may be determined that convergence has been achieved.

[0312] If it is determined that convergence has been achieved, the current potential is considered to correctly describe the self-consistent solution of the device [8], the determined current is saved, and method 600 moves to step 624; otherwise, the method moves to step 606, and the potential is updated with the electrostatic potential distribution determined after performing step 620. That is, when the self-consistent solution of the semiconductor device has been determined, the current-voltage characteristics of the semiconductor device are determined.

[0313] At step 624, method 600 includes: determining whether all bias points have been simulated. If it is determined that all bias points have been simulated, method 600 ends; otherwise, the method returns to step 604, where a new bias point is set. Then the method continues to step 606, and the previous self-consistent potential (i.e., the potential at which convergence was previously achieved) is set as the updated potential.

[0314] Thus, when method 600 ends, all bias points have been simulated, and the corresponding currents determined for each bias point can then be plotted as an I-V curve.

[0315] Now describe the advantages of using the "additional layer" BCR method described herein and the quantum annealing process described herein to estimate the characteristics of a semiconductor device.

[0316] Figure 7 The initial potential distribution of a resonant tunneling device is shown.

[0317] Using the initial potential of a resonant tunneling device (RTD) (as Figure 7 shown), the solutions obtained when using the BCR method without an additional layer to solve the discretized Schrödinger equation for the RTD, the solutions obtained when using the BCR method with an additional layer to solve the discretized Schrödinger equation for the RTD, and the solution obtained when solving the discretized Schrödinger equation for the RTD for the initial system of equations (i.e., the "entire linear system" solution) can be compared. In this embodiment, the RTD is 13 nm long and 2 nm high. Two silicon dioxide (SiO₂) layers with a thickness of 0.5 nm define an undoped well region of 2 nm x 2 nm. The cathode and anode, 5 nm long, are doped with a doping concentration N D = 10 20 cm 3 In this embodiment, n x = 130 and nz = 20. Thus, a total of n x × n z = 2600 nodes are used.

[0318] As a measure of the error, the root mean square (RMS) of the wave function is calculated, where the solution of the entire system of linear equations is considered the "correct" solution.

[0319] In this embodiment, only injection from the left lead is considered, and the cutoff energy is set to approximately 1.25 eV, resulting in 32 injection energies. In this embodiment, when using the BCR method with an additional layer to solve the discretized Schrödinger equation for the RTD, the fifth layer of the RTD is used as the additional layer.

[0320] Two standing-wave eigenenergies for which the energy spectrum is discretized are examined separately. The "sine-like" eigenenergy is called type 1 energy, while the "cosine-like" eigenenergy is called type 2 energy. In this embodiment, the wave function is not normalized.

[0321] Figure 8a The root mean square error for different type 1 energies is shown. Figure 8b The root mean square error for different type 2 energies is shown. Figure 9a The wave function of the RTD for the 10th type 2 energy obtained using a linear equation solver is shown. Figure 9b The wave function of the RTD for the 10th type 2 energy obtained using the conventional BCR method is shown. Figure 9c The wave function of the RTD for the 10th type 2 energy obtained using the BCR method with an additional layer is shown.

[0322] As Figure 8a and 8b shown, very similar errors are obtained for almost all type 1 energies, and the performance of the "conventional" BCR method and the "additional layer" BCR method is similar.

[0323] However, as Figure 8b shown, for type 2 energies, the "additional layer" BCR method produces much more accurate solutions for most energies.

[0324] As described above, when using the quantum annealing method to perform matrix inversion, the objective function for the matrix inversion can be constructed in two different ways. In some embodiments, the objective function can be constructed as a full matrix objective function (referred to as the "full matrix solver" as in the cases of methods 400 and 500 described herein), or the matrix inversion can be constructed as a linear least squares QUBO model where the right hand side is the unit vector, as described in

[11] (referred to as the "unit vector solver"). Now discuss the results of comparing these two methods when calculating the matrix inversion of a tridiagonal matrix A, where A is given by:

[0325]

[0326] The structure of matrix A is the same as the matrix decoupled in the first decoupling stage of the BCR method described with reference to FIG. 3. Matrix A is sparse, and thus embedding a binary quadratic model (BQM) on a quantum annealer does not require the same connections as would be required when matrix A is dense. This reduces the number of physical qubits required to embed the model. This property is exploited when embedding the model for the "full matrix solver" which requires more qubits than the "unit vector solver".

[0327] In the unit vector method, the solutions to the BQM created from the LLS objective function are sampled for different right hand side unit vectors. Since the problem is the same for all objective functions (since matrix A is the same each time), the same embedding can be used for each annealing. The only difference is the weights, which are adjusted when calling the sampler for a particular unit vector BQM. That is, the same embedding can be used for all unit vectors. This is beneficial because embedding is a time-consuming task. Since the problem then has to be solved for all unit vectors in the unit vector method, multiple sampling times are obtained. The total sampling time for all samplings is the value provided in Tables 1, 2, and 3.

[0328] Tables 1, 2, and 3 include the embedding and annealing times of the matrix inversion method implemented on a quantum annealer, where 3 qubit precision and 100 annealing cycles are used. The RMS error is calculated for the lowest energy sample. WMS = full matrix solver. UVS = unit vector solver.

[0329] Table 1:

[0330]

[0331] Table 2:

[0332]

[0333]

[0334] Table 3

[0335]

[0336] Tables 1, 2, and 3 include the embedding time, sampling time, number of logical qubits, number of physical qubits, RMS error, and maximum achievable error for selected domains for both the full matrix method and the unit vector method. In this embodiment, the D-Wave Quantum Annealer chip Advantage System 4.1 is used as the sampler. 100 annealing cycles are performed with a qubit precision of 3 qubits.

[0337] Figure 10 Shows the speedup of the full matrix method (referenced in Figure 4 and 5 described) compared to the unit vector method (described in

[11] ). Figure 11 Shows the embedding overhead of the full matrix method compared to the unit vector method.

[0338] Figure 10 Shows that the speed of the full matrix method for calculating the matrix inverse can generally be about 3 times faster than the unit vector method. As shown in Figure 11 , for smaller matrices, the embedding overhead of the two methods is the same, but for larger matrices, this embedding overhead of the full matrix method can increase by 7 times. However, when the full matrix method is used in the methods for estimating the characteristics of semiconductor devices described herein and the methods for simulating semiconductor devices described herein, it will be understood that since the matrix structure remains the same (since this is based on the semiconductor device configuration), the embedding only needs to be performed once. Therefore, in these methods, the cost of this embedding can be ignored.

[0339] Figure 12 Shows the qubit requirements for both the full matrix method and the unit vector method. Figure 13 Shows the resource efficiency of both the full matrix method and the unit vector method.

[0340] Considering the qubit usage of the two methods, the logical qubits scale as expected, where the full matrix method scales quadratically in terms of the number of logical qubits, while the unit vector method scales linearly. As shown in Figure 12 , the scaling of the physical qubits seems to be similar. Observing the ratio of physical qubits to logical qubits (resource efficiency) in Figure 13 provides a practical indication of the physical qubit usage. For different matrix sizes, the ratio of the full matrix method is nearly constant, while the unit vector method shows a linear increase in physical qubit usage. The full matrix method makes better use of physical qubits because zero interactions have been eliminated and thus the necessary connections are reduced.

[0341] The number of qubits in the annealer limits the size of the block matrices in the discretized Schrödinger equation. Thus, during device discretization using a rectangular grid, the number of nodes to be simulated in each layer can be selected such that the corresponding QUBO matrices corresponding to these layers can be embedded on a given annealer.

[0342] Thus, specific embodiments of the present disclosure can simulate quantum effects in sub-10nm transistor technologies by employing a self-consistent model of the nonlinearly coupled Schrödinger-Poisson equation. In some embodiments, the self-consistent model is solved by implementing a quadratic unconstrained binary optimization problem on a quantum annealer. In some embodiments, a domain decomposition method based on block cyclic reduction is utilized to make the self-consistent model of the nonlinearly coupled Schrödinger-Poisson equation tractable on a quantum annealer.

[0343] Figure 14 FIG. 1400 is a schematic diagram of an example of an apparatus 1400 for estimating characteristics of a semiconductor device. The apparatus 1400 includes processing circuitry 1402 (e.g., one or more processors) and a memory 1404 communicatively coupled to the processing circuitry 1402. The memory 1404 contains instructions executable by the processing circuitry 1402. The apparatus 1400 also includes an interface 1406 communicatively coupled to the processing circuitry 1402. Although the interface 1406, the processing circuitry 1402, and the memory 1404 are shown as being serially connected, they may also be interconnected in any other manner (e.g., via a bus).

[0344] In one embodiment, the memory 1404 contains instructions executable by the processing circuitry 1402 such that the apparatus 1400 is operable to: form a spatially discretized representation of a semiconductor device including n x layers; initialize a first set of equations based on one or more parameters associated with the spatially discretized representation of the semiconductor device, wherein the first set of equations represents characteristics of the semiconductor device, wherein each equation in the first set of equations represents layer i, where i = (1, 2,... n x-1 , n x ), and includes one or more matrix blocks H i,j , where j = (1, 2,... n x-1 , n x ), and wherein each matrix block represents any one of:

[0345] one or more interactions within layer i, or

[0346] one or more interactions between layer i and an adjacent layer to layer i in the spatially discretized representation; apply a cyclic reduction method to the first set of equations to obtain a second set of equations; determine a solution to the second set of equations; and estimate characteristics of the semiconductor device based on the solution to the second set of equations. In some examples, the apparatus 1400 is operable to perform the above with reference toFigure 1 The described method 100.

[0347] Figure 15 Is a schematic diagram of an example of an apparatus 1500 for entries of an N x N matrix B, where matrix B is the inverse of an N x N matrix A. The apparatus 1500 includes a processing circuit 1502 (e.g., one or more processors) and a memory 1504 communicatively coupled to the processing circuit 1502. The memory 1504 contains instructions executable by the processing circuit 1502. The apparatus 1500 also includes an interface 1506 communicatively coupled to the processing circuit 1502. Although the interface 1506, the processing circuit 1502, and the memory 1504 are shown as being connected in series, they may also be interconnected in any other manner (e.g., via a bus).

[0348] In one embodiment, the memory 1504 contains instructions executable by the processing circuit 1502 such that the apparatus 1500 is operable to: for each entry of B, form a representation of that entry of B including one or more binary variables; based on the representation of the entry of B, form N 2 linear equality constraints representing A·B = I, where I is an N x N identity matrix; based on the N 2 linear equality constraints, formulate a quadratic unconstrained binary optimization (QUBO) problem; execute the QUBO problem on a quantum computing device to obtain a set of values for the binary variables; and use the set of values for the binary variables to determine the entries of matrix B. In some examples, the apparatus 1500 is operable to execute the method 400 described above with reference to Figure 4 the description.

[0349] Figure 16 Is a schematic diagram of an example of a data processing apparatus 1600 for determining the entries of an N x N matrix B for use in a method for estimating characteristics of a semiconductor device, where matrix B is the inverse of an N x N matrix A, and where the entries of matrix A represent interactions within a layer of a spatially discretized representation of the semiconductor device. The data processing apparatus 1600 includes a processing circuit 1602 (e.g., one or more processors) and a memory 1604 communicatively coupled to the processing circuit 1602. The memory 1604 contains instructions executable by the processing circuit 1602. The data processing apparatus 1600 also includes an interface 1606 communicatively coupled to the processing circuit 1602. Although the interface 1606, the processing circuit 1602, and the memory 1604 are shown as being connected in series, they may also be interconnected in any other manner (e.g., via a bus).

[0350] In one embodiment, memory 1604 includes instructions executable by processing circuitry 1602 to cause data processing apparatus 1600 to be operable to: for each entry of B, form a representation of that entry of B that includes one or more binary variables; based on the representation of the entries of B, form N 2 linear equality constraints representing A·B = I, where I is the N x N identity matrix; based on the N 2 linear equality constraints, formulate a quadratic unconstrained binary optimization QUBO problem; execute the QUBO problem on a quantum computing device to obtain a set of values for the binary variables; and use the set of values for the binary variables to determine the entries of matrix B. In some examples, data processing apparatus 1600 is operable to perform method 500 described above with reference to Figure 5 description.

[0351] It should be noted that the above examples illustrate rather than limit the invention, and those skilled in the art will be able to design many alternative examples without departing from the scope of the appended claims. The word "comprising" does not exclude the presence of elements or steps other than those listed in the claims, "a" or "an" does not exclude a plurality, and a single processor or other unit may implement the functions of a number of units described in the claims below. When terms such as "first", "second", etc. are used, they are only to be understood as labels for facilitating the identification of specific features. In particular, unless explicitly stated otherwise, they are not to be construed as describing the first or second of a number of such features (i.e., the first or second such feature to occur in time or space). Unless explicitly stated otherwise, the steps in the methods disclosed herein may be performed in any order. Any reference signs in the claims should not be construed as limiting the scope of the claims.

[0352] References

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[0354] 2. M. G. Ancona, "Density-gradient theory: A macroscopic approach to quantum confinement and tunneling in semiconductor devices", Journal of Computational Electronics, Vol. 10, No. 1, pp. 65 - 97, 2011

[0355] 3. N. Sano, A. Hiroki, and K. Matsuzawa, "Device modeling and simulations toward sub-10nm semiconductor devices", IEEE Transactions on Nanotechnology, Vol. 1, No. 1, pp. 63 - 71, 2002

[0356] 4. R. A. Sweet, "A cyclic reduction algorithm for solving block tridiagonal systems of arbitrary dimension", SIAM Journal on Numerical Analysis, Vol. 14, No. 4, pp. 706 - 720, 1977

[0357] 5. G. Grosso, S. Moroni, and G. P. Parravicini, "Electronic structure of the InAs-GaSb superlattice studied by the renormalization method", Phys. Rev. B, Vol. 40, No. 12, pp. 328 - 337, December 18, 1989

[0358] 6. P. B. Vyas, M. L. Van de Put, and M. V. Fischetti, "Master-equation study of quantum transport in realistic semiconductor devices including electron-phonon and surface-roughness scattering", Phys. Rev. Applied, Vol. 13, No. 014067, January 1, 2020

[0359] 7. S. E. Laux, A. Kumar, and M. V. Fischetti, "Analysis of quantum ballistic electron transport in ultrasmall silicon devices including space-charge and geometric effects", Journal of Applied Physics, Vol. 95, No. 10, pp. 5545 - 5582, 2004

[0360] 8. P. B. Vyas, C. Naquin, H. Edwards, M. Lee, W. G. Vandenberghe, and M. V. Fischetti, "Theoretical simulation of negative differential transconductance in lateral quantum well nmos devices", Journal of Applied Physics, Vol. 121, No. 4, 044501, 2017

[0361] 9. T. B. Boykin, M. Luisier, and G. Klimeck, "Multiband transmission calculations for nanowires using an optimized renormalization method", Phys. Rev. B, Vol. 77, p. 165318, April 16, 2008

[0362] 10. M. Luisier, G. Klimeck, A. Schenk, W. Fichtner, and T. B. Boykin, "A parallel sparse linear solver for nearest-neighbor tight-binding problems", Euro-Par 2008 - Parallel Processing, edited by E. Luque, T. Margalef, and D. Benítez, Berlin Heidelberg: Springer-Verlag Berlin Heidelberg, 2008, pp. 790–800

[0363] 11. M. L. Rogers and R. L. Singleton, "Floating-point calculations on a quantum annealer: Division and matrix inversion", Frontiers in Physics, Vol. 8, 2020

[0364] 12. T. Fukushima, "Precise and fast computation of inverse fermi–dirac integral of order 1 / 2 by minimax rational function approximation", Applied Mathematics and Computation, Vol. 259, pp. 698 - 707, 2015

[0365] 13. Zhou, J.R. and Ferry, D.K., 1992. Simulation of ultra-small GaAs MESFET using quantum moment equations. IEEE Transactions on Electron Devices, Vol. 39 (No. 3), pp. 473-478

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Claims

1. A method for estimating characteristics of a semiconductor device, the method comprises: Form a spatially discretized representation of the semiconductor device including n x layers; Initialize a first set of equations based on one or more parameters related to the spatially discretized representation of the semiconductor device, wherein the first set of equations represents the characteristics of the semiconductor device, and wherein each equation in the first set of equations represents layer i, where i = (1, 2, … n x-1 , n x ), and includes one or more matrix blocks H i,j , where j = (1, 2, … n x-1 , n x ), and wherein each matrix block represents any of the following: one or more interactions within layer i, or one or more interactions between layer i and a layer adjacent to layer i in the spatially discretized representation; applying the cyclic reduction method to the first system of equations to obtain a second system of equations; determining a solution of the second system of equations; and estimating the characteristics of the semiconductor device based on the solution of the second system of equations.

2. The method according to claim 1, wherein, forming the spatially discretized representation of the semiconductor device comprises: using the finite element method to form the spatially discretized representation of the semiconductor device.

3. The method according to claim 2, wherein, using the finite element method to form the spatially discretized representation of the semiconductor device comprises: using rectangular grid cells, wherein each rectangular grid cell represents a spatial part of the device.

4. The method according to any one of the preceding claims, wherein, the first system of equations includes a two-dimensional Schrödinger equation for the spatially discretized representation of the semiconductor device.

5. The method according to any one of claims 1 - 3, wherein, the first system of equations includes a two-dimensional Poisson equation for the spatially discretized representation of the semiconductor device.

6. The method according to any one of the preceding claims, wherein, applying the cyclic reduction method to the first system of equations to obtain a second system of equations comprises: for one or more layers of the spatially discretized representation: for layer i, wherein layer i is coupled to layer i - l and layer i + r: For the matrix blocks H i-l,i , H i+r,i , H i,i-l and H i,i+r in the first set of equations, perform renormalization.

7. The method according to claim 6, wherein, For the matrix block H i-l,i , H i+r,i , H i,i-l and H i,i+r The steps for re-normalization include: Determine the inverse matrix of the matrix block H i,i ; and Based on the determined one or more inverse matrices, re-normalize the matrix blocks H i-l,i , H i+r,i , H i,i-l and H i,i+r .

8. The method according to claim 7, wherein, determining the one or more inverse matrices includes: determining the one or more inverse matrices according to the method of any one of claims 27 - 38.

9. The method according to any one of claims 6 - 8, wherein, The one or more layers of the spatial discretization representation include all layers of the spatial discretization representation except layer 1 and layer n x other than.

10. The method according to claim 9, wherein, determining a solution of the second system of equations includes: Solve the second system of equations to obtain the entry i = 1 of the solution vector and the entry i = n of the solution vector, where the first system of equations includes the solution vector. x , where the first system of equations includes the solution vector.

11. The method according to claim 10, wherein, Determining the solution of the second system of equations further includes: reconstructing the remaining entries of the solution vector other than entries 1 and n x except for these entries.

12. The method according to any one of claims 6 - 8, wherein, The one or more layers of the spatial discretization representation include all layers of the spatial discretization representation except layer 1, layer n x and another layer.

13. The method according to claim 12, wherein, determining a solution of the second system of equations includes: Solve the second set of equations to obtain the entries i = 1 of the solution vector, the entries i = n of the solution vector, and the entries of the solution vector having indices corresponding to the indices of the other layer, wherein the first set of equations includes the solution vector. x ​ 14. The method according to claim 13, wherein, Determining the solution of the second set of equations further includes: reconstructing the remaining entries of the solution vector except for entry 1 and entry n x and the entries of the solution vector having indices corresponding to the indices of the other layer.

15. The method according to any one of claims 9 - 14, wherein, renormalizing the matrix blocks for the one or more layers is first performed for one or more even-indexed layers among the one or more layers of the spatially discretized representation.

16. The method according to claim 15, comprises: after renormalizing the matrix blocks for the one or more even-indexed layers, renormalizing the matrix blocks for half of the odd-indexed layers among the one or more layers of the spatially discretized representation.

17. The method according to claim 16, comprises: renormalizing the matrix blocks for the remaining layers among the one or more layers of the spatially discretized representation.

18. The method according to any one of claims 12 - 17, wherein, the method further comprises: selecting the other layer of the spatially discretized representation.

19. The method according to claim 18, wherein, the step of selecting the other layer comprises: selecting the other layer based on: the amplitude of the wave function of the spatially discretized representation of the semiconductor device, and the amplitude of the wave function of the other layer.

20. The method according to any one of the preceding claims, wherein, the method further comprises: estimating one or more other characteristics of the semiconductor device using the estimated characteristics of the semiconductor device.

21. The method according to any one of the preceding claims, wherein, the characteristics include the wave function in the semiconductor device.

22. The method according to any one of claims 1 - 21, wherein, the characteristics include the electrostatic potential in the semiconductor device.

23. The method according to any one of claims 20 - 22, wherein, the method further comprises: estimating one or more characteristics of a circuit including the semiconductor device using the estimated one or more other characteristics of the semiconductor device.

24. The method according to any one of the preceding claims, wherein, the method further comprises: using the estimated characteristics of the semiconductor device during a design process.

25. The method according to claim 24, wherein, using the estimated characteristics of the semiconductor device during a design process includes: adjusting the design of the semiconductor device and / or adjusting the circuit including the semiconductor device based on the estimated characteristics.

26. The method according to any one of the preceding claims, wherein, the characteristics of the semiconductor device are estimated in a method of simulating the semiconductor device and / or a circuit including the semiconductor device.

27. A method for determining the entries of an N x N matrix B, wherein, the matrix B is the inverse of an N x N matrix A, and the method comprises: for each entry of B, forming a representation of the entry of B including one or more binary variables; Based on the representation of the entries of B, form N 2 linear equality constraints representing A·B = I, where I is the N x N identity matrix; Based on the above N 2 linear equality constraints, formulate the quadratic unconstrained binary optimization (QUBO) problem using a formula; executing the QUBO problem on a quantum computing device to obtain a set of values of the binary variables; and using the set of values of the binary variables to determine the entry of the matrix B.

28. The method according to claim 27, wherein, the entry of the matrix A represents an interaction within a layer of the spatially discretized representation of the semiconductor device.

29. The method according to claim 27 or 28, wherein, Based on the N 2 linear equality constraints, the steps of formulating a quadratic unconstrained binary optimization (QUBO) problem using formulas include: Express the N 2 linear equality constraints in the form of Cx = b, where x is a binary decision vector including the binary variables.

30. The method according to claim 29, wherein, Based on the N 2 linear equality constraints, formulating the QUBO problem further includes: Formulate the QUBO matrix Q such that Q = C T C - 2b T C.

31. The method according to claim 30, wherein, executing the QUBO problem on the quantum computing device to obtain the values of the binary variables includes: manipulating the quantum state of the qubits of the quantum computing device based on the QUBO matrix Q; obtaining a measurement of each of the one or more qubits; and determining the set of values of the binary variables based on the obtained measurements.

32. The method according to claim 31, wherein, The state of the qubit of the measured quantum computing device corresponds to the solution of the binary decision vector x.

33. The method according to any one of claims 27 - 32, wherein, executing the QUBO problem on the quantum computing device includes: performing a quantum annealing process.

34. The method according to any one of claims 27 - 33, wherein, the method is used in a method for estimating characteristics of a semiconductor device.

35. The method according to any one of claims 27 - 34, wherein, the method is used in a method for simulating a semiconductor device and / or a circuit including the semiconductor device.

36. The method according to claim 34, wherein, the characteristics include a wave function in the semiconductor device.

37. The method according to claim 34, wherein, the characteristics include an electrostatic potential in the semiconductor device.

38. The method according to any one of claims 27 - 37, wherein, the method is executed on a data processing device.

39. A method for determining entries of an N x N matrix B to be used in a method for estimating characteristics of a semiconductor device, the method being executed on a data processing device, wherein, the matrix B is the inverse of an N x N matrix A, and wherein the entries of the matrix A represent interactions within a layer of a spatially discretized representation of the semiconductor device, the method comprising: for each entry of B, forming a representation of that entry of B including one or more binary variables; Based on the representation of the entries of B, form N 2 linear equality constraints representing A·B = I, where I is the N x N identity matrix; Based on the above N 2 linear equality constraints, formulate the quadratic unconstrained binary optimization (QUBO) problem with a formula; executing the QUBO problem on a quantum computing device to obtain a set of values of the binary variables; and using the set of values of the binary variables to determine the entries of matrix B.

40. A computer program comprising instructions which, when executed on at least one processor, cause the at least one processor to execute the method according to any one of claims 1 to 39.

41. A carrier containing the computer program according to claim 40, wherein, the carrier includes one of an electrical signal, an optical signal, a radio signal, or a computer-readable storage medium.

42. A computer program product comprising a non-transitory computer-readable medium having stored thereon the computer program according to claim 40.

43. A device for estimating characteristics of a semiconductor device, wherein, the device is configured to: Form a spatially discretized representation of the semiconductor device including n x layers; Initialize a first set of equations based on one or more parameters related to the spatially discretized representation of the semiconductor device, where the first set of equations represents the characteristics of the semiconductor device, and where each equation in the first set of equations represents layer i, where i = (1, 2, … n x-1 , n x ), and includes one or more matrix blocks H i,j , where j = (1, 2, … n x-1 , n x ), and where each matrix block represents any one of the following: one or more interactions within layer i, or one or more interactions between layer i and an adjacent layer to layer i in the spatial discretized representation; apply cyclic reduction to the first set of equations to obtain a second set of equations; determine the solution of the second set of equations; and estimate the characteristics of the semiconductor device based on the solution of the second set of equations.

44. The device according to claim 43, wherein, the device is further configured to execute the method according to any one of claims 2 to 26.

45. A device for determining entries of an N x N matrix B, wherein, the matrix B is the inverse of an N x N matrix A, wherein the device is configured to: For each entry of B, form a representation of that entry of B that includes one or more binary variables; Based on the representation of the entries of B, form N linear equality constraints representing A·B = I, where I is the N x N identity matrix; 2 where I is the N x N identity matrix; Based on the N 2 linear equality constraints, formulate the quadratic unconstrained binary optimization (QUBO) problem with a formula; Execute the QUBO problem on a quantum computing device to obtain a set of values for the binary variables; and Use the set of values of the binary variables to determine the entry of matrix B.

46. The apparatus according to claim 45, wherein, the apparatus is further configured to execute the method according to any one of claims 28 to 38.

47. A data processing apparatus for determining entries of an N×N matrix B for use in a method of estimating characteristics of a semiconductor device, wherein, the matrix B is the inverse of an N×N matrix A, and wherein the entries of the matrix A represent interactions within a layer of a spatially discretized representation of the semiconductor device, and wherein the data processing apparatus is configured to: For each entry of B, form a representation of that entry of B that includes one or more binary variables; Based on the representation of the entries of B, form N 2 linear equality constraints representing A·B = I, where I is the N x N identity matrix; Based on the above N 2 linear equality constraints, formulate the quadratic unconstrained binary optimization (QUBO) problem with a formula; Execute the QUBO problem on a quantum computing device to obtain a set of values for the binary variables; and Use the set of values of the binary variables to determine the entry of matrix B.

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