Auto-zeroing technique for high voltage analog front end with robust AC common mode rejection

Abstract

The techniques and circuits described herein include solutions for auto-zero in auto-zero amplifiers in the presence of high frequency alternating current (AC) noise. In some aspects, a first input (114) and a second input (116) of an auto-zero amplifier (100) are coupled to a differential voltage having high AC noise. During an auto-zero phase, a first switching network (102) decouples an input (110, 112) of a first amplifier included within the auto-zero amplifier from the differential voltage with high AC noise. In some examples, the input of the first amplifier may be connected to a regulated direct current (DC) voltage (118). The regulated DC voltage provides more accurate auto-zeroing for the auto-zeroing amplifier, such that a higher overall accuracy is achieved during the operational phase.

Description

Background Art

[0001] Amplifiers (such as operational amplifiers) can be used to perform various functions in electronic circuits, such as voltage buffering, inverting, amplifying, integrating, differentiating, etc. An auto-zero amplifier is a special type of amplifier characterized by a low offset voltage. Summary of the Invention

[0002] In one example, a circuit includes a first input voltage terminal, a second input voltage terminal, a direct current (DC) voltage input terminal, and an output voltage terminal. A first amplifier has: a first input coupled to the first input voltage terminal via a first main switch; and a second input coupled to the second input voltage terminal via a second main switch. The output of the first amplifier is coupled to the output voltage terminal. An operation path extends between the output of the first amplifier and the output voltage terminal. A calibration path is arranged electrically in parallel with the operation path. A second amplifier is arranged along the calibration path and has: a first input coupled to the output of the first amplifier; a second input coupled to the DC voltage terminal; and an output coupled to the output voltage terminal. A third main switch is coupled between the first input and the second input of the first amplifier.

[0003] In one example, a circuit includes a first input voltage terminal, a second input voltage terminal, and a third input voltage terminal. A first amplifier has a first input, a second input, and an output. A first main switch is coupled between the first input voltage terminal and the first input of the first amplifier. A second main switch is coupled between the second input voltage terminal and the second input of the first amplifier. A third main switch is coupled between the third input voltage terminal and the first input of the first amplifier, and a fourth main switch is coupled between the third input voltage terminal and the second input of the first amplifier. A second amplifier has a first input, a second input, and an output. A first auto-zero switch is coupled between the output of the first amplifier and the first input of the second amplifier. A second auto-zero switch is coupled between a fourth input voltage terminal and the second input of the second amplifier. The output of the second amplifier is coupled to the output of the first amplifier.

[0004] In one example, an auto-zero amplifier includes a first amplifier having a first input, a second input, and an output. A first switch network is coupled to the first input and the second input of the first amplifier. The first switch network is configured to provide a first input voltage to the first input of the first amplifier and a second input voltage to the second input of the first amplifier during an operation phase, and is configured to couple the first input and the second input of the first amplifier during an auto-zero phase. A sampling capacitor is coupled to the second input of the first amplifier. An auto-zero circuit system is coupled to the output of the first amplifier. The auto-zero circuit system includes a first auto-zero capacitor and is configured to compensate for an input offset voltage of the first amplifier during the operation phase based on a voltage on the first auto-zero capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 FIG. is a schematic circuit diagram of an auto-zero amplifier including a switch network connected to a direct current (DC) bias voltage in some aspects of the present specification.

[0006] Figure 2 FIG. is a schematic circuit diagram of an auto-zero amplifier including a switch network and a capacitor for sampling and holding a DC voltage in some aspects of the present specification.

[0007] Figure 3 FIG. is a schematic diagram including a plurality of battery cells and a plurality of auto-zero amplifiers in some aspects of the present specification.

[0008] Figures 4A to 4B FIG. is a waveform diagram showing voltages varying with time at an input terminal of an auto-zero amplifier in some aspects of the present specification.

[0009] Figure 5 FIG. is a schematic circuit diagram of an auto-zero amplifier including a switch network connected to a DC bias voltage in some aspects of the present specification.

[0010] Figure 6 FIG. is a schematic circuit diagram of an auto-zero amplifier including a switch network and a capacitor for sampling and holding a DC voltage in some aspects of the present specification.

[0011] Figure 7 FIG. is a waveform diagram showing voltages varying with time at an auto-zero capacitor during an auto-zero phase in some aspects of the present specification.

[0012] Figure 8 FIG. is a waveform diagram showing an output voltage of an auto-zero amplifier in some aspects of the present specification.

[0013] Figure 9A logic flow diagram depicting a method for generating an auto - zero reference using a DC voltage in some aspects of this specification. Detailed Description

[0014] The figures are not drawn to scale.

[0015] A differential amplifier, such as an operational amplifier (“op amps”), is a class of electronic devices that produces an amplified output based on the potential (e.g., voltage) difference between two inputs. An auto - zero amplifier is a type of differential amplifier characterized by a low offset voltage.

[0016] Figure 1 An example of an auto - zero amplifier 100 in some aspects of this specification is shown. The auto - zero amplifier 100 includes: a first input terminal 114 and a second input terminal 116 to which input voltage potentials are received; and an output terminal 120 at which an output voltage potential is provided. A first amplifier 104 (e.g., the “main” amplifier) has a first input 110 and a second input 112 respectively coupled to the first input 114 and the second input 116. An operational path 106 extends from the output of the first amplifier 104 to the output terminal 120. A calibration path 108 extends parallel to the operational path 106 and includes an auto - zero circuit system 122 of a second amplifier 132 (e.g., the “nulling” amplifier) disposed along the calibration path 108.

[0017] During operation, an auto - zero amplifier, such as auto - zero amplifier 100, utilizes an operational mode and an auto - zero mode. During the operational mode, the auto - zero amplifier receives a differential input voltage at its first and second inputs (e.g., 114, 116) and outputs an amplified voltage at its output terminal (e.g., 120). Depending on the amplification factor, which is referred to as the “gain” of the amplifier, the amplified voltage is different from the differential input voltage. The gain can be negative (e.g., < 0 decibels (dB)), positive (e.g., > 0 dB), or unity (e.g., = 0 dB) depending on various factors such as the feedback path, open - loop gain value, etc. When the same voltage level is provided at the first and second inputs during the operational mode, the output at the main amplifier (e.g., 119) and at the output terminal ideally would be zero. However, due to slight differences in the internal components of the main amplifier (e.g., a slight mismatch in resistance values that occurs during manufacturing, etc.), it is possible for the main amplifier to deliver a non - zero output even when the same voltage is provided at the first and second inputs. This undesirable condition is referred to as a “non - zero offset”.

[0018] Use an auto - zero mode to help minimize non - zero offsets. During the auto - zero mode, the calibration path determines a correction signal to "cancel" the non - zero offset. Then, once the auto - zero mode has determined the appropriate correction signal, the auto - zero amplifier 100 returns to the operating mode, and the calibration path applies this correction signal to the output terminal to minimize the non - zero offset. In this way, the auto - zero amplifier provides a very low zero offset while still providing accurate gain.

[0019] Some aspects of this specification recognize that, for certain auto - zero amplifiers, when there is common - mode alternating - current (AC) noise present on the first and / or second input, the AC noise can cause an undesired change in the way the calibration path determines the correction signal during the auto - zero mode. In an ideal scenario, the auto - zero amplifier would have an infinitely high AC common - mode rejection ratio (CMRR), and the common - mode AC noise would simply be suppressed. However, due to limitations in manufacturing, materials, etc., this is often not achievable in reality. Under the influence of this AC noise, these undesired changes can result in a small but still noticeable non - zero offset at the output of the auto - zero amplifier. The offset error can also vary over time within multiple auto - zero cycles tracking the AC noise and become an AC residual error.

[0020] Accordingly, this specification provides an auto - zero amplifier that applies a direct - current (DC) bias to the first amplifier 104 and the second amplifier 132 during the auto - zero mode to determine the correction signal. Then, during the operating mode, this correction signal can be applied to the output terminal 120 while the AC noise still exists on the first input and / or second input in a manner that provides a reduced non - zero offset at the output of the auto - zero amplifier relative to other methods. Thus, this correction signal is independent of the AC noise and can correct only circuit errors (such as mismatches) in the first amplifier 104 and the second amplifier 132.

[0021] To help achieve robust AC noise immunity, Figure 1 the auto - zero amplifier 100 includes a DC voltage terminal 118, a first switching network 102, a second switching network 134, a first auto - zero capacitor 138, and a second auto - zero capacitor 136, which are operatively coupled as shown. The control circuit 150 provides an auto - zero signal AZ and a complementary auto - zero signal AZ', as shown. The complementary signal AZ' can be generated, for example, by connecting the signal AZ to an inverter 152. The input of the inverter 152 is AZ, and the output of the inverter is AZ'. In some aspects, during the auto - zero phase, the signal AZ is provided as TRUE or in the "high" state, and during the operating phase, the signal AZ' is provided as TRUE or in the "high" state.

[0022] The first switching network 102 includes a first main switch 124, a second main switch 126, a third main switch 128, and a fourth main switch 130. The first main switch 124 is coupled between the first input voltage terminal 114 and the first input 110 of the first amplifier 104 (e.g., the first input voltage terminal 114 is coupled to the first input 110 of the first amplifier 104 via the first main switch 124). Similarly, the second main switch 126 is coupled between the second input voltage terminal 116 and the second input 112 of the first amplifier 104. The third main switch 128 is coupled between the first input 110 of the first amplifier 104 and the third voltage input terminal 118. The fourth main switch 130 is coupled between the second input 112 of the first amplifier 104 and the third voltage input terminal 118. The control terminals of the first main switch 124 and the second main switch 126 are coupled together.

[0023] The second switching network 134 includes: a first auto - zero switch 140, which is coupled between the output 119 of the first amplifier 104 and the first input 142 of the second amplifier 132; and a second auto - zero switch 144, which is coupled between the fourth voltage input terminal 145 and the second input 146 of the second amplifier 132. The fourth voltage input terminal 145 provides a voltage Vbias2, which may be the same voltage as or different from Vbias. A first auto - zero capacitor 138 is coupled between the first input 142 of the second amplifier 132 and ground. A second auto - zero capacitor 136 is coupled between the second input 146 of the second amplifier 132 and ground. The control terminals of the third main switch 128, the fourth main switch 130, the first auto - zero switch 140, and the second auto - zero switch 144 are coupled together. The first amplifier 104 and the second amplifier 132 may be included on an integrated circuit, while the first auto - zero capacitor 138 and / or the second auto - zero capacitor 136 are often external to the integrated circuit, but in some cases may also be included on the integrated circuit. In other additional examples, the second auto - zero switch 144 and the first auto - zero capacitor 136 may be omitted.

[0024] During the auto - zero phase, the control circuit 150 enables the AZ signal, which disables the AZ' signal, such that the first master switch 124 and the second master switch 126 are opened, while the third master switch 128 and the fourth master switch 130 are closed. In this way, the inputs 110, 112 of the first amplifier 104 are disconnected from the first input voltage terminal 114 and the second input voltage terminal 116, and are coupled together (e.g., short - circuited) and held at the regulated DC voltage Vbias provided by the third input voltage terminal 118. The short - circuited inputs 110, 112 provide a differential voltage of 0 volts to the first amplifier 104 during the auto - zero phase, such that the output 119 is based only on the input offset voltage of the first amplifier 104. Since the inputs 110, 112 of the first amplifier 104 are disconnected from the first voltage input terminal 114 and the second voltage input terminal 116, they are decoupled from (and thus not affected by) any common - mode AC noise on the first voltage input terminal 114 and the second voltage input terminal 116.

[0025] In addition, during the auto - zero phase, the first auto - zero switch 140 is closed, such that the second switch network 134 couples the voltage of the output 119 of the first amplifier 104 to the first auto - zero capacitor 138 and to the input 142 of the second amplifier 132. The second auto - zero switch 144 is also closed, such that the second switch network 134 further couples the fourth voltage input terminal 145 (and thus the DC voltage Vbias2) to the second input 146 of the second amplifier 132. In this way, the first auto - zero capacitor 138 can be calibrated (e.g., charged or discharged) to the voltage of the output 119 of the first amplifier 104, and the second auto - zero capacitor 136 can be charged to the voltage Vbias2 provided by the fourth voltage input terminal 145. Thus, the second amplifier 132 delivers an output whose voltage level is "tuned" to account for manufacturing variations of the auto - zero amplifier 100 and is independent of AC noise.

[0026] During the operation phase, the control circuit 150 disables the AZ signal, which enables the AZ' signal, causing the first main switch 124 and the second main switch 126 to close and the third main switch 128 and the fourth main switch 130 to open. Accordingly, the first amplifier 104 amplifies the voltage difference between the first voltage input terminal 114 and the second voltage input terminal 116 based on the gain of the first amplifier 104. At the same time, the first auto-zero switch 140 and the second auto-zero switch 144 in the auto-zero circuit system 122 open, causing the second amplifier 132 to provide a correction signal based on the calibration voltages stored on the first auto-zero capacitor 138 and the second auto-zero capacitor 136 during the auto-zero phase, the correction signal compensating for the input offset voltage of the first amplifier 104. Accordingly, the voltage at the output terminal 120 is the "compensated" voltage, and thus the auto-zero amplifier 100 effectively "auto-zeros" itself.

[0027] Accordingly, even when there is AC noise present on the first input 114 and the second input 116, the first switching network 102 advantageously eliminates the AC noise during the auto-zero phase by decoupling the inputs 110, 112 from the first voltage input terminal 114 and the second voltage input terminal 116 and alternatively coupling the inputs 110, 112 to the voltage Vbias (e.g., a regulated voltage with little to no AC noise). Since the calibration voltage stored on the first auto-zero capacitor 138 is now based on a regulated DC signal (rather than a signal containing AC noise), the correction signal provided by the calibration path 108 during the operation mode has a higher accuracy than other methods even in the case where AC noise is present on the first voltage input terminal 114 and the second voltage input terminal 116 during the operation mode.

[0028] Figure 2 Another auto-zero amplifier 200 in some aspects of the present specification is illustrated. The auto-zero amplifier 200 again includes: a first input terminal 114 and a second input terminal 116, to which input voltage potentials are received; and an output terminal 120, at which an output voltage potential is provided. The auto-zero amplifier 200 also again includes a first amplifier 104, an operation path 106, and a calibration path 108, where the calibration path is arranged electrically in parallel with the operation path 106 and includes an auto-zero circuit system 122, as previously described.

[0029] However, in Figure 2 the first switching network 202 includes an equalization switch 206, which is coupled between the first input 110 of the first amplifier 104 and the second input 112 of the first amplifier 104. A sampling capacitor 204a is coupled between the first input 110 and ground, and a sampling capacitor 204b is coupled between the second input 112 and ground.

[0030] The operation phase corresponds to the time when the auto-zero signal (AZ) is disabled and the complementary auto-zero signal (AZ') is enabled (e.g., such that switches 124, 126 are closed and switches 206, 140, and 144 are open). Thus, during the operation phase, the voltages stored on the sampling capacitors 204a, 204b are charged or discharged to reflect the voltages of the first input terminal 114 and the second input terminal 116, respectively. In this way, the common-mode voltage between the first input terminal 114 and the second input terminal 116 is "sampled" (e.g., charged / discharged) by the sampling capacitors 204a, 204b (collectively referred to as "sampling capacitors 204") during the operation phase. During the auto-zero phase (e.g., when AZ is enabled and AZ' is disabled), the sampling capacitors 204 "hold" this voltage. The "held" voltage will be the value between the "sampled" voltages of the individual sampling capacitors 204a, 204b (e.g., the voltages of the sampling capacitors 204a, 204b will equalize since they are coupled together by the equalization switch 206). Since the sampling capacitors 204 are not coupled to the first input terminal 114 and the second input terminal 116 during the auto-zero phase and the currents flowing into the first input 110 and the second input 112 of the first amplifier 104 are extremely low (on the order of nanoamperes (nA)), the voltage of the sampling capacitors 204 remains substantially constant throughout the auto-zero phase, during which the first auto-zero capacitor 138 is calibrated. Based on the calibrated voltage stored on the first auto-zero capacitor 138 during the auto-zero phase, the input offset voltage of the auto-zero amplifier 132 can be compensated during the operation phase. Since the voltage from the second input terminal 116 is "sampled" and "held", the first input 110 and the second input 112 of the first amplifier 104 can be decoupled from the first input terminal 114 and the second input terminal 116 during the auto-zero phase, thereby reducing or even eliminating the AC noise from the first input terminal 114 and the second input terminal 116. The DC voltage held by the sampling capacitors 204 can be used to provide an accurate calibration of the first auto-zero capacitor 138. Although the voltage held by the sampling capacitors 204 may vary depending on the sampling time of the common-mode voltage between the first input terminal 114 and the second input terminal 116 (e.g., depending on which part of the AC noise is captured), since the DC voltages provided to the first input 110 and the second input 112 are the same (e.g., common-mode, potential difference of 0 volts) and the amplifier 104 typically has an extremely high DC CMRR, the auto-zero accuracy is not affected. The high DC CMRR suppresses the common-mode DC signal and the auto-zero accuracy is not affected. For example, refer to Figure 4B Describe other details of the sampling and holding techniques.

[0031] Figure 3Illustrates an electronic system 300 in some aspects of the present specification. The electronic system 300 includes N battery cells 302-1, 302-2, 302-N (e.g., as part of a battery pack), which may be arranged in series and collectively referred to as battery cells 302. As an example, the battery cells 302 may be battery cells for an electric vehicle (EV) and / or a hybrid electric vehicle (HEV). In some aspects, each of the battery cells 302 outputs a small voltage in the range of 1 to 5 volts. However, since the battery cells 302 are in series, they can collectively provide a large voltage (e.g., in the range of 50 to 100 volts, or greater).

[0032] In some EV and / or HEV applications, it may be necessary to monitor the voltage on each of the battery cells 302 during operation. Based on the monitored voltage, system parameters can be adjusted to obtain better performance, fuel efficiency, etc. To improve accuracy when measuring small battery cell voltages, an auto-zero amplifier is needed to reduce the impact of input offset voltage. However, due to inverters, charging, discharging, etc., AC noise 304 is often present in the EV environment. In some instances, the AC noise 304 can range from 1 to 10 kilohertz (kHz), up to ±4 volts.

[0033] Illustrates N auto-zero amplifiers 100-1, 100-2, 100-N (collectively referred to as auto-zero amplifiers 100), which have first voltage input terminals 114-1, 114-2, 114-N and second voltage input terminals 116-1, 116-2, 116-N respectively coupled between the terminals of the battery cells 302-1, 302-2, 302-N. In some aspects, each of the auto-zero amplifiers 100 has a gain of 1, such that the voltages at the output terminals 120-1, 120-2, 120-N are respectively approximately equal to the voltages of the battery cells 302-1, 302-2, 302-N. This example utilizes the auto-zero amplifiers 100. However, other auto-zero amplifiers (as described throughout the description) may replace the auto-zero amplifiers 100. As described above regarding Figures 1 to 2 Each of the auto-zero amplifiers 100 (e.g., 100-1, 100-2, 1002N) is advantageously designed to decouple the first amplifier within the auto-zero amplifier from the first input terminal 114 and the second input terminal 116 during the auto-zero phase, thereby removing the AC noise that may have a negative impact on the auto-zero process. In some aspects, the auto-zero amplifiers 100 are part of a high-voltage analog front-end (HV AFE), which is part of a stackable battery monitor for an EV and / or HEV.

[0034] An EV or HEV battery may include many battery cells 302 stacked together. Thus, the differential voltage between a given cell and ground may be extremely high (e.g., up to 90 volts for 18 stacked cells). By providing an interface to measure the differential voltage between two terminals of a battery cell (e.g., 90 volts and 85 volts) and level shift the voltage to a smaller voltage (e.g., 5 volts and 0 volts), the auto-zero amplifier 100 acts as an HV AFE. The smaller voltage can then be coupled to an analog-to-digital converter that may not be able to support such a high voltage with respect to ground.

[0035] In some aspects, the sampling and hold procedure described in Figure 2 advantageously avoids large voltage transients during switching. For example, if the first input terminal 114 and the second input terminal 116 are connected to the last (e.g., highest voltage) battery cell of a plurality of battery cells, then with respect to ground, the first input terminal 114 may be connected to 90 volts and the second input terminal 116 may be connected to 85 volts. Since the voltage sampled by the sampling capacitor 204 is between 85 and 90 volts (e.g., 85 to 90 volts ± 4 volts AC noise), large voltage transients can be avoided during the switching of the first master switch 124, the second master switch 126, and the equalization switch 206. Conversely, if a regulated DC voltage (e.g., from an internal or external reference) is used, then this regulated DC voltage may be extremely low (e.g., 5 volts), which will introduce large voltage transients (e.g., 90 volts and 85 volts respectively) when switching to the first input terminal 114 and the second input terminal 116, which can result in a large amount of charge injection into sensitive components.

[0036] Figure 4A A waveform diagram 410 including the voltage varying with time at the input of the auto-zero amplifier (e.g., at the second input 112 of the first amplifier 104 of the auto-zero amplifier 100, as described in Figure 1 ). During the first operation phase 404a of the auto-zero amplifier 100, the signal AZ is low and the signal AZ' is high, as depicted by waveforms 420 and 430 respectively, but in other instances, the AZ signal may be high and the AZ' signal may be low. The second input 112 of the first amplifier 104 is coupled to the second input terminal 116, which may have a voltage 412 including a DC voltage of approximately ~85 volts and an AC voltage of approximately ± 4 volts during the first operation phase 404a.

[0037] At a first time point 414, the auto-zero amplifier 100 enters an auto-zero phase 406, where the signal AZ is high and the signal AZ' is low. During the auto-zero phase 406, the first input 110 and the second input 112 of the first amplifier 104 are coupled to a regulated (e.g., constant, flat) DC voltage 415, such as the reference Figure 1 voltage Vbias described. The voltage Vbias is provided to both the first input 110 and the second input 112 of the first amplifier 104 and is used to calibrate the first auto-zero capacitor 138. At a second time point 416, the auto-zero amplifier 100 switches back to the operational phase 404b (e.g., AZ is low and AZ' is high). The second input 112 of the first amplifier 104 is coupled to the second input terminal 116, and the calibration voltage stored on the first auto-zero capacitor 138 is used to compensate for the input offset voltage of the auto-zero amplifier 100.

[0038] It is noted that in the Figure 4A example, during the operational phases 404a, 404b, an AC component (e.g., AC noise and / or ripple) of the voltage 412 is present on the first and / or second input of the first amplifier. For example, the AC component of the voltage 412 can be common-mode AC noise. To help ensure accurate auto-zeroing and promote a low voltage offset of the auto-zero amplifier, the first and second inputs only see the DC voltage 415 during the auto-zero phase 406. Thus, the auto-zeroing technique provided herein provides a lower voltage offset than other methods.

[0039] Figure 4B Includes a waveform diagram 440 depicting the voltage at the input of the auto-zero amplifier (e.g., at the second input 112 of the first amplifier 104 of the auto-zero amplifier 200, reference Figure 2 described) as a function of time. During the first operational phase 404a of the auto-zero amplifier 200, the signal AZ is low and the signal AZ' is high, as depicted by waveforms 450 and 460, respectively. The second input 112 of the first amplifier 104 is coupled to the second input terminal 116, which can have a voltage 412 including a DC voltage of approximately ~85 volts and an AC voltage of approximately ±4 volts during the first operational phase 404a.

[0040] During the first operation phase 404a, sampling capacitors 204a, 204b are coupled to the first input terminal 114 and the second input terminal 116, respectively. Thus, during the operation phase, the voltages of the sampling capacitors 204 track (e.g., "sample") the voltages of the first input terminal 114 and the second input terminal 116. At the first time point 414, the auto-zero amplifier 200 enters the auto-zero phase 406, where the signal AZ is high and the signal AZ' is low. During the auto-zero phase 406, the first input 110 and the second input 112 of the first amplifier 104 are held at the common-mode voltage 445 stored on the sampling capacitor 204. In addition, the first input 110 of the first amplifier 104 is coupled to the second input 112 of the first amplifier 104, and the first auto-zero capacitor 138 is calibrated. Although the "held" voltage 445 of the sampling capacitor 204 may vary depending on the ratio voltage of the AC component when entering the auto-zero phase at the first time 414, the exact voltage is not important for auto-zero purposes. The "held" voltage 445 has minimal AC noise and is provided to both the first input 110 and the second input 112 of the first amplifier 104 (e.g., the potential difference is 0 volts). At the second time point 416, the auto-zero amplifier 200 switches back to the operation phase 404b (e.g., AZ is low and AZ' is high). The second input 112 of the first amplifier 104 is coupled to the second input terminal 116, and the calibrated voltage stored on the first auto-zero capacitor 138 is used to compensate for the input offset voltage of the auto-zero amplifier 200.

[0041] Figure 5 And Figure 6 respectively illustrate the auto-zero amplifiers 500, 600 in some aspects of this specification. The auto-zero amplifiers 500, 600 include: a first input terminal 114 and a second input terminal 116, to which input voltage potentials are received; and an output terminal 120, at which an output voltage potential is provided. As Figure 5 illustrated, the auto-zero amplifier 500 includes a first switch network 102, a first amplifier 104, and an auto-zero circuitry 122, which may be, for example, consistent with the first switch network 102, the first amplifier 104, and the auto-zero circuitry 122 described with reference to Figure 1 As Figure 6 illustrated, the auto-zero amplifier 600 includes a first switch network 202, a first amplifier 104, and an auto-zero circuitry 122, which may be, for example, consistent with the first switch network 202, the first amplifier 104, and the auto-zero circuitry 122 described with reference to Figure 2 As

[0042] The first amplifier 104 includes a third amplifier 502 and a fourth amplifier 504. A first resistor 506 and a first capacitor 507 are coupled to a first input of the third amplifier 502. A second input of the third amplifier 502 is coupled to a first node 508. The first node 508 is coupled to a second resistor 510, a first P-type metal-oxide-semiconductor (PMOS) transistor 512, and a second PMOS transistor 514. The second PMOS transistor 514 is coupled to a third PMOS transistor 516.

[0043] A third resistor 518 and a second capacitor 520 are coupled to a first input of the fourth amplifier 504. A second input of the fourth amplifier 504 is coupled to a second node 522. The second node 522 is coupled to the second resistor 510, a fourth PMOS transistor 524, and a fifth PMOS transistor 526. The fifth PMOS transistor is coupled to a sixth PMOS transistor 528.

[0044] A voltage VB1 is provided to the gates of the third PMOS transistor 516 and the sixth PMOS transistor 528. A voltage VB2 is provided to the gates of the second PMOS transistor 514 and the fifth PMOS transistor 526. The fourth PMOS transistor is coupled to an auto-zero circuit system 122 and an output terminal 120.

[0045] The auto-zero circuit system 122 further includes a current sink / source circuit system 530. The current sink / source circuit system is configured to sink / supply current according to the voltage output of the second amplifier 132 to adjust the voltage at the output terminal 120 so as to compensate for an input offset voltage. The current sink / source circuit system 530 includes a first N-type metal-oxide-semiconductor (NMOS) transistor 532 and a second NMOS transistor 534. The output 536 of the second amplifier 132 is coupled to the first NMOS transistor 532 and the second NMOS transistor 534, and a current Ioffset adjusts the input offset voltage. Voltages VB3, VB4 are respectively provided to the gates of the first NMOS transistor 532 and the second NMOS transistor 534. A fourth resistor 538 is coupled to the output terminal 120.

[0046] When canceling the non-zero offset of an auto-zero amplifier (e.g., any one of the auto-zero amplifiers 100, 200, 500, 600), accurate calibration of the first auto-zero capacitor 138 is important. Figure 7 Illustrates improved auto-zero capacitor calibration in some examples of this specification, while Figure 8 Illustrates the resulting improved accuracy of the output.

[0047] Figure 7 Is a waveform diagram illustrating the voltage varying with time at the auto-zero capacitor during the auto-zero phase in some aspects of this specification.

[0048] As an example, waveform 704 illustrates how the voltage of the auto-zero capacitor 138 changes during the auto-zero mode, consistent with some examples of the auto-zero amplifier 100 of Figure 1 and waveform 706 illustrates how the voltage of the auto-zero capacitor 138 changes during the auto-zero mode, consistent with some examples of the auto-zero amplifier 200 of Figure 2 For both waveforms 704 and 706, a DC voltage is used for auto-zero purposes (e.g., voltage Vbias for waveform 704 and the voltage on the sampling capacitor 204 for waveform 706), thereby better calibrating the first auto-zero capacitor 138 compared to other methods (e.g., other waveform 702 where there is AC noise on the first and second inputs during the auto-zero mode). For example, waveform 704 exhibits a peak-to-peak voltage of approximately ±19 μV, and waveform 706 exhibits a peak-to-peak voltage of approximately ±391 μV; while another manner of waveform 702 exhibits a peak-to-peak voltage greater than ±10 mV.

[0049] Figure 8 A waveform diagram depicting the output voltage of the auto-zero amplifier in some aspects of this specification, and the waveform diagram follows Figure 7 the waveform of. Waveform 804 corresponds to the output voltage of the auto-zero amplifier 100 or 200 given the auto-zero capacitor voltage of the given waveform 704. The stable auto-zero capacitor voltage of waveform 704 results in a low-noise output, e.g., ±1.3 mV. Waveform 806 corresponds to the output voltage of the auto-zero amplifier 100 given the auto-zero capacitor voltage of the given waveform 706. Similarly, the stable auto-zero capacitor voltage of waveform 706 results in an extremely low-noise output, e.g., ±2.1 mV. Compared to another method where there is DC noise on the first input and / or the second input (see waveform 802), the auto-zero amplifier technology of the present invention provides an output with a significantly lower offset voltage.

[0050] Figure 9 A logic flow diagram depicting a method 900 for generating an auto-zero reference using a DC voltage in some aspects of this specification. For example, method 900 may be executed by a control circuitry (e.g., control circuit 150).

[0051] Step 910 includes monitoring a first condition. Step 920 includes checking whether the first condition is satisfied. If the first condition is satisfied, then step 930 is executed. Otherwise, step 910 is executed again. In some examples, the first condition is a condition for triggering an auto-zero phase. For example, the auto-zero phase may be initiated periodically according to a timer, and the first condition corresponds to the expiration of the timer.

[0052] Step 930 includes transmitting a signal AZ corresponding to the auto - zero phase. The signal AZ causes the first switch network to decouple the input voltage, which may include AC common - mode noise, from the input of the amplifier (e.g., the first amplifier 104). The input of the amplifier is short - circuited to a DC reference voltage, such as the voltage Vbias or the voltage stored on capacitor 204a and / or capacitor 204b. The signal AZ may be transmitted, for example, by the control circuit 150.

[0053] Step 940 includes monitoring a second condition. Step 950 includes checking whether the second condition is met. If the second condition is met, then step 960 is performed. Otherwise, step 940 is performed again. In some instances, the second condition is a condition for triggering the operation phase. For example, a timer may start after entering the auto - zero phase, and the second condition corresponds to the expiration of the timer.

[0054] At step 960, a signal AZ' is transmitted, which corresponds to the operation phase. The signal AZ' causes the first switch network to couple the input voltage to the input of the amplifier (e.g., the first amplifier 104). Subsequently, method 900 may be repeated, starting again with step 910.

[0055] The methods are described above as a series of operations or events, but the recited order of these operations or events is not restrictive. For example, some operations or events may occur in a different order and / or concurrently with other operations or events other than those described and / or depicted herein. Additionally, some of the recited operations or events are optional for implementing one or more aspects or examples of the present specification. Further, one or more of the operations or events depicted herein may be performed in one or more separate operations and / or phases. In some instances, the methods described above may be implemented in a computer - readable medium using instructions stored in a memory.

[0056] In this specification, the term "coupled" may cover connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B by a direct connection; or (b) in a second instance, if an intermediate component C does not change the functional relationship between device A and device B, then device A is coupled to device B through the intermediate component C such that device B is controlled by device A via the control signal generated by device A.

[0057] A device “configured to” perform a task or function may be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform the function, and / or may be configured (or reconfigured) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be by programming of the device's firmware and / or software, by the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0058] As used herein, the terms “terminal,” “node,” “interconnection,” “pin,” and “lead” may be used interchangeably. Unless specifically stated to the contrary, these terms are generally used to denote the interconnection between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components, or their extremities.

[0059] A circuit or device described herein as including certain components may in fact be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may in fact include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, e.g., by an end user and / or a third party.

[0060] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may alternatively be used with little or no change to the remaining circuit system. For example, field effect transistors, bipolar junction transistors (BJTs, e.g., NPN or PNP), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in combination with the devices described herein. The transistors may be depletion-mode devices, drain extension devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Additionally, the device may be implemented in or on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0061] While some elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all of the features depicted as external to the integrated circuit may be included in the integrated circuit, and / or some features depicted as internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that: (i) are incorporated in / above a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated into the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0062] The use of the phrase "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection suitable or appropriate for the teachings of this specification. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10% of that parameter. Modifications may be made within the scope of the claims, and other embodiments are possible, in the described examples.

Claims

1. A circuit, which comprises: a first input voltage terminal; a second input voltage terminal; a direct current (DC) voltage terminal; an output voltage terminal; a first amplifier, which comprises: a first input, which is coupled to the first input voltage terminal via a first main switch; a second input, which is coupled to the second input voltage terminal via a second main switch; and an output, which is coupled to the output voltage terminal; an operation path, which extends between the output of the first amplifier and the output voltage terminal; a calibration path, which is arranged electrically in parallel with the operation path; a second amplifier, which is arranged along the calibration path, wherein the second amplifier comprises: a first input, which is coupled to the output of the first amplifier; a second input, which is coupled to the DC voltage terminal; and an output, which is coupled to the output voltage terminal; and a third main switch, which is coupled between the first input and the second input of the first amplifier.

2. The circuit according to claim 1, which further comprises: a control circuit; and an inverter, which comprises: an input, which is coupled to the control circuit; and an output; wherein a control terminal of the third main switch is coupled to the control circuit; and wherein control terminals of the first main switch and the second main switch are coupled to the output of the inverter.

3. The circuit according to claim 1, which further comprises: a first auto-zero switch, wherein the output of the first amplifier is coupled to the first input of the second amplifier via the first auto-zero switch; and a second auto-zero switch, wherein the DC voltage terminal is coupled to the second input of the second amplifier via the second auto-zero switch.

4. The circuit according to claim 3, which further comprises: a first sampling capacitor, which is coupled to the first input of the first amplifier; a second sampling capacitor, which is coupled to the second input of the first amplifier; a first auto-zero capacitor, which is coupled to the first input of the second amplifier; and a second auto-zero capacitor, which is coupled to the second input of the second amplifier.

5. The circuit according to claim 1, which further comprises: a current sink / source circuit, which is coupled between the output of the second amplifier and the output voltage terminal.

6. A circuit, which comprises: a first input voltage terminal; a second input voltage terminal; a third input voltage terminal; a first amplifier, which comprises: a first input, a second input, an output; a first main switch, which is coupled between the first input voltage terminal and the first input of the first amplifier; a second main switch, which is coupled between the second input voltage terminal and the second input of the first amplifier; a third main switch, which is coupled between the third input voltage terminal and the first input of the first amplifier; a fourth main switch, which is coupled between the third input voltage terminal and the second input of the first amplifier; a second amplifier, which comprises: a first input, a second input, and an output; A first auto-zero switch, which is coupled between the output of the first amplifier and the first input of the second amplifier; and A second auto-zero switch, which is coupled between a fourth input voltage terminal and the second input of the second amplifier; wherein the output of the second amplifier is coupled to the output of the first amplifier.

7. The circuit according to claim 6, wherein the third input voltage terminal is coupled to a regulated direct current (DC) voltage, and wherein the regulated DC voltage is approximately 5 volts.

8. The circuit according to claim 6, wherein the output of the second amplifier is coupled to the output of the first amplifier via a first transistor, and wherein the output of the second amplifier is coupled to ground via a second transistor.

9. The circuit according to claim 8, which further comprises: A first auto-zero capacitor, which is coupled to the first input of the second amplifier; and A second auto-zero capacitor, which is coupled to the second input of the second amplifier.

10. The circuit according to claim 9, wherein the first amplifier comprises: A third amplifier, which has a first input, a second input and an output, and the first input is coupled to the first input of the first amplifier; A fourth amplifier, which has a first input, a second input and an output, and the first input is coupled to the second input of the first amplifier; and A first resistor; wherein the second input of the third amplifier and the second input of the fourth amplifier are coupled via a resistor.

11. The circuit according to claim 10, wherein the first amplifier further comprises: A first capacitor, which is coupled to the first input of the third amplifier; A second capacitor, which is coupled to the first input of the fourth amplifier; A second resistor; and A third resistor; wherein the first input of the third amplifier is coupled to the first input of the first amplifier via the second resistor; and wherein the first input of the fourth amplifier is coupled to the second input of the first amplifier via the third resistor.

12. The circuit according to claim 11, wherein the first amplifier further comprises: A third transistor, which has a first terminal connected to the second input voltage terminal of the third amplifier and a control terminal coupled to the output of the third amplifier; and A fourth transistor, which has a first terminal connected to the second input voltage terminal of the fourth amplifier, a second terminal connected to the output of the first amplifier and a control terminal coupled to the output of the fourth amplifier.

13. The circuit according to claim 12, wherein the first amplifier further comprises: A fifth transistor, which has a first terminal and a second terminal; and A sixth transistor, which has a first terminal and a second terminal; The first terminal of the fifth transistor is coupled to a supply voltage, the second terminal of the fifth transistor is coupled to the first terminal of the sixth transistor; and the second terminal of the sixth transistor is coupled to the second terminal of the third amplifier.

14. The circuit according to claim 13, wherein the first amplifier further comprises: a seventh transistor having a first terminal and a second terminal; and an eighth transistor having a first terminal and a second terminal; wherein the first terminal of the seventh transistor is coupled to the supply voltage, the second terminal of the seventh transistor is coupled to the first terminal of the eighth transistor; and the second terminal of the eighth transistor is coupled to the second terminal of the fourth amplifier; wherein the control terminals of the fifth transistor and the seventh transistor are coupled together; and wherein the control terminals of the sixth transistor and the eighth transistor are coupled together.

15. An auto - zero amplifier, which comprises: a first amplifier having a first input, a second input, and an output; a first switch network coupled to the first input and the second input of the first amplifier, wherein the first switch network is configured to provide a first input voltage to the first input of the first amplifier and a second input voltage to the second input of the first amplifier during an operation phase, and wherein the first switch network is configured to couple the first input and the second input of the first amplifier during an auto - zero phase; a sampling capacitor coupled to the second input of the first amplifier; and an auto - zero circuit system coupled to the output of the first amplifier, wherein the auto - zero circuit system includes a first auto - zero capacitor, and wherein the auto - zero circuit system is configured to compensate for an input offset voltage of the first amplifier during the operation phase based on the voltage of the first auto - zero capacitor.

16. The auto - zero amplifier according to claim 15, wherein the sampling capacitor is configured to sample the voltage of the second input of the first amplifier during the operation phase and hold the voltage of the second input of the first amplifier during the auto - zero phase.

17. The auto - zero amplifier according to claim 15, wherein the first switch network comprises: a first main switch configured to provide the first input voltage to the first input of the first amplifier during the operation phase; a second main switch configured to provide the second input voltage to the second input of the first amplifier during the operation phase; and a balancing switch configured to couple the first input and the second input of the first amplifier during the auto - zero phase.

18. The auto - zero amplifier according to claim 15, wherein the auto - zero circuit system further comprises: a fourth switch configured to couple the output of the first amplifier to the first auto - zero capacitor during the auto - zero phase.

19. The automatic zeroing amplifier according to claim 18, wherein the automatic zeroing circuit system further comprises: A second amplifier, comprising: a first input coupled to the first automatic zeroing capacitor; a second input coupled to an adjustable direct current (DC) voltage; and an output coupled to the output of the first amplifier.

20. The automatic zeroing amplifier according to claim 19, wherein the automatic zeroing circuit system is configured to supply current to / draw current from the output of the first amplifier to compensate for the input offset voltage of the first amplifier.

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