Carbon-containing cap layer for doped semiconductor epitaxial layer

Abstract

A semiconductor structure includes a stack of alternating doped semiconductor epitaxial layers and cap epitaxial layers formed on a substrate. Each doped semiconductor epitaxial layer includes silicon having a carrier dopant, and each cap epitaxial layer includes carbon and silicon not doped with a carrier dopant.

Description

Technical Field

[0001] Embodiments described herein generally relate to semiconductor device manufacturing, and more particularly, to systems and methods for forming doped semiconductor layers and capping layers within a semiconductor structure. Background Art

[0002] Phosphorus-doped selective epitaxy techniques have drawn attention as a method for reducing the extrinsic transistor resistance in the source / drain of n-type metal-oxide semiconductor (MOS) devices. When forming metal contacts, high phosphorus doping is required to ensure low contact resistance. However, high concentrations of phosphorus dopants tend to diffuse, thereby impeding control of the doping profile in the phosphorus-doped epitaxial layer.

[0003] Accordingly, there is a need for methods and systems for epitaxially forming doped semiconductor layers to prevent dopant diffusion in the doped semiconductor layers. Summary of the Invention

[0004] Embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes a stack of alternating doped semiconductor epitaxial layers and capping epitaxial layers formed on a substrate. Each doped semiconductor epitaxial layer includes silicon having a carrier dopant, and each capping epitaxial layer includes silicon and carbon without a carrier dopant.

[0005] Embodiments of the present disclosure also provide a method for forming a doped semiconductor layer in a semiconductor structure. The method includes performing a plurality of cycles of a first deposition process, a second deposition process after the first deposition process, and an etching process. The first deposition process forms a doped semiconductor layer on an exposed surface of a substrate. The second deposition process forms an undoped capping layer on the doped semiconductor layer. The etching process selectively removes amorphous portions of the undoped capping layer and the doped semiconductor layer, and leaves epitaxial portions of the undoped capping layer and the doped semiconductor layer. The doped semiconductor layer includes silicon having a carrier dopant, and the undoped capping layer includes carbon.

[0006] Embodiments of the present disclosure further provide a processing system. The processing system includes a processing chamber and a system controller configured to cause the processing system to perform a first deposition process, a second deposition process after the first deposition process, and an etching process for a plurality of cycles. The first deposition process forms a doped semiconductor layer on an exposed surface of a substrate. The second deposition process forms an undoped capping layer on the doped semiconductor layer. The etching process selectively removes amorphous portions of the undoped capping layer and the doped semiconductor layer, and leaves epitaxial portions of the undoped capping layer and the doped semiconductor layer. The doped semiconductor layer includes silicon having a carrier dopant, and the undoped capping layer includes carbon. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] To understand the above features of the present disclosure in detail, a more specific description of the present disclosure briefly outlined above can be made with reference to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only show typical embodiments of the present disclosure and should not be considered as limiting its scope, as the present disclosure allows other equivalent embodiments.

[0008] Figure 1 FIG. is a schematic top view of a multi-chamber processing system according to one or more embodiments of the present disclosure.

[0009] Figure 2 FIG. is a cross-sectional view of a processing chamber according to one or more embodiments.

[0010] Figure 3 FIG. is a cross-sectional view of a semiconductor structure including a doped semiconductor layer and a cap layer according to one or more embodiments.

[0011] Figure 4 FIG. is a process flow diagram depicting a method of forming a contact layer in a semiconductor structure according to one or more embodiments of the present disclosure.

[0012] Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 5D 、 Figure 5E and Figure 5F are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of Figure 4 .

[0013] For ease of understanding, the same reference numerals are used as much as possible to denote the same elements in the drawings. It is contemplated that the elements and features of one embodiment can be advantageously incorporated into other embodiments without further recitation. DETAILED DESCRIPTION

[0014] The embodiments described herein provide methods and systems for forming a doped semiconductor epitaxial layer, wherein adjacent cap epitaxial layers prevent the diffusion of dopants. The doped semiconductor epitaxial layer includes a high concentration of silicon and carrier dopants. The cap epitaxial layer includes silicon and carbon and does not dope carrier dopants. A plurality of pairs of doped semiconductor epitaxial layers and cap epitaxial layers inserted therein are formed and can be used as source / drain in N-type metal-oxide semiconductor (NMOS) devices. Due to the prevention of dopant diffusion, a sharper doping profile can be achieved. In addition, due to the tensile strain induced in the cap epitaxial layer, the electron mobility can be enhanced, resulting in high conductivity in its device applications.

[0015] These methods include cyclic deposition and etching processes that allow for selective epitaxial growth of doped semiconductor layers and capping layers.

[0016] Figure 1 FIG. 6 is a schematic top view of a multi-chamber processing system 100 according to one or more embodiments of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 having respective transfer robots 112, 114, hold chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130. As described in detail herein, substrates in the processing system 100 can be processed in various chambers and transferred between various chambers without exposing the substrates to the surrounding environment external to the processing system 100 (e.g., the ambient atmosphere as may exist in a semiconductor fabrication facility). For example, substrates can be processed in various chambers maintained at a low pressure (e.g., less than or equal to about 300 Torr) or in a vacuum environment and transferred between various chambers without breaking the low pressure or vacuum environment during the various processes performed on the substrates in the processing system 100. Thus, the processing system 100 can provide an integrated solution for some processing of substrates.

[0017] Examples of processing systems that can be suitably modified in accordance with the teachings provided herein include or integrated processing systems, or other suitable processing systems available from Applied Materials, Inc. of Santa Clara, California. It is contemplated that other processing systems (including systems from other manufacturers) may also be adapted to benefit from the aspects described herein.

[0018] In Figure 1 the illustrated example, the factory interface 102 includes a docking station 132 and a factory interface robot 134 to facilitate substrate transfer. The docking station 132 is adapted to receive one or more front opening unified pods (FOUPs) 136. In some examples, each factory interface robot 134 generally includes blades 138 disposed at one end of the respective factory interface robot 134, and the blades 138 are adapted to transfer substrates from the factory interface 102 to the load lock chambers 104, 106.

[0019] The load lock chambers 104, 106 each have respective ports 140, 142 coupled to the factory interface 102 and respective ports 144, 146 coupled to the transfer chamber 108. The transfer chamber 108 further has respective ports 148, 150 coupled to the hold chambers 116, 118 and respective ports 152, 154 coupled to the process chambers 120, 122. Similarly, the transfer chamber 110 has respective ports 156, 158 coupled to the hold chambers 116, 118 and respective ports 160, 162, 164, 166 coupled to the process chambers 124, 126, 128, 130. The ports 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, 166 can be, for example, slit valve openings having slit valves for allowing substrates to pass therethrough by the transfer robots 112, 114 and for providing a seal between the respective chambers to prevent gas from passing between the respective chambers. Generally, any port is open for transferring a substrate therethrough. Otherwise, the port is closed.

[0020] The load lock chambers 104, 106, the transfer chambers 108, 110, the hold chambers 116, 118, and the process chambers 120, 122, 124, 126, 128, 130 can be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system can include one or more gas pumps (e.g., turbopumps, cryopumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the various chambers. In operation, the factory interface robot 134 transfers a substrate from the FOUP 136 to the load lock chamber 104 or 106 through the port 140 or 142. The gas and pressure control system then evacuates the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chambers 108, 110 and the hold chambers 116, 118 in an internal low pressure or vacuum environment (which can include an inert gas). Thus, evacuation of the load lock chamber 104 or 106 facilitates passage of the substrate between the atmospheric environment, such as the factory interface 102, and the low pressure or vacuum environment of the transfer chamber 108.

[0021] The substrate in the load lock chamber 104 or 106 has been evacuated, and the transfer robot 112 transfers the substrate from the load lock chamber 104 or 106 through the ports 144 or 146 to the transfer chamber 108. The transfer robot 112 can then transfer the substrate to any processing chamber 120, 122 and / or transfer between any processing chambers 120, 122 through the corresponding ports 152, 154 for processing, and transfer the substrate to the holding chambers 116, 118 through the corresponding ports 148, 150 for holding and waiting for further transfer. Similarly, the transfer robot 114 can access the substrate in the holding chambers 116 or 118 through the ports 156 or 158, and can transfer the substrate to any processing chamber 124, 126, 128, 130 and / or transfer between any processing chambers 124, 126, 128, 130 through the corresponding ports 160, 162, 164, 166 for processing, and transfer the substrate to the holding chambers 116, 118 through the corresponding ports 156, 158 for holding and waiting for further transfer. The transfer and holding of the substrate in various chambers and between chambers can be carried out in a low pressure or vacuum environment provided by the gas and pressure control system.

[0022] The processing chambers 120, 122, 124, 126, 128, 130 can be any suitable chambers for processing the substrate. In some examples, the processing chamber 120 can perform an etching process, the processing chamber 122 can perform a cleaning process, the processing chamber 124 can perform a selective removal process, and the processing chambers 126, 128, 130 can perform corresponding epitaxial growth processes. The processing chamber 120 can be a Selectra TM etching chamber available from Applied Materials, Inc. of Santa Clara, California. The processing chamber 122 can be a SiCoNi TM pre-cleaning chamber available from Applied Materials, Inc. of Santa Clara, California. The processing chambers 126, 128 or 130 can be a Centura TM Epi chamber available from Applied Materials, Inc. of Santa Clara, California.

[0023] The system controller 168 is coupled to the processing system 100 for controlling the processing system 100 or its components. For example, the system controller 168 can control the operation of the processing system 100 by using direct control of the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130 of the processing system 100 or by controlling the controllers associated with the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130. In operation, the system controller 168 enables data collection and feedback from the corresponding chambers to coordinate the performance of the processing system 100.

[0024] The system controller 168 generally includes a central processing unit (CPU) 170, a memory 172, and support circuitry 174. The CPU 170 can be one of any form of general-purpose processor that can be used in an industrial environment. The memory 172 or non-transitory computer-readable medium can be accessed by the CPU 170 and can be one or more memories, such as random access memory (RAM), read only memory (ROM), floppy disks, hard disks, or any other form of local or remote digital storage. The support circuitry 174 is coupled to the CPU 170 and can include a cache, clock circuitry, input / output subsystems, power supplies, and the like. The various methods disclosed herein can generally be implemented by computer instruction codes stored, for example, as software routines in the memory 172 (or the memory of a particular processing chamber), and executed by the CPU 170 under the control of the CPU 170. When the computer instruction codes are executed by the CPU 170, the CPU 170 controls the chamber to perform processes according to the various methods.

[0025] Other processing systems can adopt other configurations. For example, more or fewer processing chambers can be coupled to the transfer device. In the illustrated example, the transfer device includes transfer chambers 108, 110 and holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) can be implemented as the transfer device in the processing system.

[0026] Figure 2 FIG. is a cross-sectional view of a processing chamber 200 according to one or more embodiments, suitable for performing an epitaxial (Epi) deposition process, as detailed below. The processing chamber 200 can be Figure 1 the processing chamber 126, 128, or 130 shown.

[0027] The processing chamber 200 includes an outer shell structure 202 made of a process-resistant material, such as aluminum or stainless steel, such as 216L stainless steel. The outer shell structure 202 encloses various functional elements of the processing chamber 200, such as a quartz chamber 204, which includes an upper quartz chamber 206 and a lower quartz chamber 208, which contains a processing volume 210. Reactive species are provided to the quartz chamber 204 through a gas distribution assembly 212, and processing by-products are removed from the processing volume 210 through an outlet port 214, which is generally in communication with a vacuum source (not shown).

[0028] The substrate support 216 is adapted to receive a substrate 218 transferred to the processing volume 210. The substrate support 216 is disposed along the longitudinal axis 220 of the processing chamber 200. The substrate support 216 can be made of a ceramic material or a graphite material coated with a silicon material (such as silicon carbide) or other materials resistant to processing. Reactive species from the precursor reactant material are coated onto the surface 222 of the substrate 218, and by-products can then be removed from the surface 222 of the substrate 218. Heating of the substrate 218 and / or the processing volume 210 can be provided by radiation sources, such as an upper lamp module 224A and a lower lamp module 224B.

[0029] In one embodiment, the upper lamp module 224A and the lower lamp module 224B are infrared (IR) lamps. Non-thermal energy or radiation from the lamp modules 224A and 224B travels through the upper quartz window 226 of the upper quartz chamber 206 and through the lower quartz window 228 of the lower quartz chamber 208. If needed, cooling gas for the upper quartz chamber 206 enters through the inlet 230 and exits through the outlet 232. Precursors reactant materials, diluents, purge, and exhaust gases for the processing chamber 200 enter through the gas distribution assembly 212 and exit through the outlet port 214. Although the upper quartz window 226 is shown as curved or convex, the upper quartz window 226 can be planar or concave because the pressures on both sides of the upper quartz window 226 are substantially the same (i.e., atmospheric pressure).

[0030] Low-wavelength radiation in the processing volume 210 is used to excite reactive species and helps to adsorb reactants and desorb processing by-products from the surface 222 of the substrate 218. The low-wavelength radiation generally ranges from about 0.8 μm to about 1.2 μm, for example, between about 0.95 μm to about 1.05 μm, depending on, for example, the composition of the film grown epitaxially to provide various combinations of wavelengths.

[0031] Component gases enter the processing volume 210 through the gas distribution assembly 212. The gases flow out of the gas distribution assembly 212 and exit through the outlet port 214, as shown by the flow path 234. Combinations of component gases for cleaning / passivating the substrate surface or forming silicon- and / or germanium-containing films for epitaxial growth are typically mixed before entering the processing volume 210. The total pressure in the processing volume 210 can be adjusted through a valve (not shown) on the outlet port 214. At least a portion of the inner surface of the processing volume 210 is covered by a liner 236. In one embodiment, the liner 236 includes an opaque quartz material. In this way, the chamber wall is insulated from the heat in the processing volume 210.

[0032] The surface temperature within the processing volume 210 can be controlled within a temperature range of about 200°C to about 600°C or higher through the flow of cooling gas and in combination with radiation from the upper lamp module 224A located above the upper quartz window 226. The cooling gas enters through the inlet 230 and exits through the outlet 232. By adjusting the speed of a blower unit (not shown) and through radiation from the lower lamp module 224B located below the lower quartz chamber 208, the temperature within the lower quartz chamber 208 can be controlled within a temperature range of about 200°C to about 600°C or higher. The pressure within the processing volume 210 can be between about 0.1 Torr and about 600 Torr, such as between about 5 Torr and about 30 Torr.

[0033] The temperature of the surface 222 of the substrate 218 can be controlled by adjusting the power of the lower lamp module 224B within the lower quartz chamber 208, or by adjusting the power of both the upper lamp module 224A covering the upper quartz window 226 and the lower lamp module 224B within the lower quartz chamber 208. The power density within the processing volume 210 can be between about 40 W / cm 2 and about 400 W / cm 2 , such as about 80 W / cm 2 to about 120 W / cm 2 .

[0034] In one aspect, the gas distribution assembly 212 is disposed perpendicular to the longitudinal axis 220 of the processing chamber 200 or the substrate 218, or is disposed radially 238 with respect to the longitudinal axis 220 of the processing chamber 200 or the substrate 218. In this orientation, the gas distribution assembly 212 is adapted to cause the processing gas to flow radially 238 across the surface 222 of the substrate 218, or to flow parallel to the surface. In one processing application, the processing gas is preheated when introduced into the processing chamber 200 to initiate preheating of the gas before introduction into the processing volume 210, and / or to break specific bonds in the gas. In this way, the surface reaction kinetics can be modified independently of the thermal temperature of the substrate 218.

[0035] In operation, precursors for forming silicon (Si) and silicon germanium (SiGe) blanket or selective epitaxial films are provided from one or more gas sources 240A and 240B to the gas distribution assembly 212. Infrared lamps 242 ( Figure 2 only one is shown) can be used to heat the precursors within the gas distribution assembly 212 and along the flow path 234. The gas sources 240A, 240B can be coupled to the gas distribution assembly 212 in a manner adapted to facilitate introduction into regions within the gas distribution assembly 212, such as the radially outer region and the radially inner region between the outer region when viewed from a top plan view. The gas sources 240A, 240B can include valves (not shown) to control the rate of introduction into the regions.

[0036] The gas sources 240A, 240B may include silicon precursors such as silane, including silane (SiH 4 ), disilane (Si 2 H 6 ), dichlorosilane (SiH 2 Cl 2 ), hexachlorodisilane (Si 2 Cl 6 ), dibromosilane (SiH 2 Br 2 ), higher-order silanes, their derivatives, and combinations thereof. The gas sources 240A, 240B may also include germanium precursors such as germane (GeH 4 ), digermane (Ge 2 H 6 ), germanium tetrachloride (GeCl 4 ), dichlorogermane (GeH 2 Cl 2 ), their derivatives, and combinations thereof. The silicon- and / or germanium-containing precursors may be used in combination with hydrogen chloride (HCl), chlorine gas (Cl 2 ), hydrogen bromide (HBr), and combinations thereof. The gas sources 240A, 240B may include one or more of the silicon- and germanium-containing precursors in one or both of the gas sources 340A, 340B.

[0037] The precursor material in this excited state enters the processing volume 210 through the openings or holes 244 in the perforated plate 246 ( Figure 2 only one is shown), and the perforated plate 246 is made of quartz material in one embodiment and has holes 244 formed therethrough. The perforated plate 246 is transparent to IR energy and may be made of transparent quartz material. In other embodiments, the perforated plate 246 may be any material that is transparent to IR energy and resistant to processing chemicals and other processing chemicals. The excited precursor material flows through the holes 244 in the perforated plate 246 and through the channels 248 ( Figure 2 only one is shown) to the processing volume 210. A portion of the photons and non-thermal energy from the IR lamp 242 also passes through the holes 244, the perforated plate 246, and the channels 248, which is facilitated by the reflective material and / or surface disposed on the inner surface of the gas distribution assembly 212, thereby illuminating the flow path 234 of the precursor material. In this way, the vibrational energy of the precursor material can be maintained along the flow path from the time it is introduced into the processing volume 210.

[0038] Figure 3FIG. 0 is a cross-sectional view of a semiconductor structure 300 including a doped semiconductor layer and a cap layer according to one or more embodiments of the present disclosure. The doped semiconductor layer doped with an n-type carrier dopant such as phosphorus can be used as a source / drain in a negative metal-oxide semiconductor (NMOS) device.

[0039] The semiconductor structure 300 includes a substrate 302 and a stack of alternating doped semiconductor epitaxial layers 304E formed on the substrate 302 and cap epitaxial layers 306E inserted between the doped semiconductor epitaxial layers 304E.

[0040] As used herein, the term "substrate" refers to a layer of material that serves as a basis for subsequent processing operations and includes a surface to be cleaned. As needed, the substrate can be a silicon-based material or any suitable insulating or conductive material. The substrate can include materials such as crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or unpatterned wafers, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire.

[0041] The doped semiconductor epitaxial layer 304E is formed of silicon (Si) or silicon germanium (SiGe), and the ratio of germanium (Ge) ranges between 20% and 100%. The doped semiconductor epitaxial layer 304E can be doped with an n-type carrier dopant such as phosphorus (P) or antimony (Sb) at a concentration between about 10 19 cm- 3 and 5×10 21 cm- 3 depending on the desired conductive characteristics of the semiconductor structure 300. The doped semiconductor epitaxial layer 304E can be doped with a p-type carrier dopant such as boron (B), gallium (Ga), aluminum (Al), or indium (In) at a concentration between about 10 20 cm- 3 and 5×10 21 cm- 3 depending on the desired conductive characteristics of the semiconductor structure 300.

[0042] The cap epitaxial layer 306E may be formed of undoped carbon (C), carbon-doped silicon (Si:C), or carbon-doped silicon germanium (SiGe:C). The cap epitaxial layer 306E may not be doped with carrier dopants. In the cap epitaxial layer 306E, strain is induced by replacing silicon or germanium atoms in the doped crystalline structure with carbon atoms. For example, replacing silicon (Si) atoms with carbon (C) induces tensile strain due to the difference in lattice constants between silicon (Si) (e.g., crystalline silicon (Si) has a lattice constant of 5.431 angstroms) and carbon (e.g., diamond carbon has a lattice constant of 3.567 angstroms) and germanium (Ge) and carbon (C). Replacing germanium (Ge) atoms with carbon (C) also induces tensile strain due to the difference in lattice constants between germanium (Ge) (e.g., crystalline germanium (Ge) has a lattice constant of 5.65 angstroms) and carbon (C). The strain-induced cap epitaxial layer 306 prevents carrier dopants (eg, phosphorus (P)) from migrating out of the adjacent doped semiconductor epitaxial layer 304E, thereby providing a sharp doping profile. In addition, the strain-induced cap epitaxial layer 306 enhances electron mobility, resulting in higher conductivity in its potential device applications.

[0043] The doped semiconductor epitaxial layers 304E may each have a thickness between about 15 angstroms and about 20 angstroms. The cap epitaxial layers 306E may each have a thickness between about 5 angstroms and about 15 angstroms. The semiconductor structure 300 may have about 30 pairs of doped semiconductor epitaxial layers 304E and cap epitaxial layers 306E, with a total thickness between about 500 angstroms and about 700 angstroms, such as about 600 angstroms.

[0044] Figure 4 A process flow diagram of a method 400 of forming a doped semiconductor layer in a semiconductor structure 300 is depicted in accordance with one or more embodiments of the present disclosure. Figure 5A , 5B 5C, 5D, 5E and 5F are cross-sectional views of a portion of semiconductor structure 300 corresponding to various states of method 400. It should be understood that Figure 5A , 5B 5C, 5D, 5E and 5F are only partial schematic diagrams of semiconductor structure 300, and semiconductor structure 300 may contain any number of transistor portions, dielectric layers and additional materials not shown in the figures. It should also be noted that although the order is described, Figure 4 Other process sequences that are the methods shown, but include one or more operations that have been omitted and / or added and / or have been rearranged in another desired order, are also within the scope of embodiments of the disclosure provided herein.

[0045] The method 400 begins at block 410 where a first deposition process is performed to form a doped semiconductor layer 304 on an exposed surface of the substrate 302, such as Figure 5AAs shown. The first deposition process may include any suitable deposition technique performed by flowing a deposition gas in a processing chamber (such as Figure 1 the processing chambers 126, 128, or 130 shown or Figure 2 the processing chamber 200 shown), such as epitaxial (Epi) deposition, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).

[0046] The doped semiconductor layer 304 is formed of silicon (Si) or silicon germanium (SiGe), and the ratio of germanium (Ge) ranges between 20% and 100%. The doped semiconductor layer 304 may be doped with an n-type carrier dopant having a concentration between about 10 19 cm -3 and 5×10 21 cm -3 , such as phosphorus (P) or antimony (Sb), depending on the desired conductive characteristics of the semiconductor structure 300. The doped semiconductor layer 304 may be doped with a p-type carrier dopant having a concentration between about 10 20 cm -3 and 5×10 21 cm -3 , such as boron (B), gallium (Ga), aluminum (Al), or indium (In), depending on the desired conductive characteristics of the semiconductor structure 300.

[0047] In some embodiments, the deposition gas used in the first deposition process includes a silicon precursor, a germanium precursor, and a dopant source. The silicon precursor may include silane (SiH 4 ), disilane (Si 2 H 6 ), tetrasilane (Si 4 H 10 ), or a combination thereof. The germanium precursor may include germane (GeH 4 ), germanium tetrachloride (GeCl 4 ), and digermane (Ge 2 H 6 ). The n-type dopant source may include phosphine (PH 3 ), phosphorus trichloride (PCl 3 ), triisobutylphosphine ([(CH 3 ) 3 C] 3 P), antimony trichloride (SbCl 3 ), Sb(C 2 H 5 ) 5 , arsine (AsH3 ), arsenic trichloride (AsCl 3 ), or tertiary butyl arsine (AsC 4 H 11 ). The p-type dopant source may include diborane (B 2 H 6 ), or boron trichloride (BCl 3 ).

[0048] In the first deposition process of block 410, due to different nucleation rates of the doped semiconductor layer 304 on the surface of, for example, the semiconductor region (e.g., silicon (Si) or silicon germanium (SiGe)) of the substrate 302 and the doped semiconductor layer 304 on the surface of the dielectric region (e.g., silicon dioxide (SiO 2 )) or silicon nitride (Si 3 N 4 )) of the substrate 302, the deposited doped semiconductor layer 304 may include an epitaxial portion 304E and an amorphous portion 304A. Nucleation may occur at a faster rate on the surface of the semiconductor region than on the surface of the dielectric region, and thus the epitaxial portion 304E of the doped semiconductor layer 304 may be selectively formed on the surface of the semiconductor region, while the amorphous portion 304A of the doped semiconductor layer 304 may be formed on the surface of the dielectric region. In block 430, the amorphous portion 304A of the doped semiconductor layer 304 may be removed in a subsequent etching process.

[0049] The first deposition may be performed at a low temperature below about 450 °C and a pressure of 5 Torr to 600 Torr.

[0050] In block 420, after the first deposition process, a second deposition process is performed to form a cap layer 306 on the doped semiconductor layer 304, as Figure 5B shown. The cap layer 306 may be formed of undoped carbon (C), silicon-doped carbon (Si:C), or silicon-germanium-doped carbon (SiGe:C). The cap layer 306 may not be doped with carrier dopants. The second deposition process may include any suitable deposition technique performed by flowing a deposition gas in a processing chamber, such as epitaxial (Epi) deposition, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).

[0051] In some embodiments, the deposition gas used in the second deposition process includes a silicon precursor, a germanium precursor, and a carbon source. The silicon precursor may include silane (SiH 4 ), disilane (Si 2 H 6)), tetrasilane (Si 4 H 10 ), or a combination thereof. The germanium precursor may include germane (GeH 4 ), germanium tetrachloride (GeCl 4 ), and digermane (Ge 2 H 6 ). The carbon source may include silylalkanes such as monosilylmethane, disilylmethane, trisilylmethane, and tetrasilylmethane, alkylsilanes such as monomethylsilane (MMS) and dimethylsilane.

[0052] In the second deposition process in block 420, due to the different nucleation rates of the capping layer 306 on the surface of the epitaxial portion 304E of the doped semiconductor layer 304 and the capping layer 306 on the surface of the amorphous portion 304A of the doped semiconductor layer 304, the capping layer 306 may include an epitaxial portion 306E and an amorphous portion 306A. Nucleation may occur at a faster rate on the surface of the epitaxial portion 304E of the doped semiconductor layer 304 than on the surface of the amorphous portion 304A of the doped semiconductor layer 304, and thus the epitaxial portion 306E of the capping layer 306 may be selectively formed on the surface of the epitaxial portion 304E of the doped semiconductor layer 304, while the amorphous portion 306A of the capping layer 306 may be formed on the surface of the amorphous portion 304A of the doped semiconductor layer 304. In block 430, the amorphous portion 306A of the capping layer 306 may be removed in a subsequent etching process.

[0053] The second deposition may be performed at a low temperature below about 450 °C and a pressure of 5 Torr to 600 Torr.

[0054] In block 430, an etching process is performed to remove the amorphous portion 306A of the capping layer 306 and the underlying amorphous portion 304A of the doped semiconductor layer 304, as Figure 5C and 5D shown. By flowing an etching gas in the processing chamber, the etching process in block 430 may be performed after the second deposition process in block 420, or simultaneously with the first deposition process in block 410 and the second deposition process in block 420.

[0055] In the etching process, the amorphous portion 306A of the capping layer 306 may be etched at a faster rate than the epitaxial portion 306E of the capping layer 306 by an appropriate etching gas, and the epitaxial portion 306E of the capping layer 306 is not etched, as Figure 5CAs shown. The capping layer 306 is not doped with carrier dopants, and thus the etch selectivity between the amorphous portion 306A and the epitaxial portion 306E is greater than the etch selectivity between the amorphous portion and the epitaxial portion of a doped capping layer including silicon and carbon. By using the epitaxial portion 306E of the capping layer 306 as a mask, the underlying amorphous portion 304A of the doped semiconductor layer 304 can be further etched, and the epitaxial portion 304E of the doped semiconductor layer 304 is not etched, as Figure 5D shown. Thus, the overall result of combining the epitaxial deposition process and the etching process can be the growth of the epitaxial portion 304E of the doped semiconductor layer 304 (also referred to as the "doped semiconductor epitaxial layer") and the epitaxial portion 306E of the capping layer 306 (also referred to as the "capping layer epitaxial layer") on the substrate 302.

[0056] The etch gas used in the etching process of block 430 includes an etch gas and a carrier gas. The etch gas can include a halogen-containing gas such as hydrogen chloride (HCl), chlorine gas (Cl 2 ), or hydrogen fluoride (HF). The carrier gas can include nitrogen gas (N 2 ), argon (Ar), helium (He), or hydrogen gas (H 2 ).

[0057] The cycles of the first deposition process in block 410, the second deposition process in block 420, and the etching process in block 430 can be repeated as needed, as Figure 5E and 5F shown, to obtain a desired combined thickness of the doped semiconductor epitaxial layer 304E and the capping epitaxial layer 306E between about 500 angstroms and about 700 angstroms (e.g., about 600 angstroms). The cycle can be repeated, for example, about 30 times.

[0058] The embodiments described herein provide methods and systems for forming a contact epitaxial layer in a trench on a selected portion of a transistor structure and forming a capping layer on the contact epitaxial layer to protect the contact epitaxial layer from oxidation and contamination. The contact trench structure includes a metal contact plug formed in a trench between adjacent device modules and a contact interposed between the contact plug and a silicon-based channel in the device module. The contact is formed by selective deposition, reducing parasitic resistance. A void-free metal contact plug is formed through a deposition-etching-deposition process, reducing contact resistance. The contact epitaxial layer can be p-type silicon germanium formed on an exposed surface of a p-type MOS device (such as silicon germanium), while no epitaxial layer can be formed on an n-type MOS (such as silicon) or on a dielectric layer formed on both p-type MOS devices and n-type MOS devices. Due to the capping layer, damage to the fabricated contact epitaxial layer is reduced.

[0059] The embodiments described herein provide methods and systems for forming doped semiconductor epitaxial layers, where adjacent capping epitaxial layers prevent dopant diffusion. The doped semiconductor epitaxial layer includes a high concentration of silicon and a carrier dopant. The capping epitaxial layer includes silicon and carbon and is not doped with the carrier dopant. The method includes periodic deposition and etching processes that allow for selective epitaxial growth of the doped semiconductor layer and the capping layer.

[0060] Forming multiple pairs of doped semiconductor epitaxial layers and capping epitaxial layers inserted within the doped semiconductor epitaxial layers, and these can be used as source / drains in NMOS devices. Due to the prevention of dopant diffusion, a sharper doping profile can be obtained. Additionally, due to the tensile strain induced in the capping epitaxial layer, the electron mobility can be enhanced, resulting in high conductivity in their device applications.

[0061] Although the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, the scope of which is determined by the appended claims.

Claims

1. A semiconductor structure, the semiconductor structure comprising: a stack of alternating doped semiconductor epitaxial layers and cap epitaxial layers formed on a substrate, wherein each doped semiconductor epitaxial layer comprises silicon having a carrier dopant, and each cap epitaxial layer comprises silicon and carbon without a carrier dopant.

2. The semiconductor structure according to claim 1, wherein the carrier dopant comprises phosphorus.

3. The semiconductor structure according to claim 1, wherein each doped semiconductor epitaxial layer has a thickness between 15 angstroms and 20 angstroms, and each cap epitaxial layer has a thickness between 5 angstroms and 15 angstroms.

4. The semiconductor structure according to claim 1, wherein the stack of alternating doped semiconductor epitaxial layers and cap epitaxial layers has a thickness between 500 angstroms and 700 angstroms.

5. A method of forming a doped semiconductor layer in a semiconductor structure, the method comprising: performing a plurality of cycles of a first deposition process, a second deposition process after the first deposition process, and an etching process, the first deposition process forming a doped semiconductor layer on an exposed surface of a substrate; the second deposition process forming an undoped cap layer on the doped semiconductor layer; and the etching process selectively removing an amorphous portion of the undoped cap layer and an amorphous portion of the doped semiconductor layer, and retaining an epitaxial portion of the undoped cap layer and an epitaxial portion of the doped semiconductor layer, wherein the doped semiconductor layer comprises silicon having a carrier dopant, and the undoped cap layer comprises carbon.

6. The method according to claim 5, wherein the carrier dopant comprises phosphorus.

7. The method according to claim 5, wherein the doped semiconductor layer has a thickness between 15 angstroms and 20 angstroms, and the undoped cap layer has a thickness between 5 angstroms and 15 angstroms.

8. The method according to claim 5, wherein the first deposition process comprises: flowing a silicon precursor and a dopant source in a processing chamber.

9. The method according to claim 8, wherein the second deposition process comprises: flowing a silicon precursor and a carbon source in the processing chamber.

10. The method according to claim 9, wherein the etching process comprises: after the second deposition process, flowing an etchant gas and a carrier gas in a processing gas.

11. The method according to claim 9, the etching process comprises: while the first deposition process and the second deposition process are being performed, flowing an etchant gas and a carrier gas in a processing gas.

12. The method according to claim 9, wherein the first deposition process and the second deposition process are performed at a low temperature below about 450 °C and a pressure of 5 torr to 600 torr.

13. A processing system, the processing system comprising: a processing chamber; and a system controller configured to cause the processing system to: perform a plurality of cycles of a first deposition process, a second deposition process after the first deposition process, and an etching process, the first deposition process forming a doped semiconductor layer on an exposed surface of a substrate; the second deposition process forming an undoped cap layer on the doped semiconductor layer; and The etching process selectively removes the amorphous portions of the undoped capping layer and the doped semiconductor layer, and retains the epitaxial portions of the undoped capping layer and the doped semiconductor layer, wherein the doped semiconductor layer comprises silicon having a carrier dopant, and the undoped capping layer comprises carbon.

14. The processing system of claim 13, wherein the carrier dopant comprises phosphorus.

15. The processing system of claim 13, wherein the doped semiconductor layer has a thickness between 15 angstroms and 20 angstroms, and the undoped capping layer has a thickness between 5 angstroms and 15 angstroms.

16. The processing system of claim 13, wherein the first deposition process comprises: flowing a silicon precursor and a dopant source in the processing chamber.

17. The processing system of claim 16, wherein the second deposition process comprises: flowing a silicon precursor and a carbon source in the processing chamber.

18. The processing system of claim 17, wherein the etching process comprises: after the second deposition process, flowing an etchant gas and a carrier gas in a processing gas.

19. The processing system of claim 17, the etching process comprises: while the first deposition process and the second deposition process are being performed, flowing an etchant gas and a carrier gas in a processing gas.

20. The processing system of claim 19, wherein the first deposition process and the second deposition process are performed at a low temperature below about 450 °C and a pressure of 5 torr to 600 torr.

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