Multi-data-bit and high-dynamic-range seismic data acquisition method and device

Abstract

The invention discloses a multi-data-bit and high-dynamic-range seismic data acquisition method and device, and the method comprises the steps: respectively obtaining a large signal and a small signal in original seismic signals at the same time, carrying out the attenuation processing of the large signal, and carrying out the amplification processing of the small signal; the amplified small signal enters the first ADC sampling circuit, and the attenuated large signal enters the second ADC sampling circuit; and selecting low-order data of a first preset digit from the first ADC sampling circuit, selecting high-order data of a second preset digit from the second ADC sampling circuit, and splicing and processing the high-order data and the low-order data to obtain acquisition data of a preset digit. According to the technical scheme of the invention, seismic signals with a larger dynamic range can be obtained, and the problems of large seismic amplitude limiting and the like due to the fact that the dynamic range of the collector is not wide enough are solved, so that people can master and record more accurate and more complete seismic data.

Description

Technical Field

[0001] The present invention relates to the field of digital earthquake detection and the processing and analysis of earthquake strength and weakness signals based on high dynamic range and high precision data acquisition, and in particular to a multi-data bit and high dynamic range earthquake data acquisition method and device. Background Art

[0002] Data acquisition is a critical part in the field of earthquake detection. The accuracy and quality of the collected signal directly affect the quality of the earthquake signal and the accuracy of the analysis. Therefore, the resolution and dynamic range have become the most important indicators of signal acquisition in the field of earthquake detection. Good resolution can obtain more accurate signal data, so that some micro-earthquake information can be obtained in earthquake detection, while improving the tolerance for large signals and reducing the situation of large signal limiting distortion; and the dynamic range represents the span of the maximum input signal and the minimum input signal obtained.

[0003] The seismic data collectors widely used in modern times are generally 24-bit seismic data collectors, with a dynamic range of about 135dB~138dB. There are also some 26-bit seismic data collectors, whose dynamic range can only reach about 140dB-145dB. The dynamic range of seismometers currently used for earthquake detection can reach more than 160dB, while the accuracy and dynamic range of seismic data collectors are obviously limited, resulting in insufficient resolution of small earthquake information during earthquake detection, insufficient dynamic amplitude of acquisition, easy to cause large earthquake limiting, low signal-to-noise ratio and other problems, and unable to effectively extract complete earthquake information, resulting in the loss of the opportunity to record complete earthquake data in earthquake research. Summary of the invention

[0004] To overcome the deficiencies of the prior art, the embodiments of the present invention provide a multi-data bit and high dynamic range seismic data acquisition method and device, which can obtain seismic signals with a larger dynamic range and solve problems such as large earthquake limiting caused by the insufficient dynamic range of the collector, thereby enabling humans to grasp and record more accurate and complete seismic data.

[0005] A multi-data-bit and high-dynamic-range seismic data acquisition method, comprising:

[0006] At the same time, the large signal and the small signal in the original seismic signal are respectively obtained, and the large signal is attenuated and the small signal is amplified;

[0007] The amplified small signal enters the first ADC sampling circuit, so that the attenuated large signal enters the second ADC sampling circuit; wherein the first ADC sampling circuit and the second ADC sampling circuit have the same number of sampling data bits;

[0008] A first preset number of low-bit data is selected from the first ADC sampling circuit, a second preset number of high-bit data is selected from the second ADC sampling circuit, and the high-bit data and the low-bit data are spliced ​​and processed to obtain a predetermined number of collected data; wherein the first preset number of bits and the second preset number of bits are less than the number of bits of the sampling data, and the sum of the first preset number of bits and the second preset number of bits is greater than the number of bits of the sampling data.

[0009] A multi-data bit and high dynamic range seismic data acquisition device, used to implement the multi-data bit and high dynamic range seismic data acquisition method, and comprising:

[0010] The first signal processing circuit is used to obtain a small signal in the original seismic signal and amplify the small signal;

[0011] A second signal processing circuit is used to obtain a large signal in the original seismic signal and perform attenuation processing on the large signal;

[0012] An ADC sampling circuit includes two ADC chips with sampling data bits, and the two ADC chips are used to receive a small signal after amplification and a large signal after attenuation respectively;

[0013] The decision splicing module is used to select low-bit data of a first preset number of bits from the first ADC sampling circuit, select high-bit data of a second preset number of bits from the second ADC sampling circuit, and splice and process the high-bit data and the low-bit data to obtain the collection data of a predetermined number of bits.

[0014] The above-mentioned multi-data-bit and high-dynamic-range seismic data acquisition method and device, its principle is: adopt the method of frame acquisition, design the attenuation circuit for large signals and the amplification circuit for small signals respectively, the dual-channel signals work simultaneously, after passing through the front-end circuit, they enter the two multi-bit ADC analog-to-digital conversion chips that overlap in the middle part, select the low-bit data of the first ADC sampling circuit and the high-bit data of the second ADC sampling circuit respectively for splicing processing, and finally through the judgment module, the high-precision data of the predetermined number of bits can be obtained more accurately.

[0015] Compared with the prior art, the technical solution provided by the present invention has the following advantages:

[0016] 1) Use two low-bit ADC chips to achieve high-bit data acquisition. Since AD ​​sampling has two noises, one is quantization noise. For low sampling bits, there is quantization noise, but for more than 20 bits, quantization has been divided into very fine parts. Its bottleneck lies in its thermal noise, but its thermal noise is limited by the chip itself. Its limit is now only 26 bits because its internal noise is too large and it cannot be reduced in the future. Therefore, using two low-bit AD chips cleverly solves this problem.

[0017] 2) The large signal and small signal circuits work simultaneously without interfering with each other. When a small signal is input, the amplifier circuit works normally, amplifies the small signal, and does not interfere with the attenuation circuit; when a large signal comes in, the attenuation circuit works normally, attenuates the large signal, and the amplifier circuit may produce a certain degree of saturation, but will not cause limiting, nor interfere with each other.

[0018] 3) Obtain more accurate multi-bit data than the existing sampling data. Taking the existing 24-bit ADC chip as an example, by calibrating the data of two ADC sampling circuit chips after dual-channel operation, 30-bit data can be obtained.

[0019] 4) According to the performance and functional requirements of the data collector, the splicing bits of the two ADs can be flexibly selected, that is, the number of bits of the chip in the ADC sampling circuit is not limited to 24 bits, and can be extended to a larger dynamic range or to achieve high dynamic applications at low cost.

[0020] 5) To solve the problem of data limiting in the amplifier circuit, two diodes are connected in parallel at the positive and negative ends of the feedback resistor in the conventional circuit. Experimental verification shows that the data logger will not be limited and the maximum indication error is greatly reduced.

[0021] 6) When collecting small signals, enabling the dequantization noise function will remove the collected 0-bit data, effectively improving the minimum resolution.

[0022] 7) The data processing of the low-level and high-level splicing positions adopts the function of eliminating empty steps, which can realize accurate data collection and splicing. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0024] Figure 1 It is a framework diagram of a multi-data-bit and high-dynamic-range seismic data acquisition device according to an embodiment of the present invention;

[0025] Figure 2 is a schematic diagram of a signal processing circuit in an embodiment of the present invention;

[0026] Figure 3 Schematic diagram of the operation of the judgment splicing module in the embodiment of the present invention. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] Provided is a method and device for acquiring multi-data-bit and high-dynamic-range seismic data, such as Figures 1 to 3 As shown, the multi-data bit and high dynamic range seismic data acquisition method includes the following steps:

[0029] S1, simultaneously obtains the large signal and the small signal in the original seismic signal, and attenuates the large signal and amplifies the small signal.

[0030] The original seismic signal includes large signals and small signals. By adopting the method of segmented acquisition, the two signals are processed separately. Specifically, an attenuation circuit for large signals and an amplification circuit for small signals are designed, and they are processed separately at the same time.

[0031] S2, the amplified small signal enters the first ADC sampling circuit, and the attenuated large signal enters the second ADC sampling circuit; wherein the first ADC sampling circuit and the second ADC sampling circuit have the same number of sampling data bits.

[0032] The ADC sampling circuit includes an ADC chip and auxiliary circuit devices. Two ADC sampling circuits are designed, and ADC chips with the same number of sampling data bits are used, such as a 24-bit ADC chip, but not limited thereto, to receive processed large and small signals.

[0033] S3, selecting a first preset number of low-bit data from the first ADC sampling circuit, selecting a second preset number of high-bit data from the second ADC sampling circuit, and splicing and processing the high-bit data and the low-bit data to obtain a predetermined number of bits of collected data; wherein the first preset number of bits and the second preset number of bits are less than the number of bits of the sampling data, and the sum of the first preset number of bits and the second preset number of bits is greater than the number of bits of the sampling data.

[0034] In one implementation, the first preset number of bits is 17, the second preset number of bits is 13, and the predetermined number of bits is 30; when the dual-channel signals work simultaneously, the signals enter the two 24-bit ADC analog-to-digital conversion chips with overlapping middle parts, and two 24-bit data are read simultaneously, and the lower 17 bits of the first ADC sampling circuit output and the higher 13 bits of the second ADC sampling circuit output are respectively selected for splicing processing to obtain 30-bit high-precision data for collection and recording.

[0035] Specifically, a decision splicing module is designed. When the original seismic signal enters the two ADC chips through the data processing circuit, the decision splicing module forms 30-bit seismic acquisition data with a wider dynamic range. Figure 3 As shown, No. 1 corresponds to the first ADC sampling circuit, No. 2 corresponds to the second ADC sampling circuit, and the input signal is processed in three cases:

[0036] 1) For small signals (bits 11-23 of AD No. 2 are 0), select bits 1-17 of AD No. 1 and fill the high bits with 13 zeros to form 30-bit data.

[0037] 2) For large signals (bits 12-23 of AD2 are not all 0), select bits 0-23 of AD2 and fill the low bits with 6 zeros to form 30-bit data.

[0038] 3) If the signal is exactly at the anti-stepping empty position (bit 18 of AD No. 1 is 1, bits 12-23 of AD No. 2 are 0), take bits 1-18 of AD No. 1, and fill the high bits with 12 zeros to form 30 bits of data.

[0039] Multi-bit and high dynamic range seismic data acquisition devices, such as Figure 1 As shown, including:

[0040] The first signal processing circuit is used to obtain a small signal in the original seismic signal and amplify the small signal;

[0041] The second signal processing circuit is used to obtain a large signal in the original seismic signal and perform attenuation processing on the large signal;

[0042] An ADC sampling circuit includes two ADC chips with sampling data bits, and the two ADC chips are used to receive a small signal after amplification and a large signal after attenuation respectively;

[0043] The decision splicing module is used to select low-bit data of a first preset number of bits from the first ADC sampling circuit, select high-bit data of a second preset number of bits from the second ADC sampling circuit, and splice and process the high-bit data and the low-bit data to obtain the collection data of a preset number of bits.

[0044] Specifically, the input signal is a differential signal, and the second signal processing circuit includes a plurality of resistors forming a pie-type attenuator, for example, a pie-type attenuator composed of three resistors, and its attenuation coefficient is 8. The first signal processing circuit includes a plurality of operational amplifiers and resistors, for example, an amplifier circuit composed of two operational amplifiers and three resistors, and its amplification factor is 16 times. Furthermore, two diodes are connected in parallel at the positive and negative ends of the feedback resistor of the conventional circuit. It has been verified experimentally that the data collector will not be limited and the maximum indication error is greatly reduced.

[0045] The splicing and processing process of the decision splicing module is as described above and will not be repeated here.

[0046] It can be understood that in the technical solution provided by the present invention, the amplification and attenuation multiples are not limited to 16 bits and 8 bits, the AD used is not limited to 24 bits, and the selection of splicing bits can also be flexibly selected according to the performance of the instrument, so that the technical solution can be used for a larger dynamic range or high dynamic applications with low cost, and it is convenient for chip manufacturers to integrate this solution into the chip.

[0047] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A method for acquiring multi-data-bit and high dynamic range seismic data, characterized in that: include: At the same time, the large signal and the small signal in the original seismic signal are respectively obtained, and the large signal is attenuated and the small signal is amplified; The amplified small signal enters the first ADC sampling circuit, so that the attenuated large signal enters the second ADC sampling circuit; wherein the first ADC sampling circuit and the second ADC sampling circuit have the same number of sampling data bits; A first preset number of low-bit data is selected from the first ADC sampling circuit, a second preset number of high-bit data is selected from the second ADC sampling circuit, and the high-bit data and the low-bit data are concatenated and processed to obtain a predetermined number of collected data; wherein the first preset number of bits and the second preset number of bits are less than the number of bits of the sampling data, and the sum of the first preset number of bits and the second preset number of bits is greater than the number of bits of the sampling data.

2. The multi-data-bit and high dynamic range seismic data acquisition method according to claim 1, characterized in that: The step of splicing and processing the high-order data and the low-order data includes: For a small signal, a high-order bit of the low-order data is padded with zeros so that the low-order data reaches the predetermined number of bits; For a large signal, a zero padding operation is performed on the low bits of the high-bit data so that the high-bit data reaches the predetermined number of bits; When the signal is at the anti-stepping empty position, the anti-stepping empty position of the low-order data is set to 1, and a zero padding operation is performed after the anti-stepping empty position to make the low-order data reach the predetermined number of bits.

3. The multi-data-bit and high dynamic range seismic data acquisition method according to claim 1 or 2, characterized in that: The first preset number of bits is 17, the second preset number of bits is 13, the number of sampled data bits is 24, and the predetermined number of bits is 30.

4. A multi-data-bit and high dynamic range seismic data acquisition device, characterized in that: The acquisition device is used to implement the multi-data-bit and high-dynamic-range seismic data acquisition method according to any one of claims 1 to 3, and comprises: The first signal processing circuit is used to obtain a small signal in the original seismic signal and amplify the small signal; A second signal processing circuit is used to obtain a large signal in the original seismic signal and perform attenuation processing on the large signal; An ADC sampling circuit includes two ADC chips with sampling data bits, and the two ADC chips are used to receive a small signal after amplification and a large signal after attenuation respectively; The decision splicing module is used to select low-bit data of a first preset number of bits from the first ADC sampling circuit, select high-bit data of a second preset number of bits from the second ADC sampling circuit, and splice and process the high-bit data and the low-bit data to obtain the collection data of a predetermined number of bits.

5. The multi-data-bit and high dynamic range seismic data acquisition device according to claim 4, characterized in that: The first signal processing circuit includes an operational amplifier and a preset number of resistors.

6. The multi-data-bit and high dynamic range seismic data acquisition device according to claim 5, characterized in that: The first signal processing circuit has an amplification factor of 16.

7. The multi-data-bit and high dynamic range seismic data acquisition device according to claim 4, characterized in that: The second signal processing circuit includes a preset number of Pie-type attenuators.

8. The multi-data-bit and high dynamic range seismic data acquisition device according to claim 7, characterized in that: The second signal processing circuit has an attenuation factor of 8.

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