Semiconductor device and forming method thereof

Abstract

The disclosure relates to a structure of an optical modulator and a method of forming the same. The structure includes first, second, third and fourth doped regions forming a C-shaped P-N junction in the optical waveguide. A method of forming such a structure includes forming a first doped region by implanting a dopant of a first type on a side surface of an optical waveguide and applying a first mask. The method further includes forming second, third, and fourth doped regions at different depths under the top surface of the optical waveguide by implanting dopants of the first and second types and applying a second mask. The P-N junction formed by the method is self-aligned, unaffected by on-line process overlap and critical dimensions of the first and second masks, providing an improved profile of the P-N junction as well as a reliable and consistent product.

Description

Technical Field

[0001] The disclosed embodiments relate to a semiconductor device and a method for forming the same. Background Art

[0002] The application of semiconductor photonics has revolutionized high-speed data communication systems, making it possible to transmit data over long distances with low power consumption through optical waveguides. Data in the form of optical signals can be modulated by optical modulators, which are key components of semiconductor photonics and can form PN junctions within optical waveguides. An important specification of an optical modulator is the optical modulation amplitude (OMA) of the optical signal, which is determined by the structure and doping profile of the PN junction. Summary of the invention

[0003] A method for forming a semiconductor device according to an embodiment of the present invention comprises forming a ridge on a substrate; forming an n-type region under a first side surface of the ridge; forming a mask on the substrate, wherein the mask exposes the top surface of the ridge and wherein an opening of the mask is located above the first side surface and the second side surface of the ridge; and doping the ridge with a first n-type dopant, a second n-type dopant, and a p-type dopant based on the mask, wherein: a first implantation energy of the first n-type dopant is less than a second implantation energy of the second n-type dopant; and a third implantation energy of the p-type dopant is less than the second implantation energy.

[0004] A method for forming a semiconductor device according to an embodiment of the present invention includes: forming an optical waveguide on a substrate; and forming an optical modulator in the optical waveguide, including: forming a first n-type region under a side surface of the optical waveguide; forming a mask on the substrate to expose the optical waveguide; performing a first implantation operation based on the mask, wherein the first implantation operation forms a second n-type region in the optical waveguide; performing a second implantation operation based on the mask, wherein the second implantation operation forms a third n-type region in the optical waveguide and on the second n-type region; and performing a third implantation operation based on the mask, wherein the third implantation operation forms a p-type region on the second n-type region and under the third n-type region.

[0005] A semiconductor device according to an embodiment of the present invention: a ridge on a substrate; and a PN junction in the ridge, wherein the PN junction comprises: a first n-type region in the substrate; a p-type region on the first n-type region; a second n-type region on the p-type region; and a third n-type region connecting the first n-type region and the second n-type region, wherein the third n-type region comprises a p-type dopant having substantially the same concentration as the p-type dopant in the p-type region; an n-type contact region in the substrate coupled to the third n-type region; and a p-type contact region in the substrate coupled to the p-type region. . BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures.

[0007] Figure 1A is a cross-sectional view of a light modulator according to some embodiments.

[0008] Figure 1B is a top view of a light modulator according to some embodiments.

[0009] Figure 1C is a cross-sectional view of a light modulator according to some embodiments.

[0010] Figure 2 is a flow chart of a manufacturing method for forming a light modulator according to some embodiments.

[0011] Figures 3 to 14 is a cross-sectional view of an intermediate structure during fabrication of a light modulator according to some embodiments.

[0012] Description of Figure Numbers

[0013] 100: semiconductor devices;

[0014] 102: substrate;

[0015] 103: Groove structure;

[0016] 103t: bottom surface;

[0017] 104: Light signal;

[0018] 105: Optical waveguide;

[0019] 105l, 105r, 110l, 110r: side surfaces;

[0020] 105t, 110t, 112t: top surface;

[0021] 110: optical modulator;

[0022] 112: first doping region / doping region;

[0023] 112a, 112b, 112c: Part III;

[0024] 114: second doping region / doping region;

[0025] 116: third doping region / doping region;

[0026] 118: fourth doping region / doping region;

[0027] 120: PN junction;

[0028] 120b, 120l, 120r, 120u: interface;

[0029] 122: First pick-up area / pick-up area;

[0030] 124: Second pick-up area / pick-up area;

[0031] 124t: compensation area;

[0032] 126, 128: dielectric layer;

[0033] 132: first contact area;

[0034] 134: second contact area;

[0035] 200: Methods;

[0036] 205, 210, 215, 220, 225, 230, 235, 240, 245: operation;

[0037] 355: Hard mask;

[0038] 412, 612: doping region;

[0039] 450, 550, 650, 1350, 1450: photoresist;

[0040] 460, 560, 660, 960, 1060, 1160, 1360, 1460: dopants;

[0041] 850: mask;

[0042] 855: Opening;

[0043] 855l: first boundary;

[0044] 855r: Second boundary;

[0045] 970, 1070, 1170: District;

[0046] D, D4, W1, W2, W4, Wt: width;

[0047] D1, D2, D5, D6: horizontal distance;

[0048] H: height;

[0049] H3: Depth;

[0050] L: length;

[0051] T1, T2, T3, T4, T5, T6: thickness;

[0052] Wb: distance / width;

[0053] θ4, θ5, θ6, θl, θr: angle. DETAILED DESCRIPTION

[0054] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on a second feature may include an embodiment in which the first and second features are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature may not be in direct contact with the second feature.

[0055] In addition, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0056] In some embodiments, the terms "about" and "substantially" may indicate that the value of a given amount varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are examples only and are not intended to be limiting. It should be understood that the terms "about" and "substantially" may refer to percentages of values ​​interpreted by one of ordinary skill in the relevant art based on the teachings herein.

[0057] In a semiconductor photonic device, an optical modulator is a component for modulating an optical signal propagating in an optical waveguide. An optical modulator disposed in a section of an optical waveguide may include a PN junction controlled by an external bias. Under different bias conditions (e.g., forward bias or reverse bias) determined by the external bias, the PN junction may adjust the charge carrier density, thereby adjusting the optical parameters (e.g., refractive index) of the optical modulator, so that the optical signal propagating in the optical waveguide may be modulated. The modulation efficiency of the optical modulator may be affected by the profile of the PN junction (e.g., its shape and / or doping distribution). For example, within the geometry of the optical waveguide, a C-shaped PN junction with a larger junction area may be conducive to higher modulation efficiency compared to a planar PN junction.

[0058] The C-shaped PN junction in the optical waveguide may include first, second and third doping regions with a first type (e.g., n-type) dopant, and a fourth doping region with a second type (e.g., p-type) dopant. Contrary to the first type. The second and third doping regions may be connected by the first doping region, and the fourth doping region may be partially surrounded by the first, second and third doping regions, forming a C-shaped interface between doping regions of opposite types. The manufacturing process for forming the C-shaped PN junction may undergo three photolithography / ion implantation processes and require three masks (e.g., photoresists). The photolithography / ion implantation process includes sidewall n-type implantation, upper n-type / middle p-type implantation, and bottom n-type implantation.

[0059] In some lithography / ion implantation processes, the boundaries of the mask need to be precisely arranged within a small range on the optical waveguide, which poses a challenge to the lithography operation, especially when the design window is limited by the small width of the optical waveguide. In addition, the inline process overlap (inline overlay) and / or critical dimension variation of the mask can significantly affect the profile of the PN junction, thereby compromising the performance of the semiconductor photonic device and affecting the product yield.

[0060] To overcome the above challenges, embodiments described herein relate to a semiconductor device including an optical modulator and a method of forming the semiconductor device. In some embodiments, the optical modulator may include a first doped region under the side surface of the optical waveguide, a second doped region under the top surface of the optical waveguide, a third doped region under the second doped region, and a fourth doped region between the second and third doped regions. In some embodiments, the first, second, and third doped regions may include a first type (e.g., n-type) dopant, and the fourth doped region may include a second type (e.g., p-type) dopant opposite to the first type. In some embodiments, the first, second, third, and fourth doped regions may form a PN junction having a "C" shape in the optical modulator. In some embodiments, the method of forming a semiconductor device may apply two masks to define the doped regions of the optical modulator. In some embodiments, the first doped region may be formed by implanting a first type of dopant under the side surface of the optical waveguide and applying a first mask. In some embodiments, the second, third, and fourth doped regions may be formed by implanting a first type of dopant under the top surface of the optical waveguide and applying a second mask having a boundary outside the width of the optical waveguide. In some embodiments, the method may provide a robust design window and may improve product yield. In some embodiments, multiple doped regions in an optical modulator formed by the method can be self-aligned and unaffected by variations in the first and second masks, resulting in improved reliability and consistency of the optical modulator. In some embodiments, a PN junction formed by the method can have a greater overlap with an optical mode in an optical waveguide, providing enhanced modulation efficiency than those formed by other manufacturing processes.

[0061] According to some embodiments, reference Figure 1A-Figure 1C A semiconductor device 100 is depicted having a PN junction 120 formed over a substrate 102 . Figure 1A A cross-sectional view of a semiconductor device 100 is shown in accordance with some embodiments. Figure 1B A top view of a semiconductor device 100 is shown in accordance with some embodiments. Figure 1C An enlarged cross-sectional view of a semiconductor device 100 is shown in accordance with some embodiments.

[0062] refer to Figure 1A, the substrate 102 may be a semiconductor material, such as silicon (Si). In some embodiments, the substrate 102 may include a crystalline silicon substrate (e.g., a Si wafer). In some embodiments, the substrate 102 may include (i) an elemental semiconductor, such as silicon or germanium (Ge); (ii) a compound semiconductor, including silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); (iii) an alloy semiconductor, including silicon germanium carbide (SiGeC), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), indium gallium phosphide (InGaP), indium gallium arsenide (InGaAs), indium gallium arsenide phosphide (InGaAsP), indium aluminum arsenide (InAlAs), and / or aluminum gallium arsenide (AlGaAs); or (iv) a combination thereof. In addition, the substrate 102 may be doped (e.g., a p-type substrate or an n-type substrate) according to design requirements. In some embodiments, the substrate 102 may be undoped. In some embodiments, the substrate 102 may be doped with a p-type dopant (e.g., boron (B), indium (In), aluminum (Al), or gallium (Ga)) or an n-type dopant (e.g., phosphorus (P), arsenic (As), or antimony (Sb)). In some embodiments, the crystal orientation of the substrate 102 may be (100), (110), or (111).

[0063] refer to Figure 1B , the semiconductor device 100 may include an optical waveguide 105 disposed on a substrate 102. For example, Figure 1B As shown, the optical waveguide 105 may include a ridge structure extending along a horizontal direction (e.g., along a direction y) and protruding out of the substrate 102 along a vertical direction (e.g., along a direction z). In some embodiments, the ridge structure may be set between the plurality of groove structures 103. The optical waveguide 105 may have a top surface 105t and a first side surface 105l and a second side surface 105r. In some embodiments, the optical waveguide 105 may include the same material as the substrate 102. In some embodiments, the optical waveguide 105 may include Si. In some embodiments, the optical waveguide 105 may have the same doping profile as the substrate 102. In some embodiments, the optical waveguide 105 may be undoped or lightly doped.

[0064] refer to Figure 1A-Figure 1C In some embodiments, the semiconductor device 100 may include an optical modulator 110 formed in a section of the optical waveguide 105 by selectively doping different portions of the section of the optical waveguide 105 with different dopants to form a PN junction 120. In some embodiments, the optical modulator 110 may have the same cross-sectional shape as the optical waveguide 105, such as Figure 1BAs shown. Specifically, the optical modulator 110 may have a top surface 110t that is substantially coplanar with the top surface 105t of the optical waveguide 105. The optical modulator 110 may also have a first side surface 110l and a second side surface 110r that are substantially coplanar with the first side surface 105l and the second side surface 105r of the optical waveguide 105, respectively. In some embodiments, the side surfaces 110l, 110r, 105l, and 105r may be connected to the bottom surface 103t in the groove structure 103. The ridge structure of the optical waveguide 105 and the optical modulator 110 may have a trapezoidal cross-section. For example, as Figure 1A and Figure 1C As shown, the angle θl between the side surface 110l and the bottom surface 103t can be between about 60° and about 120°, and the angle θr between the side surface 110r and the bottom surface 103t can be between about 60° and about 120°. In some embodiments, the cross-section of the ridge structure can be rectangular. For example, both the angle θl and the angle θr can be about 90°. In some embodiments, the cross-section of the ridge structure can also be other shapes, such as a triangle, a parallelogram, a polygon, or an irregular shape. In some embodiments, different sections of the ridge structure can have cross-sections of different sizes / shapes. In some embodiments, as Figure 1B As shown, the length L of the optical modulator 110 may be between about 200 nm and about 1000 nm. Figure 1B and Figure 1C As shown, the width Wt of the top surface 105t and the top surface 110t can be between about 200 nm and about 500 nm. In some embodiments, the distance Wb between the bottom edges of the side surface 110l and the side surface 110r can be between about 200 nm and about 600 nm. In some embodiments, the optical waveguide 105 and the optical modulator 110 can also include a portion of the substrate 102 directly under the ridge structure. In some embodiments, as Figure 1C As shown, the height H of the optical modulator 110 may be between about 160 nm and about 300 nm. Figure 1A As shown, the optical signal 104 may propagate in the optical waveguide 105 and may be modulated by the optical modulator 110 when the PN junction 120 is under different bias conditions.

[0065] In some embodiments, the optical modulator 110 may include a first doping region 112, a second doping region 114, a third doping region 116, and a fourth doping region 118. Figure 1A and Figure 1BIn some embodiments, the first doped region 112 may be directly below the side surface 1101. In some embodiments, the first doped region 112 may include a portion below the ridge structure and in the substrate. In some embodiments, the top surface 110t may include the top surface 112t of the first doped region 112, such as Figure 1C As shown. In some embodiments, the width W4 of the top surface 112t can be between about 50 nm and about 100 nm. In some embodiments, the bottom surface 103t can include an upper surface of a portion of the first doping region 112 below the ridge structure and in the substrate. In some embodiments, the first doping region 112 can be doped with a first type of dopant. For example, the first doping region 112 can be doped with an n-type dopant, such as P, As, Sb, and / or a combination thereof. In some embodiments, the doping concentration of the first doping region 112 can be about 1×10 18 cm -3 and about 2×10 20 cm -3 between.

[0066] In some embodiments, the second doped region 114 may be disposed directly below the top surface 110t and adjacent to the first doped region 112, such as Figure 1A and Figure 1C As shown. In some embodiments, the side surface 110r may include a side surface of the second doping region 114. In some embodiments, the second doping region 114 may be in contact with the first doping region 112. In some embodiments, the interface between the first doping region 112 and the second doping region 114 may be substantially parallel to the side surface 110l. In some embodiments, the thickness T1 of the second doping region 114 may be between about 50nm and about 100nm. In some embodiments, the second doping region 114 may be doped with a first type of dopant. For example, the second doping region 114 may be doped with an n-type dopant, such as P, As, Sb, and / or a combination thereof. In some embodiments, the doping concentration of the second doping region 114 may be about 2×10 18 cm -3 and about 1×10 20 cm -3 between.

[0067] In some embodiments, the fourth doping region 118 may be disposed directly below the second doping region 114 and adjacent to the first doping region 112. Figure 1A and Figure 1CAs shown. In some embodiments, the fourth doping region 118 may be in contact with the second doping region 114. In some embodiments, an interface 120u between the second doping region 114 and the fourth doping region 118 may be substantially parallel to the top surface 110t. In some embodiments, the fourth doping region 118 may be in contact with the first doping region 112. In some embodiments, an interface 120l between the first doping region 112 and the fourth doping region 118 may be substantially parallel to the side surface 110l. In some embodiments, the interface 120l may be curved. In some embodiments, the side surface 110r may include a side surface of the fourth doping region 118. In some embodiments, the thickness T2 of the fourth doping region 118 may be between about 50nm and about 100nm. In some embodiments, the fourth doping region 118 may be doped with a second type of dopant opposite to the first type. For example, the fourth doping region 118 may be doped with a p-type dopant, such as B, Al, Ga, In, and / or a combination thereof. In some embodiments, the doping concentration of the fourth doping region 118 may be about 2×10 18 cm -3 and about 1×10 20 cm -3 between.

[0068] In some embodiments, the third doping region 116 may be disposed directly below the fourth doping region 118 and adjacent to the first doping region 112. Figure 1A and Figure 1C As shown. In some embodiments, the third doping region 116 may be in contact with the fourth doping region 118. In some embodiments, the interface 120b between the third doping region 116 and the fourth doping region 118 may be substantially parallel to the interface 120u. In some embodiments, the interface 120b may be substantially coplanar with the bottom surface 103t. In some embodiments, the interface 120b may be higher or lower than the bottom surface 103t. In some embodiments, the third doping region 116 may be in contact with the first doping region 112. In some embodiments, the interface between the first doping region 112 and the third doping region 116 may be substantially coplanar with the interface 120l. In some embodiments, the thickness T3 of the third doping region 116 may be between about 50nm and about 100nm. In some embodiments, the third doping region 116 may be doped with a first type dopant. For example, the third doping region 116 may be doped with an n-type dopant, such as P, As, Sb and / or a combination thereof. In some embodiments, the doping concentration of the third doping region 116 may be about 2×10 18 cm -3 and about 1×10 20 cm -3 between.

[0069] In some embodiments, the first doping region 112, the second doping region 114, and the third doping region 116 having the same type of dopant may form a "C" shape. In some embodiments, despite being of the same type, the dopants in the first doping region 112, the second doping region 114, and the third doping region 116 may be the same or different. For example, the dopant in the first doping region 112 may include P and As, while the dopant in the second doping region 114 and the third doping region 116 may include only P. In some embodiments, since the second type of dopant in the fourth doping region 118 is opposite to the first type of dopant in the first doping region 112, the second doping region 114, and the third doping region 116, a PN junction 120 may be formed at the interface 120l, the interface 120u, and the interface 120b, as shown in FIG. Figure 1A and Figure 1C In some embodiments, the width W1 of the interface 120u and the width W2 of the interface 120b may be between about 150 nm and about 500 nm.

[0070] In some embodiments, the first doping region 112 may further include a first portion 112a, a second portion 112b, and a third portion 112c. Figure 1C As shown. The first portion 112a, the second portion 112b, and the third portion 112c may have different doping profiles. In some embodiments, the dopant in the first portion 112a and the third portion 112c may be of the first type. For example, the first portion 112a and the third portion 112c may be n-type doped. In some embodiments, the second portion 112b may include first and second types of dopants. For example, the second portion 112b may be doped with both n-type and p-type dopants, wherein the concentration of the n-type dopant is greater than the concentration of the p-type dopant, so that the second portion 112b as a whole may have an n-type concentration. In some embodiments, the concentration of the second type of dopant in the second portion 112b may be substantially the same as the concentration of the dopant in the fourth doping region 118. In some embodiments, the difference between the concentration of the first type dopant in the first portion 112a and the concentration of the first type dopant in the second portion 112b may be substantially equal to the concentration of the first type dopant in the second doping region 114. In some embodiments, a difference between the concentration of the first type dopant in the third portion 112 c and the concentration of the first type dopant in the second portion 112 b may be substantially equal to the concentration of the first type dopant in the third doping region 116 .

[0071] refer to Figure 1C, in some embodiments, the first portion 112a may have the same thickness T1 as the second doped region 114. In some embodiments, the interface between the first portion 112a and the second portion 112b may be connected to the interface 120u and substantially coplanar with the interface 120u. In some embodiments, the second portion 112b may have the same thickness T2 as the fourth doped region 118. In some embodiments, the interface between the third portion 112c and the second portion 112b may be connected to the interface 120b and substantially coplanar with the interface 120b. In some embodiments, the interface between the third portion 112c and the second portion 112b may be connected to the bottom surface 103t and substantially coplanar with the bottom surface 103t. In some embodiments, the third portion 112c may have the same thickness T3 as the third doped region 116.

[0072] refer to Figure 1A In some embodiments, the semiconductor device 100 may include a first contact region 132 electrically connected to the first doped region 112 through the first pick-up region 122. In some embodiments, the first pick-up region 122 and the first contact region 132 may be part of the substrate 102 and may include a first type of dopant, which is the same type of dopant in the first doped region 112. For example, the first pick-up region 122 and the first contact region 132 may include an n-type dopant, such as P, As, Sb, or a combination thereof. In some embodiments, the doping concentration of the first pick-up region 122 may be about 5×10 18 cm -3 and about 1×10 21 cm -3 In some embodiments, the doping concentration of the first pickup region 122 may be greater than the doping concentration of the first doping region 112. In some embodiments, the doping concentration of the first contact region 132 may be between about 5×10 18 cm -3 and about 1×10 21 cm -3 In some embodiments, Figure 1C As shown, the thickness T5 of the first pickup region 122 may be between about 30 nm and about 200 nm. In some embodiments, the thickness of the first contact region 132 may be between about 30 nm and about 200 nm. In some embodiments, the top surface of the first contact region 132 may be substantially coplanar with the top surface 110t.

[0073] In some embodiments, the semiconductor device 100 may include a second contact region 134 electrically connected to the fourth doped region 118 through the second pick-up region 124. In some embodiments, the second pick-up region 124 and the second contact region 134 may be part of the substrate 102 and may include a second type of dopant, which is the same type of dopant in the fourth doped region 118. For example, the second pick-up region 124 and the second contact region 134 may include a p-type dopant, such as B, Al, As, In, or a combination thereof. In some embodiments, the doping concentration of the second pick-up region 124 may be about 5×10 18 cm -3 and about 1×10 21 cm -3 In some embodiments, the doping concentration of the second pickup region 124 may be greater than the doping concentration of the fourth doping region 118. In some embodiments, the doping concentration of the second contact region 134 may be between about 5×10 18 cm -3 and about 1×10 21 cm -3 In some embodiments, Figure 1C As shown, the thickness T6 of the second pickup region 124 can be between about 30 nm and about 200 nm. In some embodiments, the thickness of the second contact region 134 can be between about 30 nm and about 200 nm. In some embodiments, the top surface of the second contact region 134 can be substantially coplanar with the top surface 110t.

[0074] In some embodiments, Figure 1A and Figure 1C As shown, the second pickup region 124 may include a compensated region 124t in contact with the third doping region 116 and the fourth doping region 118. In some embodiments, the compensation region 124t may include a first type of dopant, which is the same as those in the third doping region 116, in addition to the second type of dopant. In some embodiments, the compensation region 124t may have a doping profile in which a first concentration of the first type of dopant gradually increases toward the third doping region 116 and a second concentration of the second type of dopant gradually decreases toward the third doping region 116. In some embodiments, an interface 120r between the compensation region 124t and the third doping region 116 may be a PN junction, which may be a part of the PN junction 120. In some embodiments, the interface 120r may be curved.

[0075] refer to Figure 1A and Figure 1BIn some embodiments, the semiconductor device 100 may further include a dielectric layer 126 and a dielectric layer 128 set in the plurality of trench structures 103. In some embodiments, the dielectric layer 126 and the dielectric layer 128 may be respectively disposed on the first pickup region 122 and the second pickup region 124. In some embodiments, the top surfaces of the dielectric layer 126 and the dielectric layer 128 may be substantially coplanar with the top surface 110t.

[0076] According to some embodiments, Figure 2 shows the method for forming Figure 1A-Figure 1C 1. The present disclosure is not limited to the operations described and additional operations may be performed. Other manufacturing operations may be performed between the operations of method 200 and are omitted for clarity only. Furthermore, not all operations are required to perform the disclosure provided herein. Furthermore, certain operations may be performed simultaneously or in accordance with the description of the method 200. Figure 2 In some embodiments, one or more other operations may be performed in addition to or in place of the operations currently described. For purposes of illustration, reference is made to Figure 3-Figure 14 The structure shown is used to describe the method 200. Unless otherwise specified, Figure 1A-Figure 1C Discussions of components with the same annotation apply to Figure 3-Figure 14 .

[0077] refer to Figure 2 , method 200 begins with operation 205 and a process of forming an optical waveguide on a substrate (eg, substrate 102), as described with reference to Figure 3 As described. Figure 3 2 is a cross-sectional view of the semiconductor device 100 after operation 205 and forming the optical waveguide 105 having the top surface 105t and the first side surface 105l and the second side surface 105r. In some embodiments, forming the optical waveguide 105 may include patterning the substrate 102 with the hard mask 355 and removing the portion of the substrate 102 not covered by the hard mask 355 to form a plurality of trench structures 103 having a depth H3. In some embodiments, the hard mask 355 may be a shallow trench isolation (STI) layer. In some embodiments, the hard mask 355 may be patterned to include a stripe shape extending in a horizontal direction (e.g., direction x) and having a width Wt that determines the width of the top surface 105t of the optical waveguide 105. In some embodiments, the trench structure 103 may be formed by wet etching, dry etching, or a combination thereof. In some embodiments, the plurality of trench structures 103 may be formed by anisotropically etching the substrate 102 such that the side surface 105 l and the side surface 105 r may be inclined or substantially perpendicular to the substrate 102 .

[0078] refer to Figure 2 The method 200 continues with operation 210 and a process of doping a region below the side surface of the optical waveguide with a first type (eg, n-type) dopant, as described with reference to Figure 4 as described. Figure 4 is a cross-sectional view of the semiconductor device 100 in operation 210 during formation of the doped region 412. In some embodiments, forming the doped region 412 may include (i) covering the side surface 105r of the optical waveguide 105 with a photoresist 450 while exposing the side surface 105l of the optical waveguide 105, and (ii) doping a region of the optical waveguide 105 under the side surface 105l by implanting a dopant 460 in an ion implantation process. In some embodiments, covering the side surface 105r of the optical waveguide 105 may include covering the trench structure 103 on the same side of the optical waveguide 105 as the side surface 105r. In some embodiments, covering the side surface 105r of the optical waveguide 105 may include covering a first portion of a top surface of the hard mask 355 closer to the side surface 105r while exposing a second portion of the top surface of the hard mask 355 closer to the side surface 105l. In some embodiments, the width D4 of the exposed second portion of the top surface of the hard mask 355 may be between about 0 and about the width Wt, so that the boundary of the photoresist 450 may be formed within a margin as large as the width Wt. The hard mask 355 may act as a self-aligned mask so that the doped region 412 may be securely formed despite the different alignment of the photoresist 450 within this margin. In some embodiments, exposing the side surface 105l of the optical waveguide 105 may include exposing the trench structure 103 on the same side of the optical waveguide 105 as the side surface 105l. In some embodiments, implanting the dopant 460 may include forming the doped region 412 having a thickness T4 (between about 40 nm and about 100 nm) into the side surface 105l of the optical waveguide 105 by selecting appropriate ion implantation parameters. In some embodiments, implanting the dopant 460 may include implanting P and / or As to form the doped region 412. In some embodiments, implanting the dopant 460 may include implanting P at an energy between about 40 keV and about 80 keV. In some embodiments, implanted dopants 460 may include an amount of about 1×10 14 cm -2 With about 6×10 14 cm -2 In some embodiments, implanting dopant 460 may include implanting As at an energy between about 20 keV and about 60 keV. In some embodiments, implanting dopant 460 may include implanting As at an energy between about 5×10 13 cm -2 With about 5×10 14 cm -2In some embodiments, implanting dopant 460 may include implanting P and / or As at an angle θ4 between about 0° and about 45° relative to the vertical direction (eg, along direction z). In some embodiments, operation 210 may also include removing photoresist 450 after forming doped region 412.

[0079] The method 200 continues with operation 215 and a process for forming a pickup region by doping the substrate with a second type (eg, p-type) dopant opposite to the first type, as described with reference to FIG. Figure 5 as described. Figure 5 5 is a cross-sectional view of the semiconductor device 100 in operation 215 during the formation of the second pickup region 124. In some embodiments, forming the second pickup region 124 may include (i) covering the optical waveguide 105 with a photoresist 550 while exposing a portion of the trench structure 103 on the same side of the optical waveguide 105 as the side surface 105r, and (ii) doping the region of the exposed portion of the trench structure 103 by implanting a dopant 560 in an ion implantation process. In some embodiments, covering the optical waveguide 105 may include covering the side surface 105l together with a region on the same side of the optical waveguide 105 as the side surface 105l. In some embodiments, covering the optical waveguide 105 may include covering the side surface 105r and a portion of the trench structure 103 adjacent to the side surface 105r. In some embodiments, a horizontal distance D5 between a boundary of the photoresist 550 and the optical waveguide 105 may be between about 100 nm and about 800 nm. In some embodiments, implanting dopants 560 may include forming a second pickup region 124 having a thickness T6 into the bottom surface 103t of the trench structure 103 by selecting appropriate ion implantation parameters. In some embodiments, implanting dopants 560 may include implanting B at an energy between about 10 keV and about 30 keV. In some embodiments, implanting dopants 560 may include implanting B at an energy between about 10 keV and about 30 keV. 14 cm -2 With about 3×10 15 cm -2 In some embodiments, implanting dopant 560 may include implanting B at an angle θ5 between about 0° and about 30° relative to the vertical direction (eg, along direction z). In some embodiments, operation 215 may also include removing photoresist 550 after forming second pickup region 124 .

[0080] The method 200 continues with operation 220 and a process of forming another pickup region on an opposite side of the optical waveguide relative to the pickup region by doping the substrate with a first type (eg, n-type) dopant, as described below with reference to Figure 6 Give a description. Figure 66 is a cross-sectional view of the semiconductor device 100 after operation 220 and forming the first pickup region 122. In some embodiments, forming the first pickup region 122 may include (i) covering the optical waveguide 105 with a photoresist 650 while exposing a portion of the trench structure 103 on the same side of the optical waveguide 105 as the side surface 105l, and (ii) doping the region of the exposed portion of the trench structure 103 by implanting a dopant 660 in an ion implantation process. In some embodiments, covering the optical waveguide 105 may include covering the side surface 105r together with a region on the same side of the optical waveguide 105 as the side surface 105r. In some embodiments, covering the optical waveguide 105 may include covering the side surface 105l and a portion of the trench structure 103 adjacent to the side surface 105l. In some embodiments, a horizontal distance D6 between a boundary of the photoresist 650 and the optical waveguide 105 may be between about 100 nm and about 800 nm. In some embodiments, implanting dopants 660 may include forming a first pickup region 122 having a thickness T5 into the bottom surface 103t of the trench structure 103 by selecting appropriate ion implantation parameters. In some embodiments, implanting dopants 660 may include implanting P at an energy between about 10 keV and about 30 keV. In some embodiments, implanting dopants 660 may include implanting P at an energy between about 10 keV and about 30 keV. 14 cm -2 With about 3×10 15 cm -2 . In some embodiments, implanting dopant 660 may include implanting P at an angle θ6 between about 0° and about 30° relative to a vertical direction (e.g., along direction z). In some embodiments, first pickup region 122 may overlap a portion of doped region 412 and the remaining portion of doped region 412 becomes doped region 612. Due to being doped twice (through implanting dopant 460 and dopant 660), first pickup region 122 may have a greater doping concentration than doped region 612. In some embodiments, operation 220 may also include removing photoresist 650 and hard mask 355 after forming first pickup region 122.

[0081] refer to Figure 2 The method 200 continues with operation 225 and a process of forming a plurality of dielectric layers adjacent to the optical waveguide and over the plurality of pickup regions, as described with reference to Figure 7 As described. Figure 72 is a cross-sectional view of the semiconductor device 100 after operation 225 and the formation of the dielectric layer 126 and the dielectric layer 128. The process of forming the dielectric layer 126 and the dielectric layer 128 may include (i) blanket depositing a dielectric material layer over the optical waveguide 105 and the plurality of trench structures 103, and (ii) planarizing the dielectric material layer to expose the top surface 105t of the optical waveguide 105. In some embodiments, the dielectric material layer may be deposited by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or a combination thereof. In some embodiments, planarizing the dielectric material layer may include performing a chemical mechanical polishing (CMP) process to thin the dielectric material layer until the top surfaces of the dielectric layer 126 and the dielectric layer 128 are substantially coplanar with the top surface 105t.

[0082] refer to Figure 2 The method 200 continues with operation 230 and the process of forming a mask on the substrate and exposing the optical waveguide, as described in reference Figure 8 described. Figure 8 8 is a cross-sectional view of the semiconductor device 100 after operation 230 and the formation of the mask 850. In some embodiments, the mask 850 may be a photoresist mask and may be used as a self-aligned mask for a subsequent ion implantation operation. In some embodiments, the mask 850 may expose the top surface 105t of the optical waveguide 105 through an opening 855 having a width D greater than the width Wb of the optical waveguide 105. In some embodiments, the opening 855 may expose the top surface 105t over the entire width Wt of the top surface 105t. In some embodiments, a first boundary 855l of the opening 855 may be on the dielectric layer 126, and a horizontal distance D1 between the first boundary 855l and the optical waveguide 105 may be between about 0 nm and about 1000 nm. In some embodiments, a second boundary 855r of the opening 855 may be on the dielectric layer 128, and a horizontal distance D2 between the second boundary 855r and the optical waveguide 105 may be between about 0 nm and about 1000 nm. In some embodiments, the width D of the opening 855 can provide a margin between about 0 nm and about 2000 nm for the alignment of the mask 850 relative to the optical waveguide 105, so that subsequent ion implantation operations can be performed robustly despite variations in the alignment of the mask 850 within this margin. Figure 4 ) is applied in method 200 to define Figure 1A-Figure 1C The only two masks for the doping profile of the light modulator 110 are shown.

[0083] refer to Figure 2 The method 200 continues with operation 235 and the process of forming a PN junction by doping the optical waveguide with the first and second types of dopants using a mask, as shown in reference Figure 9-11 As described. Figure 9-11 is a cross-sectional view of the semiconductor device 100 during operation 235. In some embodiments, operation 235 may include (i) forming a region 970 in the optical waveguide 105 and the substrate 102 by implanting a first type (eg, n-type) dopant 960 in a first ion implantation process, as shown in FIG. Fig. 9 As described, (ii) by implanting a second type (eg, p-type) dopant 1060 in a second ion implantation process to form region 1070 in optical waveguide 105 and dielectric layers 126 and 128, as described with reference to Fig.10 As described above, and (iii) by implanting a first type (eg, n-type) dopant 1160 in a third ion implantation process to form region 1170 in optical waveguide 105 and dielectric layers 126 and 128, as described in reference Fig.11 As described above, regions 970, 1070, and 1170 have different depths relative to top surface 105t. Region 970 is the deepest, region 1170 is the shallowest, and region 1070 is between regions 970 and 1170. In some embodiments, based on the same mask 850, regions 970, 1070, and 1170 may have substantially the same width as width D.

[0084] In some embodiments, by selecting appropriate ion implantation parameters, region 970 can be formed at a bottom portion of optical waveguide 105 at a depth similar to first pickup region 122 and second pickup region 124. In some embodiments, forming region 970 can include implanting P at an energy between about 100 keV and about 200 keV. In some embodiments, forming region 970 can include implanting P at an energy between about 5×10 13 cm -2 With about 5×10 14 cm -2 In some embodiments, forming region 970 may include implanting P at a dose between 0° and 10°. In some embodiments, forming region 970 may include implanting P at an angle of about 0°. In some embodiments, region 970 may overlap with a lowermost portion of doped region 612. In some embodiments, region 970 may overlap with a portion of first pickup region 122 adjacent to doped region 612. In some embodiments, region 970 may overlap with a portion of second pickup region 124. In some embodiments, region 970 may be separated from second pickup region 124.

[0085] In some embodiments, formation region 1070 may include region 1070 at a depth around the middle portion of optical waveguide 105 doped by selecting appropriate ion implantation parameters. In some embodiments, formation region 1070 may include implanting B at an energy between about 20 keV and about 60 keV. In some embodiments, formation region 1070 may include implanting B at an energy between about 5×10 13 cm -2 With about 5×10 14 cm -2 In some embodiments, forming region 1070 may include implanting B at a dose between 0° and 10°. In some embodiments, forming region 1070 may include implanting B at an angle of about 0°. In some embodiments, region 1070 may overlap a middle portion of doped region 612. In some embodiments, due to exposure by mask 850, region 1070 may overlap a lower portion of dielectric layer 126 adjacent to side surface 105l. In some embodiments, due to exposure by mask 850, region 1070 may overlap a lower portion of dielectric layer 128 adjacent to side surface 105r. In some embodiments, a lower portion of dielectric layer 126 and / or a lower portion of dielectric layer 128 may include an implanted dopant of the second type. In some embodiments, the concentration of the second type dopant in the lower portion of dielectric layer 126 and the lower portion of dielectric layer 128 may be substantially the same.

[0086] In some embodiments, formation region 1170 may include region 1170 at a depth around the upper portion of optical waveguide 105 doped by selecting appropriate ion implantation parameters. In some embodiments, formation region 1170 may include implanting P at an energy between about 20 keV and about 50 keV. In some embodiments, formation region 1170 may include implanting P at an energy between about 5×10 13 cm -2 With about 5×10 14 cm -2 In some embodiments, forming region 1170 may include implanting P at a dose between 0° and 10°. In some embodiments, forming region 1170 may include implanting P at an angle of about 0°. In some embodiments, region 1170 may overlap a top portion of doped region 612. In some embodiments, due to exposure by mask 850, region 1170 may overlap an upper portion of dielectric layer 126 adjacent to side surface 105l. In some embodiments, due to exposure by mask 850, region 1170 may overlap an upper portion of dielectric layer 128 adjacent to side surface 105r. In some embodiments, an upper portion of dielectric layer 126 and / or an upper portion of dielectric layer 128 may include an implanted dopant of the first type. In some embodiments, the concentration of the first type dopant in the upper portion of dielectric layer 126 and the upper portion of dielectric layer 128 may be substantially the same.

[0087] In some embodiments, regions 970, 1070, and 1170 may be formed in a different order than described above. For example, the order may be (i) forming region 970, (ii) forming region 1170, and (iii) forming region 1070. In another example, the order may be (i) forming region 1170, (ii) forming region 1070, and (iii) forming region 970. Since regions 970, 1070, and 1170 are formed based on the same mask 850, regions 970, 1070, and 1170 may not be susceptible to in-line process variations and may provide a robust junction profile in subsequent thermal processing. In some embodiments, the boundary between regions 970 and 1070 and the boundary between regions 1070 and 1170 may be substantially parallel to each other.

[0088] refer to Figure 2 The method 200 continues with operation 240 and performing a thermal treatment to activate the dopant, as described in reference to Fig.12 as described. Fig.12 is a cross-sectional view of the semiconductor device 100 after operation 240. In some embodiments, performing the thermal treatment may include annealing the semiconductor device 100 at a temperature between about 900° C. and about 1100° C. for a period of time between about 10 seconds and about 100 minutes. In some embodiments, the thermal treatment may cause the dopants in the regions 970, 1070, and 1170 to reside in the crystal structure of the optical waveguide 105 and form the first doping region 112, the second doping region 114, the third doping region 116, and the fourth doping region 118. In some embodiments, the thermal treatment may form a “C” shape of the PN junction 120. In some embodiments, the formation of the doping regions 112, 114, 116, and 118 and the PN junction 120 may define the optical modulator 110 in the optical waveguide 105. In some embodiments, the thermal treatment may promote the diffusion of the dopants in the doping regions 112, 114, 116, and 118, so that the doping distribution in each doping region is more uniform. In some embodiments, the thermal treatment may remove defects formed in the optical waveguide 105 due to the ion implantation process.

[0089] In some embodiments, the thermal treatment may also promote diffusion of dopants in the pickup region 122 and the pickup region 124. Specifically, during the thermal treatment, the second pickup region 124 may extend toward the optical modulator 110 due to diffusion of the second type of dopant in the second pickup region 124 toward the optical modulator 110. In some embodiments, mutual diffusion between the second type of dopant in the second pickup region 124 and the first type of dopant in the doping region 116 may form a compensation region 124t. In some embodiments, during the thermal treatment, the compensation region 124t may be connected to the third doping region 116 and the fourth doping region 118. Since the dopant types in the compensation region 124t and the third doping region 116 are opposite, an interface 120r between the compensation region 124t and the third doping region 116 may form a PN junction as part of the -PN junction 120. Since the dopants in the compensation region 124t and the fourth doping region 118 are of the same type, the compensation region 124t and the fourth doping region 118 may be electrically connected without a PN junction in between.

[0090] refer to Figure 2 , method 200 continues with operation 245 and the process of forming first and second contact regions coupled to the plurality of pickup regions, as described with reference to Fig.13 and 14 As described. Fig.13 and 14 1 and 1. The cross-sectional views of the semiconductor device 100 are respectively shown when the first contact region 132 and the second contact region 134 are formed. In some embodiments, the first contact region 132 may be formed before the second contact region 134, or vice versa.

[0091] refer to Fig.13 In some embodiments, forming the first contact region 132 may include (i) covering the light modulator 110 with a photoresist 1350 while exposing a portion of the substrate 102 on the same side of the light modulator 110 as the first pickup region 122, and (ii) doping the exposed region of the substrate 102 by implanting a dopant 1360 in an ion implantation process. In some embodiments, the photoresist 1350 may also cover the dielectric layer 128 and a portion of the substrate 102 on the same side of the light modulator 110 as the dielectric layer 128. In some embodiments, the photoresist 1350 may also cover a portion of the dielectric layer 126 adjacent to the light modulator 110. In some embodiments, forming the first contact region 132 may include electrically connecting the first contact region 132 to the first pickup region 122 by selecting appropriate ion implantation parameters. In some embodiments, implanting the dopant 1360 may include implanting the first type dopant at an energy between about 5 keV and about 30 keV. In some embodiments, implanting the dopant 1360 may include implanting the first type dopant at an energy between about 1×10 14 cm -2 With about 3×1015 cm -2 In some embodiments, implanting the dopant 1360 may include implanting the first type of dopant at an angle between about 0° and about 30°. In some embodiments, forming the first contact region 132 may further include removing the photoresist 1350 after forming the first contact region 132.

[0092] refer to Fig.14 In some embodiments, forming the second contact region 134 may include (i) covering the light modulator 110 with a photoresist 1450 while exposing a portion of the substrate 102 on the same side of the light modulator 110 as the second pickup region 124, and (ii) doping the exposed region of the substrate 102 by implanting a dopant 1460 in an ion implantation process. In some embodiments, the photoresist 1450 may also cover the dielectric layer 126 and a portion of the substrate 102 on the same side of the light modulator 110 as the dielectric layer 126. In some embodiments, the photoresist 1450 may also cover a portion of the dielectric layer 128 adjacent to the light modulator 110. In some embodiments, forming the second contact region 134 may include electrically connecting the second contact region 134 to the second pickup region 124 by selecting appropriate ion implantation parameters. In some embodiments, implanting the dopant 1460 may include implanting the second type dopant at an energy between about 5 keV and about 30 keV. In some embodiments, implanting the dopant 1460 may include implanting the second type dopant at an energy between about 1×10 14 cm -2 With about 3×10 15 cm -2 In some embodiments, implanting dopant 1460 may include implanting the second type of dopant at an angle between about 0° and about 30°. In some embodiments, forming second contact region 134 may further include removing photoresist 1450 after forming second contact region 134.

[0093] Embodiments described herein relate to semiconductor devices including optical modulators and methods of forming semiconductor devices. In some embodiments, the optical modulator includes a first doped region under the side surface of the optical waveguide, a second doped region under the top surface of the optical waveguide, a third doped region under the second doped region, and a fourth doped region between the second doped region and the third doped region. In some embodiments, the first, second, and third doped regions include a first type of dopant, and the fourth doped region includes a second type of dopant opposite to the first type. In some embodiments, the first, second, third, and fourth doped regions form a PN junction having a "C" shape in the optical modulator. In some embodiments, the method of forming a semiconductor device includes forming a first doped region by implanting a first type of dopant under the side surface of the optical waveguide and applying a first mask. In some embodiments, the method also includes implanting a first and second type of dopant under the top surface of the optical waveguide and applying a second mask to form a second, third, and fourth doped region. In some embodiments, the PN junction formed by the method is self-aligned and is not affected by variations in the first and second masks, thereby providing reliable and consistent product yields.

[0094] In some embodiments, a method includes forming a ridge on a substrate, forming an n-type region below a first side surface of the ridge, and forming a mask on the substrate. The mask exposes a top surface of the ridge. An opening of the mask is located above the first side surface and the second side surface of the ridge. The method also includes doping the ridge with a first n-type dopant, a second n-type dopant, and a p-type dopant based on the mask. A first implantation energy of the first n-type dopant is less than a second implantation energy of the second n-type dopant. A third implantation energy of the p-type dopant is less than the second implantation energy. In some embodiments, the method further includes forming a dielectric layer on the substrate having a top surface coplanar with the top surface of the ridge. In some embodiments, forming the mask includes exposing a portion of the dielectric layer adjacent to the ridge. In some embodiments, forming the n-type region includes implanting a third n-type dopant at an angle between about 0° and about 45° relative to a direction perpendicular to the substrate. In some embodiments, forming the n-type region includes implanting a third n-type dopant, wherein: the dose of the third n-type dopant is about 1×10 14 cm -2 About 6×10 14 cm -2and the implantation energy of the third n-type dopant is between about 40 keV and about 80 keV. In some embodiments, doping the ridge includes implanting the first n-type dopant, the second n-type dopant, and the p-type dopant in a direction substantially perpendicular to the substrate. In some embodiments, the first implantation energy is between about 20 keV and about 50 keV; the second implantation energy is between about 20 keV and about 60 keV; and the third implantation energy is between about 100 keV and about 200 keV. In some embodiments, the first dose of the first n-type dopant is between about 5×10 13 cm -2 and about 5×10 14 cm -2 The second dosage of the second n-type dopant is between about 5×10 13 cm -2 and about 5×10 14 cm -2 and the third dose of the p-type dopant is between about 5×10 13 cm -2 and about 5×10 14 cm -2 between.

[0095] In some embodiments, a method includes forming an optical waveguide on a substrate and forming an optical modulator in the optical waveguide. Forming the optical modulator includes forming a first n-type layer below a side surface of the optical waveguide, forming a mask exposing the optical waveguide on the substrate, and performing first, second, and third implantation operations based on the mask. The first implantation operation forms a second n-type layer in the optical waveguide. The second implantation operation forms a third n-type layer in the optical waveguide and on the second n-type layer. The third implantation operation forms a p-type layer on the second n-type layer and under the third n-type layer. In some embodiments, a method includes forming an optical waveguide on a substrate and forming an optical modulator in the optical waveguide. Forming the optical modulator includes forming a first n-type region below a side surface of the optical waveguide, forming a mask exposing the optical waveguide on the substrate, and performing first, second, and third implantation operations based on the mask. The first implantation operation forms a second n-type region in the optical waveguide. The second implantation operation forms a third n-type region in the optical waveguide and on the second n-type region. The third implantation operation forms a p-type region on the second n-type region and under the third n-type region. In some embodiments, performing the first implantation operation includes implanting an n-type dopant having an energy greater than that of the dopant implanted during the second implantation operation and the third implantation operation. In some embodiments, performing the first implantation operation includes implanting an n-type dopant at an energy of about 5×10 13 cm -2 With about 5×10 14 cm -2 The second implantation operation includes implanting phosphorus at a first dose of about 5×1013 cm -2 With about 5×10 14 cm -2 and performing the third implantation operation including implanting phosphorus at a second dose of about 5×10 13 cm -2 With about 5×10 14 cm -2 In some embodiments, performing the first implantation operation, the second implantation operation, and the third implantation operation includes implanting dopants in a direction substantially perpendicular to the substrate. In some embodiments, forming the mask includes forming an opening exposing the optical waveguide, and wherein a width of the opening is greater than a width of the optical waveguide. In some embodiments, the method further includes: forming a first contact region in the substrate coupled to the first n-type region, the second n-type region, and the third n-type region; and forming a second contact region in the substrate coupled to the p-type region.

[0096] In some embodiments, a structure includes a ridge on a substrate and a PN junction in the ridge. The PN junction includes a first n-type region in the substrate, a p-type region on the first n-type region, a second n-type region on the p-type region, and a third n-type region connecting the first n-type region and the second n-type region. A first interface between the p-type region and the first n-type region is substantially parallel to a second interface between the p-type region and the second n-type region. The structure also includes an n-type contact region and a p-type contact region in the substrate. The n-type contact region is coupled to the third n-type region. The p-type contact region is coupled to the p-type region. In some embodiments, a semiconductor device includes a ridge on a substrate and a PN junction in the ridge. The PN junction includes a first n-type region in the substrate; a p-type region on the first n-type region; a second n-type region on the p-type region; and a third n-type region connecting the first n-type region and the second n-type region. The third n-type region includes a p-type dopant having substantially the same concentration as the p-type dopant in the p-type region. An n-type contact region in the substrate coupled to the third n-type region. A p-type contact region in the substrate coupled to the p-type region. In some embodiments, the PN junction has a C shape. In some embodiments, the p-type region includes boron; and the first n-type region and the second n-type region include phosphorus. In some embodiments, the third n-type region includes phosphorus and arsenic. In some embodiments, the third n-type region includes a first portion adjacent to the first n-type region and a second portion adjacent to the p-type region; and a concentration of an n-type dopant in the first portion is greater than a concentration of an n-type dopant in the second portion. In some embodiments, the concentration of the p-type dopant in the second portion is less than the concentration of the n-type dopant in the second portion.

[0097] It should be understood that the Detailed Description section, rather than the Abstract section of the disclosure, is intended to be used to interpret the claims. The Abstract section of the present disclosure may set forth one or more but not all possible embodiments of the present disclosure contemplated by the inventors, and thus is not intended to limit the appended claims in any way.

[0098] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: forming a ridge on a substrate; forming an n-type region below a first side surface of the ridge; forming a mask on the substrate, wherein the mask exposes a top surface of the ridge, and wherein an opening of the mask is located above the first and second side surfaces of the ridge; and The ridge is doped with a first n-type dopant, a second n-type dopant, and a p-type dopant based on the mask, wherein: A first implantation energy of the first n-type dopant is less than a second implantation energy of the second n-type dopant; as well as A third implantation energy of the p-type dopant is less than the second implantation energy. 2 . The method of forming a semiconductor device according to claim 1 , further comprising forming a dielectric layer on the substrate having a top surface coplanar with the top surface of the ridge. 3 . The method of forming a semiconductor device according to claim 1 , wherein forming the n-type region comprises implanting a third n-type dopant at an angle between about 0° and about 45° relative to a direction perpendicular to the substrate. 4 . The method of forming a semiconductor device according to claim 1 , wherein doping the ridge comprises implanting the first n-type dopant, the second n-type dopant, and the p-type dopant in a direction substantially perpendicular to the substrate.

5. A method of forming a semiconductor device, comprising: forming an optical waveguide on a substrate; as well as forming an optical modulator in the optical waveguide, comprising: forming a first n-type region below a side surface of the optical waveguide; forming a mask on the substrate to expose the optical waveguide; performing a first implantation operation based on the mask, wherein the first implantation operation forms a second n-type region in the optical waveguide; performing a second implantation operation based on the mask, wherein the second implantation operation forms a third n-type region in the optical waveguide and on the second n-type region; and A third implantation operation is performed based on the mask, wherein the third implantation operation forms a p-type region on the second n-type region and under the third n-type region. 6 . The method of forming a semiconductor device according to claim 5 , wherein performing the first implantation operation comprises implanting an n-type dopant having an energy greater than an energy of a dopant implanted during the second implantation operation and the third implantation operation.

7. The method for forming a semiconductor device according to claim 5, wherein: The first implantation operation includes implanting about 5×10 13 cm -2 With about 5×10 14 cm -2 The first dose of phosphorus was implanted between; The second implantation operation includes implanting about 5×10 13 cm -2 With about 5×10 14 cm -2 The second dose of phosphorus was implanted between; and Performing the third implantation operation includes implanting about 5×10 13 cm -2 With about 5×10 14 cm -2 The third dose between implants is boron. 8 . The method of forming a semiconductor device according to claim 5 , wherein forming the mask comprises forming an opening exposing the optical waveguide, and wherein a width of the opening is greater than a width of the optical waveguide.

9. A semiconductor device comprising: ridges on the substrate; A PN junction in the ridge, wherein the PN junction comprises: a first n-type region in the substrate; a p-type region on the first n-type region; a second n-type region on the p-type region; and a third n-type region connecting the first n-type region and the second n-type region, wherein the third n-type region includes a p-type dopant having substantially the same concentration as the p-type dopant in the p-type region; an n-type contact region in the substrate coupled to the third n-type region; and A p-type contact region in the substrate is coupled to the p-type region. 10 . The semiconductor device according to claim 9 , wherein the PN junction has a C shape.

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