Reading method, memory storage device and memory control circuit unit

Abstract

The invention provides a reading method, a memory storage device and a memory control circuit unit. The reading method comprises the following steps: applying a reading conduction voltage to a plurality of storage units of a first physical unit; for each of the plurality of bit lines, calculating a memory cell cut-off number of the memory cells connected to the bit line and cut off when the read break-over voltage is applied, the memory cell cut-off number corresponding to the first bit line being different from the memory cell cut-off number corresponding to the second bit line; setting a plurality of different reading voltages; when the second physical unit is read, a first read voltage is applied to the memory unit connected to the first bit line in the second physical unit, and a second read voltage is applied to the memory unit connected to the second bit line in the second physical unit, thereby obtaining a plurality of data bits of the second physical unit. Therefore, errors of data can be reduced.

Description

Technical Field

[0001] The present disclosure relates to a reading method of a rewritable non-volatile memory module, a memory storage device and a memory control circuit unit, which can solve the wear problem of the rewritable non-volatile memory module. Background Art

[0002] Portable electronic devices such as mobile phones and notebook computers have grown rapidly in recent years, resulting in a rapid increase in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are very suitable for being built into the various portable electronic devices listed above because they have the characteristics of data non-volatility, power saving, small size, and no mechanical structure.

[0003] On the other hand, with the development of artificial intelligence technology, the access frequency (especially data writing frequency) of processing circuits such as central processing unit (CPU), graphics processing unit (GPU), video processing unit (VPU), neural network processing unit (NPU) and tensor processing unit (TPU) to the rewritable non-volatile memory module has also greatly increased, resulting in a significant increase in the loss rate of the rewritable non-volatile memory module. Therefore, how to deal with the accelerated loss of the rewritable non-volatile memory module caused by a large number of access behaviors to the rewritable non-volatile memory module during the operation of the artificial intelligence model is one of the topics that technicians in this field are committed to studying. Summary of the invention

[0004] The present disclosure provides a reading method, a memory storage device and a memory control circuit unit, which can solve the problem of threshold voltage rising after physical unit wears out.

[0005] The present disclosure provides a reading method for a rewritable non-volatile memory module, which includes a plurality of physical units and a plurality of bit lines. The reading method includes: applying a read conduction voltage to a plurality of first memory cells of a first physical unit to determine whether the first memory cell is turned on or off, wherein each first memory cell is connected to a bit line; for each bit line, calculating a memory cell off number of first memory cells connected to the bit line and turned off when the read conduction voltage is applied, wherein the memory cell off number corresponding to the first bit line is different from the memory cell off number corresponding to the second bit line; setting a plurality of read voltages, including a first read voltage and a second read voltage, wherein the first read voltage is different from the second read voltage; when reading the second physical unit, applying the first read voltage to the second memory cell connected to the first bit line in the second physical unit, and applying the second read voltage to the second memory cell connected to the second bit line in the second physical unit, thereby obtaining a plurality of first data bits of the second physical unit.

[0006] In an embodiment of the present disclosure, the number of memory cells turned off corresponding to the first bit line is greater than the number of memory cells turned off corresponding to the second bit line, and the first read voltage is greater than the second read voltage.

[0007] In an embodiment of the present disclosure, the step of setting the read voltage includes: setting the read voltage according to the number of memory cells turned off corresponding to the bit line, wherein the number of memory cells turned off and the read voltage are positively correlated.

[0008] In one embodiment of the present disclosure, the above-mentioned reading method also includes: determining whether the first data bit passes the error checking procedure; if the first data bit does not pass the error checking procedure, applying a read-on voltage to multiple third storage cells of the third physical unit to determine whether the third storage cells are turned on or off, wherein each third storage cell is connected to a bit line; for each bit line, calculating a storage cell cut-off distribution of the first storage cell and the third storage cell connected to the bit line and turned off when the read-on voltage is applied, wherein the storage cell cut-off distribution corresponding to the first bit line is different from the storage cell cut-off distribution corresponding to the second bit line; and applying a third read voltage to the second storage cell connected to the first bit line in the second physical unit, and applying a fourth read voltage among the read voltages to the second storage cell connected to the second bit line in the second physical unit, thereby reading multiple second data bits of the second physical unit.

[0009] In one embodiment of the present disclosure, the number of first memory cells and third memory cells connected to the first bit line and turned off when a read-on voltage is applied is greater than the number of first memory cells and third memory cells connected to the second bit line and turned off when a read-on voltage is applied, and the third read voltage is greater than the fourth read voltage.

[0010] In one embodiment of the present disclosure, the above-mentioned reading method also includes: storing the storage cell cutoff distribution corresponding to the bit line in a buffer memory; and when reading the second physical unit, reading the storage cell cutoff distribution from the buffer memory to determine that the first bit line corresponds to the first reading voltage and the second bit line corresponds to the second reading voltage.

[0011] In an embodiment of the present disclosure, the second physical unit is different from at least the first physical unit.

[0012] From another perspective, an embodiment of the present invention provides a memory storage device, comprising: a connection interface unit for coupling to a host system; a rewritable non-volatile memory module, comprising a plurality of physical cells and a plurality of bit lines; and a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to perform a plurality of steps: applying a read conduction voltage to a plurality of first memory cells of a first physical unit to determine whether the first memory cell is turned on or off, wherein each first memory cell is connected to a bit line; for each bit line, calculating a memory cell off number of first memory cells connected to the bit line and turned off when the read conduction voltage is applied, wherein the memory cell off number corresponding to the first bit line is different from the memory cell off number corresponding to the second bit line; setting a plurality of read voltages, including a first read voltage and a second read voltage, wherein the first read voltage is different from the second read voltage; when reading the second physical unit, applying the first read voltage to the second memory cell connected to the first bit line in the second physical unit, and applying the second read voltage to the second memory cell connected to the second bit line in the second physical unit, thereby obtaining a plurality of first data bits of the second physical unit.

[0013] From another perspective, an embodiment of the present invention provides a memory control circuit unit for controlling a rewritable non-volatile memory module. The memory control circuit unit includes: a host interface for coupling to a host system; a memory interface for coupling to a rewritable non-volatile memory module; and a memory management circuit coupled to the host interface and the memory interface. The memory management circuit is used to perform multiple steps: applying a read conduction voltage to multiple first memory cells of a first physical unit to determine whether the first memory cell is turned on or off, wherein each first memory cell is connected to a bit line; for each bit line, calculating a memory cell off number of first memory cells connected to the bit line and turned off when the read conduction voltage is applied, wherein the memory cell off number corresponding to the first bit line is different from the memory cell off number corresponding to the second bit line; setting multiple read voltages, including a first read voltage and a second read voltage, the first read voltage is different from the second read voltage; when reading the second physical unit, applying the first read voltage to the second memory cell connected to the first bit line in the second physical unit, and applying the second read voltage to the second memory cell connected to the second bit line in the second physical unit, thereby obtaining multiple first data bits of the second physical unit.

[0014] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention;

[0016] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0017] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0018] Figure 4A is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0019] Figure 4B is a schematic diagram of a memory cell array according to an exemplary embodiment of the present invention;

[0020] Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0021] Figure 6is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0022] Figure 7 is a schematic diagram illustrating reading a conduction voltage according to an embodiment;

[0023] Figure 8 is a flow chart showing a reading method according to an embodiment;

[0024] Fig. 9 is a schematic diagram showing application of a read voltage according to an embodiment;

[0025] Fig.10 is a schematic diagram showing application of a read voltage according to an embodiment;

[0026] Fig.11 is a schematic diagram showing application of a read voltage according to an embodiment;

[0027] Fig.12 is a flow chart showing a reading method according to another embodiment;

[0028] Fig.13 is a schematic diagram showing selecting a third physical unit according to an embodiment. DETAILED DESCRIPTION

[0029] Some embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The referenced element symbols in the following description will be regarded as the same or similar elements when the same element symbols appear in different drawings. These embodiments are only part of the present invention and do not disclose all possible implementation methods of the present invention. More specifically, these embodiments are only examples of systems and methods within the scope of the claims of the present invention.

[0030] The terms “first,” “second,” etc. used herein do not particularly refer to an order or sequence, but are only used to distinguish elements or operations described with the same technical term.

[0031] Generally speaking, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used together with a host system so that the host system can write data to the memory storage device or read data from the memory storage device.

[0032] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0033] Please refer to Figure 1 and Figure 2 The host system 11 may include a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 may be coupled to a system bus 110.

[0034] In an exemplary embodiment, the host system 11 may be coupled to the memory storage device 10 via the data transmission interface 114. For example, the host system 11 may store data to the memory storage device 10 or read data from the memory storage device 10 via the data transmission interface 114. In addition, the host system 11 may be coupled to the I / O device 12 via the system bus 110. For example, the host system 11 may transmit an output signal to the I / O device 12 or receive an input signal from the I / O device 12 via the system bus 110.

[0035] In an exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of the data transmission interface 114 may be one or more. Through the data transmission interface 114, the motherboard 20 may be coupled to the memory storage device 10 via a wired or wireless manner.

[0036] In an exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near field communication (NFC) memory storage device, a wireless local area network (WiFi) memory storage device, a Bluetooth memory storage device, or a low power Bluetooth memory storage device (e.g., iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 may also be coupled to various I / O devices such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

[0037] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 can be any system that can substantially cooperate with the memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 can respectively include Figure 3 A memory storage device 30 and a host system 31.

[0038] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention. Figure 3 , the memory storage device 30 can be used in conjunction with a host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly couple the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0039] Figure 4A is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Figure 4A , the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42 and a rewritable non-volatile memory module 43.

[0040] The connection interface unit 41 is used to couple to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In an exemplary embodiment, the connection interface unit 41 may also comply with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard or other suitable standards. The connection interface unit 41 and the memory control circuit unit 42 may be packaged in one chip, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42 .

[0041] The memory control circuit unit 42 is coupled to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware form and perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0042] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one storage cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one storage cell), a triple level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one storage cell), a quad level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one storage cell), other flash memory modules or other memory modules with the same characteristics.

[0043] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing the voltage (hereinafter also referred to as the threshold voltage). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, thereby obtaining one or more bits stored in this memory cell.

[0044] Figure 4B is a schematic diagram of a memory cell array according to an exemplary embodiment of the present invention. Figure 4B The memory cell array 44 includes a plurality of memory cells 402 for storing data, a plurality of select gate drain (SGD) transistors 412 and a plurality of select gate source (SGS) transistors 414, a plurality of bit lines 404 (1) to 404 (3) connecting the memory cells 402, a plurality of word lines 406 (1) to 406 (N), and a common source line 408, wherein N is a positive integer. In particular, the memory cells 402 are arranged in an array at the intersections of the bit lines 404 (1) to 404 (3) and the word lines 406 (1) to 406 (N), such as Figure 4B shown. Figure 4BThis is just an example, and the present invention does not limit the number of word lines and bit lines in one memory cell array 44. In addition, the rewritable nonvolatile memory module 43 may include a plurality of memory cell arrays 44. These memory cell arrays 44 may be stacked horizontally and / or vertically.

[0045] In an example embodiment, the storage cells of the rewritable non-volatile memory module 43 may constitute a plurality of physical programming units, and these physical programming units may constitute a plurality of physical erase units. Specifically, the storage cells on the same word line may constitute one or more physical programming units. If each storage cell can store more than 2 bits, the physical programming units on the same word line may be classified into at least a lower physical programming unit and an upper physical programming unit. For example, the least significant bit (LSB) of a storage cell belongs to the lower physical programming unit, and the most significant bit (MSB) of a storage cell belongs to the upper physical programming unit. Generally speaking, in an MLC NAND type flash memory, the write speed of the lower physical programming unit is greater than the write speed of the upper physical programming unit, and / or the reliability of the lower physical programming unit is higher than the reliability of the upper physical programming unit.

[0046] In an example embodiment, the physical programming unit is the smallest unit of programming. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit may be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area includes a plurality of physical sectors for storing user data, and the redundancy bit area is used to store system data (for example, management data such as error correction codes). In an example embodiment, the data bit area includes 32 physical sectors, and the size of a physical sector is 512 bytes (byte, B). However, in other example embodiments, the data bit area may also include 8, 16 or more or less physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the physical erase unit is the smallest unit of erasure. That is, each physical erase unit contains one of the minimum number of storage cells that are erased. For example, the physical erase unit is a physical block.

[0047] Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Figure 5 The memory control circuit unit 42 includes a memory management circuit 51 , a host interface 52 and a memory interface 53 .

[0048] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and when the memory storage device 10 is in operation, these control instructions are executed to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to describing the operation of the memory control circuit unit 42 and the memory storage device 10.

[0049] In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in the form of firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

[0050] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a specific area of ​​the rewritable non-volatile memory module 43 (for example, a system area in the memory module dedicated to storing system data) in the form of program code. In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit will first execute the boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Afterwards, the microprocessor unit will execute these control instructions to perform operations such as writing, reading, and erasing data.

[0051] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be implemented in a hardware form. For example, the memory management circuit 51 includes a microcontroller, a storage unit management circuit, a memory write circuit, a memory read circuit, a memory erase circuit and a data processing circuit. The storage unit management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are coupled to the microcontroller. The storage unit management circuit is used to manage the storage unit or storage unit group of the rewritable non-volatile memory module 43. The memory write circuit is used to issue a write instruction sequence to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a read instruction sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is used to issue an erase instruction sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process data to be written to the rewritable non-volatile memory module 43 and data to be read from the rewritable non-volatile memory module 43. The write command sequence, the read command sequence and the erase command sequence may each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of command sequences to the rewritable non-volatile memory module 43 to instruct the execution of corresponding operations.

[0052] The host interface 52 is coupled to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to obtain and identify instructions and data from the host system 11. For example, the instructions and data of the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this example embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited to this, and the host interface 52 can also be compatible with the SATA standard, the PATA standard, the IEEE 1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.

[0053] The memory interface 53 is coupled to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, the data to be written to the rewritable non-volatile memory module 43 will be converted into a format acceptable to the rewritable non-volatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences may include a write instruction sequence indicating writing data, a read instruction sequence indicating reading data, an erase instruction sequence indicating erasing data, and corresponding instruction sequences for indicating various memory operations (for example, changing the read voltage level or performing a garbage collection (GC) operation, etc.). These instruction sequences are, for example, generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, in a read instruction sequence, information such as a read identification code and a memory address may be included.

[0054] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54 , a buffer memory 55 , and a power management circuit 56 .

[0055] The error checking and correction circuit 54 is coupled to the memory management circuit 51 and is used to perform error checking and correction operations to ensure the correctness of data. Specifically, when the memory management circuit 51 obtains a write command from the host system 11, the error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or an error detecting code (EDC) for the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code into the rewritable non-volatile memory module 43. Afterwards, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, the error correcting code and / or error detecting code corresponding to the data will be read at the same time, and the error checking and correction circuit 54 will perform error checking and correction operations on the read data according to the error correcting code and / or error detecting code. For example, the ECC circuit 54 may use various encoding / decoding algorithms such as low density parity check code (LDPC code), BCH code, Reed-solomon code (RS code), exclusive OR (XOR) code, etc. to encode and decode data.

[0056] The buffer memory 55 is coupled to the memory management circuit 51 and used for temporarily storing data. The power management circuit 56 is coupled to the memory management circuit 51 and used for controlling the power of the memory storage device 10 .

[0057] In an example embodiment, Figure 4A The rewritable non-volatile memory module 43 may include a flash memory module. In an example embodiment, Figure 4A The memory control circuit unit 42 may include a flash memory controller. In an example embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0058] Figure 6 FIG. 1 is a schematic diagram of managing a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention. Figure 6 The memory management circuit 51 may logically group the physical units 610 ( 0 ) to 610 (C) in the rewritable nonvolatile memory module 43 into a storage area 601 , a spare area 602 , and a system area 603 .

[0059] In an exemplary embodiment, a physical unit refers to a physical address or a physical programming unit. In an exemplary embodiment, a physical unit may also be composed of multiple continuous or discontinuous physical addresses.

[0060] In an example embodiment, physical units 610(0)-610(A) in storage area 601 are used to store user data (e.g., from Figure 1 The user data of the host system 11 of the storage area 601). For example, the physical units 610(0)~610(A) in the storage area 601 can store valid data and invalid data. The physical units 610(A+1)~610(B) in the idle area 602 do not store data (such as valid data). For example, if a physical unit does not store valid data, this physical unit can be associated (or added) to the idle area 602. In addition, the physical units in the idle area 602 (or the physical units that do not store valid data) can be erased. When writing new data, one or more physical units can be extracted from the idle area 602 to store the new data. In an exemplary embodiment, the idle area 602 is also called a free pool.

[0061] In an example embodiment, the memory management circuit 51 may configure the logical units 612(0)-612(D) to map the physical units 610(0)-610(A) in the storage area 601. In an example embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units. In an example embodiment, a logical unit may also correspond to a logical programming unit or be composed of multiple continuous or discontinuous logical addresses.

[0062] It should be noted that a logical unit can be mapped to one or more physical units. If a physical unit is currently mapped by a logical unit, it means that the data currently stored in the physical unit includes valid data. On the contrary, if a physical unit is not currently mapped by any logical unit, it means that the data currently stored in the physical unit is invalid data.

[0063] In an exemplary embodiment, the memory management circuit 51 may record management data describing the mapping relationship between the logical unit and the physical unit (also referred to as logical-to-physical mapping information) in at least one logical-to-physical mapping table (L2Ptable). When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 may access the rewritable non-volatile memory module 43 according to the information in the logical-to-physical mapping table.

[0064] In an exemplary embodiment, the memory management circuit 51 may store a specific type of data in the system area 603. For example, the physical units 610(B+1) to 610(C) in the system area 603 may be dedicated to store data of higher importance and / or data that is not intended to be accessed or modified by the host system 11. For example, the data of higher importance and / or data that is not intended to be accessed or modified by the host system 11 may include a logical-to-physical mapping table, a bad block management table, a wear leveling management table, a valid data management table, and / or other types of management data, which are not limited by the present invention. The logical-to-physical mapping table is used to record mapping information. This mapping information may reflect the mapping relationship between the logical unit and the physical unit. The bad block management table is used to record information related to at least one bad block in the rewritable non-volatile memory module 43. The wear leveling management table may be used to record information related to the wear state of at least one physical unit in the rewritable non-volatile memory module 43 (e.g., read count, write count, and / or erase count). The valid data management table may be used to record information related to the valid count of at least one physical unit in the rewritable non-volatile memory module 43 .

[0065] In an exemplary embodiment, the memory management circuit 51 may not map any logical unit to a physical unit in the system area 603. Thus, data stored in the system area 603 may be prevented from being accessed or modified by the host system 11.

[0066] Here, a read-on voltage is described. The read-on voltage is applied to other physical cells when reading a physical cell to turn on the memory cells in the other physical cells. Figure 7 is a schematic diagram illustrating reading the conduction voltage according to an embodiment. Figure 7When the physical cell on word line 406 (5) is to be read, the memory management circuit 51 applies a read voltage Vr to the memory cell connected to word line 406 (5), and simultaneously applies a read conduction voltage Vp to the memory cells on other word lines 406 (1) to 406 (4), 406 (6) to 406 (N). Generally speaking, the memory cell should be turned on when the read conduction voltage is applied, so the multiple bits obtained from the bit lines 404 (1) to 404 (3) will reflect whether the memory cell on word line 406 (5) is turned on. For example, when a memory cell on word line 406 (5) is turned on, a bit "1" can be obtained on the corresponding bit line, otherwise a bit "0" is obtained. However, in some applications (such as artificial intelligence), the rewritable non-volatile memory module 43 is frequently read, written or erased, which will increase the threshold voltage of the memory cell, even higher than the read conduction voltage, which will affect the reading of the physical cell. For example, when the threshold voltage of one or more memory cells on word line 406 (6) exceeds the read on voltage, these memory cells are turned off, thereby changing the bit obtained on the corresponding bit line. When the threshold voltage of a memory cell exceeds the read on voltage, the memory cell is called an open bit. In the following embodiments, the read voltage is determined based on the number or distribution of the open bits.

[0067] Figure 8 is a flow chart showing a reading method according to an embodiment. This method is executed by the memory management circuit 51 and will not be described in detail below. Figure 8 In step 801, a read conduction voltage is applied to a plurality of memory cells of a first physical unit (also referred to as a first memory cell) to determine whether the first memory cell is turned on or off. Here, the first physical unit is not the physical unit to be read, but as described above, whether there is a cutoff bit in other physical units will affect the physical unit to be read. The number of first physical units can be one or more, and one first physical unit is taken as an example for explanation. Fig. 9 FIG. 1 is a schematic diagram showing application of a read voltage according to an embodiment. Fig. 9In the embodiment, a read conduction voltage Vp is applied to the first physical cell on word line 406 (2), and the same or higher voltage can be applied to the memory cells on other word lines. When the voltage on word line 406 (2) is lower than the voltage on other word lines, the memory cells on other word lines have a higher probability of being turned on. In this way, it can be determined whether each first memory cell on word line 406 (2) is turned on based on the bits sensed on bit lines 404 (1) to 404 (3). When the voltage on word line 406 (2) is the same as the voltage on other word lines, it can be determined whether there are memory cells on the corresponding bit line that are turned off based on the bits sensed on bit lines 404 (1) to 404 (3). Such information also reflects the degree of degradation of this physical block and can be used to determine the read voltage.

[0068] In step 802, for each bit line, the number of first memory cells connected to the bit line and turned off when a read-on voltage is applied (referred to as the memory cell turn-off number) is calculated. It is assumed that the first memory cell connected to the bit line 404 (1) and the word line 406 (2) is turned on when the read-on voltage Vp is applied; the first memory cell connected to the bit line 404 (2) and the word line 406 (2) is turned off when the read-on voltage Vp is applied; and the first memory cell connected to the bit line 404 (3) and the word line 406 (2) is turned on when the read-on voltage Vp is applied. Therefore, the memory cell turn-off number corresponding to the bit line 404 (1) is 0, the memory cell turn-off number corresponding to the bit line 404 (2) is 1, and the memory cell turn-off number corresponding to the bit line 404 (3) is 0. In other words, the memory cell turn-off numbers corresponding to the bit lines 404 (1) and 404 (3) are different from the memory cell turn-off number corresponding to the bit line 404 (2).

[0069] In step 803, a plurality of different read voltages are set. One of the read voltages may be the same as the preset read voltage, and the other may be greater than the preset read voltage. The two read voltages are referred to herein as the first read voltage and the second read voltage.

[0070] In step 804, when reading the second physical unit (e.g., the physical unit on word line 406(5)), a first read voltage V1 is applied to the memory cell connected to bit line 404(2) in the second physical unit, and a second read voltage V2 is applied to the memory cell connected to bit lines 404(1) and 404(3) in the second physical unit, thereby obtaining a plurality of data bits of the second physical unit. The first read voltage V1 and the second read voltage V2 are applied to word line 406(5) at different time points. For example, the first read voltage V1 is first applied to word line 406(5), a read-on voltage is applied to other word lines, and one bit is obtained from bit line 404(2); then, the second read voltage V2 is applied to word line 406(5), a read-on voltage is applied to other word lines, and two bits are obtained from bit lines 404(1) and 404(3). The three bits obtained above are the plurality of data bits in the second physical unit.

[0071] In some embodiments, the number of memory cells turned off is positively correlated with the read voltage. For example, the number of memory cells turned off corresponding to bit line 404 (2) is greater than the number of memory cells turned off corresponding to bit lines 404 (1) and 404 (3). Therefore, the first read voltage V1 can be set to be greater than the second read voltage V2.

[0072] As described above, the second physical unit on word line 406 (5) is different from the first physical unit on word line 406 (2). In other words, when a physical unit is to be read, the read voltage is determined according to the cutoff bits on other physical units. In some embodiments, the position of the first physical unit can be determined in advance. After the rewritable non-volatile memory module 43 is produced, any detection means can be used to determine which memory cells on the word line are prone to defects, so the physical units on these word lines are set to the above-mentioned first physical units. In some embodiments, different first physical units can be set on different physical blocks or different dies, thereby reflecting different physical characteristics.

[0073] The number of the first physical units is 1, but in other embodiments the number of the first physical units may be greater than 1. Fig.10In the method, a read conduction voltage Vp is first applied to the memory cells of the first physical unit on the word lines 406 (2) and 406 (7) to determine whether these memory cells are turned on or off. Then, for each bit line, the number of memory cells connected to this bit line and turned off when the read conduction voltage Vp is applied (referred to as the memory cell cut-off number) is calculated. Possible values ​​of the memory cell cut-off number include 0, 1, and 2, and different memory cell cut-off numbers correspond to different read voltages. In some embodiments, the read voltage can be set according to the memory cell cut-off number, so that the memory cell cut-off number and the read voltage are positively correlated. For example, when the memory cell cut-off number is equal to 2, a first read voltage is used; when the memory cell cut-off number is equal to 1, a second read voltage is used; and when the memory cell cut-off number is equal to 0, a third read voltage is used, wherein the first read voltage is greater than the second read voltage, and the second read voltage is greater than the third read voltage.

[0074] In some embodiments, if the number of memory cells turned off in two bit lines is the same but the positions of the turned off bits are different, different read voltages may be used. Fig.11 , when a read-on voltage is applied to word lines 406(2) and 406(7), the memory cells connected to word line 406(2) and bit line 404(1) are turned off, the memory cells connected to word line 406(2) and bit line 404(2) are turned on, the memory cells connected to word line 406(2) and bit line 404(3) are turned on, the memory cells connected to word line 406(7) and bit line 404(1) are turned on, the memory cells connected to word line 406(7) and bit line 404(2) are turned on, and the memory cells connected to word line 406(7) and bit line 404(3) are turned off. In this example, the number of memory cells turned off on bit line 404(1) and bit line 404(3) is both 1, but the turned-off bit on bit line 404(1) occurs on word line 406(2), while the turned-off bit on bit line 404(3) occurs on word line 406(7). According to the distribution of the cut-off bits on a bit line, multiple groups can be generated, and each bit line belongs to one of the groups. This distribution can be represented by multiple bits, and each bit represents whether there is a cut-off bit on the corresponding word line. When a read-on voltage is applied to 1 word line, there are 2 groups (cut-off or on), when a read-on voltage is applied to 2 word lines, 4 groups can be generated, when a read-on voltage is applied to 3 word lines, 8 groups can be generated, when a read-on voltage is applied to 4 word lines, 16 groups can be generated, and so on. For example, in Fig.11 In the embodiment of the present invention, the four groups can be represented as shown in the following Table 1.

[0075] Word line 406 (2) Word line 406 (7) Group 1 1 1 Group 2 1 0 Group 3 0 1 Group 4 0 0

[0076] Table 1

[0077] "1" in Table 1 indicates that the corresponding storage unit is a cutoff bit, and "0" indicates a non-cutoff bit. Specifically, bit line 404 (1) belongs to the second group, bit line 404 (2) belongs to the fourth group, and bit line 404 (3) belongs to the third group. The above-mentioned first to fourth groups correspond to the first read voltage V1 to the fourth read voltage V4, respectively. Therefore, when reading the physical unit on the word line 406 (5), the second read voltage V2, the fourth read voltage V4 and the third read voltage V3 can be applied to the word line 406 (5) at different time points to read data bits from the storage units connected to the bit lines 404 (1) to 404 (3), respectively. It is worth noting that in Fig.11 The first to fourth read voltages V1-V4 are shown to be applied to word line 406 (5). This is because the number of bit lines is actually much greater than 3, so some bit lines belong to the first group (using the first read voltage V1).

[0078] Fig.12 FIG. 1 is a flow chart showing a reading method according to another embodiment. Fig.12 In the embodiment of the present invention, the number of word lines to which the read conduction voltage is applied gradually increases. In step 1201, a read conduction voltage is applied to a plurality of first storage cells of a first physical unit to determine whether the first storage cells are turned on or off. This step 1201 is the same as step 801.

[0079] In step 1202, for each bit line, the distribution of memory cells connected to the bit line and turned off when a read-on voltage is applied (referred to as memory cell turn-off distribution) is calculated. Here, the memory cell turn-off distribution may include position information of each turn-off bit (see Table 1). When the number of first physical cells is M, there are 2^M different memory cell turn-off distributions, where M is a positive integer.

[0080] In step 1203, a plurality of different read voltages are set. For example, a different read voltage may be set for each memory cell cutoff distribution.

[0081] At step 1204, when reading the second physical cell, different read voltages are applied to different memory cell cutoff distributions to obtain data bits from corresponding bit lines. Fig.11 In the embodiment, the cut-off distributions of the memory cells of the bit lines 404 ( 1 ) to 404 ( 3 ) are all different from each other, so three different read voltages are applied to the word line 406 ( 5 ).

[0082] In step 1205, it is determined whether the obtained data bits (also referred to as first data bits) pass an error checking procedure, for example, it is determined whether these first data bits can be completely corrected according to an error correction code. If it does not pass the error checking procedure, in step 1206, another physical unit (referred to as a third physical unit) is additionally selected, and then a read conduction voltage is applied to the third physical unit to determine whether the storage unit in the third physical unit is turned on or off. Fig.13 is a schematic diagram showing selection of a third physical unit according to an embodiment, Fig.13 Is a continuation Fig.11 In the embodiment, it is assumed that word line 406(8) is additionally selected. After applying the read-on voltage Vp to the third physical cell on word line 406(8), the memory cell connected to bit line 404(1) is turned on, the memory cell connected to bit line 404(2) is turned off, and the memory cell connected to bit line 404(3) is turned off.

[0083] Next, we return to step 1202 and recalculate the memory cell cutoff distribution. In this case, we calculate not only the memory cells of word lines 406(2) and 406(7), but also the memory cells of word line 406(8). Since three word lines are currently applied with the read-on voltage Vp, there are a total of 8 memory cell cutoff distributions (i.e., 8 groups), which can be represented as the following Table 2.

[0084] Word line 406 (2) Word line 406 (7) Word line 406 (8) Group 1 1 1 1 Group 2 1 1 0 Group 3 1 0 1 Group 4 1 0 0 Group 5 0 1 1 Group 6 0 1 0 Group 7 0 0 1 Group 8 0 0 0

[0085] Table 2

[0086] Similarly, "1" in Table 2 indicates that the corresponding storage unit is a cut-off bit, and "0" indicates a non-cut-off bit. Fig.13 In the example, bit line 404(1) belongs to the fourth group, bit line 404(2) belongs to the seventh group, and bit line 404(3) belongs to the fifth group. In other words, the memory cell cutoff distributions of bit lines 404(1) to 404(3) are different from each other.

[0087] In step 1203, multiple read voltages are set. After adding a word line, 8 different read voltages can be set, corresponding to the above-mentioned 8 groups respectively. These 8 read voltages can be determined through experiments. It is assumed that the first to eighth groups mentioned above correspond to the first to eighth read voltages respectively. In some embodiments, when the number of cutoff bits in a group is large, the corresponding read voltage is also large. For example, there are 3 cutoff bits in the first group, 2 cutoff bits in the second group, and 1 cutoff bit in the fourth group, so the first read voltage will be greater than the second read voltage, and the second read voltage will be greater than the fourth read voltage.

[0088] In step 1204, when the second physical cell on word line 406(5) is read again, different read voltages are applied to different memory cell cutoff distributions to obtain data bits from the corresponding bit lines. In this example, a fourth read voltage is first applied to word line 406(5) to obtain a data bit from bit line 404(1), a fifth read voltage is then applied to word line 406(5) to obtain a data bit from bit line 404(3), and a seventh read voltage is then applied to word line 406(5) to obtain a data bit from bit line 404(2).

[0089] The three data bits obtained above will be judged again in step 1205. If they have not passed the error checking procedure, another physical unit will be selected in step 1206. The above method can gradually increase the decoding capability and avoid reading too many times at the beginning and spending too much time or computing resources.

[0090] Please refer to Figure 5 In some embodiments, the memory management circuit 51 may apply a read conduction voltage to a plurality of physical cells in advance (e.g., when idle), and after calculating the number of memory cell cutoffs or the memory cell cutoff distribution corresponding to each bit line, the number of memory cell cutoffs or the memory cell cutoff distribution may be stored in the buffer memory 55. When a physical cell is to be read, the memory management circuit 51 may read the number of memory cell cutoffs or the memory cell cutoff distribution from the buffer memory 55, thereby determining which read voltage to apply to the memory cell on which bit line. In this way, the reading speed may be increased.

[0091] In the above embodiment, when reading the second physical unit, the read voltage is determined according to the cutoff bit on the first physical unit. In other embodiments, the initial read voltage of the second physical unit can also be determined according to the number of cutoff bits on the second physical unit. Generally speaking, the larger the number of cutoff bits on the second physical unit, the larger the initial read voltage. Here, a function or a lookup table can be used to convert the number of cutoff bits into the read voltage.

[0092] In some embodiments, the above Figure 8 as well as Fig.12The process is performed only after the general reading procedure fails. For example, the reading procedure may include a hard decoding procedure and a soft decoding procedure. In the hard decoding procedure, a reading voltage (i.e., the initial reading voltage) is set, and the data bits can be obtained according to whether the corresponding storage unit is turned on under this reading voltage. Next, the error correction code decoding procedure is implemented on these data bits to correct the error bits therein. If the number of error bits is too large and exceeds the correction capacity of the error correction code, it means that the hard decoding procedure has failed. When the hard decoding procedure fails, the soft decoding procedure will be performed. In the soft decoding procedure, multiple reading voltages are set, and a probability value can be calculated according to whether the corresponding storage unit is turned on under these reading voltages. Next, the error correction code (for example, LDPC) decoding procedure is implemented on these probability values ​​to obtain the final data bits. If these data bits cannot be completely corrected, it means that the soft decoding procedure has failed. When the soft decoding procedure fails, Figure 8 or Fig.12 In one embodiment, there are still 214 error bits in the soft decoding process, but after setting 16 groups to adjust the read voltage, the number of error bits is reduced to 131. In other words, the above method can reduce the number of error bits.

[0093] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended claims.

Claims

1. A reading method, characterized in that: For a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units and a plurality of bit lines, and the reading method includes: applying a read-on voltage to a plurality of first memory cells of at least a first physical cell among the plurality of physical cells to determine whether the plurality of first memory cells are turned on or off, wherein each of the plurality of first memory cells is connected to one of the plurality of bit lines; For each of the plurality of bit lines, calculating the number of memory cell turn-offs of the plurality of first memory cells connected to the bit line and turned off when the read-on voltage is applied, wherein the plurality of bit lines include a first bit line and a second bit line, and the number of memory cell turn-offs corresponding to the first bit line is different from the number of memory cell turn-offs corresponding to the second bit line; Setting a plurality of read voltages, wherein the plurality of read voltages include a first read voltage and a second read voltage, wherein the first read voltage is different from the second read voltage; When reading a second physical unit among the multiple physical units, the first read voltage is applied to a second storage unit in the second physical unit connected to the first bit line, and the second read voltage is applied to a second storage unit in the second physical unit connected to the second bit line, thereby obtaining multiple first data bits of the second physical unit.

2. The reading method according to claim 1, characterized in that: The number of the memory cells turned off corresponding to the first bit line is greater than the number of the memory cells turned off corresponding to the second bit line, and the first read voltage is greater than the second read voltage.

3. The reading method according to claim 1, characterized in that: The step of setting the plurality of read voltages comprises: The plurality of read voltages are set according to the plurality of memory cell cut-off numbers corresponding to the plurality of bit lines, wherein the plurality of memory cell cut-off numbers and the plurality of read voltages are positively correlated.

4. The reading method according to claim 1, characterized in that: Also includes: determining whether the plurality of first data bits pass an error checking procedure; If the plurality of first data bits do not pass the error checking procedure, applying the read-on voltage to a plurality of third memory cells of a third physical cell among the plurality of physical cells to determine whether the plurality of third memory cells are turned on or off, wherein each of the plurality of third memory cells is connected to one of the plurality of bit lines; For each of the plurality of bit lines, calculating a memory cell turn-off distribution of the plurality of first memory cells and the plurality of third memory cells connected to the bit line and turned off when the read-on voltage is applied, wherein the memory cell turn-off distribution corresponding to the first bit line is different from the memory cell turn-off distribution corresponding to the second bit line; as well as A third read voltage among the multiple read voltages is applied to the second storage unit connected to the first bit line in the second physical unit, and a fourth read voltage among the multiple read voltages is applied to the second storage unit connected to the second bit line in the second physical unit, thereby reading multiple second data bits of the second physical unit.

5. The reading method according to claim 4, characterized in that: Wherein the number of the plurality of first memory cells and the plurality of third memory cells connected to the first bit line and turned off when the read-on voltage is applied is greater than the number of the plurality of first memory cells and the plurality of third memory cells connected to the second bit line and turned off when the read-on voltage is applied, and the third read voltage is greater than the fourth read voltage.

6. The reading method according to claim 4, characterized in that: Also includes: storing the plurality of storage unit cutoff distributions corresponding to the plurality of bit lines in a buffer memory; as well as When reading the second physical unit, the plurality of memory cell cutoff distributions are read from the buffer memory to determine that the first bit line corresponds to the first read voltage and the second bit line corresponds to the second read voltage.

7. The reading method according to claim 1, characterized in that: Wherein the second physical unit is different from the at least first physical unit.

8. A memory storage device, characterized in that: include: A connection interface unit for coupling to a host system; A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical cells and a plurality of bit lines; as well as A memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module, and is used to perform a plurality of steps: applying a read-on voltage to a plurality of first memory cells of at least a first physical cell among the plurality of physical cells to determine whether the plurality of first memory cells are turned on or off, wherein each of the plurality of first memory cells is connected to one of the plurality of bit lines; For each of the plurality of bit lines, calculating the number of memory cell turn-offs of the plurality of first memory cells connected to the bit line and turned off when the read-on voltage is applied, wherein the plurality of bit lines include a first bit line and a second bit line, and the number of memory cell turn-offs corresponding to the first bit line is different from the number of memory cell turn-offs corresponding to the second bit line; Setting a plurality of read voltages, wherein the plurality of read voltages include a first read voltage and a second read voltage, wherein the first read voltage is different from the second read voltage; When reading a second physical unit among the multiple physical units, the first read voltage is applied to a second storage unit in the second physical unit connected to the first bit line, and the second read voltage is applied to a second storage unit in the second physical unit connected to the second bit line, thereby obtaining multiple first data bits of the second physical unit.

9. The memory storage device according to claim 8, characterized in that: The number of the memory cells turned off corresponding to the first bit line is greater than the number of the memory cells turned off corresponding to the second bit line, and the first read voltage is greater than the second read voltage.

10. The memory storage device according to claim 8, characterized in that The step of setting the plurality of read voltages comprises: The plurality of read voltages are set according to the plurality of memory cell cut-off numbers corresponding to the plurality of bit lines, wherein the plurality of memory cell cut-off numbers and the plurality of read voltages are positively correlated.

11. The memory storage device according to claim 8, characterized in that The multiple steps also include: determining whether the plurality of first data bits pass an error checking procedure; If the plurality of first data bits do not pass the error checking procedure, applying the read-on voltage to a plurality of third memory cells of a third physical cell among the plurality of physical cells to determine whether the plurality of third memory cells are turned on or off, wherein each of the plurality of third memory cells is connected to one of the plurality of bit lines; For each of the plurality of bit lines, calculating a memory cell turn-off distribution of the plurality of first memory cells and the plurality of third memory cells connected to the bit line and turned off when the read-on voltage is applied, wherein the memory cell turn-off distribution corresponding to the first bit line is different from the memory cell turn-off distribution corresponding to the second bit line; and A third read voltage among the multiple read voltages is applied to the second storage unit connected to the first bit line in the second physical unit, and a fourth read voltage among the multiple read voltages is applied to the second storage unit connected to the second bit line in the second physical unit, thereby reading multiple second data bits of the second physical unit.

12. The memory storage device according to claim 11, characterized in that Wherein the number of the plurality of first memory cells and the plurality of third memory cells connected to the first bit line and turned off when the read-on voltage is applied is greater than the number of the plurality of first memory cells and the plurality of third memory cells connected to the second bit line and turned off when the read-on voltage is applied, and the third read voltage is greater than the fourth read voltage.

13. The memory storage device according to claim 11, characterized in that The multiple steps also include: storing the plurality of memory cell cutoff distributions corresponding to the plurality of bit lines in a buffer memory; and When reading the second physical unit, the plurality of memory cell cutoff distributions are read from the buffer memory to determine that the first bit line corresponds to the first read voltage and the second bit line corresponds to the second read voltage.

14. The memory storage device according to claim 8, characterized in that Wherein the second physical unit is different from the at least first physical unit.

15. A memory control circuit unit, characterized in that: Used to control a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units and a plurality of bit lines, and the memory control circuit unit includes: A host interface for coupling to a host system; A memory interface for coupling to the rewritable non-volatile memory module; A memory management circuit is coupled to the host interface and the memory interface, and is used to perform a plurality of steps: applying a read-on voltage to a plurality of first memory cells of at least a first physical cell among the plurality of physical cells to determine whether the plurality of first memory cells are turned on or off, wherein each of the plurality of first memory cells is connected to one of the plurality of bit lines; For each of the plurality of bit lines, calculating the number of memory cell turn-offs of the plurality of first memory cells connected to the bit line and turned off when the read-on voltage is applied, wherein the plurality of bit lines include a first bit line and a second bit line, and the number of memory cell turn-offs corresponding to the first bit line is different from the number of memory cell turn-offs corresponding to the second bit line; Setting a plurality of read voltages, wherein the plurality of read voltages include a first read voltage and a second read voltage, wherein the first read voltage is different from the second read voltage; When reading a second physical unit among the multiple physical units, the first read voltage is applied to a second storage unit in the second physical unit connected to the first bit line, and the second read voltage is applied to a second storage unit in the second physical unit connected to the second bit line, thereby obtaining multiple first data bits of the second physical unit.

16. The memory control circuit unit according to claim 15, characterized in that: The number of the memory cells turned off corresponding to the first bit line is greater than the number of the memory cells turned off corresponding to the second bit line, and the first read voltage is greater than the second read voltage.

17. The memory control circuit unit according to claim 15, characterized in that: The step of setting the plurality of read voltages comprises: The plurality of read voltages are set according to the plurality of memory cell cut-off numbers corresponding to the plurality of bit lines, wherein the plurality of memory cell cut-off numbers and the plurality of read voltages are positively correlated.

18. The memory control circuit unit according to claim 15, characterized in that: The multiple steps also include: determining whether the plurality of first data bits pass an error checking procedure; If the plurality of first data bits do not pass the error checking procedure, applying the read-on voltage to a plurality of third memory cells of a third physical cell among the plurality of physical cells to determine whether the plurality of third memory cells are turned on or off, wherein each of the plurality of third memory cells is connected to one of the plurality of bit lines; For each of the plurality of bit lines, calculating a memory cell turn-off distribution of the plurality of first memory cells and the plurality of third memory cells connected to the bit line and turned off when the read-on voltage is applied, wherein the memory cell turn-off distribution corresponding to the first bit line is different from the memory cell turn-off distribution corresponding to the second bit line; and A third read voltage among the multiple read voltages is applied to the second storage unit connected to the first bit line in the second physical unit, and a fourth read voltage among the multiple read voltages is applied to the second storage unit connected to the second bit line in the second physical unit, thereby reading multiple second data bits of the second physical unit.

19. The memory control circuit unit according to claim 18, characterized in that: Wherein the number of the plurality of first memory cells and the plurality of third memory cells connected to the first bit line and turned off when the read-on voltage is applied is greater than the number of the plurality of first memory cells and the plurality of third memory cells connected to the second bit line and turned off when the read-on voltage is applied, and the third read voltage is greater than the fourth read voltage.

20. The memory control circuit unit according to claim 18, wherein: The multiple steps also include: storing the plurality of memory cell cutoff distributions corresponding to the plurality of bit lines in a buffer memory; and When reading the second physical unit, the plurality of memory cell cutoff distributions are read from the buffer memory to determine that the first bit line corresponds to the first read voltage and the second bit line corresponds to the second read voltage.

21. The memory control circuit unit according to claim 15, characterized in that: Wherein the second physical unit is different from the at least first physical unit.

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