Reading method, memory storage device and memory control circuit unit

Abstract

The present application provides a reading method, a memory storage device and a memory control circuit unit. The reading method includes: applying a reading on voltage to a plurality of memory cells of a first physical unit; for each of a plurality of bit lines, calculating a number of memory cells connected to the bit line and turned off when the reading on voltage is applied; wherein the number of memory cells connected to a first bit line is different from the number of memory cells connected to a second bit line; setting a plurality of different reading voltages; when reading a second physical unit, applying a first reading voltage to memory cells connected to the first bit line in the second physical unit, and applying a second reading voltage to memory cells connected to the second bit line in the second physical unit, thereby obtaining a plurality of data bits of the second physical unit. Thus, the error of the data can be reduced.

Description

Technical Field

[0001] This disclosure relates to a method for reading a rewritable non-volatile memory module, a memory storage device, and a memory control circuit unit, which can solve the wear and tear problem of rewritable non-volatile memory modules. Background Technology

[0002] The rapid growth of portable electronic devices such as mobile phones and laptops in recent years has led to a surge in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are ideally suited for integration into the aforementioned portable electronic devices due to their non-volatile data, low power consumption, small size, and lack of mechanical structure.

[0003] On the other hand, with the development of artificial intelligence technology, the access frequency (especially the data write frequency) of rewritable non-volatile memory modules by processing circuits such as Central Processing Units (CPUs), Graphics Processing Units (GPUs), Video Processing Units (VPUs), Neural Network Processing Units (NPUs), and Tensor Processing Units (TPUs) has greatly increased, resulting in a significant increase in the wear and tear of rewritable non-volatile memory modules. Therefore, how to address the accelerated wear and tear of rewritable non-volatile memory modules caused by the large number of accesses performed on them during the computation of artificial intelligence models is one of the research topics that those skilled in the art are dedicated to studying. Summary of the Invention

[0004] This disclosure proposes a reading method, a memory storage device, and a memory control circuit unit, which can solve the problem of threshold voltage rise after physical unit loss.

[0005] This disclosure proposes a read method for a rewritable non-volatile memory module, the rewritable non-volatile memory module including multiple physical cells and multiple bit lines. The read method includes: applying a read-on voltage to multiple first memory cells of a first physical cell to determine whether the first memory cell is on or off, wherein each first memory cell is connected to a bit line; for each bit line, calculating the number of memory cells cut off when the first memory cell connected to this bit line is cut off when the read-on voltage is applied, wherein the number of memory cells cut off corresponding to the first bit line is different from the number of memory cells cut off corresponding to the second bit line; setting multiple read voltages, including a first read voltage and a second read voltage, the first read voltage being different from the second read voltage; when reading a second physical cell, applying the first read voltage to the second memory cell in the second physical cell connected to the first bit line, and applying the second read voltage to the second memory cell in the second physical cell connected to the second bit line, thereby obtaining multiple first data bits of the second physical cell.

[0006] In one embodiment of this disclosure, the number of memory cells cut off corresponding to the first bit line is greater than the number of memory cells cut off corresponding to the second bit line, and the first read voltage is greater than the second read voltage.

[0007] In one embodiment of this disclosure, the step of setting the read voltage includes: setting the read voltage according to the number of memory cells cut off corresponding to the bit line, wherein the number of memory cells cut off and the read voltage are positively correlated.

[0008] In one embodiment of this disclosure, the above-described reading method further includes: determining whether a first data bit passes an error checking procedure; if the first data bit fails the error checking procedure, applying a read-on voltage to a plurality of third storage cells of a third physical unit to determine whether the third storage cells are on or off, wherein each third storage cell is connected to a bit line; for each bit line, calculating a storage cell cutoff distribution of the first and third storage cells connected to the bit line and cut off when a read-on voltage is applied, wherein the storage cell cutoff distribution corresponding to the first bit line is different from the storage cell cutoff distribution corresponding to the second bit line; and applying a third read voltage to the second storage cell in the second physical unit connected to the first bit line, and applying a fourth read voltage to the second storage cell in the second physical unit connected to the second bit line, thereby reading a plurality of second data bits of the second physical unit.

[0009] In one embodiment of this disclosure, the number of first and third memory cells connected to the first bit line and turned off when a read-on voltage is applied is greater than the number of first and third memory cells connected to the second bit line and turned off when a read-on voltage is applied, and the third read voltage is greater than the fourth read voltage.

[0010] In one embodiment of this disclosure, the above-described reading method further includes: storing the cutoff distribution of the memory cells corresponding to the bit lines in a buffer memory; and when reading the second physical cell, reading the cutoff distribution of the memory cells from the buffer memory to determine that the first bit line corresponds to the first read voltage and the second bit line corresponds to the second read voltage.

[0011] In one embodiment of this disclosure, the second physical unit described above is different from at least the first physical unit.

[0012] From another perspective, embodiments of the present invention provide a memory storage device, comprising: a connection interface unit for coupling to a host system; a rewritable non-volatile memory module including multiple physical cells and multiple bit lines; and a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit performs multiple steps: applying a read-on voltage to multiple first memory cells of a first physical cell to determine whether the first memory cell is on or off, wherein each first memory cell is connected to a bit line; for each bit line, calculating the number of memory cells off when connected to that bit line and off when a read-on voltage is applied, wherein the number of memory cells off corresponding to the first bit line is different from the number of memory cells off corresponding to the second bit line; setting multiple read voltages, including a first read voltage and a second read voltage, the first read voltage being different from the second read voltage; when reading a second physical cell, applying the first read voltage to a second memory cell in the second physical cell connected to the first bit line, and applying the second read voltage to a second memory cell in the second physical cell connected to the second bit line, thereby obtaining multiple first data bits of the second physical cell.

[0013] From another perspective, embodiments of the present invention provide a memory control circuit unit for controlling a rewritable non-volatile memory module. The memory control circuit unit includes: a host interface for coupling to a host system; a memory interface for coupling to the rewritable non-volatile memory module; and a memory management circuit coupled to the host interface and the memory interface. The memory management circuit performs multiple steps: applying a read-on voltage to a plurality of first memory cells of a first physical unit to determine whether the first memory cells are on or off, wherein each first memory cell is connected to a bit line; for each bit line, calculating the number of memory cells off when connected to that bit line and turned off by the applied read-on voltage, wherein the number of memory cells off corresponding to the first bit line is different from the number of memory cells off corresponding to the second bit line; setting a plurality of read voltages, including a first read voltage and a second read voltage, the first read voltage being different from the second read voltage; when reading a second physical unit, applying the first read voltage to a second memory cell in the second physical unit connected to the first bit line, and applying the second read voltage to a second memory cell in the second physical unit connected to the second bit line, thereby obtaining a plurality of first data bits of the second physical unit.

[0014] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of a host system, memory storage device, and input / output (I / O) device according to an exemplary embodiment of the present invention;

[0016] Figure 2 This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0017] Figure 3 This is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0018] Figure 4A This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0019] Figure 4B This is a schematic diagram of a storage cell array according to an exemplary embodiment of the present invention;

[0020] Figure 5 This is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0021] Figure 6This is a schematic diagram illustrating the management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention;

[0022] Figure 7 This is a schematic diagram illustrating the reading of the conduction voltage according to one embodiment;

[0023] Figure 8 This is a flowchart illustrating a reading method according to one embodiment;

[0024] Figure 9 This is a schematic diagram illustrating the application of a read voltage according to one embodiment;

[0025] Figure 10 This is a schematic diagram illustrating the application of a read voltage according to one embodiment;

[0026] Figure 11 This is a schematic diagram illustrating the application of a read voltage according to one embodiment;

[0027] Figure 12 This is a flowchart illustrating a reading method according to another embodiment;

[0028] Figure 13 This is a schematic diagram illustrating the selection of a third physical unit according to one embodiment. Detailed Implementation

[0029] Some embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Component symbols used in the following description, when appearing in different drawings, are considered to be the same or similar components. These embodiments are only a part of the present invention and do not disclose all possible implementations of the invention. More precisely, these embodiments are merely examples of systems and methods within the scope of the claims of the present invention.

[0030] The terms "first," "second," etc., used in this article do not specifically refer to order or sequence; they are merely used to distinguish elements or operations described using the same technical terms.

[0031] Generally, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as control circuitry). The memory storage device can be used with a host system to enable the host system to write data to or read data from the memory storage device.

[0032] Figure 1 This is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0033] Please refer to Figure 1 and Figure 2 The host system 11 may include a processor 111, random access memory (RAM) 112, read-only memory (ROM) 113, and a data transfer interface 114. The processor 111, RAM 112, ROM 113, and data transfer interface 114 may be coupled to a system bus 110.

[0034] In one exemplary embodiment, the host system 11 can be coupled to the memory storage device 10 via a data transfer interface 114. For example, the host system 11 can store data to or read data from the memory storage device 10 via the data transfer interface 114. Furthermore, the host system 11 can be coupled to the I / O device 12 via a system bus 110. For example, the host system 11 can transmit output signals to or receive input signals from the I / O device 12 via the system bus 110.

[0035] In one exemplary embodiment, the processor 111, random access memory 112, read-only memory 113, and data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transfer interface 114, the motherboard 20 may be coupled to the memory storage device 10 via wired or wireless means.

[0036] In one exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid-state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a Wireless Local Area Network (WiFi) memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy (BLE) memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be coupled to various I / O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the system bus 110. For example, in one exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0037] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 may be any system that can substantially cooperate with a memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 may each include… Figure 3 The memory storage device 30 and the host system 31.

[0038] Figure 3 This is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention. Please refer to... Figure 3 The memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 can be a digital camera, camcorder, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly couple the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0039] Figure 4A This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Please refer to... Figure 4A The memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0040] The interface unit 41 is used to couple to the host system 11. The memory storage device 10 can communicate with the host system 11 via the interface unit 41. In one exemplary embodiment, the interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In one exemplary embodiment, the connection interface unit 41 may also conform to the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be packaged in a chip with the memory control circuit unit 42, or the connection interface unit 41 can be disposed outside a chip containing the memory control circuit unit 42.

[0041] The memory control circuit unit 42 is coupled to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform data writing, reading and erasing operations in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0042] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one cell), other flash memory modules, or other memory modules with the same characteristics.

[0043] Each memory cell in the rewritable nonvolatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, each memory cell has a charge trapping layer between its control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 43 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, thereby retrieving the one or more bits stored in that memory cell.

[0044] Figure 4B This is a schematic diagram of a storage cell array according to an exemplary embodiment of the present invention. Please refer to... Figure 4B The memory cell array 44 includes multiple memory cells 402 for storing data, multiple select gate-drain (SGD) transistors 412 and multiple select gate-source (SGS) transistors 414, multiple bit lines 404(1) to 404(3) connecting these memory cells 402, multiple word lines 406(1) to 406(N), and a common source line 408, where N is a positive integer. Specifically, the memory cells 402 are arranged in an array at the intersections of the bit lines 404(1) to 404(3) and the word lines 406(1) to 406(N), such as... Figure 4B As shown. Figure 4BThis is merely an example, and the present invention does not limit the number of word lines and bit lines in a single memory cell array 44. Furthermore, the rewritable non-volatile memory module 43 may include multiple memory cell arrays 44. These memory cell arrays 44 may be stacked horizontally and / or vertically.

[0045] In one example embodiment, the memory cells of the rewritable non-volatile memory module 43 can constitute multiple physical programming units, and these physical programming units can constitute multiple physical erase units. Specifically, memory cells on the same word line can form one or more physical programming units. If each memory cell can store more than two bits, then physical programming units on the same word line can be classified into lower physical programming units and upper physical programming units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally, in MLCNAND type flash memory, the write speed of the lower physical programming unit is greater than that of the upper physical programming unit, and / or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit.

[0046] In one example embodiment, a physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit of writing data. For example, a physical programming unit can be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units can include data bit areas and redundant bit areas. The data bit area contains multiple physical sectors for storing user data, while the redundant bit area is used to store system data (e.g., management data such as error correction codes). In one example embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other example embodiments, the data bit area may also contain 8, 16, or more or fewer physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, a physical erase unit is the smallest unit of erasure. That is, each physical erase unit contains one of the minimum number of memory units that are erased. For example, a physical erase unit is a physical block.

[0047] Figure 5 This is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Please refer to... Figure 5 The memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53.

[0048] The memory management circuit 51 controls the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has multiple control instructions, and these control instructions are executed when the memory storage device 10 is operating to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to describing the operation of the memory control circuit unit 42 and the memory storage device 10.

[0049] In one example embodiment, the control instructions for the memory management circuit 51 are implemented in firmware form. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0050] In one example embodiment, the control instructions of the memory management circuit 51 can also be stored in the form of program code in a specific area of ​​the rewritable non-volatile memory module 43 (e.g., a system area in the memory module dedicated to storing system data). Furthermore, the memory management circuit 51 includes a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). Specifically, this read-only memory has boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Subsequently, the microprocessor unit executes these control instructions to perform operations such as writing, reading, and erasing data.

[0051] In one example embodiment, the control instructions for the memory management circuit 51 can also be implemented in hardware. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, memory write circuit, memory read circuit, memory erase circuit, and data processing circuit are coupled to the microcontroller. The memory cell management circuit manages the memory cells or groups of memory cells in the rewritable non-volatile memory module 43. The memory write circuit issues a sequence of write instructions to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit issues a sequence of read instructions to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit issues a sequence of erase instructions to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuitry is used to process data to be written to and read from the rewritable non-volatile memory module 43. The write instruction sequence, read instruction sequence, and erase instruction sequence may each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an example embodiment, the memory management circuitry 51 may also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct it to perform corresponding operations.

[0052] The host interface 52 is coupled to the memory management circuitry 51. The memory management circuitry 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to acquire and identify instructions and data from the host system 11. For example, instructions and data from the host system 11 can be transmitted to the memory management circuitry 51 through the host interface 52. Furthermore, the memory management circuitry 51 can transmit data to the host system 11 through the host interface 52. In this example embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the invention is not limited thereto, and the host interface 52 may also be compatible with SATA, PATA, IEEE 1394, USB, SD, UHS-I, UHS-II, MS, MMC, eMMC, UFS, CF, IDE, or other suitable data transmission standards.

[0053] Memory interface 53 is coupled to memory management circuitry 51 and used to access rewritable non-volatile memory module 43. For example, memory management circuitry 51 can access rewritable non-volatile memory module 43 through memory interface 53. That is, data to be written to rewritable non-volatile memory module 43 is converted by memory interface 53 into a format acceptable to rewritable non-volatile memory module 43. Specifically, if memory management circuitry 51 needs to access rewritable non-volatile memory module 43, memory interface 53 transmits a corresponding sequence of instructions. For example, these sequence of instructions may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences indicating various memory operations (e.g., changing the read voltage level or performing garbage collection (GC) operations, etc.). These instruction sequences are generated by memory management circuitry 51 and transmitted to rewritable non-volatile memory module 43 through memory interface 53. These instruction sequences may include one or more signals or data on a bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as the read identification code and memory address.

[0054] In one example embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

[0055] Error checking and correction circuit 54 is coupled to memory management circuit 51 and is used to perform error checking and correction operations to ensure data integrity. Specifically, when memory management circuit 51 obtains a write command from host system 11, error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code to rewritable non-volatile memory module 43. Subsequently, when memory management circuit 51 reads data from rewritable non-volatile memory module 43, it simultaneously reads the corresponding error correcting code and / or error detecting code for this data, and error checking and correction circuit 54 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code. For example, the error checking and correction circuit 54 can use various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code to encode and decode data.

[0056] The buffer memory 55 is coupled to the memory management circuit 51 and is used to temporarily store data. The power management circuit 56 is coupled to the memory management circuit 51 and is used to control the power supply of the memory storage device 10.

[0057] In one example embodiment, Figure 4A The rewritable non-volatile memory module 43 may include a flash memory module. In one example embodiment, Figure 4A The memory control circuit unit 42 may include a flash memory controller. In one example embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0058] Figure 6 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Please refer to... Figure 6 The memory management circuit 51 can logically group the physical units 610(0) to 610(C) in the rewritable non-volatile memory module 43 into the storage area 601, the spare area 602 and the system area 603.

[0059] In one example embodiment, a physical unit refers to a physical address or a physical programming unit. In another example embodiment, a physical unit may also consist of multiple consecutive or non-consecutive physical addresses.

[0060] In one example embodiment, physical units 610(0) to 610(A) in storage area 601 are used to store user data (e.g., from...) Figure 1 The host system 11 contains user data. For example, physical units 610(0) to 610(A) in storage area 601 can store valid and invalid data. Physical units 610(A+1) to 610(B) in free area 602 do not store data (e.g., valid data). For example, if a physical unit does not store valid data, this physical unit can be associated (or added) to free area 602. In addition, physical units in free area 602 (or physical units that do not store valid data) can be erased. When new data is written, one or more physical units can be retrieved from free area 602 to store this new data. In an example embodiment, free area 602 is also referred to as a free pool.

[0061] In one example embodiment, memory management circuitry 51 may configure logic units 612(0) to 612(D) to map physical units 610(0) to 610(A) in memory area 601. In one example embodiment, each logic unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units. In one example embodiment, a logic unit may also correspond to a logical programming unit or consist of multiple consecutive or non-consecutive logical addresses.

[0062] It should be noted that a logical unit can be mapped to one or more physical units. If a physical unit is currently mapped to a logical unit, it means that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped to any logical unit, it means that the data currently stored in this physical unit is invalid data.

[0063] In one example embodiment, the memory management circuit 51 may record management data (also known as logic-to-physical mapping information) describing the mapping relationship between logical units and physical units in at least one logic-to-physical mapping table (L2Ptable). When the host system 11 wants to read data from or write data to the memory storage device 10, the memory management circuit 51 may access the rewritable non-volatile memory module 43 according to the information in this logic-to-physical mapping table.

[0064] In one example embodiment, the memory management circuit 51 can store specific types of data in the system area 603. For example, physical units 610(B+1) to 610(C) in the system area 603 can be dedicated to storing data of high importance and / or data that is not intended to be accessed or modified by the host system 11. For example, the data of high importance and / or data that is not intended to be accessed or modified by the host system 11 may include a logical-to-physical mapping table, a bad block management table, a wear leveling table, a valid data management table, and / or other types of management data, which are not limited by this invention. The logical-to-physical mapping table is used to record mapping information. This mapping information can reflect the mapping relationship between logical units and physical units. The bad block management table is used to record information related to at least one bad block in the rewritable non-volatile memory module 43. The wear leveling table can be used to record information related to the wear state of at least one physical unit in the rewritable non-volatile memory module 43 (e.g., read count, write count, and / or erase count). The valid data management table can be used to record information related to the valid count of at least one physical cell in the rewritable nonvolatile memory module 43.

[0065] In one example embodiment, the memory management circuitry 51 may not map any logical units to physical units in the system area 603. This prevents data stored in the system area 603 from being accessed or modified by the host system 11.

[0066] This section explains the read-on voltage, which is applied to other physical cells while reading one physical cell to enable the memory cells in those other physical cells. Figure 7 This is a schematic diagram illustrating the reading of the conduction voltage according to one embodiment. Please refer to... Figure 7When a physical cell on word line 406(5) needs to be read, the memory management circuit 51 applies a read voltage Vr to the memory cell connected to word line 406(5) and a read turn-on voltage Vp to the memory cells on other word lines 406(1) to 406(4) and 406(6) to 406(N). Generally, the memory cell should be turned on when the read turn-on voltage is applied, so multiple bits obtained from bit lines 404(1) to 404(3) will reflect whether the memory cell on word line 406(5) is turned on. For example, when a memory cell on word line 406(5) is turned on, a bit "1" can be obtained on the corresponding bit line, and vice versa. However, in some applications (such as artificial intelligence), the rewritable non-volatile memory module 43 is frequently read, written, or erased, which will increase the threshold voltage of the memory cell, even higher than the read turn-on voltage, which will affect the reading of the physical cell. For example, when the threshold voltage of one or more memory cells on word line 406(6) exceeds the read on voltage, these memory cells will be turned off, thus changing the bit obtained on the corresponding bit line. When the threshold voltage of a memory cell exceeds the read on voltage, this memory cell is called an open bit. In the following embodiments, the read voltage will be determined based on the number or distribution of open bits.

[0067] Figure 8 This is a flowchart illustrating a reading method according to one embodiment. This method is executed by the memory management circuit 51, and will not be described in detail below. Please refer to... Figure 8 In step 801, a read-on voltage is applied to multiple memory cells (also referred to as first memory cells) of the first physical unit to determine whether the first memory cell is on or off. Here, the first physical unit is not the physical unit to be read, but as mentioned above, whether there is a cutoff bit in other physical units will affect the physical unit to be read. The number of first physical units can be one or more; here, we will use one first physical unit as an example. Figure 9 This is a schematic diagram illustrating the application of a read voltage according to one embodiment. Figure 9In this embodiment, a read-on voltage Vp is applied to the first physical cell on word line 406(2), and the same or higher voltage can be applied to the memory cells on other word lines. When the voltage on word line 406(2) is lower than the voltage on other word lines, the memory cells on other word lines have a higher probability of being turned on. In this way, the presence or absence of each first memory cell on word line 406(2) can be determined based on the bits sensed on bit lines 404(1) to 404(3). When the voltage on word line 406(2) is the same as the voltage on other word lines, the presence or absence of a memory cell on the corresponding bit line can be determined based on the bits sensed on bit lines 404(1) to 404(3). This information also reflects the degree of degradation of this physical block and can be used to determine the read voltage.

[0068] In step 802, for each bit line, the number of first memory cells connected to this bit line and turned off when a read on voltage is applied is calculated (referred to as the memory cell cutoff number). Here, it is assumed that the first memory cells connected to bit line 404(1) and word line 406(2) are turned on when a read on voltage Vp is applied; the first memory cells connected to bit line 404(2) and word line 406(2) are turned off when a read on voltage Vp is applied; and the first memory cells connected to bit line 404(3) and word line 406(2) are turned on when a read on voltage Vp is applied. Therefore, the number of memory cells turned off corresponding to bit line 404(1) is 0, the number of memory cells turned off corresponding to bit line 404(2) is 1, and the number of memory cells turned off corresponding to bit line 404(3) is 0. In other words, the number of memory cells turned off corresponding to bit lines 404(1) and 404(3) is different from the number of memory cells turned off corresponding to bit line 404(2).

[0069] In step 803, multiple different read voltages are set. One of these read voltages can be the same as a preset read voltage, while the other can be greater than the preset read voltage. Here, these two read voltages are referred to as the first read voltage and the second read voltage, respectively.

[0070] In step 804, when reading the second physical unit (e.g., a physical unit on word line 406(5)), a first read voltage V1 is applied to the memory cell in the second physical unit connected to bit line 404(2), and a second read voltage V2 is applied to the memory cell in the second physical unit connected to bit lines 404(1) and 404(3), thereby obtaining multiple data bits of the second physical unit. The first read voltage V1 and the second read voltage V2 are applied to word line 406(5) at different times. For example, firstly, the first read voltage V1 is applied to word line 406(5), a read-on voltage is applied to other word lines, and one bit is obtained from bit line 404(2); next, the second read voltage V2 is applied to word line 406(5), a read-on voltage is applied to other word lines, and two bits are obtained from bit lines 404(1) and 404(3). The three bits obtained are the multiple data bits in the second physical unit.

[0071] In some embodiments, the number of memory cell cutoffs is positively correlated with the read voltage. For example, the number of memory cell cutoffs corresponding to bit line 404(2) is greater than the number of memory cell cutoffs corresponding to bit lines 404(1) and 404(3). Therefore, the first read voltage V1 can be set to be greater than the second read voltage V2.

[0072] As described above, the second physical cell on word line 406(5) is different from the first physical cell on word line 406(2). In other words, when reading a physical cell, the read voltage is determined based on the cutoff bits on other physical cells. In some embodiments, the position of the first physical cell can be predetermined. After the rewritable non-volatile memory module 43 is manufactured, any detection method can be used to determine which memory cells on word lines are prone to defects, and therefore the physical cells on these word lines will be set as the first physical cells described above. In some embodiments, different first physical cells can be set on different physical blocks or different dies, thereby reflecting different physical characteristics.

[0073] The number of the first physical units mentioned above is 1, but in other embodiments, the number of the first physical units can be greater than 1. For example, in... Figure 10First, a read turn-on voltage Vp is applied to the memory cells of the first physical cell on word lines 406(2) and 406(7) to determine whether these memory cells are on or off. Then, for each bit line, the number of memory cells connected to this bit line and turned off when the read turn-on voltage Vp is applied is calculated (called the memory cell turn-off number). The possible values ​​of the memory cell turn-off number include 0, 1, and 2, and different memory cell turn-off numbers correspond to different read voltages. In some embodiments, the read voltage can be set according to the memory cell turn-off number, such that the memory cell turn-off number and the read voltage are positively correlated. For example, a first read voltage is used when the memory cell turn-off number is equal to 2; a second read voltage is used when the memory cell turn-off number is equal to 1; and a third read voltage is used when the memory cell turn-off number is equal to 0, wherein the first read voltage is greater than the second read voltage, and the second read voltage is greater than the third read voltage.

[0074] In some embodiments, if the number of memory cell cutoffs on two bit lines is the same but the positions of the cutoff bits are different, different read voltages can also be used. For example, please refer to... Figure 11 When a read-on voltage is applied to word lines 406(2) and 406(7), the memory cells connected to word line 406(2) and bit line 404(1) are turned off, the memory cells connected to word line 406(2) and bit line 404(2) are turned on, the memory cells connected to word line 406(2) and bit line 404(3) are turned on, the memory cells connected to word line 406(7) and bit line 404(1) are turned on, the memory cells connected to word line 406(7) and bit line 404(2) are turned on, and the memory cells connected to word line 406(7) and bit line 404(3) are turned off. In this example, the number of memory cells turned off on bit line 404(1) and bit line 404(3) is 1, but the cutoff bit on bit line 404(1) occurs on word line 406(2), while the cutoff bit on bit line 404(3) occurs on word line 406(7). Multiple groups can be generated based on the distribution of cutoff bits on a bit line. Each bit line belongs to one of these groups, and this distribution can be represented by multiple bits, each indicating whether there is a cutoff bit on the corresponding word line. When a read-on voltage is applied to one word line, there are two groups (cutoff or on). Applying a read-on voltage to two word lines generates four groups, applying a read-on voltage to three word lines generates eight groups, applying a read-on voltage to four word lines generates sixteen groups, and so on. For example, in... Figure 11 In the embodiments, the four groups can be represented as shown in Table 1 below.

[0075] Word line 406(2) Word line 406(7) First group 1 1 Second group 1 0 Third group 0 1 Fourth group 0 0

[0076] Table 1

[0077] In Table 1, "1" indicates that the corresponding memory cell is a cutoff bit, and "0" indicates a non-cutoff bit. Specifically, bit line 404(1) belongs to the second group, bit line 404(2) belongs to the fourth group, and bit line 404(3) belongs to the third group. The first to fourth groups mentioned above correspond to the first read voltage V1 to the fourth read voltage V4, respectively. Therefore, when reading the physical cell on word line 406(5), the second read voltage V2, the fourth read voltage V4, and the third read voltage V3 can be applied to word line 406(5) at different time points to read data bits from the memory cells connected to bit lines 404(1) to 404(3), respectively. It is worth noting that in Figure 11 The diagram shows the application of first to fourth read voltages V1 to V4 to word line 406 (5). This is because the actual number of bit lines is much greater than 3, and therefore some bit lines will belong to the first group (using the first read voltage V1).

[0078] Figure 12 This is a flowchart illustrating a reading method according to another embodiment. Figure 12 In the embodiments, the number of word lines to which the read turn-on voltage is applied gradually increases. In step 1201, the read turn-on voltage is applied to a plurality of first memory cells of the first physical unit to determine whether the first memory cell is turned on or off. This step 1201 is the same as step 801.

[0079] In step 1202, for each bit line, the distribution of memory cells connected to this bit line and cut off when a read-on voltage is applied is calculated (referred to as the memory cell cutoff distribution). Here, the memory cell cutoff distribution may include the location information of each cutoff bit (see Table 1). When the number of the first physical cells is M, there are 2^M different memory cell cutoff distributions, where M is a positive integer.

[0080] In step 1203, multiple different read voltages are set. For example, a different read voltage can be set for each type of memory cell cutoff distribution.

[0081] In step 1204, when reading the second physical cell, different read voltages are applied to different memory cell cutoff distributions to obtain data bits from the corresponding bit lines. For example, in Figure 11 In the embodiment, the cutoff distribution of the memory cells of bit lines 404(1) to 404(3) are different from each other, so three different read voltages are applied to word line 406(5).

[0082] In step 1205, it is determined whether the acquired data bits (also referred to as the first data bits) have passed an error checking procedure, such as determining whether these first data bits can be completely corrected based on the error correction code. If the error checking procedure has not passed, in step 1206, another physical unit (referred to as the third physical unit) is selected, and then a read-on voltage is applied to the third physical unit to determine whether the memory cells in the third physical unit are turned on or off. Figure 13 This is a schematic diagram illustrating the selection of a third physical unit according to one embodiment. Figure 13 It is a continuation Figure 11 In this embodiment, it is assumed that word line 406 (8) is additionally selected. After applying the read turn-on voltage Vp to the third physical cell on word line 406 (8), the memory cell connected to bit line 404 (1) is turned on, the memory cell connected to bit line 404 (2) is turned off, and the memory cell connected to bit line 404 (3) is turned off.

[0083] Next, we return to step 1202 and recalculate the memory cell cutoff distribution. This time, we calculate not only the memory cells of word lines 406(2) and 406(7), but also the memory cells of word line 406(8). Since there are currently three word lines with the read on voltage Vp applied, there are a total of 8 memory cell cutoff distributions (i.e., 8 groups), which can be represented as shown in Table 2 below.

[0084] Word line 406(2) Word line 406(7) Word line 406(8) First group 1 1 1 Second group 1 1 0 Third group 1 0 1 Fourth group 1 0 0 Fifth group 0 1 1 Sixth group 0 1 0 Seventh group 0 0 1 Eighth group 0 0 0

[0085] Table 2

[0086] Similarly, in Table 2, "1" indicates that the corresponding storage unit is a cutoff bit, and "0" indicates a non-cutoff bit. Figure 13 In the example, bit line 404(1) belongs to the fourth group, bit line 404(2) belongs to the seventh group, and bit line 404(3) belongs to the fifth group. In other words, the memory cell cutoff distributions of bit lines 404(1) to 404(3) are different from each other.

[0087] In step 1203, multiple read voltages are set. After adding a word line, eight different read voltages can be set, corresponding to the eight groups mentioned above. These eight read voltages can be determined experimentally. Assume that the first to eighth groups correspond to the first to eighth read voltages, respectively. In some embodiments, when the number of cutoff bits in a group is larger, the corresponding read voltage is also larger. For example, if the first group has three cutoff bits, the second group has two cutoff bits, and the fourth group has one cutoff bit, then the first read voltage will be greater than the second read voltage, and the second read voltage will be greater than the fourth read voltage.

[0088] In step 1204, when reading the second physical cell on word line 406(5) again, different read voltages are applied to different memory cell cutoff distributions to obtain data bits from the corresponding bit lines. In this example, a fourth read voltage can be applied to word line 406(5) first to obtain a data bit from bit line 404(1), then a fifth read voltage can be applied to word line 406(5) to obtain a data bit from bit line 404(3), and then a seventh read voltage can be applied to word line 406(5) to obtain a data bit from bit line 404(2).

[0089] The three data bits obtained above will then be evaluated in step 1205. If they still fail the error checking procedure, another physical unit will be selected in step 1206. This approach can gradually increase decoding capability and avoid reading too many times at the beginning, thus avoiding excessive time or computational resources.

[0090] Please refer to Figure 5 In some embodiments, the memory management circuit 51 can pre-apply a read on voltage to multiple physical cells (e.g., during idle time). After calculating the number or distribution of memory cell cutoffs for each bit line, it can store these cutoff numbers or distributions in the buffer memory 55. When a physical cell needs to be read, the memory management circuit 51 can read the number or distribution of memory cell cutoffs from the buffer memory 55, thereby determining which read voltage to apply to which bit line's memory cell. This increases the read speed.

[0091] In the above embodiment, the read voltage is determined based on the cutoff bits on the first physical unit when reading the second physical unit. In other embodiments, the initial read voltage of the second physical unit can also be determined based on the number of cutoff bits on the second physical unit. Generally, the larger the number of cutoff bits on the second physical unit, the larger the initial read voltage. Here, the number of cutoff bits can be converted into the read voltage using a function or a lookup table.

[0092] In some embodiments, the above Figure 8 as well as Figure 12The process only proceeds after a general read procedure fails. For example, a read procedure might include both hardware and software decoding. In the hardware decoding procedure, a read voltage (i.e., the initial read voltage) is set. Data bits are obtained based on whether the corresponding memory cell is conducting under this read voltage. Next, an error correction code decoding procedure is applied to these data bits to correct the erroneous bits. If the number of erroneous bits exceeds the correction capability of the error correction code, the hardware decoding procedure fails. When the hardware decoding procedure fails, a software decoding procedure is performed. In the software decoding procedure, multiple read voltages are set. A probability value is calculated based on whether the corresponding memory cell is conducting under these read voltages. Next, an error correction code (e.g., LDPC) decoding procedure is applied to these probability values ​​to obtain the final data bits. If these data bits cannot be completely corrected, the software decoding procedure fails. When the software decoding procedure fails, a further process is performed. Figure 8 Or Figure 12 The process is as follows. In one embodiment, the software decoding program still has 214 error bits, but when 16 groups are set to adjust the read voltage, the number of error bits is reduced to 131. That is to say, the above approach can reduce the number of error bits.

[0093] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended claims.

Claims

1. A reading method, characterized in that, A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple physical cells and multiple bit lines, and the read method includes: A read-on voltage is applied to a plurality of first memory cells of at least a first physical cell of the plurality of physical cells to determine whether the plurality of first memory cells are on or off, wherein each of the plurality of first memory cells is connected to one of the plurality of bit lines; For each of the plurality of bit lines, calculate the number of memory cells cut off for the plurality of first memory cells connected to the bit line and cut off when the read-on voltage is applied, wherein the plurality of bit lines include a first bit line and a second bit line, and the number of memory cells cut off corresponding to the first bit line is different from the number of memory cells cut off corresponding to the second bit line. Multiple read voltages are set, wherein the multiple read voltages include a first read voltage and a second read voltage, and the first read voltage is different from the second read voltage; When reading the second physical unit among the plurality of physical units, the first read voltage is applied to the second storage unit in the second physical unit that is connected to the first bit line, and the second read voltage is applied to the second storage unit in the second physical unit that is connected to the second bit line, thereby obtaining a plurality of first data bits of the second physical unit.

2. The reading method according to claim 1, characterized in that, The number of memory cells cutoff corresponding to the first bit line is greater than the number of memory cells cutoff corresponding to the second bit line, and the first read voltage is greater than the second read voltage.

3. The reading method according to claim 1, characterized in that, The step of setting the plurality of reading voltages includes: The plurality of read voltages are set according to the plurality of cutoff numbers of the plurality of memory cells corresponding to the plurality of bit lines, wherein the plurality of cutoff numbers of the plurality of memory cells and the plurality of read voltages are positively correlated.

4. The reading method according to claim 1, characterized in that, Also includes: Determine whether the plurality of first data bits pass the error checking procedure; If the plurality of first data bits fail the error checking procedure, the read-on voltage is applied to the plurality of third storage cells of the third physical unit in the plurality of physical units to determine whether the plurality of third storage cells are turned on or off, wherein each of the plurality of third storage cells is connected to one of the plurality of bit lines; For each of the plurality of bit lines, calculate the memory cell cutoff distribution of the plurality of first memory cells and the plurality of third memory cells that are connected to the bit line and cut off when the read on voltage is applied, wherein the memory cell cutoff distribution corresponding to the first bit line is different from the memory cell cutoff distribution corresponding to the second bit line. as well as A third read voltage from the plurality of read voltages is applied to the second storage cell in the second physical unit that is connected to the first bit line, and a fourth read voltage from the plurality of read voltages is applied to the second storage cell in the second physical unit that is connected to the second bit line, thereby reading a plurality of second data bits from the second physical unit.

5. The reading method according to claim 4, characterized in that, The number of the plurality of first memory cells and the plurality of third memory cells connected to the first bit line and turned off when the read on voltage is applied is greater than the number of the plurality of first memory cells and the plurality of third memory cells connected to the second bit line and turned off when the read on voltage is applied, and the third read voltage is greater than the fourth read voltage.

6. The reading method according to claim 4, characterized in that, Also includes: The multiple storage cells corresponding to the multiple bit lines are distributed and stored in the buffer memory. as well as When reading the second physical unit, the cutoff distribution of a plurality of the memory cells is read from the buffer memory to determine that the first bit line corresponds to the first read voltage and the second bit line corresponds to the second read voltage.

7. The reading method according to claim 1, characterized in that, The second physical unit is different from the at least first physical unit.

8. A memory storage device, characterized in that, include: A connection interface unit for coupling to the host system; A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple physical cells and multiple bit lines; as well as A memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module, is used to perform multiple steps: A read-on voltage is applied to a plurality of first memory cells of at least a first physical cell of the plurality of physical cells to determine whether the plurality of first memory cells are on or off, wherein each of the plurality of first memory cells is connected to one of the plurality of bit lines; For each of the plurality of bit lines, calculate the number of memory cells cut off for the plurality of first memory cells connected to the bit line and cut off when the read-on voltage is applied, wherein the plurality of bit lines include a first bit line and a second bit line, and the number of memory cells cut off corresponding to the first bit line is different from the number of memory cells cut off corresponding to the second bit line. Multiple read voltages are set, wherein the multiple read voltages include a first read voltage and a second read voltage, and the first read voltage is different from the second read voltage; When reading the second physical unit among the plurality of physical units, the first read voltage is applied to the second storage unit in the second physical unit that is connected to the first bit line, and the second read voltage is applied to the second storage unit in the second physical unit that is connected to the second bit line, thereby obtaining a plurality of first data bits of the second physical unit.

9. The memory storage device according to claim 8, characterized in that, The number of memory cells cutoff corresponding to the first bit line is greater than the number of memory cells cutoff corresponding to the second bit line, and the first read voltage is greater than the second read voltage.

10. The memory storage device according to claim 8, characterized in that, The step of setting the plurality of reading voltages includes: The plurality of read voltages are set according to the plurality of cutoff numbers of the plurality of memory cells corresponding to the plurality of bit lines, wherein the plurality of cutoff numbers of the plurality of memory cells and the plurality of read voltages are positively correlated.

11. The memory storage device according to claim 8, characterized in that, The plurality of steps further include: Determine whether the plurality of first data bits pass the error checking procedure; If the plurality of first data bits fail the error checking procedure, the read-on voltage is applied to the plurality of third storage cells of the third physical unit in the plurality of physical units to determine whether the plurality of third storage cells are turned on or off, wherein each of the plurality of third storage cells is connected to one of the plurality of bit lines; For each of the plurality of bit lines, calculate the cell cutoff distribution of the plurality of first memory cells and the plurality of third memory cells connected to the bit line and cut off when the read-on voltage is applied, wherein the cell cutoff distribution corresponding to the first bit line is different from the cell cutoff distribution corresponding to the second bit line; and A third read voltage from the plurality of read voltages is applied to the second storage cell in the second physical unit that is connected to the first bit line, and a fourth read voltage from the plurality of read voltages is applied to the second storage cell in the second physical unit that is connected to the second bit line, thereby reading a plurality of second data bits from the second physical unit.

12. The memory storage device according to claim 11, characterized in that, The number of the plurality of first memory cells and the plurality of third memory cells connected to the first bit line and turned off when the read on voltage is applied is greater than the number of the plurality of first memory cells and the plurality of third memory cells connected to the second bit line and turned off when the read on voltage is applied, and the third read voltage is greater than the fourth read voltage.

13. The memory storage device according to claim 11, characterized in that, The plurality of steps further include: The multiple storage cells corresponding to the multiple bit lines are distributed and stored in a buffer memory; and When reading the second physical unit, the cutoff distribution of a plurality of the memory cells is read from the buffer memory to determine that the first bit line corresponds to the first read voltage and the second bit line corresponds to the second read voltage.

14. The memory storage device according to claim 8, characterized in that, The second physical unit is different from the at least first physical unit.

15. A memory control circuit unit, characterized in that, This is used to control a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple physical units and multiple bit lines, and the memory control circuit unit includes: Host interface, used to couple to the host system; A memory interface for coupling to the rewritable non-volatile memory module; A memory management circuit, coupled to the host interface and the memory interface, is used to perform multiple steps: A read-on voltage is applied to a plurality of first memory cells of at least a first physical cell of the plurality of physical cells to determine whether the plurality of first memory cells are on or off, wherein each of the plurality of first memory cells is connected to one of the plurality of bit lines; For each of the plurality of bit lines, calculate the number of memory cells cut off for the plurality of first memory cells connected to the bit line and cut off when the read-on voltage is applied, wherein the plurality of bit lines include a first bit line and a second bit line, and the number of memory cells cut off corresponding to the first bit line is different from the number of memory cells cut off corresponding to the second bit line. Multiple read voltages are set, wherein the multiple read voltages include a first read voltage and a second read voltage, and the first read voltage is different from the second read voltage; When reading the second physical unit among the plurality of physical units, the first read voltage is applied to the second storage unit in the second physical unit that is connected to the first bit line, and the second read voltage is applied to the second storage unit in the second physical unit that is connected to the second bit line, thereby obtaining a plurality of first data bits of the second physical unit.

16. The memory control circuit unit according to claim 15, characterized in that, The number of memory cells cutoff corresponding to the first bit line is greater than the number of memory cells cutoff corresponding to the second bit line, and the first read voltage is greater than the second read voltage.

17. The memory control circuit unit according to claim 15, characterized in that, The step of setting the plurality of reading voltages includes: The plurality of read voltages are set according to the plurality of cutoff numbers of the plurality of memory cells corresponding to the plurality of bit lines, wherein the plurality of cutoff numbers of the plurality of memory cells and the plurality of read voltages are positively correlated.

18. The memory control circuit unit according to claim 15, characterized in that, The plurality of steps further include: Determine whether the plurality of first data bits pass the error checking procedure; If the plurality of first data bits fail the error checking procedure, the read-on voltage is applied to the plurality of third storage cells of the third physical unit in the plurality of physical units to determine whether the plurality of third storage cells are turned on or off, wherein each of the plurality of third storage cells is connected to one of the plurality of bit lines; For each of the plurality of bit lines, calculate the cell cutoff distribution of the plurality of first memory cells and the plurality of third memory cells connected to the bit line and cut off when the read-on voltage is applied, wherein the cell cutoff distribution corresponding to the first bit line is different from the cell cutoff distribution corresponding to the second bit line; and A third read voltage from the plurality of read voltages is applied to the second storage cell in the second physical unit that is connected to the first bit line, and a fourth read voltage from the plurality of read voltages is applied to the second storage cell in the second physical unit that is connected to the second bit line, thereby reading a plurality of second data bits from the second physical unit.

19. The memory control circuit unit according to claim 18, characterized in that, The number of the plurality of first memory cells and the plurality of third memory cells connected to the first bit line and turned off when the read on voltage is applied is greater than the number of the plurality of first memory cells and the plurality of third memory cells connected to the second bit line and turned off when the read on voltage is applied, and the third read voltage is greater than the fourth read voltage.

20. The memory control circuit unit according to claim 18, characterized in that, The plurality of steps further include: The multiple storage cells corresponding to the multiple bit lines are distributed and stored in a buffer memory; and When reading the second physical unit, the cutoff distribution of a plurality of the memory cells is read from the buffer memory to determine that the first bit line corresponds to the first read voltage and the second bit line corresponds to the second read voltage.

21. The memory control circuit unit according to claim 15, characterized in that, The second physical unit is different from the at least first physical unit.

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