A control method for a storage device, a storage device, and a computer storage medium

Abstract

The present invention provides a control method for a storage device, a storage device, and a computer storage medium. The method includes using the data read out at an initial threshold voltage as original data; symmetrically offsetting the initial threshold voltage centered on the initial threshold voltage, and then re-reading the data as bias voltage data; logically processing the mutually symmetric bias voltage data to obtain decision data; combining the original data and the decision data to obtain a partition array, and obtaining the credibility of the partition array through a look-up table, where the credibility is positively correlated with the accuracy of the decision data; preferentially trusting the decision data with high credibility and decoding the decision data; simultaneously with the start of the decoding process, increasing the number of times of symmetrically offsetting the initial threshold voltage and re-reading the data as the bias voltage data for the next round; and looping through the steps of obtaining the decision data, obtaining the credibility, and the decoding process until the decoding is successful or the number of times of symmetric offsetting reaches the offset times threshold.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a control method for a storage device, a storage device, and a computer storage medium. Background Art

[0002] Low-density parity check (LDPC) is widely used in communication systems due to its high coding efficiency and excellent error correction capabilities. By selecting an appropriate decoding algorithm, such as belief propagation or the minimum-sum algorithm, the original stored information can be effectively recovered. Even in the presence of noise, LDPC maintains high error correction capabilities. Therefore, LDPC codes are often used for error checking and correction in flash-based storage devices.

[0003] In flash-based storage devices, LDPC codes are used in the soft decoding process. The more bits of soft information used in the soft decoding, the stronger the error correction capability. However, the more complex the probability combinations that need to be processed, the longer the decoding latency. Therefore, balancing decoding capability and latency directly impacts the storage reliability and performance of the storage device. Summary of the Invention

[0004] The purpose of the present invention is to provide a control method for a storage device, a storage device, and a computer storage medium, which can improve the efficiency of soft decoding during data rereading, balance the decoding delay and decoding capability of the storage device, thereby improving the data storage reliability of the storage device and improving the performance of the storage device.

[0005] To solve the above technical problems, the present invention is achieved through the following technical solutions:

[0006] The present invention provides a method for controlling a storage device, comprising the following steps:

[0007] The data read out at the initial threshold voltage is taken as the original data;

[0008] Taking the initial threshold voltage as the center, symmetrically shifting the initial threshold voltage, and re-reading data as bias data;

[0009] logically processing the mutually symmetrical bias data to obtain decision data;

[0010] Combining the original data and the decision data to obtain a partition array, and obtaining the credibility of the partition array through a lookup table, wherein the credibility is positively correlated with the accuracy of the decision data;

[0011] Prioritizing the decision data with high credibility, and decoding and processing the decision data;

[0012] Simultaneously with the start of the decoding process, increase the number of times of symmetrically offsetting the initial threshold voltage, and reread the data as the bias data for the next round; and

[0013] Loop through the steps of obtaining the decision data, obtaining the confidence level, and the decoding process until the decoding is successful or the number of times of symmetric offsetting reaches the offset number threshold.

[0014] In an embodiment of the present invention, the step of obtaining the bias data includes:

[0015] Set the bias amplitude and the number of quantization bits; and

[0016] Perform left-offset processing and right-offset processing on the initial threshold voltage respectively, and obtain the left-offset voltage and the right-offset voltage, where the voltage offset amplitude of the left-offset processing and the right-offset processing is the bias amplitude or an integer multiple of the bias amplitude, and the number of the left-offset voltage and the right-offset voltage is equal to the current number of quantization bits; and

[0017] Read the data at the left-offset voltage and the right-offset voltage respectively to obtain the left-offset data and the right-offset data, where the left-offset voltage and the right-offset voltage are symmetric about the initial threshold voltage.

[0018] In an embodiment of the present invention, in the step of obtaining the decision data, perform exclusive-OR processing on the mutually symmetric left-offset data and right-offset data to obtain the decision data.

[0019] In an embodiment of the present invention, in the step of offsetting the initial threshold voltage, as the number of rounds of obtaining the bias data increases, the number of quantization bits increases arithmetically, and the number of the bias data has a linear relationship or an exponential relationship with the number of quantization bits.

[0020] In an embodiment of the present invention, in the step of offsetting the initial threshold voltage, the voltage difference between adjacent left-offset voltages is the bias amplitude, and the voltage difference between adjacent right-offset voltages is the bias amplitude.

[0021] In an embodiment of the present invention, in the step of offsetting the initial threshold voltage, when offsetting the initial threshold voltage in the next round, use the bias data obtained at the same threshold voltage in this round or reread the new bias data at the offset threshold voltage.

[0022] In an embodiment of the present invention, when the step of the decoding process fails, obtain the decision data and the confidence level according to the bias data of the next round, and start a parallel process of the step of the decoding process and reading the bias data of the next round until the decoding process obtains a result.

[0023] In an embodiment of the present invention, when the step of decoding processing is successful, the decoded successful data is used as the read data, all invalid data in the decoding process is deleted, and the read process ends.

[0024] The present invention provides a computer storage medium, in which computer instructions are stored, and when the computer instructions are executed by a processor, the steps of the control method of the storage device described in any one of the above are implemented.

[0025] The present invention provides a storage device, including:

[0026] A flash memory chip;

[0027] A read module, configured to read data from the flash memory chip at a set threshold voltage, where the data read at the initial threshold voltage is the original data;

[0028] A bias module, configured to symmetrically offset the initial threshold voltage centered on the initial threshold voltage, and the data read at the offset threshold voltage is the bias data;

[0029] A decision module, configured to logically process the symmetric bias data to obtain decision data;

[0030] A confidence module, configured to combine the original data and the decision data to obtain a partition array, and obtain the credibility of the partition array through a look-up table, where the credibility is positively correlated with the accuracy of the decision data;

[0031] A decoding module, configured to preferentially trust the decision data with high credibility and decode the decision data;

[0032] A timing control module, configured to control the start timing of all processes in the storage device. When the decoding process starts, the timing control module outputs a trigger signal to increase the number of times of symmetrically offsetting the initial threshold voltage and start the next round of the step of obtaining the bias data; and

[0033] A loop control module, configured to loop through the steps of obtaining the decision data, obtaining the credibility, and the decoding process until the decoding is successful or the number of times of symmetric offsetting reaches the offset times threshold.

[0034] As described above, the present invention provides a control method for a storage device, a storage device, and a computer storage medium, which can dynamically adjust the threshold voltage and improve the reliability of data storage. Moreover, based on a credibility-driven parallel decoding mechanism, the present invention utilizes the acquisition of decision data in multiple rounds, so as to be able to balance the control of the occupation of storage resources while improving the data decoding efficiency. The present invention preferentially decodes high-credibility data, which can accelerate the error correction process. The decoding process is executed in parallel with the reading of the next-round bias data, reducing the overall latency and improving the reading efficiency, and supports the reuse of historical bias data or the dynamic generation of new data to balance the computational overhead and precision requirements. The present invention supports modular design and algorithm design, enabling flexible adaptation to different flash memory chips, and the algorithm can be deployed through a computer storage medium, facilitating firmware upgrade. The storage device provided by the present invention is applicable to high-density flash memory applications such as MLC / TLC / QLC, alleviates the threshold voltage interference problem caused by the increase in the number of write operations, and can meet the requirements of high-speed data access and low-power design.

[0035] Of course, it is not necessary for any product implementing the present invention to simultaneously achieve all the above-mentioned advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0037] Figure 1 It is a flowchart of the control method for the storage device in an embodiment of the present invention.

[0038] Figure 2 It is a schematic flowchart of step S200 in an embodiment of the present invention.

[0039] Figure 3 It is a schematic diagram of voltage offset when the quantization bit number is 1 in an embodiment of the present invention.

[0040] Figure 4 It is a schematic diagram of voltage offset when the quantization bit number is 2 in an embodiment of the present invention.

[0041] Figure 5 It is a schematic flowchart of steps S500 to S700 in an embodiment of the present invention.

[0042] Figure 6 It is a schematic structural diagram of the storage device in an embodiment of the present invention.

[0043] Figure 7 It is a schematic structural diagram of the computer storage medium in an embodiment of the present invention.

[0044] In the figure: 10, main controller; 11, reading module; 12, bias module; 13, decision module; 14, confidence module; 15, decoding module; 16, timing control module; 17, loop control module; 20, flash chip; 30, processor; 40, computer storage medium; 41, computer instruction. Specific embodiments

[0045] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0046] Please refer to Figure 1 、 Figure 6 and Figure 7 As shown, the present invention provides a control method for a storage device, a storage device, and a computer storage medium 40. The storage is an embedded storage device, such as an embedded MultiMedia Card (eMMC), a Universal Flash Storage (UFS), etc. In the present invention, the storage medium for storing user data in the storage device is the flash chip 20, and specifically, it is a NAND flash. The storage device includes a processor 30 and a flash chip 20, and the processor 30 and the flash chip 20 are electrically connected. The processor 30 can implement the control method for the storage device provided by the present invention by executing computer instructions, so as to control the reading process of the flash chip 20. In the present invention, the computer storage medium 40 is a memory for storing control firmware, such as a Read-Only Memory (ROM). In another embodiment of the present invention, the processor 30 can also implement the control method for the storage device provided by the present invention in the form of component function modules and functional circuits. In this embodiment, the processor 30 is, for example, an ARM processor 30.

[0047] Please refer to Figure 1 As shown, the control method for the storage device provided by the present invention includes steps S100 to S700.

[0048] Step S100: Use the data read at the initial threshold voltage as the original data.

[0049] Step S200: Symmetrically offset the initial threshold voltage with the initial threshold voltage as the center, and then read the data again as the bias data.

[0050] Step S300: Logically process the bias data that is symmetric to each other to obtain decision data.

[0051] Step S400: Combine the original data and the decision data to obtain a partition array, and obtain the credibility of the partition array through a look-up table, where the credibility is positively correlated with the accuracy of the decision data.

[0052] Step S500: Prioritize the decision data with high confidence credibility and decode the decision data.

[0053] Step S600: While starting the decoding process, increase the number of times of raising the initial threshold voltage of the symmetric offset, and re-read the data as the bias data for the next round.

[0054] Step S700: Loop through the steps of obtaining decision data, obtaining credibility, and the decoding process until the decoding is successful or the number of times of symmetric offset reaches the offset times threshold.

[0055] Please refer to Figure 1 As shown, in the present invention, when obtaining data from the flash memory chip 20, it involves the data reading process and the error correction process. In this embodiment, the decoding method used in the error correction process can be a Low Density Parity Check Code (LDPC). In the data reading process, data is read out according to the default or set threshold voltage. When the data reading fails, the data can be re-read. In this embodiment, the initial threshold voltage can be the threshold voltage used when the data reading fails, or the default voltage preset when triggering the data re-reading or the optimal voltage obtained through training. The original data obtained in step S100 can be the data directly called by the hard decoding after the hard decoding fails, or the data re-read according to the initial threshold voltage. It should be noted that in an embodiment of the present invention, the initial threshold voltage is not changed after it is determined. If all decoding processes fail, it is determined that the data cannot be read out. In another embodiment of the present invention, when all decoding processes fail, the initial threshold voltage can be adjusted, and steps S100 to S700 are re-executed, and so on, until the decoding is successful or all available initial threshold voltages are traversed. The initial threshold voltage can be a value set in the voltmeter or a value obtained through training calculation.

[0056] Please refer to Figure 1 and Figure 2 As shown, in the present invention, in step S200, in the step of obtaining bias data in each round, the number of bias data is an even number. And the step of obtaining bias data includes steps S210 to S230.

[0057] Step S210: Set the bias amplitude and the quantization number of bits.

[0058] Step S220: Perform left-offset processing and right-offset processing on the initial threshold voltage respectively, and obtain the left-offset voltage and the right-offset voltage, where the voltage offset amplitudes of the left-offset processing and the right-offset processing are the bias voltage amplitude or an integer multiple of the bias voltage amplitude, and the number of the left-offset voltage and the right-offset voltage is equal to the current quantization bit number.

[0059] Step S230: Read data at the left-offset voltage and the right-offset voltage respectively to obtain the left-offset data and the right-offset data, where the left-offset voltage and the right-offset voltage are symmetric about the initial threshold voltage.

[0060] Please refer to Figures 1 to 3 As shown, in an embodiment of the present invention, in step S210, a bias voltage range is obtained. For example, using -1.28V to represent the logic level 1 and 1.27V to represent the logic level 0, then the bias voltage range is from -1.28V to 1.27V. As the storage device is used, the voltage ranges for determining the logic levels will overlap. As Figure 3 shown, the parabolic curve is used to represent the numerical curve of the read voltage, and the area of the red straight line is used to indicate the range where the logic levels overlap. When the read voltage value is in the overlapping area, the read logic level may be regarded as 0 or 1. Therefore, the read data in this voltage overlapping area is inaccurate. As Figure 3 shown, Vth represents the initial threshold voltage. In this embodiment, a bias voltage number threshold is set to limit the number of bias voltages, where the bias voltage number threshold is an even number. One left bias voltage and one right bias voltage represent two bias voltage processes. In other embodiments of the present invention, the number of bias voltages can also be limited by a threshold voltage threshold. In an embodiment of the present invention, according to the bias voltage range and the bias voltage number threshold, the bias voltage range can be evenly divided into multiple levels, and the bias voltage amplitude is carried out according to the levels. For example, the bias voltage amplitude is set to 1 level. In another embodiment of the present invention, the bias voltage amplitude is set to, for example, 1~30mV, and specifically it can be 10mV. In this embodiment, the optimal bias voltage range can be set to, for example, 1~5mV.

[0061] Please refer to Figures 1 to 3As shown, in an embodiment of the present invention, in step S210, the quantization bit number is used to set the number of left bias voltages and right bias voltages acquired each time, and is used to limit the number of acquired bias voltage data. Among them, as the number of rounds of acquiring bias voltage data increases, the quantization bit number increases arithmetically. The initial quantization bit number is set to 1. While decoding the decision data obtained when the quantization bit number is 1, the quantization bit number is increased to 2, and the next round of bias voltage data is acquired according to the new quantization bit number, and so on. In this embodiment, the increment of the quantization bit number in each round is 1. In the present invention, the number of bias voltage data has a linear relationship or an exponential relationship with the quantization bit number. In this embodiment, the number of bias voltage data is twice the quantization bit number. For example, when the quantization bit number is 1, that is, the left bias voltage is applied once and the right bias voltage is applied once, 2 bias voltage data are obtained. For example, when the quantization bit number is 2, that is, the left bias voltage is applied twice and the right bias voltage is applied twice, 4 bias voltage data are obtained. In another embodiment of the present invention, the number of bias voltage data is calculated with 2 as the base and the quantization bit number as the exponent. For example, when the quantization bit number is 1, that is, the left bias voltage is applied once and the right bias voltage is applied once, 2 bias voltage data are obtained. When the quantization bit number is 3, that is, the left bias voltage is applied four times and the right bias voltage is applied four times, 8 bias voltage data are obtained. And so on.

[0062] Please refer to Figures 1 to 4As shown, in an embodiment of the present invention, in step S220, the initial threshold voltage is offset to the left by an offset amount equal to one or multiple times the bias voltage amplitude to obtain a left-biased voltage. In this embodiment, when the left-biased process is performed for the first time, the offset amount is one times the bias voltage amplitude. When the left-biased process is performed for the Nth time, the offset amount is N times the bias voltage amplitude. Similarly, the initial threshold voltage is offset to the right by an offset amount equal to one or multiple times the bias voltage amplitude to obtain a right-biased voltage. When the right-biased process is performed for the Nth time, the offset amount is N times the bias voltage amplitude. Here, N is an integer. The offset amount can be offset with reference to the initial threshold voltage. Therefore, for the cases of multiple left-biased processes and multiple right-biased processes, the voltage difference between adjacent left-biased voltages is the bias voltage amplitude, and the voltage difference between adjacent right-biased voltages is the bias voltage amplitude. In this embodiment, in the step of performing the bias voltage process for each round, the number of left-biased times and the number of right-biased times are equal, and the number of obtained left-biased voltages and right-biased voltages is equal to the current quantization bit number. In this embodiment, in the step of performing the bias voltage process for each round, the left-biased voltage and the right-biased voltage are symmetrically offset with respect to the initial threshold voltage. In step S230, data is read out respectively under the left-biased voltage and the right-biased voltage to obtain left-biased data and right-biased data. In the embodiment, when the quantization bit number is 1, for example, 1 left-biased data and 1 right-biased data are obtained. When the quantization bit number is 2, for example, 2 left-biased data and 2 right-biased data are obtained. When the quantization bit number is 3, for example, 3 left-biased data and 3 right-biased data are obtained, or 4 left-biased data and 4 right-biased data are obtained. It should be noted that in this embodiment, when the bias voltage amplitude remains unchanged and the quantization bit number is 2, one set of bias voltage data is the bias voltage data obtained when the quantization bit number is 1. Therefore, when the quantization bit number increases and the bias voltage amplitude remains unchanged, when obtaining the bias voltage data in the next round, the bias voltage data obtained under the same threshold voltage in this round can be directly used to save the readout time, or the data can be read out again under this threshold voltage as new bias voltage data to improve the accuracy of the readout data. By dynamically increasing the number of bias voltage times and adjusting the bias voltage amplitude in multiple rounds, the optimal threshold voltage is gradually approached to adapt to the voltage distribution changes caused by flash memory aging or environmental changes.

[0063] Please refer to Figures 1 to 4 As shown, in an embodiment of the present invention, it should be noted that for the overlapping region of the decision, such as the red broken line region, the left-biased voltage and the right-biased voltage can divide the decision overlapping region into multiple regions. Such as Figure 3 and Figure 4As shown, as the number of left-bias voltages and right-bias voltages increases, the number of parts into which the overlapping region is divided also increases, thereby dividing the overlapping region into finer parts. This allows for clearer judgment of each divided part, thereby determining the actual logic level value of the corresponding region. Therefore, in this embodiment, the bias voltage amplitude can be set to 1-5mV to subdivide the overlapping region as much as possible.

[0064] See also Figures 1 to 4 As shown, in one embodiment of the present invention, in step S300, the logic processing is, for example, an XOR processing. The objects of the XOR processing are mutually symmetrical left-biased data and right-biased data. For example, the left-biased data read under a left-biased voltage with a left offset of 10mV, and the right-biased data read under a right-biased voltage with a right offset of 10mV, these two data are mutually symmetrical bias data. After XOR processing the mutually symmetrical left-biased data and right-biased data, the data obtained is used as judgment data. By generating multiple sets of bias data with a symmetrical offset centered on the initial threshold voltage, and combining the logic processing to generate judgment data, the read errors caused by threshold voltage drift can be effectively identified, thereby improving data reliability.

[0065] See also Figures 1 to 4 As shown, in one embodiment of the present invention, in step S400, the partition array includes the original data and all the judgment data. It should be noted that for the data to be read, each bit corresponds to an original data and at least one judgment data, so each bit corresponds to a partition array. In the decoding process, each bit is decoded and judged. Figure 3 As shown in , when only one round of voltage is offset, there is only one set of judgment data, which can be distinguished without numbering. Figure 4 As shown, when there are two or more voltage offsets, each round of judgment data is distinguished by number or name. In the partition array, the first data point is the original data, the second data point is the judgment data from the first round, the third data point is the judgment data from the second round, and so on. The mth data point in the partition array is the judgment data from the m-1th round. In this embodiment, the corresponding reliability value of the partition array is found through a lookup table. In this embodiment, the higher the absolute value of the reliability point, the more accurate the judgment data.

[0066] See also Figures 1 to 4 As shown, in one embodiment of the present invention, in step S400, the method of obtaining the credibility can be to directly find the credibility value corresponding to the partition array by looking up the table, or to obtain the credibility value corresponding to the partition array by calculation. The credibility is the log-likelihood ratio (LLR). Figure 3As shown, when performing voltage offset in the first round, the obtained partition arrays are, for example, (1, 0), (1, 1), (0, 1), and (0, 0). The first data in them represents the original data, and the second data represents the decision data. The credibility values corresponding to the partition arrays are -7, -3, 3, and 7 respectively. To represent negative credibility values, add 16 to the negative credibility value. Therefore, a -7 credibility can also be represented as 0x9, and a -3 credibility can also be represented as 0xD. As Figure 4 shown, when performing voltage offset in the second round, the obtained partition arrays are, for example, (1, 0, 0), (1, 0, 1), (1, 1, 1), (0, 1, 1), (0, 0, 1), and (0, 0, 0). The first data in them represents the original data, the second data represents the decision data of the first-round bias voltage, and the third data represents the decision data of the second-round bias voltage. The credibility values corresponding to the partition arrays are -7, -5, -3, 3, 5, and 7 respectively. To represent negative credibility values, add 16 to the negative credibility value. Therefore, a -7 credibility can also be represented as 0x9, a -5 credibility can also be represented as 0xB, and a -3 credibility can also be represented as 0xD.

[0067] Please refer to Figures 1 to 5 As shown, in an embodiment of the present invention, in step S500, the decision data is decoded by LDPC codes. Among them, the decision data with high credibility can be given priority in confidence, while the data with low credibility is given priority in doubt. The present invention does not limit the specific determination process of the decoding process. Specifically, step S500 includes step S510 and step S520.

[0068] Step S510: Set the trust priority of the decision data according to the credibility of the decision data.

[0069] Step S520: Start the iterative process of decoding processing and trigger step S600.

[0070] Please refer to Figure 5 As shown, in an embodiment of the present invention, in step S510, for example, when performing iterative decoding for the first time, the decision data with credibility of -3 and 3 is preferentially recognized as incorrect data. The decision data with credibility of 9 and 7 is preferentially recognized as correct data. Based on this determination, iterative decoding is started. In step S520, the iterative decoding process of decoding processing is started. While starting the iterative decoding process, step S600 is triggered for execution. Among them, step S600 can be triggered for execution by means of generating signals, establishing a task queue and task content. In this embodiment, the decoding iteration method can be the decoding iteration of LDPC codes. Each iteration guesses the accuracy of each decision data based on the credibility.

[0071] Please refer to Figures 1 to 5As shown, in an embodiment of the present invention, in step S600, at the same time when the decoding process starts, increase the number of times of raising the initial threshold voltage of the symmetric offset, and re-read the data as the bias data for the next round. In step S700, loop through the steps of obtaining the decision data, obtaining the confidence level, and the decoding process until the decoding is successful or the number of times of symmetric offset reaches the offset number threshold. Among them, step S600 includes step S610 and step S620.

[0072] In step S610, increment the number of quantization bits by one.

[0073] In step S620, trigger the execution of step S200 to obtain the bias data for the next round.

[0074] Please refer to Figures 1 to 5 As shown, in an embodiment of the present invention, in step S610, after triggering step S600, the number of quantization bits is incremented by one compared to the value set in this round. Then in step S620, after the number of quantization bits is incremented, trigger the execution of step 200 to offset the initial threshold voltage and obtain a new round of bias data. In this embodiment, step S200 is executed in the form of establishing a task item. It should be noted that step S520 and step S600 are executed synchronously. The decoding iteration process can be executed separately by the decoder, and the step of re-obtaining the bias data can be executed by the processor 30. In step S700, monitor the decoding iteration process and the read process of the bias data for the next round to trigger the execution of the loop process. In this embodiment, multiple processors 30 can be set, and different processors 30 can be divided to monitor the loop while reading the bias data. Among them, step S700 includes steps S710 to S760.

[0075] In step S710, determine whether the decoding is successful.

[0076] In step S720, when the decoding is successful, delete the obtained bias data or terminate the process of obtaining the bias data.

[0077] In step S730, when the decoding is successful, output the decoded successful data.

[0078] In step S740, when the decoding fails, determine whether the number of iterations reaches the upper limit threshold. If the number of iterations does not reach the upper limit threshold, continue the next iteration.

[0079] In step S750, when the decoding fails and the number of iterations reaches the upper limit threshold, trigger a loop signal.

[0080] In step S760, under the trigger of the loop signal, trigger the execution of step S300 and step S400.

[0081] Please refer toFigures 1 to 5 As shown, in an embodiment of the present invention, in step S700, the decoding process and the process of reading bias data are executed synchronously. However, the speeds of the decoding process and the process of reading bias data are uncontrollable. Therefore, after decoding is successful, the bias data may have been read out or may not have been read out yet. Therefore, after decoding is successful, if the bias data has been read out, the obtained bias data is deleted. After decoding is successful, if the bias data has not been read out, the process of reading bias data is terminated and the redundant data is deleted. The process of deleting the bias data and the step of outputting the successfully decoded data can be executed synchronously or sequentially. In this embodiment, an upper limit threshold for the number of decoding iterations can be set. When the number of decoding iterations reaches the upper limit threshold and decoding is still not successful, it is determined that the decoding process at the current offset voltage has failed. If decoding fails and the number of iterations has not reached the upper limit threshold, the next iteration is continued until decoding is successful or the number of iterations reaches the upper limit threshold. When decoding fails and the number of iterations reaches the upper limit threshold, the occurrence of a cycle signal is triggered. Under the trigger of the cycle signal, the execution of steps S300 and S400 is triggered. Under the trigger of the cycle signal, according to the bias data of the next round obtained in advance, the decision data and the reliability of the decision data are continuously obtained, and based on the bias data, the decision data, and the reliability, step S500 is restarted. Among them, while the decoding iteration in step S500 starts, the bias data of the next round is continuously obtained, and so on until decoding is successful or the offset voltage range is traversed. Among them, in this embodiment, it can be determined that the current data reading fails according to decoding failure and traversing the adjustable voltage range. In another embodiment of the present invention, it can also be determined that the current data reading fails according to decoding failure and reaching the offset number threshold.

[0082] Please refer to Figure 1 and Figure 6As shown in the figure, the present invention provides a storage device, which includes a main controller 10 and a flash chip 20. The main controller 10 and the flash chip 20 are electrically connected, and the main controller 10 controls the data reading and writing of the flash chip 20 and manages the addresses of the flash chip 20. The main controller 10 includes a reading module 11, an error correction module, a bias module 12, a decision module 13, a confidence module 14, a decoding module 15, a timing control module 16, and a loop control module 17. Among them, the reading module 11 is used to read data from the flash chip 20 at a set threshold voltage, and the data read at the initial threshold voltage is the original data. The bias module 12 is used to symmetrically offset the initial threshold voltage centered on the initial threshold voltage, and the data read at the offset threshold voltage is the bias data. The decision module 13 is used to logically process the symmetric bias data to obtain decision data. The confidence module 14 is used to combine the original data and the decision data to obtain a partition array, and obtain the credibility of the partition array through a look-up table, where the credibility is positively correlated with the accuracy of the decision data. The decoding module 15 is used to preferentially trust the decision data with high credibility and decode the decision data. The timing control module 16 is used to control the start timing of all processes in the storage device. When the decoding process starts, the timing control module 16 outputs a trigger signal to increase the number of times of symmetrically offsetting the initial threshold voltage and start the next round of obtaining bias data steps. The loop control module 17 is used to loop through the steps of obtaining decision data, obtaining credibility, and the decoding process until the decoding is successful or the number of symmetric offsets reaches the offset number threshold.

[0083] Please refer to Figure 1 and Figure 6 As shown in the figure, in an embodiment of the present invention, the timing control module 16 includes a plurality of clock trigger units to control the process of the control method of the storage device. The first clock unit is used to control the generation of a bias signal, and the bias signal is used to trigger the execution of step S600. In this embodiment, when hard decoding fails, when the voltage offset process is first executed, and when the decoding process of the decision data starts, the generation of the bias signal is triggered. In this embodiment, the bias signal can be used to trigger the parallel execution of obtaining bias data and decoding. The second clock unit is used to control the generation of a loop signal, and the loop signal occurs when decoding fails and the number of iterations reaches the upper limit threshold. The loop signal is used to trigger the execution of step S300 and step S400 according to the previously obtained bias data. In this embodiment, for each set step, there is a corresponding timing signal to trigger the execution. In another embodiment of the present invention, by setting a task queue and setting task items, task items are set according to the control method of the storage device, and the tasks in the task queue are executed in sequence according to the task queue and task priorities. The task priorities are set according to the control method of the storage device.

[0084] Please refer to Figure 1 , Figure 6 and Figure 7 As shown, the present invention further provides a computer storage medium 40, and the computer storage medium 40 stores computer instructions 41. Among them, when the computer instructions 41 are executed by the processor 30, the steps of the control method of the storage device provided by the present invention are realized, so as to successfully read data from the flash memory chip 20, or timely terminate the read process to avoid excessive resource occupation. The processor 30 may be an ARM processor 30. The computer storage medium 40 may be a read-only memory.

[0085] The embodiments of the present invention disclosed above are only used to help explain the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, according to the content of this specification, many modifications and changes can be made. This specification selects and specifically describes these embodiments to better explain the principle and practical application of the present invention, so that those skilled in the art can well understand and utilize the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A control method for a storage device, characterized in that, It includes the following steps: Taking the data read out at the initial threshold voltage as the original data; Centering on the initial threshold voltage, symmetrically offsetting the initial threshold voltage, and then rereading the data as the bias voltage data; Logically processing the symmetric bias voltage data to obtain the decision data; Combining the original data and the decision data to obtain a partition array, and obtaining the credibility of the partition array through a look-up table, where the credibility is positively correlated with the accuracy of the decision data; Prioritizing and trusting the decision data with high credibility and decoding the decision data; At the same time when the decoding process starts, increasing the number of times of symmetrically offsetting the initial threshold voltage and rereading the data as the bias voltage data for the next round; And Repeatedly performing the steps of obtaining the decision data, obtaining the credibility, and decoding process until the decoding is successful or the number of times of symmetric offset reaches the offset times threshold.

2. The control method of a storage device according to claim 1, wherein, The step of obtaining the bias voltage data includes: Setting the bias voltage amplitude and the quantization bit number; and Performing left-biased processing and right-biased processing on the initial threshold voltage respectively, and obtaining the left-biased voltage and the right-biased voltage, where the voltage offset amplitude of the left-biased processing and the right-biased processing is the bias voltage amplitude or an integer multiple of the bias voltage amplitude, and the number of the left-biased voltage and the right-biased voltage is equal to the current quantization bit number; and Reading out the data at the left-biased voltage and the right-biased voltage respectively to obtain the left-biased data and the right-biased data, where the left-biased voltage and the right-biased voltage are symmetric about the initial threshold voltage.

3. The control method of a storage device according to claim 2, characterized in that, In the step of obtaining the decision data, performing exclusive OR processing on the symmetric left-biased data and right-biased data to obtain the decision data.

4. A control method for a storage device according to claim 2, wherein In the step of offsetting the initial threshold voltage, as the number of rounds of obtaining the bias voltage data increases, the quantization bit number increases arithmetically, and the number of the bias voltage data has a linear relationship or an exponential relationship with the quantization bit number.

5. The control method of a storage device according to claim 2, characterized in that, In the step of offsetting the initial threshold voltage, the voltage difference between adjacent left-biased voltages is the bias voltage amplitude, and the voltage difference between adjacent right-biased voltages is the bias voltage amplitude.

6. A control method for a storage device according to claim 1, characterized in that, In the step of offsetting the initial threshold voltage, when offsetting the initial threshold voltage in the next round, using the bias voltage data obtained at the same threshold voltage in this round or rereading the new bias voltage data at the offset threshold voltage.

7. A control method for a storage device according to claim 1, characterized in that, When the decoding process fails, obtaining the decision data and the credibility according to the bias voltage data of the next round, and starting the parallel process of the decoding process and reading out the bias voltage data of the next round until the decoding process gets a result.

8. A control method for a storage device according to claim 1, wherein, When the decoding process is successful, taking the decoded successful data as the read-out data, deleting all invalid data in the decoding process, and ending the read-out process.

9. A storage device, characterized in that, It includes: A flash memory chip; A read-out module for reading out data from the flash memory chip at a set threshold voltage, where the data read out at the initial threshold voltage is the original data; A bias voltage module for symmetrically offsetting the initial threshold voltage with the initial threshold voltage as the center, where the data read out at the offset threshold voltage is the bias voltage data; A decision module for logically processing the symmetric bias data to obtain decision data; A confidence module for combining the original data and the decision data to obtain a partition array, and obtaining the credibility of the partition array through a look-up table, where the credibility is positively correlated with the accuracy of the decision data; A decoding module for preferentially trusting the decision data with high credibility and decoding the decision data; A timing control module for controlling the start timing of all processes in the storage device, where at the same time as the decoding process starts, the timing control module outputs a trigger signal to increase the number of times of symmetrically offsetting the initial threshold voltage and start the next round of the step of obtaining the bias data; And A loop control module for looping through the steps of obtaining the decision data, obtaining the credibility, and decoding process until the decoding is successful or the number of symmetric offsets reaches the offset number threshold.

10. A computer storage medium storing computer instructions, characterized in that, When the computer instructions are executed by a processor, the steps of the control method of the storage device according to any one of claims 1 to 8 are implemented.

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