Computer system, interrupt resource allocation method, device, medium and program product

Abstract

The embodiments of the present application provide a computer system, an interrupt resource allocation method, a device, a medium, and a program product. In the embodiments of the present application, by configuring the number of processor cores of the Managed IRQ mechanism affinity to a set number M, M is less than or equal to the total number of processor cores of the computer system divided by 2 rounded down. When allocating interrupt vectors to IO devices, M idle interrupt vectors in the same row or column in the interrupt matrix can be allocated to the IO devices, so that the same row or column in the interrupt matrix can be allocated to multiple IO devices or to multiple physical queues in the IO devices. Compared with the traditional Managed IRQ mechanism interrupt matrix in which the same row or column can only be allocated to one IO device or to one physical queue in the IO device, the interrupt resource allocation method provided in this embodiment can expand the number of IO devices that support interrupt processing in the same computing instance.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a computer system, an interrupt resource allocation method, a device, a medium, and a program product. Background Art

[0002] The Interrupt Request (IRQ) mechanism is a signaling mechanism used to notify the central processing unit (CPU) of external devices or events requiring processing. This allows various hardware devices to communicate with the processor and, when needed, obtain processor time slices to perform tasks or handle events. In computer systems, the IRQ mechanism is crucial for managing various hardware resources and ensuring efficient system operation.

[0003] An interrupt vector is an interrupt resource, a unique number assigned by the operating system or hardware architecture to each possible interrupt type. These numbers form a table, called the Interrupt Vector Table (IVT), which stores the entry points to each interrupt handler. Proper interrupt vector management is crucial to ensure efficient data processing and high system availability. However, existing interrupt resource management mechanisms limit the input / output (IO) devices supported by compute instances. Summary of the Invention

[0004] Embodiments of the present application provide a computer system, an interrupt resource allocation method, a device, a medium, and a program product for expanding the number of IO devices that a computing instance supports for interrupt processing.

[0005] An embodiment of the present application provides a computer system, comprising: a processor and an input / output device; the processor and the input / output device are electrically connected; the processor comprises a plurality of processor cores; the processor cores provide a plurality of interrupt vectors; the interrupt vectors provided by the plurality of processor cores form an interrupt matrix;

[0006] The processor is configured to: determine, in response to an interrupt application request from the input / output device, a target row or target column corresponding to the input / output device from the interrupt matrix; and allocate a set number of interrupt vectors in an idle state to the input / output device from the target row or target column; the set number being greater than or equal to 1 and less than or equal to the total number of processor cores divided by 2 rounded down.

[0007] The embodiment of the present application further provides an interrupt resource allocation method, which is applicable to a processor, wherein the processor is electrically connected to an input / output device; the processor includes multiple processor cores; the processor cores provide multiple interrupt vectors; the interrupt vectors provided by the multiple processor cores form an interrupt matrix;

[0008] The method comprises:

[0009] In response to an interrupt application request from the input / output device, determining a target row or a target column corresponding to the input / output device from the interrupt matrix;

[0010] A set number of interrupt vectors in an idle state are allocated to the input / output device from the target row or target column; the set number is greater than or equal to 1 and less than or equal to the total number of processor cores divided by 2 rounded down.

[0011] An embodiment of the present application further provides an electronic device, comprising: a memory and a processor; wherein the memory is used to store a computer program;

[0012] The processor is coupled to the memory and configured to execute the computer program to perform the steps in the above interrupt resource allocation method.

[0013] An embodiment of the present application further provides a computer-readable storage medium storing computer instructions. When the computer instructions are executed by one or more processors, the one or more processors are caused to execute the steps in the above-mentioned interrupt resource allocation method.

[0014] An embodiment of the present application further provides a computer program product, comprising a computer program. When the computer program is executed by one or more processors, the one or more processors are caused to execute the steps in the above-mentioned interrupt resource allocation method.

[0015] In an embodiment of the present application, the number of processor cores of the Managed IRQ mechanism affinity is configured to a set number M, where M is less than or equal to the total number of processor cores of the computer system divided by 2 rounded down. When allocating interrupt vectors to IO devices, M idle interrupt vectors in the same row or column in the interrupt matrix can be allocated to the IO devices, so that the same row or column in the interrupt matrix can be allocated to multiple IO devices or to multiple physical queues in the IO devices. Compared to the traditional Managed IRQ mechanism in which the same row or column in the interrupt matrix can only be allocated to one IO device or one physical queue in the IO device, the interrupt resource allocation method provided in this embodiment can expand the number of IO devices that support interrupt processing in the same computing instance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0017] Figure 1 A schematic diagram of the structure of a computer system provided in an embodiment of the present application;

[0018] Figure 2 and Figure 3 A flowchart of the interrupt resource allocation method provided in an embodiment of the present application;

[0019] Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] To make the purpose, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the specific embodiments of this application and the corresponding drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0021] It should be noted that when the embodiments of the present application involve user information, the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the embodiments of the present application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0022] The following is an explanation of the terms or concepts involved in the embodiments of the present application.

[0023] Interrupt Affinity: Interrupt affinity refers to the mechanism by which the operating system binds specific interrupt requests (IRQs) to one or more specific CPU cores for processing. This mechanism allows the system administrator or operating system to optimize performance based on system load, hardware configuration, and other factors. By assigning specific types of interrupts to specific CPU cores, context switching between different CPU cores can be reduced, thereby improving performance. For example, for frequently triggered network interrupts, if they are handled by the same CPU core, then this CPU core can maintain a higher cache hit rate, thereby speeding up interrupt processing.

[0024] Non-Volatile Memory Express (NVMe): NVMe is a high-speed storage access protocol designed for solid-state drives based on NAND (Not AND) flash memory.

[0025] Interrupt Vector: An interrupt vector is a mechanism used by operating systems and hardware to handle interrupts. It is an address or index that points to the entry point of an interrupt handler, allowing the processor to quickly find and jump to the appropriate handler when a specific interrupt occurs. An interrupt vector is a unique number assigned by the operating system or hardware architecture to each possible interrupt type. These numbers form a table called the Interrupt Vector Table (IVT), which stores the entry point to each interrupt service routine.

[0026] Interrupt Matrix (IRQ Matrix): An interrupt matrix describes the relationship between interrupt vectors and processor cores (such as CPU cores) in a computer system. It consists of two dimensions: CPU cores and interrupt vectors. For example, a single CPU core in the traditional x86 architecture provides 256 interrupt vectors. Therefore, the interrupt matrix is a matrix of dimensions N*256, where N represents the number of CPU cores and is a positive integer.

[0027] Managed IRQ: Managed IRQ is an interrupt management mechanism in the operating system kernel that aims to optimize interrupt processing and distribution. The kernel dynamically adjusts interrupt affinity to improve system performance and manageability.

[0028] Non-Uniform Memory Access (NUMA): NUMA is a multiprocessor system architecture designed to address some of the limitations of traditional symmetric multi-processing (SMP) systems. The NUMA architecture is designed to optimize memory access patterns in multiprocessor systems. In a NUMA architecture, system memory is divided into multiple sections or "nodes," known as NUMA nodes. Each node is closely connected to one or more processors. In a NUMA architecture, memory is not centralized but distributed across the NUMA nodes. Each NUMA node typically contains a set of CPU cores, their corresponding cache, and a portion of local memory. Each processor (or group of processors) in each NUMA node has its own local memory, and the latency of accessing local memory is lower than the latency of accessing remote memory (that is, the local memory of other processors).

[0029] Virtual Block Device (Virtio Blk): A Virtio Blk is a device type within the Virtual Input / Output (Virtio) framework, specifically designed to provide access to block storage devices (such as hard disks) within virtual machines. Virtio is an I / O paravirtualization standard designed to improve communication efficiency between the Virtual Machine Monitor (VMM) and virtual machines. Virtioblk is the specific implementation of block storage devices within this framework, enabling virtual machines to efficiently read and write disks. By using Virtioblk, virtual machines can directly interact with physical storage devices on the host machine, achieving better performance. Therefore, virtual block devices are a key component of virtualization technology, primarily used to provide efficient support for virtual block devices (block storage devices).

[0030] Some traditional interrupt resource allocation mechanisms are described below.

[0031] In some traditional solutions, interrupts can be allocated through the interrupt affinity mechanism. Specifically, the operating system binds specific interrupt requests to one or more specific CPU cores for processing. However, if all CPUs with interrupt affinity for the IO device are manually taken offline, the upper-layer application will become unavailable. To avoid this situation, the operating system will forcibly set the interrupt type to the interrupt management mechanism (Managed IRQ). When the interrupt type of the IO device is set to ManagedIRQ. The interrupt of the IO device will occupy the interrupt vectors of all CPUs included in the affinity of the Managed IRQ mechanism. All CPUs included in the affinity of the Managed IRQ mechanism refer to all CPUs in the computing instance where the IO device is located. This greatly limits the number of IO devices that support interrupt processing on the same computing instance.

[0032] For example, assume a virtual machine instance with 128 CPU cores. Each NVMe drive has 128 physical queues (requiring 128 interrupt vectors). An NVMe drive is a type of SSD. For x86 processors, each CPU core provides 256 interrupt vectors, 0-255. The interrupt matrix composed of the interrupt vectors for the 128 CPU cores is shown in Table 1. Interrupt vectors for the 128 CPU cores are placed in the same row of the interrupt vector matrix, with the same interrupt vector number.

[0033] Table 1 Interrupt matrix diagram

[0034]

[0035] As shown in Table 1, interrupt vectors with the same number are located in the same row of the interrupt matrix. Accordingly, the interrupt matrix shown in Table 1 includes 256 interrupt vectors, ranging from 0 to 255. If allocated according to the aforementioned Managed IRQ mechanism, without considering reserved interrupt vectors and other system interrupts, the virtual machine instance can theoretically support interrupt processing for a maximum of two NVMe drives. This significantly limits the number of NVMe drives that can be processed by this virtual machine instance.

[0036] In order to expand the number of IO devices that the computing instance supports for interrupt processing, in some embodiments of the present application, the number of processor cores with the affinity of the Managed IRQ mechanism is configured to a set number M, where M is less than or equal to the total number of processor cores of the computer system divided by 2 rounded down. When allocating interrupt vectors to IO devices, M free interrupt vectors in the same row or column in the interrupt matrix can be allocated to the IO devices, so that the same row or column in the interrupt matrix can be allocated to multiple IO devices or to multiple physical queues in the IO devices. Compared to the traditional Managed IRQ mechanism in which the same row or column in the interrupt matrix can only be allocated to one IO device or one physical queue in the IO device, the interrupt resource allocation method provided in this embodiment can expand the number of IO devices that the same computing instance supports for interrupt processing.

[0037] The following describes in detail the technical solutions provided by various embodiments of the present application in conjunction with the accompanying drawings.

[0038] It should be noted that the same reference numerals represent the same objects or steps in the following drawings and embodiments. Therefore, once an object or a step is defined in one drawing or embodiment, it does not need to be further discussed in the subsequent drawings and embodiments.

[0039] Figure 1 This is a schematic diagram of the structure of the computer system provided in the embodiment of the present application. Figure 1 As shown, the computer system mainly includes: a processor 10 and an input / output (IO) device 20. The processor 10 and the IO device 20 are electrically connected.

[0040] The processor 10 can be any hardware processing device capable of executing the logic of the above method. Optionally, the processor can be a central processing unit (CPU), a graphics processing unit (GPU), or a microcontroller unit (MCU); it can also be a programmable device such as a field-programmable gate array (FPGA), a programmable array logic device (PAL), a general array logic device (GAL), or a complex programmable logic device (CPLD); or it can be an advanced reduced instruction set compute (RISC) processor (Advanced RISC Machines, ARM) or a system on chip (SoC), etc., but is not limited thereto.

[0041] The processor 10 includes multiple processor cores 101. Each processor core 101 can provide multiple interrupt vectors. Figure 1 The total number of processor cores is N, which is used for illustration. Wherein, N≥2 and is an integer. For example, each CPU core in an x86 architecture processor can have 256 interrupt vectors. In the various embodiments of the present application, "a plurality" refers to more than 2 (including 2). The interrupt vectors provided by multiple processor cores 101 form an interrupt matrix. For the implementation form of the interrupt matrix, please refer to the relevant content of the aforementioned embodiment, which will not be repeated here. It is worth noting that the aforementioned Table 1 only uses the example of the interrupt vectors provided by the processor cores being located in the same row of the interrupt matrix according to the interrupt vectors with the same number. Of course, the interrupt vectors provided by the processor cores can also be arranged in the interrupt matrix according to the interrupt vectors with the same column number being located in the same column of the interrupt matrix.

[0042] IO devices 20 refer to all physical or virtual components in a computer system that can exchange data with the external world. These devices allow the computer to receive information from the external environment (input) and send information to the external environment (output). IO devices 20 may include storage devices such as disks, hard disk drives (HDDs), solid-state drives (SSDs), and flash memory. IO devices 20 may also include network interface devices such as network cards. Of course, IO devices 20 may also include virtual components such as virtual block devices (e.g., Virtio blk).

[0043] Because the traditional managed IRQ mechanism severely limits the number of I / O devices that can be processed by a single computing instance, in embodiments of the present application, a new interrupt resource management mechanism, such as the new managed IRQ mechanism, is proposed to expand the number of I / O devices that a computing instance can support. A computing instance refers to any entity or environment in a computer system that can execute program code, process data, and provide computing power. It can be an entity based on physical hardware (such as a physical machine) or a virtual environment created by software virtualization technology (such as a virtual machine). Accordingly, a computing instance can be a physical machine or a virtual machine (VM).

[0044] The new interrupt resource management mechanism refers to changing the affinity of the Managed IRQ mechanism and configuring the number of processor cores with the affinity of the Managed IRQ mechanism to a set number M. Wherein, M is a positive integer, 1≤M≤N. N refers to the total number of all processor cores in the computing instance where the processor 10 is located, that is, the total number of processor cores contained in the aforementioned processor 10. Correspondingly, the total number of interrupt vectors contained in a row or a column in the interrupt matrix is also N. Preferably, 1≤M≤ .in, Indicates rounding down. Where 1≤M≤ , so that the number of interrupt vectors assigned to an IO device or a physical queue in an IO device will not be greater than half of the total number of interrupt vectors contained in the same row or column in the interrupt matrix. Therefore, the same row or column in the interrupt matrix can be assigned to at least two IO devices or at least two physical queues in an IO device. Therefore, 1≤M≤ , which allows the same row or column in the interrupt matrix to be assigned to multiple IO devices or to multiple physical queues in the IO devices. Multiple means more than 2 (including 2). The number of IO devices or physical queues in the IO device that can be assigned to the same row or column in the specific interrupt matrix is determined by the value of N divided by M. For example, if N=128 and M=2, then N divided by M equals 64. Without considering the reserved interrupt vectors and other system interrupts, theoretically, the same row or column in the interrupt matrix can be assigned to 64 IO devices or 64 physical queues in the IO device. Compared with the traditional Managed IRQ mechanism, in which the same row or column in the interrupt matrix can only be assigned to one IO device or one physical queue in the IO device, the new interrupt management mechanism provided in this embodiment can expand the number of IO devices that support interrupt processing in the same computing instance.

[0045] The physical queues in an I / O device are the actual data structures used to communicate commands and completion status between the I / O device and the host. These queues are the foundation for efficient, parallel I / O operations, allowing the I / O device and host to process multiple I / O requests concurrently.

[0046] The aforementioned set number M is pre-set in the kernel of the computer system. An interrupt vector number parameter can be added to the kernel of the computer system to configure the number of processor cores for the affinity of the Managed IRQ mechanism. The set number M can be the default setting of the computer system, or an interface can be provided for the user to independently set the interrupt vector number parameter. For example, in a cloud computing scenario, users can use the computing resources provided by the cloud service by purchasing a virtual instance. A configuration interface for the interrupt vector number parameter can be provided to users of the virtual instance, and users can flexibly configure the interrupt vector number parameter according to actual needs. Accordingly, the user-configured number can be obtained as the set number M.

[0047] Based on the preset number of processor cores of the affinity of the Managed IRQ mechanism, that is, the set number M, an embodiment of the present application provides another interrupt resource allocation method, which is described in detail below.

[0048] like Figure 1 As shown in step 1, during the startup process, the IO device 20 may send an interrupt request to the processor 10. In response to the interrupt request, the processor 10 may determine the target row or target column corresponding to the IO device from the interrupt matrix. The interrupt vectors provided by multiple processor cores are arranged in the interrupt matrix such that the interrupt vectors with the same number are located in the same row. Figure 1 As shown in step 2, the processor 10 may determine the target row corresponding to the IO device from the interrupt matrix in response to the interrupt request. For interrupt vectors provided by multiple processor cores, the interrupt matrix arranges interrupt vectors with the same number in the same column. The processor 10 may determine the target column corresponding to the IO device from the interrupt matrix in response to the interrupt request. Figure 1 The interrupt vectors provided by multiple processor cores are arranged in the same row to form an interrupt matrix as an example for illustration, but this does not constitute a limitation.

[0049] Specifically, the processor 10 may assign an interrupt (IRQ) identifier, such as an interrupt (IRQ) number, to the IO device 20 in response to an interrupt request. There is a correspondence between the interrupt identifier and the interrupt vector number. One interrupt identifier may correspond to one or more interrupt vector numbers. Based on this correspondence, the processor 10 may determine the interrupt vector number corresponding to the interrupt identifier assigned to the IO device 20 from the correspondence; and determine the row or column corresponding to the interrupt vector number in the interrupt matrix as the target row or target column corresponding to the IO device.

[0050] Further, if Figure 1 As shown in step 3, the processor 10 may allocate M (i.e., a set number) interrupt vectors in an idle state to the IO device 20 from the target row or target column. In this embodiment, 1≤M≤ . In this embodiment, the number of processor cores of the Managed IRQ mechanism affinity is configured to a set number M, where M is less than or equal to the total number of processor cores of the computer system divided by 2 rounded down. When allocating interrupt vectors to IO devices, M idle interrupt vectors in the same row or column in the interrupt matrix can be allocated to the IO devices, so that the same row or column in the interrupt matrix can be allocated to multiple IO devices or to multiple physical queues in the IO devices. Compared with the traditional Managed IRQ mechanism in which the same row or column in the interrupt matrix can only be allocated to one IO device or to one physical queue in the IO device, the interrupt resource allocation method provided in this embodiment can expand the number of IO devices that support interrupt processing in the same computing instance.

[0051] Furthermore, the total number N of processor cores in the computer system is an integer multiple of M. Thus, without considering reserved interrupt vectors and other system interrupts, theoretically, a row or column in an interrupt vector can be allocated to N / M (N divided by M) I / O devices or N / M physical queues in an I / O device, which helps reduce interrupt resource fragmentation and thereby improve interrupt resource utilization.

[0052] It is worth noting that the above-mentioned new Managed IRQ mechanism can be automatically enabled, that is, the above-mentioned new Managed IRQ mechanism is automatically adopted. Of course, the user can also choose whether to adopt the new Managed IRQ mechanism. For users who choose to adopt the new Managed IRQ mechanism, the above-mentioned new Managed IRQ mechanism can be enabled by configuring the interrupt vector quantity parameter. Accordingly, the processor 20 can query whether the pre-set interrupt vector quantity parameter is configured with a valid quantity before allocating M interrupt vectors to the IO device 20 from the target row or target column. The valid quantity may be a quantity within a set numerical range. The numerical range may be [1, N] or a numerical range of [1, ].

[0053] The upper limit of the value range is set to Because it is greater than When the number of processor cores with managed IRQ affinity exceeds half the number of processor cores, the same row or column in the interrupt matrix can only support interrupt processing for the same I / O device or the same physical queue within the same I / O device. This prevents the compute instance from expanding the number of I / O devices that support interrupt processing. Accordingly, an invalid number can be a number that is not within the specified range or a default invalid character.

[0054] Furthermore, if the interrupt vector quantity parameter is configured with a valid quantity, the valid quantity can be determined as the set quantity M, and M interrupt vectors are allocated to the IO device 20 from the target row or target column. If the interrupt vector quantity parameter is configured with an invalid quantity, the traditional managed IRQ mechanism can be used to allocate interrupt resources, that is, all interrupt vectors contained in the target row or target column are allocated to the IO device. This embodiment allows the user to independently choose whether to enable the new managed IRQ mechanism by setting the interrupt vector quantity parameter, thereby increasing the flexibility of interrupt resource allocation and meeting the diverse needs of users.

[0055] The following describes an exemplary implementation of allocating M interrupt vectors in an idle state to the IO device 20 from a target row or a target column by using the above-mentioned new Managed IRQ mechanism.

[0056] Specifically, the processor 10 may obtain the usage status of each interrupt vector in the target row or target column. The usage status of the interrupt vector is used to indicate whether the interrupt vector is occupied, that is, whether it has been allocated to an IO device. In some embodiments, "0" may indicate that the interrupt vector is occupied; "1" may indicate that the interrupt vector is not occupied, that is, in an idle state. Alternatively, "1" may indicate that the interrupt vector is occupied; "0" may indicate that the interrupt vector is not occupied, that is, in an idle state.

[0057] In some embodiments, for each interrupt vector in the interrupt matrix, after the interrupt vector is assigned to the IO device, the corresponding interrupt vector may be labeled with a used tag. Accordingly, whether each interrupt vector in the target row or target column is labeled with a used tag may be obtained as the usage status of the interrupt vector. Further, based on the labeled used tags, M interrupt tags may be determined from the interrupt vectors in the target row or target column that are not labeled with a used tag, i.e., the M interrupt tags in the idle state. Further, the M interrupt tags in the idle state may be assigned to the IO device 20.

[0058] In other embodiments, a global allocation information table corresponding to the interrupt matrix, i.e., the interrupt vectors provided by each processor core in processor 10, may be established. In this global allocation information table, each bit corresponds to an interrupt vector, and the bit corresponding to the interrupt vector records the usage status of the interrupt vector. A "0" may indicate that the interrupt vector is occupied; a "1" may indicate that the interrupt vector is not occupied, i.e., in an idle state. Alternatively, a "1" may indicate that the interrupt vector is occupied; a "0" may indicate that the interrupt vector is not occupied, i.e., in an idle state.

[0059] Specifically, a global allocation information table can be established in response to the startup operation of the operating system in the processor 10. The global allocation information table is used to record the usage status of each interrupt vector in the interrupt matrix. In the startup process of the operating system, a global allocation information table of the interrupt matrix is established, and the global allocation information table can be used to record the usage status of each interrupt vector in the interrupt matrix in real time to provide support for subsequent interrupt vector allocation. Accordingly, the global allocation information table corresponding to the interrupt matrix can be obtained. The global allocation information table records the usage status of each interrupt vector in the interrupt matrix; further, the usage status of each interrupt vector in the target row or target column can be obtained from the global allocation information table. In particular, the global allocation information table provides a centralized view, allowing the operating system to quickly obtain the status of all interrupt vectors, simplifying the management of interrupt resources and helping to improve the efficiency of interrupt vector allocation.

[0060] Furthermore, based on the usage status of each interrupt vector in the target row or target column, M idle interrupt vectors can be allocated to the IO device 20 from the target row or target column. In this embodiment, by monitoring the usage status of each interrupt vector in the target row or target column in real time, it is possible to dynamically identify which interrupt vectors are currently idle and allocate the idle interrupt vectors to the IO device. This approach avoids the resource waste or shortage that may be caused by static allocation.

[0061] The interrupt vector allocation method provided in the aforementioned embodiment is applicable to the case where the number of interrupt vectors in the target row or target column that are in an idle state is greater than or equal to M. If the number of interrupt vectors in the target row or target column that are in an idle state is less than the set number M, it is possible to detect whether the interrupt vectors in the target row or target column that are in a used state have been released; if all the interrupt vectors in a used state have been released, the traditional Managed IRQ mechanism is used to allocate interrupt vectors to the IO device 20, that is, all the interrupt vectors contained in the target row or target column are allocated to the IO device 20. This embodiment uses the traditional Managed IRQ mechanism as a backup solution when there are not enough idle interrupt vectors in the target row or target column of the interrupt matrix, ensuring that interrupt vector allocation can be successfully completed even in extreme cases. This provides additional security for the system while maintaining compatibility with existing systems. Accordingly, if not all the interrupt vectors in a used state have been released, the interrupt allocation processing operation is terminated.

[0062] The number of interrupt vectors in the aforementioned target row or target column that are in an idle state can be counted using a counter. In some embodiments, to maintain the inherent code properties of some operating systems (such as Linux), the interrupt vectors in the target row or target column that are in an idle state can be sequentially assigned to the IO device 20 until M interrupt vectors have been assigned to the IO device or no interrupt vectors in the target row or target column are in an idle state. If the number of interrupt vectors assigned to the IO device is less than M when there are no interrupt vectors in the target row or target column that are in an idle state, it is determined that the number of interrupt vectors in the target row or target column that are in an idle state is less than a set number M. In this embodiment, while sequentially assigning the interrupt vectors in the target row or target column to the IO device, the usage status of the interrupt vectors assigned to the IO device in the global interrupt information table is simultaneously modified. If the number of interrupt vectors in the target row or target column that are in an idle state is less than the set number M, the interrupt vector assignment fails, and the usage status of the interrupt vector assigned to the IO device can be reset to unused, i.e., idle. Thereafter, an operation is performed to detect whether the interrupt vectors in the target row or target column that are in an idle state have been released. This implementation method can reuse the original code logic of the operating system, reducing the modification of the original code logic of the operating code.

[0063] The interrupt resource allocation method provided in the embodiments of the present application is applicable to computing instances of any architecture, such as the non-uniform memory access (NUMA) architecture and the uniform memory access (UMA) architecture. In the UMA architecture, all processors share the same physical memory, and the time to access any memory address is the same.

[0064] For embodiments in which the computing instance to which processor 10 belongs is a NUMA architecture, the computing instance may include at least one NUMA node. In the embodiments of the present application, for ease of description, the total number of NUMA nodes is defined as P, that is, the computing instance includes P NUMA nodes. P ≥ 1 and is an integer. Generally, for a computing instance with a NUMA architecture, if the NUMA architecture is enabled, the computing instance includes multiple NUMA nodes. Multiple means two or more (including two). If the NUMA architecture is not enabled, the computing instance includes one NUMA node.

[0065] Since NUMA nodes have their own processor cores, when establishing the global allocation information table corresponding to the interrupt matrix, the processor core corresponding to each of the at least one NUMA nodes can be determined in response to a startup operation of the operating system in the processor. Specifically, in response to the startup operation of the operating system in the processor, a query command of the operating system can be used to query NUMA topology information. This NUMA topology information includes processor architecture information, including the number of NUMA nodes and the processor cores corresponding to each NUMA node. Furthermore, the processor core corresponding to each NUMA node can be obtained from the NUMA topology information. For Linux systems (an operating system), the query command can be the lscpu command or the numactl-hardware command. The lscpu command is a command-line tool that can be used to display information about the processor architecture. It provides detailed information about the system's processors, including the number of cores, the number of threads, and NUMA topology information. The numactl-hardware command is a tool for controlling and managing NUMA hardware. The numactl-hardware command provides detailed information about the NUMA hardware layout (i.e., NUMA topology information) in the system, including the number of processor cores, the total amount of memory, and its distribution for each NUMA node.

[0066] Furthermore, a global allocation information table corresponding to each NUMA node is established based on the interrupt vectors provided by the processor core corresponding to at least one NUMA node. Because the NUMA architecture emphasizes data access locality, prioritizing access to local memory to reduce latency, establishing a global allocation information table for each NUMA node can better utilize this characteristic. This allows for subsequent interrupt vector allocations to prioritize interrupt vectors from processor cores located on the same NUMA node as the I / O device, reducing cross-node data transmission and communication overhead.

[0067] In some embodiments, when allocating an interrupt vector to an IO device 20, the global allocation information table corresponding to the NUMA node where the IO device 20 is located can be obtained, and the usage status of each interrupt vector in the target row or target column can be obtained from the global allocation information table corresponding to the NUMA node. Furthermore, the usage status of the interrupt vector provided by the processor core corresponding to the NUMA node can be obtained from the usage status of each interrupt vector in the target row or target column. Thereafter, based on the usage status of the interrupt vector provided by the processor core corresponding to the NUMA node, M interrupt vectors in an idle state can be obtained from the interrupt vectors provided by the processor core corresponding to the NUMA node; and these M interrupt vectors can be allocated to the IO device 20. This interrupt vector allocation method can allocate the interrupt vector of the processor core located in the same NUMA node as the IO device to the IO device, which can reduce data transmission and communication overhead across nodes.

[0068] In other embodiments, when allocating interrupt vectors to the IO device 20, each NUMA node allocates a set number (M) of interrupt vectors to the IO device. In this embodiment, in order to enable the computing instance to support interrupt processing for more IO devices, the set number M may be less than or equal to the total number of processor cores N of the computing instance divided by the total number of NUMA nodes, and then divided by 2, rounded down, that is, M≤ Where N / P represents the number of processor cores corresponding to each NUMA node. Dividing N / P by 2 and rounding it down allows a row or column in the interrupt matrix formed by the interrupt vectors provided by the processor cores corresponding to each NUMA node to be assigned to multiple IO devices or multiple physical arrays in the IO device. Compared with the traditional Managed IRQ mechanism, the same row or column in the interrupt matrix can only be assigned to one IO device or one physical queue in the IO device. M≤ The number of I / O devices supported by the same compute instance for interrupt processing can be expanded. Preferably, N is an integer multiple of M*P. Thus, without considering reserved interrupt vectors and other system interrupts, a row or column in the interrupt matrix corresponding to each NUMA node can theoretically be allocated to N / (M*P) I / O devices or N / (M*P) physical queues within an I / O device. This helps reduce interrupt resource fragmentation and improves interrupt resource utilization.

[0069] In an embodiment where each NUMA node allocates a set number (M) of interrupt vectors to the IO device, the usage status of each interrupt vector in a target row or target column can be obtained from the global allocation information table corresponding to each of the multiple NUMA nodes. Subsequently, for any NUMA node, the usage status of the interrupt vectors provided by the processor core corresponding to that NUMA node can be obtained from the usage status of each interrupt vector in the target row or target column corresponding to that NUMA node. Based on the usage status of the interrupt vectors provided by the processor core corresponding to that NUMA node, M idle interrupt vectors can be allocated to the IO device 20 from the interrupt vectors provided by the processor core corresponding to that NUMA node. Using the same method, M idle interrupt vectors can be allocated to each IO device 20 from the interrupt vectors provided by the processor cores corresponding to all NUMA nodes. In this embodiment, M idle interrupt vectors are allocated to the IO device 20 from the interrupt vectors provided by the processor core corresponding to each NUMA node. In this way, when the core of the computer system processes an interrupt, load balancing can be performed among multiple NUMA nodes, which can avoid the situation where some NUMA nodes are overloaded while other NUMA nodes are idle, and help improve interrupt resource utilization.

[0070] For an IO device including multiple physical queues, during the startup of the IO device, an interrupt vector may be applied for each physical queue in turn, and the processor 20 may allocate M interrupt vectors to each physical queue according to the interrupt vector allocation method provided in the above embodiment. , allowing the same row or column in the interrupt matrix to be assigned to multiple physical queues in an I / O device. Compared to the traditional managed IRQ mechanism, where the same row or column in the interrupt matrix can only be assigned to one physical queue in an I / O device, the interrupt resource allocation method provided in this embodiment can expand the number of I / O devices that support interrupt processing in the same computing instance.

[0071] For example, for a virtual machine instance with 128 CPU cores provided in the aforementioned embodiment, each NVMe disk has 128 physical queues (i.e., 128 interrupt vectors are required); for an x86 architecture processor, each CPU core can provide 256 interrupt vectors, i.e., for example, interrupt vectors 0-255. Assuming that the number M is set to 64, then without considering the reserved interrupt vectors and other system interrupts, each row of the interrupt matrix shown in Table 1 can theoretically support the interrupt processing requirements of 2 physical queues. Therefore, theoretically, the above virtual machine instance can support the interrupt processing of 4 NVMe disks. For another example, assuming that M = 16, then without considering the reserved interrupt vectors and other system interrupts, each row of the interrupt matrix shown in Table 1 can theoretically support the interrupt processing requirements of 8 physical queues. Therefore, theoretically, the above virtual machine instance can support the interrupt processing of 16 NVMe disks. Therefore, compared to the traditional managed IRQ mechanism, the interrupt resource allocation method provided in the embodiments of the present application can expand the number of IO devices that support interrupt processing on the same computing instance, making it more suitable for interrupt allocation to high-density IO devices in cloud computing scenarios. High-density IO devices refers to the number of IO devices on the same computing instance being greater than or equal to a set threshold. The set threshold is greater than or equal to 3, and can be, for example, 64, 128, or 256, but is not limited thereto.

[0072] In an embodiment of the present application, when allocating M (i.e., a set number) interrupt vectors to the IO device 20 from a target row or a target column, M unused interrupt vectors can be determined from the target row or the target column; and the M unused interrupt vectors are bound to the interrupt identifier allocated to the IO device 20, thereby allocating a set number (i.e., M) of interrupt vectors to the IO device 20.

[0073] In some embodiments, the online status of the M target processor cores to which the M interrupt vectors assigned to the IO device 20 belong can also be monitored; and when the number of target processor cores in an online state reaches a set lower limit Q, the response to the offline operation of the target processor core in an online state is rejected. The set lower limit Q is a positive integer, 1≤Q<M. In some embodiments, Q=1. In particular, when the number of target processor cores in an online state reaches a set lower limit Q, the response to the offline operation of the target processor core in an online state is rejected, which can prevent the situation where all processors corresponding to the M interrupt vectors assigned to the IO device 20 are offline, resulting in the unavailability of upper-layer application services, and helps to improve the service performance of the computing instance where the processor is located.

[0074] In addition to the computer system provided in the aforementioned embodiment, the embodiment of the present application also provides an interruption resource allocation method. The interruption resource allocation method provided in the embodiment of the present application is exemplarily described below.

[0075] Figure 2 Schematic diagram of the flow of the interrupt resource allocation method provided in the embodiment of the present application. The method is mainly applicable to the processor of the electronic device. The processor is electrically connected to the IO device. The processor includes multiple processor cores. Each processor core can provide multiple interrupt vectors. The interrupt vectors provided by the multiple processor cores form an interrupt matrix. For the description of the interrupt matrix, please refer to the relevant content of the above embodiment, which will not be repeated here. Figure 2 As shown, the interrupt resource allocation method mainly includes the following steps:

[0076] 201. In response to an interrupt application request from an input / output device, determine a target row or a target column corresponding to the input / output device from an interrupt matrix.

[0077] 202. Allocate a set number of interrupt vectors in an idle state to the input / output device from the target row or target column; the set number is greater than or equal to 1 and less than or equal to the total number of processor cores divided by 2 rounded down.

[0078] Since the traditional Managed IRQ mechanism greatly limits the number of IO devices that the same computing instance supports for interrupt processing, in an embodiment of the present application, in order to expand the number of IO devices that the computing instance can support for processing, a new interrupt resource management mechanism, such as a new Managed IRQ mechanism, is proposed.

[0079] The new interrupt resource management mechanism refers to changing the affinity of the Managed IRQ mechanism and configuring the number of processor cores with the affinity of the Managed IRQ mechanism to a set number M. Where M is a positive integer, 1≤M≤N. N refers to the total number of all processor cores in the computing instance where the processor 20 is located, that is, the total number of processor cores included in the aforementioned processor 10. Preferably, 1≤M≤ . Among them, 1≤M≤ The same row or column in the interrupt matrix can be assigned to multiple IO devices or multiple physical queues within an IO device. Multiple refers to two or more. Compared to the traditional ManagedIRQ mechanism, where the same row or column in the interrupt matrix can only be assigned to one IO device or one physical queue within an IO device, the new interrupt management mechanism provided in this embodiment can expand the number of IO devices supported by the same compute instance.

[0080] The aforementioned set number M is pre-set in the kernel of the computer system. An interrupt vector number parameter can be added to the kernel of the computer system to configure the number of processor cores for the affinity of the Managed IRQ mechanism. The set number M can be the default setting of the computer system, or an interface can be provided for the user to independently set the interrupt vector number parameter. For example, in a cloud computing scenario, users can use the computing resources provided by the cloud service by purchasing virtual machine instances. A configuration interface for the interrupt vector number parameter can be provided to users of the virtual machine instance, allowing users to flexibly configure the interrupt vector number parameter according to actual needs. Accordingly, the user-configured number can be obtained as the set number M.

[0081] Based on the number of processor cores with the pre-set affinity of the Managed IRQ mechanism, that is, the set number M, the IO device can send an interrupt application request to the processor during the startup process. Accordingly, for the processor, in step 201, the target row or target column corresponding to the IO device can be determined from the interrupt matrix in response to the interrupt application request. For the interrupt vectors provided by multiple processor cores, the interrupt vectors with the same number are arranged in the same row. Specifically, the target row corresponding to the IO device can be determined from the interrupt matrix in response to the interrupt application request. For the interrupt vectors provided by multiple processor cores, the interrupt vectors with the same number are arranged in the same column. Accordingly, the target column corresponding to the IO device can be determined from the interrupt matrix in response to the interrupt application request.

[0082] Specifically, an interrupt (IRQ) identifier, such as an interrupt (IRQ) number, can be assigned to an IO device in response to an interrupt request. There is a correspondence between the interrupt identifier and the interrupt vector number. One interrupt identifier can correspond to one or more interrupt vector numbers. Based on this correspondence, the interrupt vector number corresponding to the interrupt identifier assigned to the IO device can be determined from this correspondence. The row or column corresponding to the interrupt vector number in the interrupt matrix can then be determined as the target row or column corresponding to the IO device.

[0083] Furthermore, in step 202, M (i.e., a set number) interrupt vectors in an idle state may be allocated to the IO device from the target row or target column. In this embodiment, 1≤M≤ . In this embodiment, the number of processor cores of the Managed IRQ mechanism affinity is configured to a set number M, where M is less than or equal to the total number of processor cores of the computer system divided by 2 rounded down. When allocating interrupt vectors to IO devices, M idle interrupt vectors in the same row or column in the interrupt matrix can be allocated to the IO devices, so that the same row or column in the interrupt matrix can be allocated to multiple IO devices or to multiple physical queues in the IO devices. Compared with the traditional Managed IRQ mechanism in which the same row or column in the interrupt matrix can only be allocated to one IO device or to one physical queue in the IO device, the interrupt resource allocation method provided in this embodiment can expand the number of IO devices that support interrupt processing in the same computing instance.

[0084] Furthermore, the total number N of processor cores in the computer system is an integer multiple of M. Thus, without considering reserved interrupt vectors and other system interrupts, theoretically, a row or column of interrupt vectors can be allocated to N / M (N divided by M) I / O devices or N / M physical queues in an I / O device, which helps reduce interrupt resource fragmentation and thus improves interrupt resource utilization.

[0085] It is worth noting that the above-mentioned new Managed IRQ mechanism can be automatically enabled, that is, the above-mentioned new Managed IRQ mechanism is automatically adopted. Of course, the user can also choose whether to adopt the new Managed IRQ mechanism. For users who choose to adopt the new Managed IRQ mechanism, the above-mentioned new Managed IRQ mechanism can be enabled by configuring the interrupt vector quantity parameter. Accordingly, before allocating M interrupt vectors to the IO device from the target row or target column, it can be queried whether the pre-set interrupt vector quantity parameter is configured with a valid quantity. The valid quantity may be a quantity within a set numerical range. The numerical range may be [1, N] or a numerical range of [1, ].

[0086] The upper limit of the value range is set to Because it is greater than When the number of processor cores with managed IRQ affinity exceeds half the number of processor cores, the same row or column in the interrupt matrix can only support interrupt processing for the same I / O device or the same physical queue within the same I / O device. This prevents the compute instance from expanding the number of I / O devices that support interrupt processing. Accordingly, an invalid number can be a number that is not within the specified range or a default invalid character.

[0087] Furthermore, if the interrupt vector quantity parameter is configured with a valid quantity, the valid quantity can be determined as the set quantity M, and M interrupt vectors are allocated to the IO device from the target row or target column. If the interrupt vector quantity parameter is configured with an invalid quantity, the traditional managed IRQ mechanism can be used to allocate interrupt resources, that is, all interrupt vectors contained in the target row or target column are allocated to the IO device. This embodiment, by setting the interrupt vector quantity parameter, allows the user to independently choose whether to enable the new managed IRQ mechanism, thereby increasing the flexibility of interrupt resource allocation and meeting the diverse needs of users.

[0088] The following describes an exemplary implementation of allocating M interrupt vectors in an idle state to an IO device from a target row or a target column by using the above-mentioned new Managed IRQ mechanism.

[0089] Specifically, the usage status of each interrupt vector in the target row or target column can be obtained. In some embodiments, for each interrupt vector in the interrupt matrix, the corresponding interrupt vector can be marked with a used label after the interrupt vector is assigned to the IO device. Accordingly, whether each interrupt vector in the target row or target column is marked with a used label can be obtained as the usage status of the interrupt vector. Further, based on the marked used labels, M interrupt labels can be determined from the interrupt vectors in the target row or target column that are not marked with a used label, that is, M interrupt labels in an idle state. Further, the M interrupt labels in an idle state can be assigned to the IO device.

[0090] In other embodiments, a global allocation information table corresponding to the interrupt matrix can be established for the interrupt vectors provided by each processor core in the processor, that is, the interrupt matrix. In this case, one bit in the global allocation information table corresponds to an interrupt vector, and the bit corresponding to the interrupt vector is used to record the usage status of the interrupt vector. Specifically, a global allocation information table can be established in response to the startup operation of the operating system in the processor. The global allocation information table is used to record the usage status of each interrupt vector in the interrupt matrix. Accordingly, the global allocation information table corresponding to the interrupt matrix can be obtained. The global allocation information table records the usage status of each interrupt vector in the interrupt matrix; further, the usage status of each interrupt vector in the target row or target column can be obtained from the global allocation information table. In this case, the global allocation information table provides a centralized view, allowing the operating system to quickly obtain the status of all interrupt vectors, simplifying the management of interrupt resources and helping to improve the efficiency of interrupt vector allocation.

[0091] Furthermore, based on the usage status of each interrupt vector in the target row or column, M idle interrupt vectors can be allocated to the IO device from the target row or column. In this embodiment, by monitoring the usage status of each interrupt vector in the target row or column in real time, it is possible to dynamically identify which interrupt vectors are currently idle and allocate the idle interrupt vectors to the IO device. This approach avoids the resource waste or shortage that may result from static allocation.

[0092] The interrupt vector allocation method provided in the aforementioned embodiment is applicable to the case where the number of interrupt vectors in the target row or target column that are in an idle state is greater than or equal to M. If the number of interrupt vectors in the target row or target column that are in an idle state is less than the set number M, it is possible to detect whether the interrupt vectors in the target row or target column that are in a used state are released; if all the interrupt vectors in a used state are released, the traditional Managed IRQ mechanism is used to allocate interrupt vectors to the IO device, that is, all the interrupt vectors contained in the target row or target column are allocated to the IO device. This embodiment uses the traditional Managed IRQ mechanism as a backup solution when there are not enough idle interrupt vectors in the target row or target column of the interrupt matrix, ensuring that the interrupt vector allocation can be completed smoothly even in extreme cases. This provides additional security for the system while maintaining compatibility with existing systems. Accordingly, if the interrupt vectors in a used state are not all released, the interrupt allocation processing operation is terminated.

[0093] The interrupt resource allocation method provided in the embodiments of the present application is applicable to computing instances of any architecture, such as the non-uniform memory access (NUMA) architecture and the uniform memory access (UMA) architecture. In the UMA architecture, all processors share the same physical memory, and the time to access any memory address is the same.

[0094] In embodiments where the compute instance to which the processor belongs uses a NUMA architecture, the compute instance may include at least one NUMA node. Generally, for a compute instance using a NUMA architecture, if the NUMA architecture is enabled, the compute instance includes multiple NUMA nodes. Multiple refers to two or more NUMA nodes. If the NUMA architecture is not enabled, the compute instance includes a single NUMA node. Since NUMA nodes have their own processor cores, when establishing a global allocation information table corresponding to the interrupt matrix, the processor core corresponding to each of the at least one NUMA nodes can be determined in response to a startup operation of the operating system in the processor. Furthermore, a global allocation information table corresponding to each of the multiple NUMA nodes is established based on the interrupt vectors provided by the processor cores corresponding to each of the multiple NUMA nodes. Since the NUMA architecture emphasizes data access locality, prioritizing access to local memory to reduce latency, establishing a global allocation information table for each NUMA node can better utilize this characteristic. This allows for subsequent interrupt vector allocation, prioritizing interrupt vectors from processor cores located in the same NUMA node as the I / O device, thereby reducing cross-node data transmission and communication overhead.

[0095] In some embodiments, when allocating interrupt vectors to an IO device, the global allocation information table corresponding to the NUMA node where the IO device is located can be obtained, and the usage status of each interrupt vector in the target row or target column can be obtained from the global allocation information table corresponding to the NUMA node. Furthermore, the usage status of the interrupt vector provided by the processor core corresponding to the NUMA node can be obtained from the usage status of each interrupt vector in the target row or target column. Thereafter, based on the usage status of the interrupt vector provided by the processor core corresponding to the NUMA node, M interrupt vectors in an idle state can be obtained from the interrupt vectors provided by the processor core corresponding to the NUMA node; and these M interrupt vectors can be allocated to the IO device. This interrupt vector allocation method can allocate the interrupt vector of the processor core located in the same NUMA node as the IO device to the IO device, which can reduce data transmission and communication overhead across nodes.

[0096] In other embodiments, when allocating interrupt vectors to IO devices, each NUMA node allocates a set number (M) of interrupt vectors to the IO device. In this embodiment, in order to enable the computing instance to support interrupt processing for more IO devices, the set number M may be less than or equal to the total number of processor cores N of the computing instance divided by the total number of NUMA nodes, and then divided by 2, rounded down, that is, M≤ Where N / P represents the number of processor cores corresponding to each NUMA node. Dividing N / P by 2 and rounding it down allows a row or column in the interrupt matrix formed by the interrupt vectors provided by the processor cores corresponding to each NUMA node to be assigned to multiple IO devices or multiple physical arrays in the IO device. Compared with the traditional Managed IRQ mechanism, the same row or column in the interrupt matrix can only be assigned to one IO device or one physical queue in the IO device. M≤ The number of I / O devices supported by the same compute instance for interrupt processing can be expanded. Preferably, N is an integer multiple of M*P. Thus, without considering reserved interrupt vectors and other system interrupts, a row or column in the interrupt matrix corresponding to each NUMA node can theoretically be allocated to N / (M*P) I / O devices or N / (M*P) physical queues within an I / O device. This helps reduce interrupt resource fragmentation and improves interrupt resource utilization.

[0097] In an embodiment where each NUMA node allocates a set number (M) of interrupt vectors to the IO device, the usage status of each interrupt vector in a target row or target column can be obtained from the global allocation information table corresponding to each of the multiple NUMA nodes. Subsequently, for any NUMA node, the usage status of the interrupt vectors provided by the processor core corresponding to that NUMA node can be obtained from the usage status of each interrupt vector in the target row or target column corresponding to that NUMA node. Based on the usage status of the interrupt vectors provided by the processor core corresponding to that NUMA node, M idle interrupt vectors can be allocated to the IO device from the interrupt vectors provided by the processor core corresponding to that NUMA node. Using the same method, M idle interrupt vectors can be allocated to each IO device from the interrupt vectors provided by the processor cores corresponding to all NUMA nodes. In this embodiment, M idle interrupt vectors are allocated to the IO device from the interrupt vectors provided by the processor core corresponding to each NUMA node. In this way, when the core of the computer system processes an interrupt, load balancing can be performed among multiple NUMA nodes, which can avoid the situation where some NUMA nodes are overloaded while other NUMA nodes are idle, and help improve interrupt resource utilization.

[0098] For an IO device that includes multiple physical queues, during the startup of the IO device, an interrupt vector can be applied for each physical queue in turn, and M interrupt vectors can be allocated to each physical queue according to the interrupt vector allocation method provided in the above embodiment. , allowing the same row or column in the interrupt matrix to be assigned to multiple physical queues in an I / O device. Compared to the traditional managed IRQ mechanism, where the same row or column in the interrupt matrix can only be assigned to one physical queue in an I / O device, the interrupt resource allocation method provided in this embodiment can expand the number of I / O devices that support interrupt processing in the same computing instance.

[0099] In an embodiment of the present application, when allocating M (i.e., a set number) interrupt vectors to an IO device from a target row or target column, M unused interrupt vectors can be determined from the target row or target column; and the M unused interrupt vectors are bound to the interrupt identifier allocated to the IO device, thereby allocating a set number (i.e., M) of interrupt vectors to the IO device.

[0100] In some embodiments, the online status of the M target processor cores to which the M interrupt vectors assigned to the IO device belong can also be monitored; and when the number of target processor cores in an online state reaches a set lower limit Q, the response to the offline operation of the target processor core in an online state is rejected. The set lower limit Q is a positive integer, 1≤Q<M. In some embodiments, Q=1. In particular, when the number of target processor cores in an online state reaches a set lower limit Q, the response to the offline operation of the target processor core in an online state is rejected, which can prevent the situation where all processors corresponding to the M interrupt vectors assigned to the IO device go offline, resulting in the unavailability of upper-layer application services, and helps to improve the service performance of the computing instance where the processor is located.

[0101] In order to facilitate understanding of the interrupt resource allocation method provided in the embodiment of the present application, the following is a detailed description using the NUMA architecture as an example of a computing instance where the processor is located. Figure 3 As shown, the interrupt resource allocation method mainly includes the following steps:

[0102] S1. In response to an interruption request sent by an IO device, an interruption identifier is allocated to the IO device.

[0103] S2. Determine the target row corresponding to the interruption identifier from the interruption matrix.

[0104] S3. Check whether the preset interrupt vector quantity parameter is configured with a valid quantity. If the interrupt vector quantity parameter is configured with a valid quantity, the valid quantity is determined as the set quantity M and the process continues with step S4. If the interrupt vector quantity parameter is configured with an invalid quantity, the process continues with step S10.

[0105] S4. Obtain the usage status of each interrupt vector in the target row from the global allocation information table corresponding to each of the multiple NUMA nodes.

[0106] S5. For each NUMA node, the usage status of the interrupt vector provided by the processor core corresponding to the NUMA node may be obtained from the usage status of each interrupt vector in the target row corresponding to the NUMA node.

[0107] S6. Determine whether the number of idle interrupt vectors provided by the processor core corresponding to the NUMA node is greater than or equal to M. If yes, execute step S7. If no, execute step S9.

[0108] S7. Determine M interrupt vectors in an idle state from the interrupt vectors provided by the processor core corresponding to the NUMA node.

[0109] S8. Bind the M interrupt vectors in the idle state corresponding to each NUMA node to the aforementioned interrupt identifier to complete the interrupt allocation.

[0110] S9. Reset the usage status of the interrupt vector allocated to the IO device in the global interrupt information table corresponding to each NUMA node to an idle state.

[0111] S10: Check whether all interrupt vectors in the target row that are in use are released. If all are released, execute step S11; if not, execute step S12.

[0112] S11. Allocate all interrupt vectors contained in the target row to the IO device.

[0113] S12. End the interrupt allocation.

[0114] It should be noted that the execution entity of each step of the method provided in the above embodiment can be the same device, or the method can be executed by different devices. For example, the execution entity of steps 201 and 202 can be device A; for another example, the execution entity of step 201 can be device A, and the execution entity of step 202 can be device B; and so on.

[0115] In addition, some of the processes described in the above embodiments and the accompanying drawings include multiple operations that appear in a specific order. However, it should be clearly understood that these operations may not be executed in the order in which they appear in this document or may be executed in parallel. The sequence numbers of the operations, such as 201, 202, etc., are merely used to distinguish between different operations and do not represent any execution order. In addition, these processes may include more or fewer operations, and these operations may be executed sequentially or in parallel.

[0116] Accordingly, an embodiment of the present application further provides a computer-readable storage medium storing computer instructions. When the computer instructions are executed by one or more processors, the one or more processors are caused to execute the steps in the interrupt resource allocation method provided in the aforementioned embodiments.

[0117] The computer-readable storage medium may be volatile or non-volatile, or a combination thereof, and may be removable or non-removable. Examples of computer-readable storage media include, but are not limited to, phase-change random access memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium.

[0118] An embodiment of the present application also provides a computer program product, comprising a computer program. When the computer program is executed by one or more processors, the one or more processors are caused to execute the steps of the interrupt resource allocation method provided in the aforementioned embodiments.

[0119] In the embodiments of this application, the specific implementation form of the computer program product is not limited. In some embodiments, the computer program product may be implemented as an application (APP), a mini-program, a computer-side client, a program module, a plug-in, an installation package, a software development kit (SDK), an optical disk image file (such as an ISO file), a plug-in, or software in the form of Software as a Service (SaaS), etc., but is not limited thereto.

[0120] The computer program product should be understood to implement each process or a combination of multiple processes in the above-mentioned method processes by computer programs or instructions. In addition, these computer programs or instructions can be applied to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device, so that the processor of the general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing device can be implemented as a device to implement the corresponding functions in the above-mentioned method embodiments.

[0121] Figure 4 This is a schematic diagram of the structure of the electronic device provided in the embodiment of the present application. Figure 4 As shown, the electronic device includes a memory 40a, a processor 40b, and an I / O device 40c. The memory 40a is used to store computer programs and can be configured to store various other data to support operations on the computing platform. Examples of such data include instructions for any application or method operating on the electronic device, data structures, contact data, phone book data, messages, images, videos, etc.

[0122] The processor 40b is coupled to the memory 40a and the IO device 40c, and is used to execute a computer program to execute the steps of the interrupt resource allocation method provided in the above embodiments. The specific implementation of each step can be found in the relevant description of the above embodiments, which will not be repeated here.

[0123] In some optional embodiments, such as Figure 4 As shown, the electronic device may further include optional components such as a communication component 40d, a power component 40e, a display component 40f and an audio component 40g. Figure 4 Some components are shown schematically, and this does not mean that the electronic device must include Figure 4 All components shown do not mean that the electronic device can only include Figure 4 Components shown.

[0124] in addition, Figure 4 The components within the dashed box are optional, not mandatory, and may vary depending on the form factor of the electronic device. The electronic device of this embodiment can be implemented as a terminal device such as a desktop computer, laptop computer, mobile phone, or IoT device; or as a server device such as a traditional server, cloud server, or server cluster.

[0125] In the embodiments of the present application, the implementation of the processor can refer to the relevant content of the aforementioned embodiments and will not be repeated here. The memory is used to store computer programs and can be configured to store various other data to support operations on the device where it is located. Among them, the processor can execute the computer program stored in the memory to implement the corresponding control logic. The memory can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), electrically erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0126] In an embodiment of the present application, the communication component is configured to facilitate wired or wireless communication between the device in which it is located and other devices. The device in which the communication component is located can access a wireless network based on a communication standard, such as 2G or 3G, 4G, 5G, or a combination thereof. In an exemplary embodiment, the communication component receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel.

[0127] In embodiments of the present application, the display assembly may include a liquid crystal display (LCD) and a touch panel (TP). If the display assembly includes a touch panel, the display assembly may be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touches, slides, and gestures on the touch panel. The touch sensors may not only sense the boundaries of a touch or slide action, but also the duration and pressure associated with the touch or slide action.

[0128] In embodiments of the present application, a power supply assembly is configured to provide power to various components of the device in which it is located. The power supply assembly may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the device in which the power supply assembly is located.

[0129] In an embodiment of the present application, the audio component may be configured to output and / or input audio signals. For example, the audio component includes a microphone (MIC), and when the device where the audio component is located is in an operating mode, such as call mode, recording mode, and voice recognition mode, the microphone is configured to receive external audio signals. The received audio signal may be further stored in a memory or sent via a communication component. In some embodiments, the audio component further includes a speaker for outputting audio signals. For example, for a device with a language interaction function, voice interaction with the user may be achieved through the audio component.

[0130] It should be noted that the descriptions such as "first" and "second" in this article are used to distinguish different messages, devices, modules, etc., and do not represent the order of precedence, nor do they limit "first" and "second" to different types.

[0131] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a..." does not preclude the presence of additional identical elements in the process, method, commodity, or apparatus comprising the aforementioned elements.

[0132] The above contents are merely embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. A computer system, characterized in that: include: A processor and an input / output device; the processor and the input / output device are electrically connected; the processor includes a plurality of processor cores; The processor core provides multiple interrupt vectors; The interrupt vectors provided by the multiple processor cores form an interrupt matrix; an interrupt vector quantity parameter is added to the core of the computer system; the interrupt vector quantity parameter is used to configure the number of processor cores to which the managed interrupt mechanism is affinity; the interrupt vector quantity parameter is configured as a set number; the set number is greater than or equal to 1 and less than or equal to the total number of the processor cores divided by 2 rounded down; The processor is configured to: determine, in response to an interrupt application request from the input / output device, a target row or target column corresponding to the input / output device from the interrupt matrix; and allocate a set number of interrupt vectors in an idle state to the input / output device from the target row or target column.

2. A method for allocating interrupt resources, applicable to a processor, characterized in that: The processor is electrically connected to an input / output device; the processor includes multiple processor cores; the processor cores provide multiple interrupt vectors; the interrupt vectors provided by the multiple processor cores form an interrupt matrix; an interrupt vector quantity parameter is added to the core of the computer system where the processor is located; the interrupt vector quantity parameter is used to configure the number of processor cores to which the managed interrupt mechanism is affinity; the interrupt vector quantity parameter is configured to be a set number; The set number is greater than or equal to 1 and less than or equal to the total number of processor cores divided by 2 rounded down; The method comprises: In response to an interrupt application request from the input / output device, determining a target row or a target column corresponding to the input / output device from the interrupt matrix; A set number of interrupt vectors in an idle state are allocated to the input / output device from the target row or the target column.

3. The method according to claim 2, characterized in that Allocating a set number of interrupt vectors in an idle state to the input / output device from the target row or target column includes: Obtaining a global allocation information table corresponding to the interrupt matrix; the global allocation information table records the usage status of each interrupt vector in the interrupt matrix; Obtaining, from the global allocation information table, a usage status of each interrupt vector in the target row or target column; According to the usage status of each interrupt vector in the target row or target column, a set number of interrupt vectors in an idle state are allocated to the input / output device from the target row or target column.

4. The method according to claim 2, characterized in that The method further comprises: If the number of interrupt vectors in the target row or target column that are in an idle state is less than the set number, detecting whether the interrupt vectors in the target row or target column that are in a used state are released; If all the interrupt vectors in the used state are released, all the interrupt vectors included in the target row or the target column are allocated to the input / output device.

5. The method according to claim 3, characterized in that The method further comprises: The global allocation information table is established in response to a startup operation of an operating system in the processor.

6. The method according to claim 5, characterized in that The computing instance to which the processor belongs is a non-uniform memory access NUMA architecture; the computing instance includes at least one NUMA node; the set number is less than or equal to the total number of the processor cores divided by the total number of the NUMA nodes, and then divided by 2, rounded down; The step of establishing the global allocation information table in response to a startup operation of the operating system in the processor includes: In response to a startup operation of the operating system, determining a processor core corresponding to each of the at least one NUMA nodes; For any NUMA node among the at least one NUMA node, a global allocation information table corresponding to the any NUMA node is established according to an interrupt vector provided by a processor core corresponding to the any NUMA node.

7. The method according to claim 6, characterized in that There are multiple NUMA nodes; and obtaining the usage status of each interrupt vector in the target row or target column from the global allocation information table includes: Obtaining the usage status of each interrupt vector in the target row or target column from the global allocation information table corresponding to each of the multiple NUMA nodes; The allocating a set number of interrupt vectors in an idle state from the target row or target column to the input / output device according to the usage status of each interrupt vector in the target row or target column includes: For any NUMA node, obtaining the usage status of the interrupt vector provided by the processor core corresponding to the any NUMA node from the usage status of each interrupt vector in the target row or target column corresponding to the any NUMA node; According to the usage status of the interrupt vectors provided by the processor core corresponding to any NUMA node, the set number of interrupt vectors in the idle state are allocated to the input / output device from the interrupt vectors provided by the processor core corresponding to any NUMA node.

8. The method according to any one of claims 2 to 7, characterized in that: Before allocating a set number of interrupt vectors from the target row or target column to the input / output device, the method further includes: Check whether the preset interrupt vector quantity parameter is configured with a valid quantity; If the interrupt vector quantity parameter is configured with a valid quantity, the valid quantity is determined as the set quantity; or if the interrupt vector quantity parameter is configured with an invalid quantity, all interrupt vectors included in the target row or the target column are allocated to the input / output device.

9. The method according to any one of claims 2 to 7, characterized in that: The method further comprises: Monitoring online status of a set number of target processor cores to which the set number of interrupt vectors belong; If the number of target processor cores in an online state reaches a set lower limit, the offline operation of the target processor core in an online state is rejected.

10. An electronic device, characterized in that: include: Memory, processor and input and output devices; wherein the memory is used to store computer programs; The processor is coupled to the memory and the input and output devices, and is configured to execute the computer program to perform the steps of the method according to any one of claims 2 to 9.

11. A computer-readable storage medium storing computer instructions, characterized in that: When the computer instructions are executed by one or more processors, the one or more processors are caused to perform the steps of the method according to any one of claims 2 to 9.

12. A computer program product, characterized in that The method comprises a computer program which, when executed by one or more processors, causes the one or more processors to perform the steps of the method according to any one of claims 2 to 9.

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