Big data communication method, device and equipment under intelligent driving system and storage medium

Abstract

The embodiment of the invention provides a big data communication method and device under an intelligent driving system, equipment and a storage medium. The method comprises the following steps: after monitoring new bare data, a producer determines a target memory block according to the states of a plurality of shared memory blocks, writes the bare data into the target memory block, modifies the state of the target memory block, and synchronizes an index of the target memory block to a consumer annular queue through an Nvscissync synchronization mechanism, and a consumer queues the target memory block based on the index of the target memory block. And accessing the data in the target memory block in a read-only manner. By means of the method, zero copy is achieved, simultaneous access of multiple downstream modules is supported, the data distribution efficiency is improved, delay is reduced, and system space resources are saved.

Description

Technical Field

[0001] The present application relates to the field of intelligent driving technology, and in particular to a big data communication method, device, equipment and storage medium under an intelligent driving system. Background Art

[0002] With the development of current social life, software functions are becoming more and more abundant, the scale of software is becoming larger and larger, and it is becoming more and more difficult to maintain. The software is divided into multiple sub-functional modules, each of which is a process. The processes exchange and synchronize data through some communication method to achieve a larger software function.

[0003] In the intelligent driving system, large-scale data communication in a multi-process architecture usually adopts a communication protocol specifically used for in-vehicle network communication, such as Scalable service-oriented middleware over IP (SOME / IP). However, this method requires many copies, resulting in large delays, consuming a lot of system resources, and seriously reducing system performance.

[0004] To sum up, how to improve the efficiency of multi-process large data transmission under the intelligent driving system is a technical problem that needs to be solved urgently in this field. Summary of the invention

[0005] The embodiments of the present application provide a big data communication method, device, equipment and storage medium in an intelligent driving system, which are used to solve the problem of how to improve the efficiency of multi-process large data transmission in an intelligent driving system.

[0006] In a first aspect, an embodiment of the present application provides a big data communication method in an intelligent driving system, which is applied to any producer in the intelligent driving system, and the method includes:

[0007] After detecting new raw data, determining a target memory block according to the states of the multiple shared memory blocks, where the states are Writable or Readable, Writable means writable, and Readable means readable;

[0008] Writing the raw data into the target memory block and modifying the state of the target memory block;

[0009] The index of the target memory block is synchronized to the consumer ring queue through the Nvscisync synchronization mechanism.

[0010] In a possible implementation, the method further includes:

[0011] Establish NvSciIpc channel and send handshake requests to multiple consumers;

[0012] After successfully shaking hands with each consumer, receiving the memory configuration requirements sent by each consumer through the NvSciIpc channel, the memory configuration requirements including memory type, access rights, memory alignment requirements and security attributes;

[0013] Coordinate processing based on memory configuration requirements of all consumers to obtain configuration information, wherein the configuration information includes memory size, memory type, and access mode;

[0014] Based on the configuration information, applying for the multiple shared memory blocks;

[0015] The attribute information of the multiple shared memory blocks is sent to all consumers, wherein the attribute information includes the index, memory size, memory block address, memory type and access permission of the shared memory block.

[0016] In a possible implementation, the method further includes:

[0017] receiving access completion signals sent by the multiple consumers;

[0018] Based on the access completion signal of each consumer, the state of the target memory block is changed to Writable.

[0019] In a possible implementation manner, after the new raw data is detected, determining the target memory block according to the states of the multiple shared memory blocks includes:

[0020] Read the status of each shared memory block and determine the shared memory block with a Writable status as the initial memory block;

[0021] The shared memory block with the earliest release time in the initial memory blocks is determined as the target memory block.

[0022] In a second aspect, an embodiment of the present application provides a big data communication method under an intelligent driving system, which is applied to any consumer under the intelligent driving system, and the method includes:

[0023] Monitor the consumer ring queue and obtain the index of the target memory block through the Nvscisync synchronization mechanism;

[0024] Based on the index of the target memory block, data in the target memory block is accessed in a read-only manner.

[0025] In a possible implementation, the method further includes:

[0026] Receive a handshake request sent by the producer through the NvSciIpc channel;

[0027] After successfully shaking hands with the producer, sending a memory configuration requirement to the producer through the NvSciIpc channel, the memory configuration requirement including memory type, access rights, memory alignment requirements and security attributes;

[0028] Receive attribute information of multiple shared memory blocks sent by the producer, wherein the attribute information includes an index of the shared memory block, a memory size, a memory block address, a memory type, and access rights;

[0029] Based on the attribute information of each shared memory block, local cross-process mapping is performed.

[0030] In a possible implementation, the method further includes:

[0031] After the data access is completed, an access completion signal is sent to the producer through the Nvscisync synchronization mechanism.

[0032] In a third aspect, an embodiment of the present application provides a big data communication device under an intelligent driving system, including:

[0033] A determination module is used to determine a target memory block according to the status of multiple shared memory blocks after detecting new raw data, wherein the status is Writable or Readable, Writable means writable, and Readable means readable;

[0034] A first modification module, used for writing the raw data into the target memory block and modifying the state of the target memory block;

[0035] The first sending module is used to synchronize the index of the target memory block to the consumer ring queue through the Nvscisync synchronization mechanism.

[0036] In a possible implementation, the device further includes:

[0037] Establish a module for establishing NvSciIpc channels and sending handshake requests to multiple consumers;

[0038] A first receiving module, configured to receive a memory configuration requirement sent by each consumer through the NvSciIpc channel after successfully handshaking with each consumer, wherein the memory configuration requirement includes a memory type, access rights, memory alignment requirements, and security attributes;

[0039] A coordination module, used for performing coordination processing based on the memory configuration requirements of all consumers to obtain configuration information, wherein the configuration information includes memory size, memory type and access mode;

[0040] An application module, used for applying for the multiple shared memory blocks based on the configuration information;

[0041] The second sending module is used to send the attribute information of the multiple shared memory blocks to all consumers, wherein the attribute information includes the index, memory size, memory block address, memory type and access permission of the shared memory block.

[0042] In a possible implementation, the device further includes:

[0043] A second receiving module, configured to receive access completion signals sent by the multiple consumers;

[0044] The second modification module is used to modify the state of the target memory block to Writable based on the access completion signal of each consumer.

[0045] In a possible implementation manner, the determining module is specifically configured to:

[0046] Read the status of each shared memory block and determine the shared memory block with a Writable status as the initial memory block;

[0047] The shared memory block with the earliest release time in the initial memory blocks is determined as the target memory block.

[0048] In a fourth aspect, an embodiment of the present application provides a big data communication device under an intelligent driving system, including:

[0049] The acquisition module is used to monitor the consumer ring queue and obtain the index of the target memory block through the Nvscisync synchronization mechanism;

[0050] An access module is used to access the data in the target memory block in a read-only manner based on the index of the target memory block.

[0051] In a possible implementation, the device further includes:

[0052] A first receiving module, configured to receive a handshake request sent by the producer through an NvSciIpc channel;

[0053] A first sending module is used to send a memory configuration requirement to the producer through the NvSciIpc channel after successfully shaking hands with the producer, wherein the memory configuration requirement includes a memory type, access rights, memory alignment requirements and security attributes;

[0054] A second receiving module is used to receive attribute information of multiple shared memory blocks sent by the producer, wherein the attribute information includes an index of the shared memory block, a memory size, a memory block address, a memory type, and access rights;

[0055] The mapping module is used to perform local cross-process mapping based on the attribute information of each shared memory block.

[0056] In a possible implementation, the device further includes:

[0057] The second sending module is used to send an access completion signal to the producer through the Nvscisync synchronization mechanism after the data access is completed.

[0058] In a fifth aspect, an embodiment of the present application provides an electronic device, including: a memory, a processor;

[0059] The memory stores computer-executable instructions;

[0060] The processor executes the computer-executable instructions stored in the memory, so that the processor executes various possible implementations of the first and second aspects as described above.

[0061] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement various possible implementations of the first and second aspects above.

[0062] In a seventh aspect, an embodiment of the present application provides a computer program product, including a computer program, which, when executed by a processor, implements various possible implementations of the first and second aspects above.

[0063] The big data communication method, device, equipment and storage medium under the intelligent driving system provided by the embodiment of the present application, after the producer monitors the new raw data, it determines the target memory block according to the status of multiple shared memory blocks, writes the raw data to the target memory block, and modifies the status of the target memory block. Through the Nvscisync synchronization mechanism, the index of the target memory block is synchronized to the consumer ring queue. The consumer accesses the data in the target memory block in a read-only manner based on the index of the target memory block. The above method realizes zero copy and supports simultaneous access by multiple downstream modules, which improves the efficiency of data distribution, reduces latency, and saves system space resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0065] Figure 1 Schematic diagram of the process of the big data communication method under the intelligent driving system provided in this application Figure 1 ;

[0066] Figure 2Schematic diagram of the process of the big data communication method under the intelligent driving system provided in this application Figure 2 ;

[0067] Figure 3 Schematic diagram of the process of the big data communication method under the intelligent driving system provided in this application Figure 3 ;

[0068] Figure 4 Schematic diagram of the process of the big data communication method under the intelligent driving system provided in this application Figure 4 ;

[0069] Figure 5 A schematic diagram of the structure of a big data communication device under the intelligent driving system provided in this application;

[0070] Figure 6 A schematic diagram of the structure of a big data communication device in another intelligent driving system provided in this application;

[0071] Figure 7 A schematic diagram of the structure of the electronic device provided in this application.

[0072] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0073] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0074] With the development of current social life, software functions are becoming more and more abundant, the scale of software is becoming larger and larger, and it is becoming more and more difficult to maintain. The software is divided into multiple sub-functional modules, each sub-module is a process, and the processes use some communication method to exchange and synchronize data to achieve a larger software function. Corresponding to this is a multi-threaded architecture. That is, each sub-module is a thread, and there are multiple threads in a process, which work together to complete specific functions. Multi-process architecture and multi-threaded architecture each have their own advantages and disadvantages. Among them, the main advantage of multi-process architecture is that the crash of a process does not affect other processes, and the crashed process only needs to be restarted to restore to normal working state. A major disadvantage is that the communication efficiency is low. The multi-threaded architecture is the opposite.

[0075] Solve the communication efficiency problem of large amounts of data in multi-process architecture in the intelligent driving system. Common inter-process communication solutions include:

[0076] Communicate through the SOME / IP protocol. This communication is specially designed for vehicle network communication and has service discovery and service binding mechanisms. This protocol is an application layer protocol based on the IP protocol and is mainly service-oriented communication. Take the distribution of raw data from 4-channel lidars to multiple downstreams as an example. If the data is compressed before being sent downstream, each downstream consumer needs to decompress the data after receiving it, which will take two additional periods of time, and there will be many copies in this process, resulting in large delays and consuming a lot of system resources; if the data is not compressed, then due to the large amount of data that needs to be transmitted, the delay is still very large, and due to the huge amount of data copies, a large amount of memory bandwidth will be consumed, seriously reducing system performance.

[0077] The communication scheme of the Data Distribution Service (DDS). In single-machine communication, the underlying layer uses shared host memory. This method is efficient and excellent in most systems, but under DriveOS, NVIDIA provides a more efficient mechanism. Because the unified computing device architecture (Compute Unified Device Architecture, CUDA) is used for consumption, on DriveOS, additional copies between device memory and host memory are required, and there is a large room for performance improvement.

[0078] In response to the above problems, the present application provides a big data communication method, device, equipment and storage medium under an intelligent driving system, which achieves the purpose of improving the efficiency of multi-process large data transmission under an intelligent driving system. Specifically, the existing SOME / IP protocol communication is specially designed for vehicle network communication, with service discovery and service binding mechanisms. The protocol is an application layer protocol based on the IP protocol, which is mainly service-oriented communication. If the data is compressed before being sent downward, each downstream consumer needs to decompress the data after receiving it, which will add two additional periods of time, and there are many copies in this process, resulting in large delays and large consumption of system resources; if the data is not compressed, then due to the large amount of data to be transmitted, the delay is still large, and due to the huge amount of data copies, a large amount of memory bandwidth will be consumed, seriously reducing system performance; for the DDS communication solution, the efficiency is low under DriveOS. Considering these problems, the inventor studied whether it is possible to map multiple Nvscibuf shared memory blocks to consumers, and each shared memory block maps a device memory pointer and a host memory pointer, and then write a large amount of raw data into the shared memory block, and transfer ownership to the consumer through the Nvscisync synchronization signal. After the consumer completes the processing, it sends an Nvscisync synchronization signal to inform the producer that the consumption is complete, so as to realize the reuse of memory blocks, thereby efficiently distributing data to multiple consumers, saving system resources and reducing latency. Based on this, the technical solution of this application is proposed.

[0079] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0080] Figure 1 Schematic diagram of the process of the big data communication method under the intelligent driving system provided in this application Figure 1 ,like Figure 1 As shown, the method includes:

[0081] S101: After detecting new raw data, the producer determines a target memory block according to the status of multiple shared memory blocks.

[0082] In this step, in order to achieve efficient data distribution, the producer needs to determine the target memory block after detecting new raw data.

[0083] Specifically, the state of each shared memory block is read, a shared memory block whose state is Writable is determined as the initial memory block, and a shared memory block whose release time is the earliest in the initial memory blocks is determined as the target memory block.

[0084] Exemplarily, the producer receives a new frame of raw data through a sensor interface, such as a lidar driver, with a data volume of 4MB and a timestamp of T1. The producer then performs an integrity check on the data to ensure that the data is not damaged, wherein the check may be a cyclic redundancy check (CRC).

[0085] Optionally, the producer maintains a memory block status table, where each entry can contain the following information:

[0086] Memory block index (e.g. Block_001).

[0087] Current state (Writable or Readable), where Writable means writable and Readable means readable.

[0088] The last used timestamp (e.g. T0).

[0089] A list of associated consumers (e.g. [Consumer_A, Consumer_B]).

[0090] Optionally, a priority tag (eg, high priority or low priority) may also be included.

[0091] The producer scans all memory blocks in the state table in order, and selects the initial memory block with the Writable state, and then determines the initial memory block with the earliest release time as the target memory block.

[0092] S102: Write the raw data into the target memory block, and modify the state of the target memory block.

[0093] In this step, after the target memory block is determined, the raw data is written into the target memory block and its state is rewritten.

[0094] Specifically, writing raw data to the target memory block may include the following two methods:

[0095] Host memory write: If the data comes from the CPU, it is written directly through the host memory pointer.

[0096] Device memory write: If the data needs GPU preprocessing, write to the device memory pointer via DMA (direct memory access).

[0097] After writing is completed, the state of the target memory block is changed from Writable to Readable.

[0098] S103: Synchronize the index of the target memory block to the consumer ring queue through the Nvscisync synchronization mechanism.

[0099] In this step, after the raw data is written to the target memory block, in order to enable multiple consumers to access it efficiently, reduce latency, and achieve zero copy, the index of the target memory block is synchronized to the consumer ring queue through the Nvscisync synchronization mechanism, thereby transferring ownership to downstream consumers.

[0100] S104: The consumer accesses the data in the target memory block in a read-only manner based on the index of the target memory block.

[0101] In this step, after monitoring the index update in the message queue, the consumer locates the target memory block according to the updated index, and then directly accesses the data in the target memory block.

[0102] Optionally, after obtaining the read permission of Nvscibuf, downstream consumers can directly use the pointer of Nvscibuf to process the data. Because there is a device memory pointer, downstream consumers can also directly use CUDA for efficient processing.

[0103] The big data communication method under the intelligent driving system provided by the embodiment of the present application is that after the producer monitors the new raw data, it determines the target memory block according to the status of multiple shared memory blocks, writes the raw data to the target memory block, and modifies the status of the target memory block. Through the Nvscisync synchronization mechanism, the index of the target memory block is synchronized to the consumer ring queue. The consumer accesses the data in the target memory block in a read-only manner based on the index of the target memory block. The above method realizes zero copy and supports simultaneous access by multiple downstream modules, which improves the efficiency of data distribution, reduces latency, and saves system space resources.

[0104] Figure 2 Schematic diagram of the process of the big data communication method under the intelligent driving system provided in this application Figure 2 ,like Figure 2 As shown, based on the above embodiment, the method further includes:

[0105] S201: The producer establishes an NvSciIpc channel and sends handshake requests to multiple consumers.

[0106] In this step, a communication channel is established between the producer and the consumer, laying the foundation for subsequent configuration negotiation and data transmission.

[0107] Specifically, the producer can call NvSciIpcOpenEndpoint to create an IPC endpoint (such as / var / nvsciipc / lidar_stream).

[0108] Send a handshake request to all consumers via NvSciIpcConnect, including the protocol version number and authentication information.

[0109] Use the heartbeat mechanism to detect the consumer connection status (such as sending a heartbeat packet every 1 second).

[0110] Optionally, the producer can also maintain a connection status table to record the response status of each consumer. If the consumer does not respond within the timeout period, a retry or error callback is triggered.

[0111] S202: After successfully shaking hands with the producer, the consumer sends a memory configuration request to the producer through the NvSciIpc channel.

[0112] In this step, in order to ensure that the subsequently allocated memory blocks are compatible with all consumers, after the handshake between the consumer and the producer is successful, the consumer can pass the consumer's local memory requirements, that is, the memory configuration requirements, to the producer, where the memory configuration requirements include memory type, access rights, memory alignment requirements and security attributes.

[0113] S203: The producer coordinates and processes the memory configuration requirements of all consumers to obtain configuration information.

[0114] In this step, a unified memory configuration scheme is generated by negotiating the hardware limitations and functional requirements of all consumers to ensure that the physical properties of the memory block (such as size and permissions) are acceptable to all consumers.

[0115] Specifically, the producer performs a logical “AND” operation on the attribute lists of all consumers to generate an intersection list that satisfies all constraints.

[0116] For example, memory size: take the maximum value among all requirements;

[0117] Access rights: take the most stringent permission (if any consumer requires ReadOnly, the final permission is ReadOnly);

[0118] Memory Type: Device is preferred (if there are consumers that need GPU access).

[0119] Optionally, if coordination fails (e.g. consumer A requires 256MB, but consumer B only supports 128MB), dynamic downgrade negotiation or error reporting is triggered.

[0120] S204: The producer applies for multiple shared memory blocks based on the configuration information.

[0121] S205: The producer sends the attribute information of the multiple shared memory blocks to all consumers.

[0122] According to the coordinated configuration, apply for physical memory resources and complete initialization to provide a reusable memory pool for subsequent data distribution. Among them, the number of shared memory blocks applied for can be determined according to the actual situation, and the shared memory blocks applied for are Nvscibuf memory blocks. And after applying for shared memory blocks, each memory block is mapped to the host pointer (CPU access) through NvSciBufGetCpuPtr and the device pointer (GPU access) through cuMemHostRegister. The memory block is marked as Writable, indicating that the producer can write data.

[0123] The physical description information of the memory block is passed to the consumer so that it can complete the mapping within the address space of the current process and achieve zero-copy access.

[0124] NvSciIpcSend is used to send serialized data, i.e., attribute information of multiple shared memory blocks, to all consumers, using multicast mode to reduce the number of transmissions. The attribute information includes the index, memory size, memory block address, memory type, and access rights of the shared memory block.

[0125] S206: The consumer performs local cross-process mapping based on the attribute information of each shared memory block.

[0126] In this step, the memory block requested by the producer is mapped to the consumer's local address space, allowing the consumer to directly access the data and avoid copying overhead.

[0127] Specifically, first call NvSciBufObjImport to deserialize the received memory descriptor and verify the access token and permissions. Secondly, for host memory, get the Host pointer through NvSciBufGetCpuPtr; for device memory, call CUDA API cuMemHostRegister to register the Device pointer. Finally, create a local memory pool state table to record the index, address, and current state (such as Readable / Writable) of each memory block.

[0128] The big data communication method under the intelligent driving system provided in the embodiment of the present application is that the producer establishes an NvSciIpc channel and sends a handshake request to multiple consumers. After the consumer successfully shakes hands with the producer, it sends a memory configuration requirement to the producer through the NvSciIpc channel. The producer coordinates and processes the memory configuration requirements of all consumers to obtain configuration information. The producer applies for multiple shared memory blocks based on the configuration information. The producer sends the attribute information of multiple shared memory blocks to all consumers. The consumers perform local cross-process mapping based on the attribute information of each shared memory block. The above method eliminates the Host↔Device memory copy through the cross-process mapping of NvSciBuf, reduces latency, has high reliability, and improves resource utilization.

[0129] Figure 3 Schematic diagram of the process of the big data communication method under the intelligent driving system provided in this application Figure 3 ,like Figure 3 As shown, based on the above embodiments, the method further includes:

[0130] S301: After completing data access, the consumer sends an access completion signal to the producer through the Nvscisync synchronization mechanism.

[0131] In this step, in order to save system resources and achieve efficient reuse of memory blocks, after the consumer completes data access, it releases ownership and notifies the producer that the current consumer has completed data reading, allowing the memory block to be reused.

[0132] S302: The producer changes the state of the target memory block to Writable based on the access completion signal of each consumer.

[0133] In this step, after receiving the access completion signal from the consumer, the producer waits until all consumers have completed the access and then changes the state of the target memory block from Readable to Writable.

[0134] Optionally, you can use an atomic reference counter to record the number of currently active consumers. After the producer receives the access completion signal, the counter decreases. When the counter reaches zero, the memory block state automatically switches to Writable. If the consumer crashes or times out without releasing the signal (for example, more than 5ms), the producer forcibly reclaims the memory block through heartbeat detection.

[0135] For example, the producer listens to events:

[0136] - Receive the completion signal of consumer A for memory block 3 → reference counter 2 → 1,

[0137] - Receive the completion signal of consumer B for memory block 3 → reference counter 1 → 0,

[0138] - Set the state of memory block 3 to Writable and add it to the idle queue.

[0139] The next frame of lidar data is written to memory block 3 first (cache locality optimization).

[0140] In the big data communication method under the intelligent driving system provided in the embodiment of the present application, after the consumer completes the data access, the Nvscisync synchronization mechanism sends an access completion signal to the producer, and based on the access completion signal of each consumer, the state of the target memory block is changed to Writable. The above method reduces the delay, improves the data processing efficiency, and saves system resources.

[0141] Figure 4 Schematic diagram of the process of the big data communication method under the intelligent driving system provided in this application Figure 4 ,like Figure 4 As shown, based on the above embodiment, step S101 specifically includes:

[0142] S401: Read the status of each shared memory block, and determine the shared memory block with a Writable status as the initial memory block.

[0143] S402: Determine the shared memory block with the earliest release time in the initial memory blocks as the target memory block.

[0144] In order to determine the target memory block, the earliest released memory block in the writable state may be determined as the target memory block.

[0145] Optionally, priority weights can be assigned based on the functional importance of the consumer module (e.g. collision warning = 10, data logging = 3). The system gives priority to memory blocks released by high-priority consumers to ensure that key modules quickly acquire new data. This can reduce latency in emergency braking scenarios.

[0146] You can also record the data write timestamp of the memory block and calculate the data freshness (current time - write time). Give priority to the memory block with the best freshness (such as <5ms) to ensure that the algorithm processes the latest road conditions. This method can improve data timeliness when applied in high-speed scenarios.

[0147] The big data communication method under the intelligent driving system provided in the embodiment of the present application reads the status of each shared memory block, determines the shared memory block with the status of Writable as the initial memory block, and determines the shared memory block with the earliest release time in the initial memory block as the target memory block. The above method reduces the memory allocation overhead, avoids memory fragmentation, and improves resource utilization efficiency.

[0148] Figure 5 This is a schematic diagram of the structure of the big data communication device under the intelligent driving system provided in this application, such as Figure 5 As shown, the big data communication device 500 under the intelligent driving system specifically includes:

[0149] The determination module 501 is used to determine the target memory block according to the status of multiple shared memory blocks after monitoring the new raw data. The status is Writable or Readable. Writable means writable, and Readable means readable.

[0150] The first modifying module 502 is used to write the raw data into the target memory block and modify the state of the target memory block.

[0151] The first sending module 503 is used to synchronize the index of the target memory block to the consumer ring queue through the Nvscisync synchronization mechanism.

[0152] In a possible implementation, the big data communication device 500 in the intelligent driving system further includes:

[0153] The establishing module 504 is used to establish an NvSciIpc channel and send handshake requests to multiple consumers.

[0154] The first receiving module 505 is used to receive the memory configuration requirements sent by each consumer through the NvSciIpc channel after successfully handshaking with each consumer, and the memory configuration requirements include memory type, access rights, memory alignment requirements and security attributes.

[0155] The coordination module 506 is used to perform coordination processing based on the memory configuration requirements of all consumers to obtain configuration information, where the configuration information includes memory size, memory type and access mode.

[0156] The application module 507 is used to apply for the multiple shared memory blocks based on the configuration information.

[0157] The second sending module 508 is used to send the attribute information of the multiple shared memory blocks to all consumers, where the attribute information includes the index, memory size, memory block address, memory type and access permission of the shared memory block.

[0158] In a possible implementation, the big data communication device 500 in the intelligent driving system further includes:

[0159] The second receiving module 509 is used to receive access completion signals sent by multiple consumers.

[0160] The second modification module 510 is used to modify the state of the target memory block to Writable based on the access completion signal of each consumer.

[0161] In a possible implementation, the determination module 501 is specifically configured to:

[0162] Read the status of each shared memory block and determine the shared memory block with a Writable status as the initial memory block;

[0163] The shared memory block with the earliest release time in the initial memory block is determined as the target memory block.

[0164] The big data communication device under the intelligent driving system provided in this embodiment can execute the producer-side solution in the big data communication method under the intelligent driving system provided in the above-mentioned method embodiments. Its implementation principle and technical effect are similar, and this embodiment will not be repeated here.

[0165] Figure 6 A structural diagram of a big data communication device in another intelligent driving system provided in this application is shown in FIG. Figure 6 As shown, the big data communication device 600 under the intelligent driving system specifically includes:

[0166] The acquisition module 601 is used to monitor the consumer ring queue and obtain the index of the target memory block through the Nvscisync synchronization mechanism.

[0167] The access module 602 is used to access the data in the target memory block in a read-only manner based on the index of the target memory block.

[0168] In a possible implementation, the big data communication device 600 in the intelligent driving system further includes:

[0169] The first receiving module 603 is used to receive a handshake request sent by the producer through the NvSciIpc channel.

[0170] The first sending module 604 is used to send a memory configuration requirement to the producer through the NvSciIpc channel after successfully shaking hands with the producer. The memory configuration requirement includes memory type, access rights, memory alignment requirements and security attributes.

[0171] The second receiving module 605 is used to receive attribute information of multiple shared memory blocks sent by the producer, where the attribute information includes the index, memory size, memory block address, memory type and access permission of the shared memory block.

[0172] The mapping module 606 is used to perform local cross-process mapping based on the attribute information of each shared memory block.

[0173] In a possible implementation, the big data communication device 600 in the intelligent driving system further includes:

[0174] The second sending module 607 is used to send an access completion signal to the producer through the Nvscisync synchronization mechanism after the data access is completed.

[0175] The big data communication device under the intelligent driving system provided in this embodiment can execute the consumer-side solution in the big data communication method under the intelligent driving system provided in the above-mentioned method embodiments. Its implementation principle and technical effect are similar, and this embodiment will not be repeated here.

[0176] Figure 7 This is a schematic diagram of the structure of the electronic device provided in this application. Figure 7 As shown, the electronic device 700 provided in this embodiment includes: at least one processor 701 and a memory 702. Optionally, the device 700 also includes a communication component 703. The processor 701, the memory 702 and the communication component 703 are connected via a bus 704.

[0177] In a specific implementation process, at least one processor 701 executes the computer-executable instructions stored in the memory 702, so that at least one processor 701 executes the above method.

[0178] The specific implementation process of the processor 701 can be found in the above method embodiment, and its implementation principle and technical effect are similar, so this embodiment will not be repeated here.

[0179] In the above embodiments, it should be understood that the processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the invention can be directly implemented as a hardware processor, or can be implemented by a combination of hardware and software modules in the processor.

[0180] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (NVM), such as at least one disk storage.

[0181] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of this application is not limited to only one bus or one type of bus.

[0182] The present application also provides a computer program product, including a computer program, which implements the above method when executed by a processor.

[0183] The present application also provides a computer-readable storage medium, in which computer-executable instructions are stored. When a processor executes the computer-executable instructions, the above method is implemented.

[0184] The above-mentioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The readable storage medium can be any available medium that can be accessed by a general or special-purpose computer.

[0185] An exemplary readable storage medium is coupled to a processor so that the processor can read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can be located in an application specific integrated circuit (Application Specific Integrated Circuits, referred to as: ASIC). Of course, the processor and the readable storage medium can also exist in the device as discrete components.

[0186] The division of units is only a logical function division, and there may be other divisions in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0187] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0188] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0189] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0190] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk and other media that can store program codes.

[0191] Finally, it should be noted that those skilled in the art will readily conceive of other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses or adaptations of the present invention, which follow the general principles of the present invention and include common knowledge or customary technical means in the art not disclosed by the present invention, are not limited to the precise structure described above and shown in the drawings, and may be modified and changed in various ways without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A big data communication method in an intelligent driving system, characterized in that: Applied to any producer under the intelligent driving system, the method includes: After detecting new raw data, determining a target memory block according to the states of the multiple shared memory blocks, where the states are Writable or Readable, Writable means writable, and Readable means readable; Writing the raw data into the target memory block and modifying the state of the target memory block; The index of the target memory block is synchronized to the consumer ring queue through the Nvscisync synchronization mechanism.

2. The method according to claim 1, characterized in that The method further comprises: Establish NvSciIpc channel and send handshake requests to multiple consumers; After successfully shaking hands with each consumer, receiving the memory configuration requirements sent by each consumer through the NvSciIpc channel, the memory configuration requirements including memory type, access rights, memory alignment requirements and security attributes; Coordinate processing based on memory configuration requirements of all consumers to obtain configuration information, wherein the configuration information includes memory size, memory type, and access mode; Based on the configuration information, applying for the multiple shared memory blocks; The attribute information of the multiple shared memory blocks is sent to all consumers, wherein the attribute information includes the index, memory size, memory block address, memory type and access permission of the shared memory block.

3. The method according to claim 2, characterized in that The method further comprises: receiving access completion signals sent by the multiple consumers; Based on the access completion signal of each consumer, the state of the target memory block is changed to Writable.

4. The method according to claim 1, characterized in that: After the new raw data is detected, determining the target memory block according to the states of the multiple shared memory blocks includes: Read the status of each shared memory block and determine the shared memory block with a Writable status as the initial memory block; The shared memory block with the earliest release time in the initial memory blocks is determined as the target memory block.

5. A big data communication method in an intelligent driving system, characterized in that: Applied to any consumer under the intelligent driving system, the method includes: Monitor the consumer ring queue and obtain the index of the target memory block through the Nvscisync synchronization mechanism; Based on the index of the target memory block, data in the target memory block is accessed in a read-only manner.

6. The method according to claim 5, characterized in that The method further comprises: Receive a handshake request sent by the producer through the NvSciIpc channel; After successfully shaking hands with the producer, sending a memory configuration requirement to the producer through the NvSciIpc channel, the memory configuration requirement including memory type, access rights, memory alignment requirements and security attributes; Receive attribute information of multiple shared memory blocks sent by the producer, wherein the attribute information includes an index of the shared memory block, a memory size, a memory block address, a memory type, and access rights; Based on the attribute information of each shared memory block, local cross-process mapping is performed.

7. The method according to claim 6, characterized in that The method further comprises: After the data access is completed, an access completion signal is sent to the producer through the Nvscisync synchronization mechanism.

8. A big data communication device in an intelligent driving system, characterized in that: include: A determination module, used for determining a target memory block according to the status of multiple shared memory blocks after detecting new raw data, wherein the status is Writable or Readable, Writable means writable, and Readable means readable; A first modification module, used for writing the raw data into the target memory block and modifying the state of the target memory block; The first sending module is used to synchronize the index of the target memory block to the consumer ring queue through the Nvscisync synchronization mechanism.

9. A big data communication device under an intelligent driving system, characterized in that: include: The acquisition module is used to monitor the consumer ring queue and obtain the index of the target memory block through the Nvscisync synchronization mechanism; An access module is used to access the data in the target memory block in a read-only manner based on the index of the target memory block.

10. An electronic device, characterized in that: include: Memory, processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory, so that the processor performs the method according to any one of claims 1 to 7.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 7 when executed by a processor.

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