Table item learning method and device based on DMA, electronic equipment and readable medium

Abstract

The invention provides a table item learning method and device based on DMA, electronic equipment and a readable medium, and belongs to the field of communication. The table item learning method comprises the following steps: a switching chip encodes learning information into a table writing command to form a learning message when learning is needed; the DMA is written into a memory and is set to be valid in a learning queue record address; the processor writes the address into a table writing queue after detection; the table writing queue executes hard table writing accordingly; and after completion, updating the learning queue into a completion state. According to the table item learning method and device based on DMA, the electronic equipment and the readable medium, the learning message is encoded into the table writing command capable of being directly executed on the switch chip side, the table writing command is written into the memory and the address is registered through the DMA module, a processor can trigger table writing only by transferring the memory address between the learning queue and the table writing queue, and the table writing efficiency is improved. Therefore, a zero-copy and zero-analysis rapid learning link is realized.

Description

Technical Field

[0001] This invention belongs to the field of communication technology, and specifically relates to a DMA-based entry learning method, apparatus, electronic device, and readable medium. Background Technology

[0002] In live network applications of Ethernet switching chips, forwarding database learning is the core mechanism for implementing Layer 2 forwarding. There are generally two methods for learning entries: one is a hardware-based learning method that relies entirely on the chip side, and the other is a software-based learning method that requires CPU participation.

[0003] In the chip-side hardware learning method, when the packet processing unit of the switching chip detects that the source MAC address of a packet needs to be learned, it directly writes the new table entry into the hardware table. However, this method has a significant drawback: in multi-core scenarios, the hardware learning results are only effective within the current processing core, making it difficult to achieve consistent learning across cores. This can easily lead to table entry synchronization problems in multi-core systems.

[0004] Another approach is CPU-involved software learning. When the chip detects a need for learning, it sends the learning message to the CPU via a DMA channel. This method effectively ensures consistency in table entry learning within a multi-core environment. However, the learning message requires a memory copy from the DMA to the CPU, increasing data transfer overhead. Furthermore, the CPU needs to parse the key-value information and associated action information required by the learning mechanism within the learning message and regenerate configuration commands, which consumes significant processing resources. In scenarios with high network load or a large influx of learning messages within a short period, the surge of messages into the CPU can overwhelm its processing capacity, consuming excessive CPU computing resources and thus affecting the normal execution of other business logic. Summary of the Invention

[0005] The purpose of this disclosure is to provide a DMA-based table entry learning method, apparatus, electronic device, and readable medium that can enhance existing switching chip architectures without introducing additional hardware engines, thereby meeting the dynamic table entry learning requirements in high-performance network environments.

[0006] To achieve the above objectives, the technical solution provided in this disclosure is as follows:

[0007] Firstly, this disclosure provides a DMA-based entry learning method, which includes:

[0008] When the switching chip determines that a message triggers learning, it encodes the learning information into a directly executable table entry write command to form a learning message. The DMA module writes the learning message into memory, records the memory address of the learning message in the descriptor of the learning queue, and updates the descriptor of the learning queue to a valid state. When the processor detects that the descriptor of the learning ring is in a valid state, it writes the memory address of the learning message into the descriptor of the write table queue. The write table queue processes the learning message according to the memory address to perform a write operation on the switching chip's hard table. After the write operation is completed, the descriptor of the learning queue is updated to a completed state.

[0009] In one or more embodiments, the learning message is consistent with the data structure used for downsizing entries in the driver IO. The learning message includes a write command, a write position, and a write content. The write command represents the operation type, the write position represents the target address to be written, and the write content carries the key-value information and associated action information required by the learning mechanism.

[0010] In one or more embodiments, both the learning queue and the write queue are circular queues. The descriptors of the learning queue and the write queue include an address field, a validity flag, and a completion flag. The learning queue and the write queue satisfy the constraint of processing in index order, and subsequent descriptors are not processed while the current descriptor has not been processed.

[0011] In one or more embodiments, the table entry learning method further includes: storing the learning message in the learning FIFO of the switching chip, and pushing the learning message to the DMA module in batches through the learning FIFO.

[0012] In one or more embodiments, the table entry learning method further includes: when a conflict occurs during the table writing process, the processor processes the conflicting table entries, and after processing, the processor updates the descriptor of the corresponding learning queue to the completed state.

[0013] In one or more embodiments, when performing a write operation, the write queue directly uses the memory address recorded by the descriptor of the learning queue for processing, without performing memory copying and parsing of the learning message.

[0014] In one or more embodiments, the DMA module implements register read / write, message transmission / reception, and batch read / write of table entries through descriptors, and maintains the descriptors through a circular queue.

[0015] Secondly, this disclosure provides a DMA-based entry learning apparatus, which includes:

[0016] The message processing module is used to encode the learning information into a directly executable table entry write command to form a learning message when the switching chip determines that a message triggers learning. The DMA module is used to write the learning message into memory, record the memory address of the learning message in the descriptor of the learning queue, and update the descriptor of the learning queue to a valid state. The detection module is used to write the memory address of the learning message into the descriptor of the write table queue when the processor detects that the descriptor of the learning ring is in a valid state. The write module is used to enable the write table queue to process the learning message according to the memory address to perform a write operation on the switching chip's hard table. The update module is used to update the descriptor of the learning queue to a completed state after the write operation is completed.

[0017] Thirdly, this disclosure provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the DMA-based entry learning method as described above.

[0018] Fourthly, this disclosure provides a computer-readable medium carrying computer-executable instructions, which, when executed by a processor, are used to implement the DMA-based entry learning method as described above.

[0019] The DMA-based table entry learning method, apparatus, electronic device, and readable medium disclosed herein encode the learning message into a directly executable write command on the switching chip side, and write it into memory and register the address by the DMA module. The processor only needs to transfer the memory address between the learning queue and the write queue to trigger the write operation, thereby realizing a fast learning link with zero copy and zero parsing. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments recorded in this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a flowchart of a DMA-based entry learning method in one embodiment of this disclosure;

[0022] Figure 2 This is a schematic diagram illustrating the organization of the learning queue and the write queue in one embodiment of this disclosure;

[0023] Figure 3 This is a schematic diagram of a DMA-based entry learning device according to an embodiment of the present disclosure;

[0024] Figure 4 This is a schematic diagram of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0025] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0026] In existing network environments using switching chips, entry learning is a crucial step in ensuring the correctness of packet forwarding. Current technologies typically employ two approaches: hardware learning, performed independently by the chip, and software learning, which relies on CPU involvement. While the former eliminates CPU intervention and enables rapid entry writing, the independent learning by each core can easily lead to desynchronization issues in multi-core scenarios. The latter achieves cross-core consistency through centralized CPU processing, but inevitably involves memory copying and field parsing, placing high demands on CPU performance and creating performance bottlenecks when the volume of learned messages surges. These issues make it difficult for existing technologies to balance performance efficiency with multi-core consistency, limiting the scalability and stability of switching chips in high-concurrency environments.

[0027] To address the shortcomings of existing technologies, this disclosure proposes a novel approach: reorganizing the entry learning process while retaining the existing DMA and configuration paths. The core of this approach lies in transforming learning messages into a format consistent with the entry configuration and efficiently transferring them between the chip and CPU via DMA. This eliminates the need for the CPU to directly parse and copy messages, allowing it to act as a lightweight coordinator for necessary instruction transfers. In this way, learning messages can enter the entry configuration path through a unified mechanism, achieving cross-core consistency. Simultaneously, the CPU is freed from heavy data processing tasks, preventing it from becoming a bottleneck in high-concurrency learning scenarios.

[0028] Overall, this disclosure, on the one hand, unifies message transmission and execution paths through a DMA mechanism, ensuring consistency in learning within a multi-core environment; on the other hand, it significantly reduces CPU load and eliminates redundant copies by optimizing the structure of learning messages and redistributing processing responsibilities. Thus, without introducing an additional hardware engine, it achieves a highly efficient enhancement of the existing switching chip architecture, providing a novel approach that balances performance and stability for addressing the dynamic entry learning requirements in high-performance network environments.

[0029] The technical solution disclosed herein can be applied to learning scenarios that automatically extract and issue table entries based on message information, including FDB dynamic learning in Layer 2 forwarding, and flow-learning based on flow characteristics and issuing ACL / action tables. For the latter, the chip side can extract key fields from the message and associate them with actions (such as obtaining forwarding / dropping / counting information by associating with AD tables), uniformly encode them into directly executable table entry write commands, and then report them to the DMA and write table path.

[0030] Since the technical solution disclosed herein is based on the core principle of learning messages and driver-driven table structure consistency, DMA registration address, and CPU only performing address-level translation, it does not depend on specific table type or specific chip learning engine. Therefore, it can be implemented in multi-core switching chips, network processors, white-box switches, virtual switches / SmartNICs, etc. It is also compatible with different DMA and bus architectures (on-chip DMA, PCIe peripheral DMA, etc.) as well as various ring queue depths and batch strategies.

[0031] Please refer to Figure 1 The diagram shows a flowchart of a DMA-based entry learning method according to an embodiment of this disclosure. The DMA-based entry learning method specifically includes the following steps:

[0032] S101: When the switching chip determines that learning has been triggered, it encodes the learning information into a directly executable table entry and writes it into a command to form a learning message.

[0033] In step S101, the learning message is moved forward from a two-stage link requiring CPU parsing before assembling configuration commands to a one-time, directly executable write command generated at the chip level. When the switching chip determines in the packet processing pipeline that learning is needed (e.g., a missed FDB or an existing entry being invalid / aged), the switching chip no longer simply outputs the raw learning fields. Instead, it organizes the learning information into a learning message consistent with the driver's table entry structure: containing the write command (operation type and target table semantics), the write location (address / index and other location information of the target table entry), and the write content (the mapping from key values ​​to the forwarding behavior table, such as MAC+FID / VLAN→port mapping data). This learning message maintains the same format as the write table structure used by the driver IO, allowing it to be directly executed as a configuration command in subsequent stages.

[0034] In terms of implementation, S101 can have the microcode / hard logic of the message processing unit extract and encode fields when it determines that learning is required. For example, for FDB learning, it can read MAC_SA, VLAN (or its mapped FID), and ingress port identifier from the current message metadata bus and write them into a continuous buffer in a predefined field order. At the same time, it generates the write table position (such as table entry index / address) according to the chip's existing FDB addressing rules and marks the operation type (such as add / update) in the message header. To ensure zero copying later, the field length and alignment are consistent with the driver-side structure, and no special tags that can only be parsed by the CPU are introduced. After encoding, the learning message can be placed into the chip-side learning message FIFO, waiting to be pushed to the DMA in batches (corresponding to the processing of subsequent steps).

[0035] In one exemplary embodiment, the learning message is consistent with the data structure used by the driver IO for the down table entry. The learning message includes a write command, a write position, and a write content. The write command represents the operation type, the write position represents the target address to be written, and the write content carries the key-value information and associated action information (such as MAC, FID / VLAN and port mapping information) required by the learning mechanism.

[0036] By making the learning messages into configuration units that are isomorphic to the published items under the driver I / O, once the chip side confirms that learning is needed, it directly produces a data block that corresponds one-to-one with the structure required by the driver to write the table and is aligned byte by byte. Since the structures at both ends are consistent, subsequent paths can directly execute this data as a ready-made table write command, eliminating the field parsing, structure conversion and repackaging on the CPU side in traditional solutions.

[0037] The write command can be understood as the logical entry point of the data block, serving as an identifier of the instruction semantics. It represents the type and scope of this operation, such as adding or updating a key-value pair of a table entry, and may include necessary control bits (such as whether overwriting is allowed, whether to participate in aging timer, etc.). This allows subsequent execution units to determine which existing write path and register sequence to follow simply by recognizing this field, without needing to guess the semantics, thus ensuring that the behavior is consistent with the driver's regular output.

[0038] The write position serves as the addressing location, indicating the location of the target entry in the hard table. Typical forms include indexes, hash bucket numbers, or address offsets used by the driver layer. Its encoding rules are consistent with the driver. For example, if the driver uses linear addressing (base address + index × step size), then the learning message is written directly to the chip side according to the same rules. This homogeneous design eliminates the need for the execution end to recalculate the target position, avoiding the overhead and potential inconsistencies of calculating one set of data at the chip and another at the CPU.

[0039] The write table content is the key-value data body, carrying the minimum necessary information for forwarding decisions, such as the key composed of MAC and FID / VLAN, and the value mapped to the port (or port set / outgoing interface identifier). Its field order, length, and alignment are strictly consistent with the driver's write table structure. For example, the MAC address is written in 48 bits according to the driver's predetermined end order, the VLAN or FID occupies the same bit width as the driver, and the port number / port mask follows the same encoding method. In this way, the execution unit only needs to write this content directly to the corresponding field of the hard table, without needing to interpret and move each field individually.

[0040] To illustrate with a concrete example, suppose the device receives the first packet with VLAN 100 and source MAC address 00:11:22:33:44:55 on port 5. After determining that the File Table (FDB) is missing, the chip immediately writes a write command to add the FDB to the learning message header, writes the index or bucket / slot location calculated using the same rules as the driver in the location field, and writes {MAC=00:11:22:33:44:55,FID / VLAN=100,PORT=5} in the content field. This contiguous memory segment is isomorphic to the driver's write table structure. Therefore, when it is moved to memory and its address is filled into subsequent write paths, the execution unit does not need to parse any fields; it directly completes the write table according to the driver's regular process. For update scenarios (such as port changes due to host relocation), it is similarly sufficient to mark the write command as an update, and write the location and content according to the established rules. The behavior of the entire link remains consistent with the driver's output.

[0041] In one exemplary embodiment, after the learning information is encoded into learning messages, the learning messages are stored in the learning FIFO of the switching chip, and the learning messages are pushed to the DMA module in batches through the learning FIFO.

[0042] When learning is required, the switching chip does not immediately send the learning messages to the DMA one by one. Instead, it first writes the learning messages, which have been encoded into directly executable table entry write commands, into the learning FIFO. Then, the learning FIFO pushes the messages to the DMA module in batches. This inserts an elastic buffer between the source of the learning messages (message processing pipeline) and the source of the messages (DMA), which smooths out the instantaneous traffic and merges scattered small-granular transactions into more efficient batch transmission transactions.

[0043] In its implementation, the learning FIFO can reside in the on-chip storage area of ​​the switching chip. The write path involves the message processing unit directly pushing the formatted learning messages sequentially. The read path is handled by the dequeue control logic, which retrieves a number of messages at once and submits them to the DMA when the batch trigger condition is met. The batch trigger condition can be a threshold for the number of entries (e.g., triggering when N messages are accumulated) or a time threshold (e.g., triggering when the maximum waiting time is reached) to achieve a balance between throughput and latency. During batch push, the DMA side only needs to receive these messages and write them sequentially to the learning data area in memory. Simultaneously, it records the corresponding memory address and status in the consecutive descriptor slots of the LearningRing, forming a sequence that interfaces with the subsequent write queue. Since the learning message itself is already a structure of write command + write location + write content, the DMA does not need to parse the content; it only undertakes the responsibility of batch transport and address registration.

[0044] The learning FIFO also acts as a backpressure buffer. On one hand, the message processing pipeline converts the events to be learned into messages and enqueues them in the order they appear, avoiding direct coupling with the instantaneous service capabilities of DMA. On the other hand, when the downstream learning queue or main memory write rate cannot keep up temporarily, the FIFO provides the ability to absorb micro-bursts for a short time until the batch conditions are met before sending them out in a unified manner. In conjunction with the constraint that the learning queue must process descriptors in order within a given ring, the batch dequeueing of the FIFO to DMA also maintains the order, making the message generation order, memory write order and queue consumption order consistent, so that subsequent processors can drive the write table path by simply transferring addresses.

[0045] S102: The DMA module writes the learning message into memory, records the memory address of the learning message in the descriptor of the learning queue, and updates the descriptor of the learning queue to a valid state.

[0046] After the switching chip encodes the learning information into directly executable write commands in S101, the DMA module sequentially writes the learning message into the learning data area of ​​the CPU-side system memory. It also records the starting address of this learning message in memory in the target descriptor of the learning queue and updates the descriptor's status to valid for subsequent processor processing and consumption. The learning queue can maintain descriptors in a circular structure, stored in contiguous memory on the CPU side. Within a given ring, descriptors must be processed sequentially according to their index; subsequent indices cannot be processed until the current index has been processed. Correspondingly, there is a one-to-one correspondence between the learning data area and the descriptors. Each descriptor is associated with at least the starting address and size of a data memory segment, enabling subsequent stages to locate and process the learning message solely based on its address, without requiring further content parsing or reassembly.

[0047] In terms of implementation, DMA can adopt a batch transfer and sequential registration organization. After the chip-side learning FIFO meets the batch condition, it pushes a group of learning messages to the DMA. The DMA then writes these messages into the learning data area in a continuous or reserved step size, and then writes the corresponding addr / size into several consecutive descriptor slots in the learning queue and sets them to valid (valid state).

[0048] Since the learning queue and the learning data area have a pre-defined mapping relationship of contiguous space, fixed step size, or explicit length during initialization, DMA does not need to understand the message content itself; it only needs to maintain a set of indicators: message → address → valid state. The progress of the loop is controlled by index pointers. When a descriptor is set to valid, the processor can scan for this state in subsequent S103 and directly write the address to the write table queue. Only when the write table process is completed in S105 and the entry is reclaimed is the learning descriptor considered processed, freeing up space for new learning messages. In extreme cases where all descriptors in the learning queue are occupied, DMA will temporarily suspend further registration (a brief accumulation in the learning FIFO) until downstream slots are released, thus ensuring order and integrity through a backpressure mechanism.

[0049] In one exemplary embodiment, the DMA module can also implement register read / write, message transmission / reception, and batch read / write of table entries through descriptors, and maintain descriptors through a circular queue.

[0050] In implementation, each function occupies one or more Rings (circular queues). During initialization, the driver allocates contiguous memory as a descriptor area for each Ring, sets its base address and length, and assigns one or more data memory segments to hold the actual data or parameters. There is a one-to-one correspondence between descriptors and data memory. Each descriptor records at least the starting address and size of the data block, supplemented by status bits such as valid / done. Rings advance in index order; subsequent indexes are not processed until the current index is completed. This continuous, sequential, and status-driven organization facilitates efficient traversal by DMA hardware and allows the CPU to reduce interrupt and lock contention through linear scanning / batch reclamation.

[0051] Taking register read / write as an example, if a driver needs to read a group of on-chip registers in batches, it can first write the list of register addresses to be read and the target write-back buffer in the data memory, then fill in the address and length of the corresponding descriptor in the register access ring, set the valid flag, and notify the DMA. The DMA then traverses the list, reads the registers one by one, writes the results back to the same data block or the specified result area, and then marks the descriptor as done.

[0052] Taking the message transmission and reception path as an example, in the RX direction, the driver pre-fills the addresses of a batch of free buffers into the RX Ring descriptors and sets them to valid. When a message arrives, the DMA directly writes the frame data into these buffers, updates the length, and sets it to done. The CPU only needs to poll or use interrupts to detect which descriptors are complete, then assign the corresponding buffers to the upper-layer protocol stack for processing, and then reclaim and re-deliver the descriptors. In the TX direction, the driver fills the address and length of the message buffer to be sent into the TXRing. The DMA retrieves the frame from memory and sends it to the MAC / PHY, then sets it to done so that the driver can reclaim it.

[0053] S103: When the processor detects that the descriptor of the learning ring is in a valid state, the memory address of the learning message is written to the descriptor of the write table queue.

[0054] Once the DMA has written the learning message to system memory and set the corresponding descriptor in the learning queue to valid, the processor does not read, parse, or reassemble the message body. Instead, upon detecting this valid state, it simply fills the starting address of the learning message recorded in the descriptor into the target descriptor of the WriteRing. Thus, the learning message, as a contiguous block of memory containing directly executable write commands and content, is consumed by the write path by address. The processor only undertakes a very light address translation task in the link, thereby maintaining the zero-copy and zero-parse characteristics.

[0055] In practice, a lightweight scan driven by polling can be used. The processor reads the descriptor status sequentially along the current index of the write table queue. When a series of valid entries are encountered, their memory addresses and lengths are read in batches, and an equal number of free descriptor slots are requested in the write table queue. These addresses are written one by one, and then the commit pointer of the write table queue is advanced.

[0056] To ensure data visibility, address transpilation follows the order of reading the valid bit first, then the address, and finally the target descriptor. This order guarantees that by the time the processor sees the valid data, the data written by DMA has been completely committed. On architectures with weaker consistency, necessary memory barriers can be added between reading the valid bit and reading the address, and after writing the target descriptor, to avoid occasional invisibility due to out-of-order delivery. In terms of implementation details, a small batch threshold can be set, triggering a transpilation when a certain number of valid learned items are cached or the maximum expected time is reached. This prevents individual messages from waiting in the queue for extended periods while merging multiple messages into a single commit, achieving a balance between throughput and latency.

[0057] In one exemplary embodiment, both the learning queue and the write queue are circular queues. The descriptors of the learning queue and the write queue include an address field, a validity flag, and a completion flag. The learning queue and the write queue satisfy the constraint of processing in index order, and subsequent descriptors are not processed until the current descriptor has been processed.

[0058] Both the learning queue and the write queue use a circular queue data structure to organize descriptors. Each descriptor contains at least an address field, a valid flag, and a done flag. Both queues adhere to strict sequential semantics; only after the descriptor pointed to by the current index has been processed can the next descriptor be processed. A circular queue is essentially a fixed-length circular array where producers and consumers advance using indices, wrapping back to the beginning after reaching the end. Placing descriptors in this structure facilitates continuous traversal and burst access in hardware, and allows software to reduce the frequency of locks and interrupts through linear scanning. Figure 2 This is a schematic diagram illustrating the organization of the learning queue and the write queue in one embodiment.

[0059] In practical implementation, the learning queue is used to hold catalog records after the DMA has written the learning messages to system memory. When the DMA completes the memory write of a learning message, it writes the starting address (address field) of this message to the descriptor of the current slot in the learning queue, and then sets the valid bit to 1, indicating that this record is available for consumption by the upper layer. After the processor scans and finds that the entry is valid, it does not read or parse the message body, but writes the address recorded in the descriptor to the descriptor of the corresponding slot in the write table queue as is; the write table queue then drives the write table execution path based on this address. After the write table hardware is completed, the entry in the write table queue is set to done, and the corresponding entry in the learning queue is also set to done. Throughout the process, the address in the descriptor → valid → done constitutes a minimal complete state machine. The CPU only uses the address as a credential to advance the process, ensuring zero copy.

[0060] Sequential semantics ensures that the order in which learning messages are written to memory, the order in which the learning queue becomes valid, the order in which messages are enqueued in the write queue, and the order in which hard tables are written are consistent. This avoids race conditions and difficult-to-reproduce problems caused by out-of-order delivery, and also facilitates index-based location, replay, or rollback in abnormal scenarios. To achieve sequential advancement, the queue may maintain one or a pair of index pointers (e.g., head / tail or the current index). DMA and CPU each only move the pointers they are responsible for, and perform minimal checks based on the valid / done bits before and after advancement. Since the descriptor area is contiguous memory, hardware can prefetch or burst access multiple slots at once, and software can also batch process a continuous range of valid items.

[0061] S104: The write queue processes the learning message according to the memory address to perform a write operation on the hard table of the switching chip.

[0062] In step S104, the WriteRing consumes the learning message already stored in memory from the previous steps via the address, and directly treats the message as an executable entry write instruction to complete the hard table update. Specifically, after the processor fills the memory address of the learning message in the learning queue descriptor into the WriteRing in S103, the WriteRing path reads a continuous block of message data based on this address. Since the learning message has been encoded in S101 into a layout isomorphic to the entry in the driver IO (including the write command, write position, and write content), the WriteRing path does not need to perform any field parsing or reassembly. Instead, it executes directly according to the existing configuration process, determines the operation type (such as add or update) based on the write command, locks the target position of the hard table based on the write position, and finally writes the write content into the corresponding entry field. After the write is completed, the result state is written back to the descriptor of the WriteRing, providing a basis for subsequent state reclamation and updates in S105.

[0063] In implementation, the write path can be index-based, where the learning message already contains the index or address offset of the target table entry, and the write unit directly writes the content to the hard table using an access model of base address + index × step size; or it can be hash / bucket-slot-based, where the learning message carries hash information or slot identifiers for location, and the write unit first hits the target bucket and slot, then places the content into the corresponding table entry. The common feature of both methods is that neither requires CPU involvement in computation and conversion; the write unit relies solely on the location information and content provided in the message to complete the write operation.

[0064] To illustrate with a concrete example, suppose the eight learning messages corresponding to indices 10-17 in the learning queue have been written to memory by DMA and made valid in S102. In S103, the processor sequentially fills these eight addresses into the write table queue. Upon entering S104, the write table path retrieves the first address from the write table queue, reads the message header to identify it as a new FDB, obtains the target table entry index from the write table location, and then writes the write table content {MAC=00:11:22:33:44:55,VLAN / FID=100,PORT=5} into the corresponding field of the hard table. If subsequent entries are updates to the FDB, the process is the same, except that existing entries are overwritten. Upon completion of each entry, the completion status is updated in the corresponding write table descriptor.

[0065] In one exemplary embodiment, when a conflict occurs during the table writing process, the processor processes the conflicting entries, and after processing, the processor updates the descriptor of the corresponding learning queue to the completed state.

[0066] The write unit updates the hard table based on the write command, write location, and write content in the learning message. If the target is already occupied and cannot be overwritten, if concurrent updates detect version inconsistencies, or if the bucket / slot is temporarily full, the exception result will be written back to the descriptor of that item in the write queue. When the processor recycles the write queue during regular polling or event-driven polling, it can locate the specific index and the corresponding learning message address by reading the exception flag, and then enter the conflict handling logic. For example, it reads the same key items in the current hard table for comparison, decides whether to merge / overwrite the update (e.g., port movement) or abandon the new write (e.g., there is already a valid item with higher priority), and if necessary, initiates another targeted write or cleans up the old item before writing.

[0067] For example, a message with source MAC A first appears on port 5, and a few milliseconds later, a message with the same source MAC A appears on port 7. The first learning message may have already been queued or just written to the hard table; when the second learning message arrives at the write table path, the target slot is already occupied by the same key, and the write table unit determines it as a conflict according to its policy, marking an anomaly in the write table descriptor. After the processor reads this mark, it locates the key value using the learning message address (no large-scale parsing is required, only key fields need to be compared), finds that it belongs to the port movement case, and then performs a controlled overwrite or deletion-then-write compensation operation; after the operation is completed, the corresponding item in the learning queue is set to the completed state, and the loop bit is released. At the same time, other non-conflicting learning messages are still completed in sequence in the hardware write table unit, and the overall learning latency is not amplified by individual conflicts.

[0068] S105: After the write operation is completed, update the descriptor of the learning queue to the completion status.

[0069] After the write queue completes the update of the hard table based on the memory address of the learning message, it needs to perform a cleanup on the corresponding item in the learning queue. The processor changes the item's descriptor from valid to done and reclaims the queue slot and data buffer it occupied for its lifetime. In implementation, the processor usually first detects the completion status of the corresponding descriptor in the write queue (e.g., the done bit or result code), then finds the corresponding item in the learning queue using the same index or associated marker. After ensuring that the write operation has been successfully completed, the processor sets the item in the learning queue to done, and cleans up or reattaches the memory block associated with the item for reuse by subsequent learning messages if necessary.

[0070] To ensure visibility and ordering, a common practice is to add a lightweight memory barrier between reading the write-to-complete state and writing back to the learning queue to prevent artifacts on weakly consistent platforms where learning is complete but the queue still displays as valid. If an entry has a conflict during the write phase and the CPU has handled the conflict, the processor will also set the learning queue to complete only after the conflict is resolved, maintaining the lifecycle constraint of each learning message being exactly once.

[0071] Taking high-concurrency batch processing as an example, assume that 32 items (indices 200-231) in the learning queue have been written to the write queue and executed by the processor. The processor sequentially reads the completion flags and optional result codes of these 32 items in the write queue. After confirming that everything is correct, it marks the corresponding 32 items in the learning queue as completed one by one. When the entire consecutive window is completed, the consumed pointer of the learning queue can be advanced to 232, thereby releasing these 32 descriptor slots and their corresponding data buffers back to the pool all at once. At this time, if the upstream DMA is suppressed due to the learning queue being close to full, it can immediately continue to register new learning messages as the completion flags and pointers advance. If some items have an anomaly such as the return position being occupied during the write operation, the CPU will first perform migration or retry processing before marking the item as completed; other normal items will not be affected, and the overall progress of the batch processing will still proceed in sequence.

[0072] In summary, the DMA-based entry learning method disclosed herein encodes learning messages into directly executable write commands on the switching chip side, and then writes them to memory and registers their addresses via the DMA module. The processor only needs to transfer memory addresses between the learning queue and the write queue to trigger the write operation, thus achieving a fast learning chain with zero copy and zero parsing. This scheme effectively avoids the performance bottleneck caused by frequent copying and parsing in traditional CPU learning, significantly reducing CPU resource consumption and processing latency. Simultaneously, write operations are uniformly executed sequentially through the write queue, ensuring the consistency and synchronization of entry learning in multi-core scenarios. Through this design, the learning process is automatically completed by the data plane, with the CPU only intervening when necessary to handle conflicts, greatly improving the system's throughput and stability. This allows the switching chip to maintain low latency and high efficiency even when facing high-concurrency learning messages, exhibiting good engineering adaptability and scalability.

[0073] Please refer to Figure 3 As shown, based on the same inventive concept as the aforementioned DMA-based entry learning method, this disclosure provides a DMA-based entry learning device 300, which includes: a message processing module 301, a DMA module 302, a detection module 303, a writing module 304, and an update module 305.

[0074] The message processing module 301 encodes the learning information into a directly executable table entry write command to form a learning message when the switching chip determines that the source MAC address of the message needs to be learned. The DMA module 302 writes the learning message to memory, records the memory address of the learning message in the descriptor of the learning queue, and updates the descriptor of the learning queue to a valid state. The detection module 303 writes the memory address of the learning message to the descriptor of the write table queue when the processor detects that the descriptor of the learning ring is in a valid state. The write module 304 causes the write table queue to process the learning message according to the memory address to perform a write operation on the switching chip's hard table. The update module 305 updates the descriptor of the learning queue to a completed state after the write operation is completed.

[0075] Please refer to Figure 4 As shown, embodiments of this disclosure also provide an electronic device 400, which includes at least one processor 401, a memory 402 (e.g., non-volatile memory), a main memory 403, and a communication interface 404, wherein the at least one processor 401, the memory 402, the main memory 403, and the communication interface 404 are connected together via an internal bus 405. The at least one processor 401 is configured to invoke at least one program instruction stored or encoded in the memory 402 to cause the at least one processor 401 to perform various operations and functions of the DMA-based entry learning method described in the various embodiments of this specification.

[0076] In the embodiments of this specification, electronic device 400 may include, but is not limited to: personal computer, server computer, workstation, desktop computer, laptop computer, notebook computer, mobile electronic device, smartphone, tablet computer, cellular phone, personal digital assistant (PDA), handheld device, messaging device, wearable electronic device, consumer electronic device, etc.

[0077] This disclosure also provides a computer-readable medium carrying computer-executable instructions, which, when executed by a processor, can be used to implement various operations and functions of the DMA-based entry learning method described in the various embodiments of this specification.

[0078] The computer-readable medium in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0079] In this disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which can transmit, propagate, or transfer a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to: wireless, wireline, optical fiber, RF, etc., or any suitable combination thereof.

[0080] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0081] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus, systems, and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0082] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0083] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A DMA-based entry learning method, characterized in that, include: When the switching chip determines that a message triggers learning, it encodes the learning information into a directly executable table entry and writes it into a command to form a learning message. The DMA module writes the learning message into memory, records the memory address of the learning message in the descriptor of the learning queue, and updates the descriptor of the learning queue to a valid state. When the processor detects that the descriptor of the learning loop is in a valid state, it writes the memory address of the learning message into the descriptor of the write table queue. The write queue processes the learning message according to the memory address to perform a write operation on the hard table of the switching chip; After the write operation is completed, the descriptor of the learning queue is updated to the completed state.

2. The DMA-based entry learning method according to claim 1, characterized in that, The learning message is consistent with the data structure used for downloading entries in the driver IO. The learning message includes a write command, a write position, and a write content. The write command represents the operation type, the write position represents the target address to be written, and the write content carries the key-value information and associated action information required by the learning mechanism.

3. The DMA-based entry learning method according to claim 1, characterized in that, Both the learning queue and the write queue are circular queues. The descriptors of the learning queue and the write queue include an address field, a validity flag, and a completion flag. The learning queue and the write queue satisfy the constraint of processing in index order. If the current descriptor has not been processed, the subsequent descriptors will not be processed.

4. The DMA-based entry learning method according to claim 1, characterized in that, The table item learning method also includes: The learning messages are stored in the learning FIFO of the switching chip, and then pushed to the DMA module in batches through the learning FIFO.

5. The DMA-based entry learning method according to claim 1, characterized in that, The table item learning method also includes: When a conflict occurs during the table writing process, the processor handles the conflicting entries, and after the handling is complete, the processor updates the descriptor of the corresponding learning queue to the completed state.

6. The DMA-based entry learning method according to claim 1, characterized in that, When performing a write operation, the write queue directly uses the memory address recorded by the descriptor of the learning queue for processing, without performing memory copying and parsing of the learning message.

7. The DMA-based entry learning method according to claim 1, characterized in that, The DMA module implements register read / write, message transmission / reception, and batch read / write of table entries through descriptors, and maintains the descriptors through a circular queue.

8. A DMA-based entry learning device, characterized in that, include: The message processing module is used to encode the learning information into directly executable table entries and write them into commands to form a learning message when the switching chip determines that the message triggers learning. The DMA module is used to write the learning message into memory, record the memory address of the learning message in the descriptor of the learning queue, and update the descriptor of the learning queue to a valid state. The detection module is used to write the memory address of the learning message into the descriptor of the write table queue when the processor detects that the descriptor of the learning loop is in a valid state. The write module is used to enable the write queue to process the learning message according to the memory address in order to perform a write operation on the hard table of the switching chip. An update module is used to update the descriptor of the learning queue to a completed state after the write operation is completed.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the DMA-based entry learning method as described in any one of claims 1 to 7.

10. A computer-readable medium, characterized in that, The computer-readable medium carries computer-executable instructions, which, when executed by a processor, are used to implement the DMA-based entry learning method as described in any one of claims 1 to 7.

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