Memory fault processing method and device, electronic equipment and storage medium

Abstract

The invention provides a memory fault processing method and device, electronic equipment and a storage medium, and the method comprises the steps: if a fault prediction self-healing system is in an open state, responding to a fault event of a memory, and sending a fault isolation request which comprises a memory fault feature; the basic input and output system responds to the fault isolation request and determines an isolation repair mode according to the memory fault features; based on the isolation repairing mode, repairing a memory fault; if the fault prediction self-healing system is in a closed state, the basic input and output system responds to a preset triggering condition triggered event, and the memory fault is repaired. According to the memory fault processing method disclosed by the invention, the stability of the system is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of storage technology, and in particular to a memory failure processing method, device, electronic device and storage medium. Background Art

[0002] PCLS (Partial Cache Line Sparing) is a new standard RAS (Reliability Availability and Serviceability) function. When the system detects a persistent error in the memory, the PCLS mechanism is triggered. PCLS uses the spare capacity in the IMC (Internal Memory Controller) to map the memory bits with errors to spare bits. In this way, when the system accesses these erroneous memories, it actually accesses the data on the spare bits, thus avoiding the occurrence of errors.

[0003] However, in areas where ADDDC (Adaptive Double Device Data Correction) has been activated, PCLS cannot be used in addition because these areas have already adopted other backup technologies to handle these memory errors. In addition, the performance of PCLS is also limited by the backup capacity in the IMC. If the backup capacity is insufficient, PCLS cannot effectively handle all memory errors. Therefore, a more complete memory error handling solution is urgently needed. Summary of the invention

[0004] The present disclosure provides a memory fault processing method, device, electronic device and storage medium to at least solve the above technical problems existing in the prior art.

[0005] According to a first aspect of the present disclosure, a memory fault processing method is provided, the method comprising:

[0006] If the fault prediction self-healing system is in an open state, in response to a memory fault event, a fault isolation request is sent, wherein the fault isolation request includes a memory fault feature;

[0007] The basic input and output system responds to the fault isolation request and determines an isolation and repair method according to the memory fault characteristics;

[0008] Repairing the memory fault based on the isolation repair method;

[0009] If the fault prediction and self-healing system is in a closed state, the basic input and output system responds to an event in which a preset trigger condition is triggered to repair the memory fault.

[0010] In one possible implementation manner, determining the isolation repair method according to the memory fault characteristics includes:

[0011] Determine the fault type according to the memory fault characteristics;

[0012] If the fault type is a single-bit error, determining the isolation repair method to be the first repair method;

[0013] If the fault type is a row error, determining the isolation repair method to be the second repair method;

[0014] If the fault type is other errors, the isolation repair method is determined to be the third repair method.

[0015] In one possible implementation, the first repair method includes:

[0016] Determine whether some cache lines reserve PCLS resources;

[0017] If there are PCLS resources, perform PCLS isolation;

[0018] If there is no PCLS resource, the page is taken offline through the operating system.

[0019] In one possible implementation, the second repair method includes:

[0020] Update the physical location repair record and determine whether the memory is X4 particles. If so, determine whether there is an adaptive dual-particle data correction Adddc resource;

[0021] If there is an Adddc resource, execute Adddc to isolate the storage array according to the physical location repair record;

[0022] If there is no Adddc resource, determine whether there is a single-particle data correction Sddc resource;

[0023] If there are Sddc resources, Sddc is executed to isolate particles according to the physical location repair record.

[0024] In one possible implementation, the third repair method includes:

[0025] Determine whether the memory is X4 particles. If so, determine whether there are Adddc resources.

[0026] If there are Adddc resources, execute Adddc to isolate the storage array;

[0027] If there is no Adddc resource, determine whether there is an Sddc resource;

[0028] If there are Sddc resources, execute Sddc to isolate particles.

[0029] In one possible implementation, the preset trigger condition includes a PCLS trigger condition; accordingly,

[0030] The responding to the event that the preset trigger condition is triggered to repair the memory fault includes:

[0031] In response to the PCLS trigger condition being triggered, determining whether there are PCLS resources;

[0032] If there are PCLS resources, perform PCLS isolation;

[0033] If there is no PCLS resource, the page is taken offline through the operating system.

[0034] In one possible implementation, the preset trigger condition also includes a trigger condition that can be modified; accordingly,

[0035] The responding to the event that the preset trigger condition is triggered to repair the memory fault includes:

[0036] In response to the event that the modifiable trigger condition is triggered, determining whether the memory is an X4 particle, and if so, determining whether there is an Adddc resource;

[0037] If there are Adddc resources, execute Adddc to isolate the storage array;

[0038] If there is no Adddc resource, determine whether there is an Sddc resource;

[0039] If there are Sddc resources, execute Sddc to isolate particles.

[0040] According to a second aspect of the present disclosure, a memory fault processing device is provided, the device comprising:

[0041] A repair request module, configured to send a fault isolation request in response to a memory fault event if the fault prediction self-healing system is in an open state, wherein the fault isolation request includes a memory fault feature;

[0042] A repair module, used for the basic input and output system to respond to the fault isolation request and determine the isolation repair method according to the memory fault characteristics;

[0043] The repair module is further used to repair the memory fault based on the isolation repair method;

[0044] The repair module is further used for repairing the memory fault when the fault prediction self-healing system is in a closed state and the basic input and output system responds to an event in which a preset trigger condition is triggered.

[0045] According to a third aspect of the present disclosure, there is provided an electronic device, including:

[0046] at least one processor; and

[0047] a memory communicatively connected to the at least one processor; wherein,

[0048] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method described in the present disclosure.

[0049] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause the computer to execute the method described in the present disclosure.

[0050] The memory fault processing method, device, electronic device and storage medium disclosed in the present invention, if the FPC is in the on state, responds to the fault isolation request through the BIOS. And according to the memory fault characteristics, determine the corresponding isolation and repair method to repair the memory fault. If the FPC is in the off state, the BIOS responds to the event triggered by the preset trigger condition, and repairs the memory fault according to the fault type. The present invention implements a more complete memory fault isolation mechanism through BIOS-level fault isolation. Ensure that the operating system only uses flawless memory units, thereby significantly reducing the system instability and crash risks caused by memory faults.

[0051] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, in which:

[0053] In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.

[0054] Figure 1 The following is a schematic diagram showing the implementation process of a memory fault processing method according to an embodiment of the present disclosure. Figure 1 ;

[0055] Figure 2 The following is a schematic diagram showing the implementation process of a memory fault processing method according to an embodiment of the present disclosure. Figure 2 ;

[0056] Figure 3 A schematic diagram of the structure of a memory fault processing method according to an embodiment of the present disclosure is shown;

[0057] Figure 4 A schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0058] In order to make the purpose, features, and advantages of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0059] According to a first aspect of an embodiment of the present disclosure, a method for handling a memory failure is provided, such as Figure 1 As shown, the method comprises the following steps:

[0060] Step 101: If the fault prediction and self-healing system is in an open state, in response to a memory fault event, a fault isolation request is sent, wherein the fault isolation request includes a memory fault feature.

[0061] The FPC system (Failure Prediction and Correction) is a computer system management mechanism that can provide system stability and reliability by predicting potential hardware or software failures and automatically taking measures to correct or isolate them before or in the early stages. During the server startup phase, the BIOS (Basic Input Output System) determines whether the FPC system is in the on state through a flag sent by the BMC (Baseboard Management Controller). If the FPC system is in the on state, the preset trigger condition is turned off. The preset trigger condition refers to the RAS preset trigger condition that comes with the CPU. The preset trigger condition may include the correctable error leak bucket reaching a threshold, the PCLS reaching a threshold, etc., which are used to trigger the corresponding mechanism when the number of executions reaches a threshold, such as an alarm, restart, etc.

[0062] In this embodiment, if it is detected that the FPC system is in the open state, the preset trigger condition is closed. During the server operation stage, if the memory fails, the BIOS responds to the SMI (System Management Interrupt) interrupt, collects the fault information, and reports the fault information to the BMC. The BMC parses the error information and extracts the key fault characteristics. Based on the fault characteristics, the SMI interrupt is triggered and a fault isolation request is sent to the BIOS.

[0063] Step 102: The basic input / output system responds to the fault isolation request and determines an isolation and repair method according to the memory fault characteristics.

[0064] Step 103: Repair the memory fault based on the isolation repair method.

[0065] The BIOS responds to the fault isolation request and obtains information such as the memory fault type, address, and location. The corresponding isolation and repair method is selected according to the fault characteristics. Through the selected isolation and repair method, the faulty memory area is isolated from the system so that the system can continue to operate normally.

[0066] Step 104: If the fault prediction and self-healing system is in a closed state, the basic input and output system responds to a triggering event of a preset trigger condition to repair the memory fault.

[0067] BIOS determines whether the FPC system is in the off state through the flag sent by BMC. If the FPC system is in the off state, BIOS does not process the preset trigger condition of the CPU, that is, the preset trigger condition remains in the default state (on state). In one embodiment, the user can manually set the switch state of the preset trigger condition in the BIOS interface. In this embodiment, if the preset trigger condition is triggered, the CPU will generate an SMI signal to notify the BIOS that the preset trigger condition is triggered. The BIOS responds to this interrupt and repairs the memory fault according to the specific type of the preset trigger condition that is triggered.

[0068] The memory fault handling method of this embodiment implements a BIOS-level memory fault isolation mechanism to ensure that the operating system only uses healthy memory units without defects, thereby significantly reducing the system instability and crash risks caused by memory faults. This mechanism can quickly isolate the faulty memory unit, greatly reducing the unplanned downtime caused by memory problems, and ensuring the continuity and high stability of business operations. In addition, BIOS-level fault isolation promptly cuts off the connection channel between the faulty memory and the system, which can prevent sensitive information from being leaked through damaged memory units.

[0069] In one embodiment of the present disclosure, an isolation repair method is determined according to the memory fault characteristics, which can be specifically implemented through the following steps: determine the fault type according to the memory fault characteristics; if the fault type is a single-bit error, determine the isolation repair method as the first repair method; if the fault type is a row error, determine the isolation repair method as the second repair method; if the fault type is other errors, determine the isolation repair method as the third repair method.

[0070] In the present disclosure, it is first determined whether the fault type is a single-bit error, a row error, or other types of errors other than the two. Then, corresponding repair methods are performed according to different types of errors.

[0071] Specifically, if it is a single-bit error, the first repair method is executed. The first repair method includes: first determining whether there are available PCLS resources; if so, immediately performing a PCLS isolation operation. This allows the system to continue to use the cache line normally and will not be affected by the single-bit error. If there are no available PCLS resources, the operating system performs a page offline operation to remove the memory page with the error from the system to prevent the erroneous data from being used.

[0072] If it is a row error, execute the second repair method. The second repair method includes: updating the physical location repair record (PPRAdress), and determining whether the memory where the error occurs is an X4 particle. If so, determine whether there are available Adddc (Adaptive Double Device Data Correction) resources. If so, perform the Adddc operation according to the updated physical location repair record to isolate the storage array, and isolate the storage array with errors from the system. If not, determine whether there are available Sddc (Single Device Data Correction) resources. If so, perform the Sddc operation according to the updated physical location repair record to isolate the particles, and isolate the memory particles with errors from the system.

[0073] If it is an error other than a particle error and a row error, execute the third repair method. The third repair method includes: directly determining whether the memory in which the error occurs is an X4 particle, and if so, determining whether there are available Adddc resources. If so, executing the Adddc operation to isolate the storage array, and isolate the storage array containing the error from the system. If not, determine whether there are available Sddc resources. If so, executing the Sddc operation to isolate the particles, and isolate the memory particles containing the error from the system.

[0074] Through the above method, a more comprehensive memory fault isolation operation is achieved. The problem that all memory errors cannot be effectively handled due to the limited PCLS resources and the inability to be used in conjunction with other backup technologies in the existing technology is solved, and the impact of errors on system performance is minimized, ensuring system stability and data integrity.

[0075] In one embodiment, the preset trigger condition includes a PCLS trigger condition; accordingly, the response to the preset trigger condition being triggered event repairs the memory fault, including: responding to the PCLS trigger condition being triggered event, determining whether there are PCLS resources; if there are PCLS resources, executing PCLS isolation; if there are no PCLS resources, executing page offline through the operating system.

[0076] The CPU has a preset threshold for the number of times a PCLS operation can be executed. If the number of times a PCLS operation is executed exceeds the set threshold, the PCLS trigger condition will be triggered. The BIOS responds to the PCLS trigger condition being triggered and determines whether there are any available PCLS resources. If so, the PCLS isolation operation continues to be performed to replace the cache line data with errors. If not, the page offline operation is performed.

[0077] In one possible implementation, the preset trigger condition also includes a modifiable trigger condition; accordingly, the response to the preset trigger condition being triggered to repair the memory fault includes: responding to the modifiable trigger condition being triggered to determine whether the memory is an X4 particle, and if so, determining whether there is an Adddc resource; if there is an Adddc resource, executing Adddc to isolate the storage array; if there is no Adddc resource, determining whether there is an Sddc resource; if there is an Sddc resource, executing the Sddc resource to isolate the particle.

[0078] The CPU has a preset threshold for the number of times that a repair of a correctable fault can be performed. When the number of times a repair of a correctable fault can be performed exceeds the set threshold, the correctable trigger condition will be triggered. The BIOS then responds to the event that the correctable trigger condition is triggered, and determines whether the memory where the error occurs is an X4 particle. If so, determine whether there are available Adddc resources. If so, perform the Adddc operation to isolate the storage array. If not, determine whether there are available Sddc resources. If so, perform the Sddc operation to isolate the particles.

[0079] In order to better understand the above embodiment, a specific implementation method is provided below for illustration. Figure 2 Said method comprises the following steps:

[0080] During the server startup phase:

[0081] The BIOS receives a flag from the BMC that indicates whether the FPC system is turned on.

[0082] If the FPC system is turned on, the BIOS turns off the RAS preset trigger conditions of the CPU. The RAS preset trigger conditions include the correctable trigger conditions (correctable error leak bucket reaches the threshold) and (PCLS trigger condition) PCLS reaches the threshold.

[0083] If the FPC system is turned off, the BIOS does not process the RAS preset trigger conditions of the CPU, that is, these preset trigger conditions remain enabled. Users can also manually set the switch status of the RAS preset trigger conditions in the BIOS interface.

[0084] During server operation:

[0085] If the FPC system is on.

[0086] When an error occurs in the memory module, the BIOS responds to the SMI interrupt and collects detailed information about the fault. The BIOS reports the collected fault information to the BMC. The FDM in the BMC parses the fault information and outputs the fault characteristics through the fault prediction system. The BMC fills in the fault isolation information table and triggers another SMI interrupt through GPIO to send a fault isolation request to the BIOS, notifying the BIOS to perform the isolation operation.

[0087] The BIOS responds to the SMI interrupt from the BMC, obtains the fault isolation request, and obtains memory fault characteristics such as memory fault type, address, and location information.

[0088] Determine the fault type according to the fault characteristics. For different fault types, perform corresponding isolation and repair methods. Specifically, if the fault type is a single bit error (Single Bit Error), determine whether there is a PCLS resource (Sparing). If so, perform PCLS isolation and report the isolation information to the BMC. If not, if there is no executable PCLS resource, the BIOS fills in the APEI table according to the GHES standard. The APEI table is a standardized hardware error reporting structure used to provide detailed information about hardware errors to the operating system. The BIOS notifies the operating system of a hardware error through SCI and provides the error information in the APEI table. After receiving this notification, the operating system will perform corresponding error handling operations, such as pageoffline (remove the faulty memory page from the system). At the same time, the BIOS reports the isolation information to the BMC. If the error type is a row error (Row Error), update the PPR address. And determine whether the memory is an X4 particle. If so, determine whether there is an available Adddc resource. If so, execute Adddc for Bank isolation and report the isolation information to the BMC; if not, determine whether there is an available Sddc resource. If yes, execute Sddc to isolate the particles. If no, report the isolation information to BMC. If the type is other types of errors, directly enter the X4 particle judgment process. If yes, determine whether there are available Adddc resources. If yes, execute Adddc to isolate the storage array (Bank) and report the isolation information to BMC. If no, determine whether there are available Sddc resources. If yes, execute Sddc to isolate the particles and report the isolation information to BMC. If it is not an X4 particle, report the isolation information directly to BMC. BMC records the isolation execution results in the maintenance log based on the received isolation information.

[0089] If the FPC system is in the off state.

[0090] If a single-bit error occurs, PCLS isolation is performed. When the PCLS threshold reaches or exceeds the preset threshold, the PCLS trigger condition is triggered. The CPU generates an SMI to notify the BIOS that an over-threshold event has occurred. The BIOS responds to this SMI interrupt to determine whether there are executable PCLS resources. If so, PCLS isolation is performed. If there are no executable PCLS resources, the BIOS fills in the APEI table according to the GHES standard. The BIOS notifies the operating system of a hardware error through SCI and provides error information in the APEI table. After receiving this notification, the operating system executes page offline. Regardless of whether PCLS isolation is successful, the BIOS will report the results of the isolation operation (including information about the isolated memory area) to the BMC.

[0091] If it is a CE fault (Correctable Error), the corresponding repair method is used for repair (the present disclosure does not limit the specific repair method). When the number of times a correctable fault is repaired exceeds the leak bucket count threshold, the correctable trigger condition is triggered, and the CPU will generate an SMI interrupt to notify the BIOS that an over-threshold event has occurred. In response to this interrupt, the BIOS first determines the type of memory particle that caused the CE fault, whether it is an X4 particle. If so, check whether there are available Adddc resources in the system. If so, the BIOS executes Adddc to perform Bank isolation. After the isolation operation is completed, the BIOS reports the isolation information to the BMC. If not, the BIOS will check whether there are Sddc resources. If so, Sddc is executed for particle isolation to isolate the faulty X4 particle from the system. After the isolation operation is completed, the BIOS reports the isolation information to the BMC. If Sddc isolation fails, the BIOS will not be able to isolate the fault and report it to the BMC.

[0092] According to another aspect of the present disclosure, a memory fault processing device is provided. Figure 3 As shown, the device comprises:

[0093] A repair request module 301 is used to send a fault isolation request in response to a memory fault event if the fault prediction self-healing system is in an open state, wherein the fault isolation request includes a memory fault feature;

[0094] A repair module 302, for the basic input and output system to respond to the fault isolation request and determine an isolation repair method according to the memory fault characteristics;

[0095] The repair module 302 is further used to repair the memory fault based on the isolation repair method;

[0096] The repair module 302 is further configured to repair the memory fault when the fault prediction self-healing system is in a closed state and the basic input / output system responds to an event in which a preset trigger condition is triggered.

[0097] In one embodiment of the present disclosure, the repair module 302 is also used to determine the fault type according to the memory fault characteristics; if the fault type is a single-bit error, the isolation repair method is determined to be the first repair method; if the fault type is a row error, the isolation repair method is determined to be the second repair method; if the fault type is other errors, the isolation repair method is determined to be the third repair method.

[0098] In one embodiment of the present disclosure, the preset trigger condition includes a PCLS trigger condition; accordingly, the repair module 302 is also used to respond to the event that the PCLS trigger condition is triggered to determine whether there are PCLS resources; if there are PCLS resources, perform PCLS isolation; if there are no PCLS resources, execute page offline through the operating system.

[0099] In one embodiment of the present disclosure, the preset trigger condition also includes a modifiable trigger condition; accordingly, the repair module 302 is also used to respond to the event that the modifiable trigger condition is triggered, determine whether the memory is an X4 particle, and if so, determine whether there is an Adddc resource; if there is an Adddc resource, execute Adddc to isolate the storage array; if there is no Adddc resource, determine whether there is an Sddc resource; if there is an Sddc resource, execute Sddc to isolate the particle.

[0100] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device and a readable storage medium.

[0101] Figure 4 A schematic block diagram of an example electronic device 800 that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0102] like Figure 4 As shown, the device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0103] A number of components in the device 800 are connected to the I / O interface 805, including: an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a disk, an optical disk, etc.; and a communication unit 809, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 809 allows the device 800 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0104] The computing unit 801 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 801 performs the various methods and processes described above, such as a memory fault handling method. For example, in some embodiments, the memory fault handling method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of the memory fault handling method described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform the memory fault handling method in any other appropriate manner (e.g., by means of firmware).

[0105] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0106] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0107] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0108] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0109] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0110] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0111] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0112] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0113] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory fault processing method, characterized in that: The method comprises: If the fault prediction self-healing system is in an open state, in response to a memory fault event, a fault isolation request is sent, wherein the fault isolation request includes a memory fault feature; The basic input and output system responds to the fault isolation request and determines an isolation and repair method according to the memory fault characteristics; Repairing the memory fault based on the isolation repair method; If the fault prediction and self-healing system is in a closed state, the basic input and output system responds to an event in which a preset trigger condition is triggered to repair the memory fault.

2. The method according to claim 1, characterized in that The determining of the isolation and repair method according to the memory fault characteristics includes: Determine the fault type according to the memory fault characteristics; If the fault type is a single-bit error, determining the isolation repair method to be the first repair method; If the fault type is a row error, determining the isolation repair method to be the second repair method; If the fault type is other errors, the isolation repair method is determined to be the third repair method.

3. The method according to claim 2, characterized in that The first repair method includes: Determine whether some cache lines reserve PCLS resources; If there are PCLS resources, perform PCLS isolation; If there is no PCLS resource, the page is taken offline through the operating system.

4. The method according to claim 2, characterized in that: The second repair method includes: Update the physical location repair record and determine whether the memory is X4 particles. If so, determine whether there is an adaptive dual-particle data correction Adddc resource; If there is an Adddc resource, execute Adddc to isolate the storage array according to the physical location repair record; If there is no Adddc resource, determine whether there is a single-particle data correction Sddc resource; If there are Sddc resources, Sddc is executed to isolate particles according to the physical location repair record.

5. The method according to claim 2, characterized in that: The third repair method comprises: Determine whether the memory is X4 particles. If so, determine whether there are Adddc resources. If there are Adddc resources, execute Adddc to isolate the storage array; If there is no Adddc resource, determine whether there is an Sddc resource; If there are Sddc resources, execute Sddc to isolate particles.

6. The method according to claim 1, characterized in that The preset trigger condition includes a PCLS trigger condition; accordingly, The responding to the event that the preset trigger condition is triggered to repair the memory fault includes: In response to the PCLS trigger condition being triggered, determining whether there are PCLS resources; If there are PCLS resources, perform PCLS isolation; If there is no PCLS resource, the page is taken offline through the operating system.

7. The method according to claim 1, characterized in that The preset trigger conditions also include trigger conditions that can be modified; accordingly, The responding to the event that the preset trigger condition is triggered to repair the memory fault includes: In response to the event that the modifiable trigger condition is triggered, determining whether the memory is an X4 particle, and if so, determining whether there is an Adddc resource; If there are Adddc resources, execute Adddc to isolate the storage array; If there is no Adddc resource, determine whether there is an Sddc resource; If there are Sddc resources, execute Sddc to isolate particles.

8. A memory fault processing device, characterized in that: The device comprises: A repair request module, configured to send a fault isolation request in response to a memory fault event if the fault prediction self-healing system is in an open state, wherein the fault isolation request includes a memory fault feature; A repair module, used for the basic input and output system to respond to the fault isolation request and determine the isolation repair method according to the memory fault characteristics; The repair module is further used to repair the memory fault based on the isolation repair method; The repair module is further used for repairing the memory fault when the fault prediction self-healing system is in a closed state and the basic input and output system responds to an event in which a preset trigger condition is triggered.

9. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to make a computer execute the method according to any one of claims 1-7.

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