System and method for testing data access performance of high-bandwidth memory HBM
Through the HBM data memory access performance testing system and methods combining hardware and software, the problems of poor performance testing of HBM data memory access performance and high testing costs in the existing technology are solved, and efficient and convenient HBM data memory access performance testing and simulation are achieved, reducing trial and error costs.
Patent Information
- Application Number
- CN202510178163.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-18
- Publication Date
- 2025-06-06
AI Technical Summary
When testing the data memory access performance of high-bandwidth memory HBM, it is difficult to effectively explain the memory access behavior of the accelerator under complex computing tasks, resulting in poor simulation testing. In addition, hardware testing is carried out for each memory access strategy and each computing task. The test is difficult and time-consuming, resulting in excessive testing costs.
It provides a HBM data memory access performance testing system and method. Through the combination of hardware and software, it tests the HBM memory access behavior of the hardware to be tested under a specific HBM data access/storage strategy, generates an HBM memory access performance report, and establishes an HBM memory access simulation model based on the report, conducts simulation testing, and supports the testing/simulation of complex memory access behavior.
It realizes efficient and convenient HBM data memory access performance testing/simulation, reduces the trial and error cost of HBM memory access strategy design, supports the testing of complex memory access behavior, and improves the testing accuracy and efficiency.
Smart Images
Figure CN120104490A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of testing technology, and in particular to a high bandwidth memory (HBM) data access performance testing system and method. Background Art
[0002] With the development of large models, the demand for computing bandwidth for dedicated accelerators for large models continues to grow. As an advanced data storage and transmission architecture, High Bandwidth Memory (HBM) has shown unique advantages in dedicated accelerators that solve the "memory wall" with its high bandwidth and low latency. In order to achieve the versatility of high-bandwidth transmission, the current HBM data access routing form is relatively complex. There are usually multiple routing nodes (Switch) at the data exchange point, and the HBM access (access / storage in this disclosure) strategy (how to access / store HBM) has a great impact on the performance of the accelerator. Therefore, when a certain HBM access strategy is designed for the accelerator, it is necessary to test the HBM access performance when the HBM access strategy is adopted to verify whether the HBM access strategy is suitable for the accelerator. Summary of the invention
[0003] In the related art, the test / simulation method for HBM memory access performance only obtains the HBM memory access performance test result of the accelerator by actually testing the HBM single memory access behavior of the accelerator under a specific computing task, or only simulating the HBM memory access behavior of the accelerator through software. However, for system-level accelerator hardware design, software simulation alone cannot explain the memory access behavior of the accelerator under complex computing tasks, such as access merging, non-continuous memory access, etc., resulting in poor simulation test results. If hardware testing is performed for each memory access strategy and each computing task, the test will be difficult and time-consuming, resulting in excessively high test costs.
[0004] In response to the problems existing in the related technology, the present disclosure provides an HBM data memory access performance testing system and method, which provides an efficient and convenient HBM data memory access performance testing / simulation system and method in a combination of hardware and software, supports testing / simulation of complex memory access behaviors of HBM, and reduces the trial and error cost of HBM memory access strategy design.
[0005] In a first aspect, an embodiment of the present disclosure provides a high bandwidth memory HBM data access performance test system, comprising:
[0006] The HBM test hardware platform is configured to test the HBM memory access performance of the hardware under test under a predetermined HBM memory access behavior using a test instruction, and generate an HBM memory access performance report of the hardware under test according to the test result, wherein the test instruction is generated according to the predetermined HBM memory access behavior;
[0007] The HBM software analyzer is configured to establish an HBM memory access simulation model of the hardware to be tested based on the HBM memory access performance report, and use simulation instructions to enable the HBM memory access simulation model to simulate the HBM memory access performance of the hardware to be tested when performing a predetermined computing task, wherein the simulation instructions are generated according to the predetermined computing task.
[0008] Furthermore, the HBM test hardware platform includes:
[0009] An HBM interface, including an HBM and a data path interconnect, wherein the data path interconnect connects a data path of the HBM and has a data interface connected to the hardware to be tested;
[0010] A test instruction interface, comprising an instruction transmitting component and a controller, wherein the instruction transmitting component stores the test instruction for the hardware to be tested, and the controller controls the instruction transmitting component to transmit the test instruction according to a test start signal; and
[0011] The hardware to be tested includes one or more processing units, and the one or more processing units perform corresponding HBM memory access behaviors according to the test instructions.
[0012] In addition, the HBM test hardware platform also includes a monitor, which is configured to monitor the HBM memory access behavior of each processing unit of the hardware to be tested, and feed back the HBM memory access latency of each processing unit as a test result.
[0013] In addition, a test instruction corresponding to the predetermined HBM memory access behavior defined by the user is generated by the compiler, and the test instruction is saved to the instruction issuing component.
[0014] In addition, a simulation instruction corresponding to the predetermined computing task is generated by a compiler, and the simulation instruction is input into the HBM memory access simulation model, so that the HBM memory access simulation model simulates the HBM memory access performance of the hardware under test when executing the predetermined computing task.
[0015] In a second aspect, an embodiment of the present disclosure provides a method for testing the data access performance of a high bandwidth memory HBM, including:
[0016] Using a test instruction to test the HBM memory access performance of the hardware under test under a predetermined HBM memory access behavior, and generating an HBM memory access performance report of the hardware under test according to the test result, wherein the test instruction is generated according to the predetermined HBM memory access behavior; and
[0017] An HBM memory access simulation model of the hardware to be tested is established based on the HBM memory access performance report, and the HBM memory access simulation model is used to simulate the HBM memory access performance of the hardware to be tested when executing a predetermined computing task using simulation instructions, wherein the simulation instructions are generated according to the predetermined computing task.
[0018] In addition, the method also includes: transmitting a test instruction according to a test start signal to make the hardware under test perform the predetermined HBM memory access behavior, thereby testing the HBM memory access performance of the hardware under test under the predetermined HBM memory access behavior; and using a monitor to monitor the HBM memory access behavior of the hardware under test, and feeding back the HBM memory access latency of the hardware under test as a test result.
[0019] In addition, the method further includes: generating, by a compiler, a test instruction corresponding to the predetermined HBM memory access behavior defined by a user.
[0020] In addition, the method further includes: generating simulation instructions corresponding to the predetermined computing task through a compiler, and inputting the simulation instructions into the HBM memory access simulation model, so that the HBM memory access simulation model simulates the HBM memory access performance of the hardware under test when executing the predetermined computing task.
[0021] In a third aspect, an embodiment of the present disclosure provides an electronic device, including:
[0022] at least one processor; and
[0023] a memory communicatively coupled to the at least one processor, wherein:
[0024] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the high bandwidth memory HBM data access performance testing method according to the embodiment of the present disclosure.
[0025] Other optional features and technical effects of the embodiments of the present disclosure are partially described below, and partially can be understood by reading this document.
[0026] Compared with the related art, the present invention has the following beneficial technical effects:
[0027] The HBM data access performance test system and method disclosed in the present invention can test the performance of the hardware under test when performing corresponding HBM memory access behavior under a specific HBM data access / storage strategy, such as memory access latency, in a combination of hardware and software. An efficient and convenient HBM data access performance test / simulation system and method are provided, which supports testing / simulation of complex memory access behaviors of HBM and reduces the trial-and-error cost of HBM memory access strategy design. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] In order to make the purpose, technical solution and advantages of the present disclosure more clear, the present disclosure is further described in detail below in conjunction with specific implementation methods and drawings. Here, the illustrative implementation methods and descriptions of the present disclosure are used to explain the present disclosure, but are not intended to limit the present disclosure.
[0029] As used herein, the term "including" and its variations mean open inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "based at least in part on". The terms "an example embodiment" and "an embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may also be included below.
[0030] Figure 1 An exemplary structural block diagram of an HBM data access performance test system according to an embodiment of the present disclosure is shown;
[0031] Figure 2 An exemplary structural block diagram of an HBM test hardware platform according to an embodiment of the present disclosure is shown;
[0032] Figure 3 An exemplary flow chart of a method for testing HBM data access performance according to an embodiment of the present disclosure is shown;
[0033] Figure 4 An exemplary structural diagram of a device capable of implementing the method according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION
[0034] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
[0035] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.
[0036] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein may be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present disclosure, it should be understood by those skilled in the art that an aspect described herein may be implemented independently of any other aspect, and two or more of these aspects may be combined in various ways. For example, any number of aspects described herein may be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein may be used to implement this device and / or practice this method.
[0037] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present disclosure. The drawings only show components related to the present disclosure rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0038] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.
[0039] Refer to the following Figures 1 to 3 The details of the HBM data access performance testing system and method according to the embodiment of the present disclosure are described in detail. Figure 1 FIG. 4 shows an exemplary structural block diagram of an HBM data access performance test system according to an embodiment of the present disclosure. Figure 2 FIG. 4 shows an exemplary structural block diagram of an HBM test hardware platform according to an embodiment of the present disclosure. Figure 3 An exemplary flow chart of a method for testing HBM data access performance according to an embodiment of the present disclosure is shown.
[0040] like Figure 1 As shown, the HBM data access performance testing system according to the embodiment of the present disclosure includes an HBM testing hardware platform and an HBM software analyzer.
[0041] The HBM test hardware platform is configured to test the HBM memory access performance of the hardware under test under a predetermined HBM memory access behavior using a test instruction, and generate an HBM memory access performance report of the hardware under test according to the test result, wherein the test instruction is generated according to the predetermined HBM memory access behavior. The above operation of the HBM test hardware platform may correspond to, for example Figure 3 Step S101 in the HBM data access performance testing method 100.
[0042] The HBM software analyzer is configured to establish an HBM memory access simulation model of the hardware under test based on the HBM memory access performance report, and use simulation instructions to enable the HBM memory access simulation model to simulate the HBM memory access performance of the hardware under test when performing a predetermined computing task, wherein the simulation instructions are generated according to the predetermined computing task. The above operations of the HBM software analyzer may correspond to, for example, Figure 3 Step S102 in the HBM data access performance testing method 100.
[0043] In some embodiments, the HBM test hardware platform may include, for example, an HBM interface, a test instruction interface, and hardware to be tested. Figure 2 As shown, the HBM interface may include, for example, HBM and data path interconnection. HBM is a high bandwidth memory, which is formed by stacking multiple DRAM chips together and packaging them. The data path interconnection is used to provide a data transmission path between the HBM and the hardware under test, which can connect to the data path of the HBM and has a data interface connected to the hardware under test. The hardware under test includes one or more processing units (such as GPU, CPU, etc.). Figure 2 In the application scenario of a large model dedicated accelerator, the hardware to be tested may be, for example, a hardware accelerator, and the processing unit may be, for example, a computing unit of the accelerator, which is used to perform a specific large model computing task. In the present disclosure, the purpose of performing HBM data access performance testing is to test the performance of the hardware to be tested, such as memory access latency, when the hardware to be tested performs corresponding HBM memory access behaviors under specific HBM data access / storage strategies. Therefore, the HBM test hardware platform according to an embodiment of the present disclosure enables one or more processing units of the hardware to be tested to perform corresponding HBM memory access behaviors according to test instructions to test the memory access performance of the hardware to be tested. It should be understood that although the memory access performance of the hardware to be tested is described in the present disclosure using memory access latency as an example, the memory access performance of the hardware to be tested is not limited to memory access latency, but may also be performance indicators such as data throughput, response time, and resource utilization.
[0044] like Figure 2 As shown, the test instruction interface of the HBM test hardware platform may include an instruction transmitting component ( Figure 2 The instruction emission component is used to store the test instructions for the hardware to be tested, and the controller controls the instruction emission component to emit the test instructions according to the test start signal. The instruction emission component can be as follows Figure 2 As in the example, each instruction emission component is set up separately for each processing unit of the hardware to be tested, and each instruction emission component only saves and emits the test instruction for the corresponding processing unit. The instruction emission component can also be set up one for each fixed number of processing units, or one for all processing units in the hardware to be tested, as long as the function of saving and emitting the test instruction for each processing unit can be realized.
[0045] In some embodiments, the HBM test hardware platform may also include a monitor, for example. The monitor may be configured to monitor the HBM memory access behavior of each processing unit of the hardware to be tested during the test, and feedback, for example, the HBM memory access latency of each processing unit as a test result. Specifically, the monitor may be configured to monitor whether each processing unit of the hardware to be tested correctly performs the HBM memory access behavior corresponding to the test instruction, as well as the memory access progress, memory access speed, etc., and record and feedback the HBM memory access latency of each processing unit as a test result, thereby enabling the user to intuitively grasp the HBM memory access performance of each processing unit. The monitor may be, for example, the same as the display of the host computer described later, or it may be a separate monitor.
[0046] The HBM data access performance testing method according to an embodiment of the present disclosure is described in detail below.
[0047] When the HBM memory access performance test system according to the embodiment of the present disclosure is used to perform the HBM memory access performance test of the hardware to be tested, first, the user can customize the HBM memory access behavior according to the designed HBM memory access strategy. For example, the user can customize the HBM memory access behavior that the user wants to test on the hardware to be tested in the graphical user interface displayed on the display of the host computer, or customize the HBM memory access behavior by entering a command line, programming code, etc. in the display of the host computer. The HBM memory access behavior can, for example, indicate which processing unit or units of the hardware to be tested perform access / storage of how much data at what timing. The user-defined HBM memory access behavior can, for example, generate a test instruction corresponding to the HBM memory access behavior that can be executed by the compiler in the host computer, and send the test instruction to the instruction emission component in the HBM test hardware platform, and the instruction emission component saves the test instruction for the corresponding processing unit of the hardware to be tested.
[0048] At the beginning of the test, the user can, for example, input a test start signal through the host computer, and the host computer sends the test start signal to the controller in the HBM test hardware platform. The controller controls the instruction transmitting component to transmit the test instruction to the corresponding processing unit of the hardware to be tested according to the test start signal. After receiving the test instruction, the corresponding processing unit performs the corresponding HBM memory access behavior according to the test instruction, that is, accesses / stores a specific amount of data on the HBM at a specific timing through the data path interconnection. The monitor of the HBM test hardware platform monitors the HBM memory access behavior of each processing unit of the hardware to be tested, and feeds back the HBM memory access latency of each processing unit as the test result. When the monitor of the HBM test hardware platform is the same as the display of the host computer, the user can directly grasp the test process and test results intuitively through the display of the host computer. When the monitor of the HBM test hardware platform is different from the display of the host computer, the monitor of the HBM test hardware platform feeds back the HBM memory access latency of each processing unit to the host computer as the test result.
[0049] After obtaining the test results (e.g., memory access latency) of the HBM memory access performance of the hardware to be tested under the predetermined HBM memory access behavior through testing, the HBM test hardware platform can also generate an HBM memory access performance report of the hardware to be tested based on the test results. After generating the HBM memory access performance report of the hardware to be tested, the HBM test hardware platform can, for example, send the performance report to the HBM software analyzer. The HBM software analyzer can establish an HBM memory access simulation model of the hardware to be tested based on the HBM memory access performance report. The format of the HBM memory access performance report and the method for establishing the HBM memory access simulation model are not limited in the present disclosure, as long as the HBM memory access performance report can be used to establish the HBM memory access simulation model, and the HBM memory access simulation model is established based on the HBM memory access performance report and can simulate the HBM memory access behavior of the hardware to be tested.
[0050] After the HBM software analyzer establishes the HBM memory access simulation model of the hardware to be tested based on the HBM memory access performance report obtained by the HBM test hardware platform, the HBM memory access simulation model can be used to simulate the HBM memory access performance of the hardware to be tested when performing a predetermined computing task. When performing the simulation, the user can, for example, first specify the computing task. In the application scenario of a large model dedicated accelerator, the computing task can, for example, be a related computing task to be performed by the accelerator during the training / inference process. The user specifies the computing task to be simulated, for example, in a graphical user interface displayed on the display of the host computer, or can specify the computing task in the display of the host computer by entering a command line, programming code, etc. The hardware to be tested has different HBM memory access behaviors under different computing tasks. Therefore, by specifying the computing task, the HBM software analyzer can simulate the HBM memory access behavior corresponding to the specified computing task.
[0051] The computing task specified by the user can, for example, generate simulation instructions corresponding to the computing task that can be executed by the HBM software analyzer through the compiler in the host computer, and input the simulation instructions into the HBM memory access simulation model in the HBM software analyzer. The HBM memory access simulation model simulates the HBM memory access performance of the hardware under test when executing the computing task according to the simulation instructions, and obtains, for example, the HBM memory access latency of the hardware under test as the simulation result.
[0052] Therefore, when it is desired to test the HBM memory access performance of the hardware under test when executing a specific computing task, it is not necessary to make the hardware under test actually execute the computing task, but it is possible to efficiently and conveniently simulate the HBM memory access performance of the hardware under test when executing a specific computing task by making the HBM software analyzer run the HBM memory access simulation model of the hardware under test, saving the testing cost and testing time, and being able to support the testing / simulation of complex memory access behaviors of HBM, reducing the trial-and-error cost of HBM memory access strategy design. Since the HBM memory access simulation model is established based on the HBM test hardware platform actually testing the memory access performance of the hardware under test under the predetermined HBM memory access behavior, the simulation accuracy of the HBM memory access simulation model can be guaranteed.
[0053] It should be understood that when using the HBM software analyzer to perform HBM memory access performance simulation, the host computer, display, and compiler used by the user can be the same host computer, display, and compiler as when using the HBM test hardware platform to perform HBM memory access performance testing, or they can be different host computers, displays, or compilers. The HBM software analyzer can be directly installed on the host computer as software or an application, or it can be installed on a computer or server different from the host computer. When using the same host computer, display, and compiler to perform HBM memory access performance testing and simulation and the HBM software analyzer is directly installed on the host computer, an example of the host computer can be, for example Figure 4 Device 1000 in.
[0054] like Figure 4As shown, the device 1000 includes a processor 1001, which can perform various appropriate operations and processes according to the program and / or data stored in the read-only memory (ROM) 1002 or the program and / or data loaded from the storage part 1008 to the random access memory (RAM) 1003. Processor 1001 can be a multi-core processor or can include multiple processors. In some embodiments, processor 1001 can include a general main processor and one or more special coprocessors, such as a central processing unit (CPU), a graphics processing unit (GPU), a neural network processor (NPU), a digital signal processor (DSP), etc. In RAM 1003, various programs and data required for the operation of device 1000 are also stored. Processor 1001, ROM 1002 and RAM 1003 are connected to each other via bus 1004. Input / output (I / O) interface 1005 is also connected to bus 1004.
[0055] The processor and the memory are used together to execute the program stored in the memory, and when the program is executed by a computer, the method, steps or functions described in the embodiments of the present disclosure can be implemented.
[0056] The following components are connected to the I / O interface 1005: an input section 1006 including a keyboard, a mouse, a touch screen, etc.; an output section 1007 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 1008 including a hard disk, etc.; and a communication section 1009 including a network interface card such as a LAN card, a modem, etc. The communication section 1009 performs communication processing via a network such as the Internet. A drive 1010 is also connected to the I / O interface 1005 as needed. A removable medium 1011, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 1010 as needed, so that a computer program read therefrom is installed into the storage section 1008 as needed. Figure 4 Only some components are schematically shown in the figure, which does not mean that the device 1000 only includes Figure 4 Components shown.
[0057] The systems, devices, modules or units described in the above embodiments may be implemented by a computer or its associated components. The computer may be, for example, a mobile terminal, a smart phone, a personal computer, a laptop computer, a vehicle-mounted human-computer interaction device, a personal digital assistant, a media player, a navigation device, a game console, a tablet computer, a wearable device, a smart TV, an Internet of Things system, a smart home, an industrial computer, a server or a combination thereof.
[0058] Although not shown, in an embodiment of the present disclosure, a computer-readable storage medium is provided, on which a computer program / instruction is stored. When the computer program / instruction is executed by a processor, the HBM data access performance testing method described in the embodiment is implemented.
[0059] The storage media in the embodiments of the present disclosure include permanent and non-permanent, removable and non-removable items that can be implemented by any method or technology to store information. Examples of storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices or any other non-transmission medium that can be used to store information that can be accessed by a computing device.
[0060] Although not shown, the embodiments of the present disclosure further provide a computer program product, including: a computer program / instruction, which implements the HBM data access performance testing method described in the embodiments when executed by a processor.
[0061] The methods, programs, systems, devices, etc. of the embodiments of the present disclosure may be executed or implemented in a single or multiple networked computers, or may be practiced in a distributed computing environment. In the embodiments of the present specification, in these distributed computing environments, tasks may be performed by remote processing devices connected via a communication network.
[0062] Those skilled in the art should understand that the embodiments of the present specification may be provided as methods, systems or computer program products. Therefore, those skilled in the art may imagine that the functional modules / units or controllers and related method steps described in the above embodiments may be implemented in software, hardware or a combination of software / hardware.
[0063] Unless explicitly stated, the actions or steps of the methods, programs, and embodiments of the present disclosure do not have to be performed in a specific order and can still achieve the desired results. In some implementations, multitasking and parallel processing are also possible or may be advantageous.
[0064] In this article, multiple embodiments of the present disclosure are described, but for the sake of brevity, the description of each embodiment is not exhaustive, and the same or similar features or parts between the embodiments may be omitted. In this article, "one embodiment", "some embodiments", "example", "specific example", or "some examples" are meant to be applicable to at least one embodiment or example according to the present disclosure, rather than all embodiments. The above terms do not necessarily mean to refer to the same embodiment or example. In the absence of contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples.
[0065] The exemplary systems and methods of the present disclosure have been specifically shown and described with reference to the above embodiments, which are merely examples of the best modes for implementing the present systems and methods. It will be appreciated by those skilled in the art that various changes may be made to the embodiments of the systems and methods described herein when implementing the present systems and / or methods without departing from the spirit and scope of the present disclosure as defined in the appended claims.
Claims
1. A high bandwidth memory HBM data access performance test system, characterized in that: include: The HBM test hardware platform is configured to test the HBM memory access performance of the hardware under test under a predetermined HBM memory access behavior using a test instruction, and generate an HBM memory access performance report of the hardware under test according to the test result, wherein the test instruction is generated according to the predetermined HBM memory access behavior; The HBM software analyzer is configured to establish an HBM memory access simulation model of the hardware to be tested based on the HBM memory access performance report, and use simulation instructions to enable the HBM memory access simulation model to simulate the HBM memory access performance of the hardware to be tested when performing a predetermined computing task, wherein the simulation instructions are generated according to the predetermined computing task.
2. The HBM data access performance test system according to claim 1, characterized in that: The HBM test hardware platform includes: An HBM interface, including an HBM and a data path interconnect, wherein the data path interconnect connects a data path of the HBM and has a data interface connected to the hardware to be tested; A test instruction interface, comprising an instruction transmitting component and a controller, wherein the instruction transmitting component stores the test instruction for the hardware to be tested, and the controller controls the instruction transmitting component to transmit the test instruction according to a test start signal; and The hardware to be tested includes one or more processing units, and the one or more processing units perform corresponding HBM memory access behaviors according to the test instructions.
3. The HBM data access performance test system according to claim 2, characterized in that: The HBM test hardware platform also includes a monitor, which is configured to monitor the HBM memory access behavior of each processing unit of the hardware to be tested, and feed back the HBM memory access latency of each processing unit as a test result.
4. The HBM data access performance test system according to claim 2 or 3, characterized in that: A test instruction corresponding to the predetermined HBM memory access behavior defined by the user is generated by a compiler, and the test instruction is saved to the instruction issuing component.
5. The HBM data access performance test system according to claim 1, characterized in that: A simulation instruction corresponding to the predetermined computing task is generated by a compiler, and the simulation instruction is input into the HBM memory access simulation model, so that the HBM memory access simulation model simulates the HBM memory access performance of the hardware under test when executing the predetermined computing task.
6. A method for testing the data access performance of a high bandwidth memory HBM, characterized in that: include: Using a test instruction to test the HBM memory access performance of the hardware under test under a predetermined HBM memory access behavior, and generating an HBM memory access performance report of the hardware under test according to the test result, wherein the test instruction is generated according to the predetermined HBM memory access behavior; as well as An HBM memory access simulation model of the hardware to be tested is established based on the HBM memory access performance report, and the HBM memory access simulation model is used to simulate the HBM memory access performance of the hardware to be tested when executing a predetermined computing task using simulation instructions, wherein the simulation instructions are generated according to the predetermined computing task.
7. The HBM data access performance testing method according to claim 6, characterized in that: The method further comprises: transmitting a test instruction according to a test start signal, so as to make the hardware under test perform the predetermined HBM memory access behavior, thereby testing the HBM memory access performance of the hardware under test under the predetermined HBM memory access behavior; and A monitor is used to monitor the HBM memory access behavior of the hardware under test, and the HBM memory access latency of the hardware under test is fed back as a test result.
8. The HBM data access performance testing method according to claim 7, characterized in that: The method further comprises: A test instruction corresponding to the predetermined HBM memory access behavior defined by the user is generated by the compiler.
9. The HBM data access performance testing method according to claim 6, characterized in that: The method further comprises: A simulation instruction corresponding to the predetermined computing task is generated by a compiler, and the simulation instruction is input into the HBM memory access simulation model, so that the HBM memory access simulation model simulates the HBM memory access performance of the hardware under test when executing the predetermined computing task.
10. An electronic device, comprising: at least one processor; as well as a memory communicatively coupled to the at least one processor, wherein: The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the high bandwidth memory HBM data access performance testing method according to any one of claims 6 to 9.