Differential signal transmission link, high-speed differential signal transmission composite chip and intra-chip differential signal transmission link configuration method

Abstract

The invention discloses a differential signal transmission link, a high-speed differential signal transmission composite chip and an intra-core differential signal transmission link configuration method. A strip line is arranged in a perforated cylinder in a penetrating manner, two differential microstrip lines are horizontally arranged at two ends of the perforated cylinder, one end of one differential microstrip line is connected with the upper end of the strip line, and one end of the other differential microstrip line is connected with the lower end of the strip line; the conductor strip and the two grounding strips in each differential microstrip line are arranged on the total slide glass side by side in the length direction of the total slide glass, the conductor strip is arranged between the two grounding strips, and the multiple capacitors and the multiple inductors are alternately arranged on the conductor strip in the length direction of one side of the conductor strip. The plurality of conductive blocks are uniformly arranged on the conductor belt along the length direction of the other side of the conductor belt; a high-bandwidth storage chip and a GPU chip in the high-speed differential signal transmission composite chip are horizontally arranged on a PCB composite board in parallel, and a differential signal transmission system is arranged among the PCB composite board, the high-bandwidth storage chip and the GPU chip in a penetrating mode.

Description

Technical Field

[0001] This invention specifically relates to a differential signal transmission link, a high-speed differential signal transmission composite chip, and an in-chip differential signal transmission link configuration method, belonging to the field of signal transmission technology. Background Technology

[0002] In the field of high-speed signal transmission, existing differential signal link interconnection structures have many shortcomings. Traditional differential microstrip line structures, due to their open layout, suffer from poor electromagnetic shielding, making it difficult to precisely control the electric field distribution. This results in inaccurate impedance matching, significant electromagnetic interference (EMI) problems, and susceptibility to interference from surrounding circuits and external electromagnetic signals, thus affecting signal transmission quality. Furthermore, existing differential stripline structures exhibit large impedance fluctuations, leading to reflections and attenuation during signal transmission due to impedance instability. This significantly impacts signal transmission stability and fails to meet the stringent requirements of stable transmission for high-speed signals.

[0003] For applications requiring signal delay matching and electromagnetic interference suppression, effective structural designs are currently lacking. Existing signal transmission structures cannot provide good solutions for increasing signal and electromagnetic wave path lengths, making it difficult to achieve accurate delay matching for high-speed signals, and their effectiveness in reducing electromagnetic interference is limited, thus affecting signal integrity.

[0004] Furthermore, existing technologies have significant shortcomings in addressing issues such as signal reflection, attenuation, and crosstalk. Signal reflection leads to signal distortion at the receiving end, attenuation reduces signal strength and recognizability, and crosstalk introduces additional noise, severely compromising signal integrity. Consequently, the overall performance of the circuit is unsatisfactory in practical use, falling far short of expectations.

[0005] On complex multilayer PCBs, signals often need to be transferred between layers via vias. As signal frequencies and bandwidths increase, the impedance matching between vias and signal lines becomes increasingly critical, significantly impacting signal transmission and integrity within the channel. System analysis reveals two main factors affecting impedance matching between vias and signal lines: first, the via's structure itself, commonly including the via itself and anti-pads; and second, the useless residual spikes left after the signal transfers through the via. Based on these two factors, commonly used methods for adjusting via impedance matching include: 1. Establishing a simulation model and adjusting the anti-pad diameter in simulation software to achieve impedance matching; 2. Adding terminating resistors, capacitors, or inductors at the via's end to counteract the effects of residual spikes; and 3. Removing residual spikes using back drilling.

[0006] However, the via structure in existing technologies is too simple. Even with simulation software optimization, only the diameter of the anti-pad for each via on the PCB layer can be adjusted, which cannot achieve good impedance matching over a wide bandwidth. Adding terminating capacitors, resistors, and inductors to remove residual vias only works in very narrow signal bandwidths. When back-drilling vias, the deeper the drill, the larger the tolerance becomes, making tolerance control difficult when the board thickness exceeds 3mm. At high signal bandwidths and frequencies, back-drilling may not even provide any beneficial effects.

[0007] Furthermore, existing through-silicon via (TSV) structures also have shortcomings in signal integrity, making it difficult to effectively reduce inter-symbol interference (ISI), reflected signals, and suppress crosstalk. For complex interference problems in high-speed signal transmission scenarios, TSV structures cannot provide an ideal solution, limiting their application in high-performance electronic systems. In short, currently, there is a lack of active standardization quantization compensation processing methods that combine high speed and stability in signal transmission. Summary of the Invention

[0008] This invention provides a differential signal transmission link, a high-speed differential signal transmission composite chip, and an in-chip differential signal transmission link configuration method to solve the above problems.

[0009] A differential signal transmission link includes a perforated cylinder, a stripline, and two differential microstrip lines. The perforated cylinder is vertically positioned, and the stripline passes through the cylinder along its axial direction. The two differential microstrip lines are horizontally positioned at both ends of the perforated cylinder from top to bottom. One end of one of the differential microstrip lines is connected to the upper end of the stripline, and one end of the other differential microstrip line is connected to the lower end of the stripline. Each differential microstrip line includes a carrier and a conductor. The device consists of a conductor strip, two grounding strips, multiple capacitors, multiple inductors, and multiple conductive blocks. The overall carrier sheet is a strip-shaped sheet. The conductor strip and the two grounding strips are arranged side by side on the overall carrier sheet along its length. The conductor strip is positioned between the two grounding strips. The multiple capacitors, multiple inductors, and multiple conductive blocks are all arranged on the conductor strip. The multiple capacitors and multiple inductors are alternately arranged on one side of the conductor strip along its length, and the multiple conductive blocks are evenly arranged on the conductor strip along the other side of its length.

[0010] A high-speed differential signal transmission composite chip, utilizing the aforementioned differential signal transmission link, includes a PCB composite board, a high-bandwidth memory chip, a GPU chip, and a differential signal transmission system. The PCB composite board is horizontally arranged, and the high-bandwidth memory chip and GPU chip are horizontally arranged side-by-side on the PCB composite board. A differential signal transmission system is disposed between the PCB composite board, the high-bandwidth memory chip, and the GPU chip. The differential signal transmission system includes multiple perforated cylinders, multiple striplines, and multiple differential microstrip lines. At least one perforated cylinder is disposed within the PCB composite board along its height direction, at least one perforated cylinder is disposed within the high-bandwidth memory chip along its height direction, and at least one perforated cylinder is disposed within the GPU chip along its height direction. A stripline is disposed within each perforated cylinder, and a differential microstrip line is horizontally disposed between two adjacent striplines.

[0011] An intra-chip differential signal transmission link configuration method is used to form the above-mentioned high-speed differential signal transmission composite chip. The intra-chip differential signal transmission link configuration method is a process of matching the arrangement height and position of the differential signal transmission system according to the height and length values ​​of the PCB composite board, high-bandwidth memory chip and GPU chip. The differential signal transmission system is divided into three components: one component is set in the PCB composite board, one component is set in the high-bandwidth memory chip, and one component is set in the GPU chip. The process of configuring the components within the PCB composite board is as follows: 2N perforated cylinders are vertically arranged side-by-side according to the height of the PCB composite board. Each perforated cylinder contains a strip line. The total height of the N perforated cylinders is matched to the height of the PCB composite board. A differential microstrip line is horizontally arranged between two adjacent perforated cylinders, and the length of the differential microstrip line corresponds to the horizontal distance between the two perforated cylinders. The differential microstrip line between the two vertically arranged perforated cylinders at the bottom of the PCB composite board is the maximum length differential microstrip line, ensuring that the length of the maximum length differential microstrip line and the length of the PCB composite board meet the predetermined quantity arrangement requirements. The strip lines within the two vertically arranged perforated cylinders at the bottom of the PCB composite board are connected to the components within the high-bandwidth memory chip and the GPU chip, respectively. The process of configuring the components within the high-bandwidth memory chip is as follows: A perforated cylinder is configured according to the height value of the high-bandwidth memory chip. The height of the perforated cylinder is set to match the height of the high-bandwidth memory chip. The perforated cylinder is vertically inserted into the high-bandwidth memory chip. A strip line is inserted into the perforated cylinder. A differential microstrip line is horizontally arranged between the perforated cylinder and a perforated cylinder on the top of the adjacent PCB composite board. The length of the differential microstrip line and the length of the high-bandwidth memory chip meet the arrangement requirements of a predetermined quantity relationship. A differential microstrip line is installed inside the GPU chip. This differential microstrip line is connected to a strip line inside a perforated cylinder at the top of the PCB composite board. The length of the differential microstrip line is less than or equal to the length of the GPU chip.

[0012] Compared with the prior art, the present invention provides a differential signal transmission link, a high-speed differential signal transmission composite chip, and an in-chip differential signal transmission link configuration method, which has the following beneficial effects: The differential signal transmission link in this invention is a transmission link formed by using a perforated cylinder, stripline, and differential microstrip line as basic components. It can be adapted to both horizontal and vertical transmission forms, forming an electromagnetic shielding effect. By changing the electric field distribution, the impedance control target is achieved, which can minimize electromagnetic interference and ensure the high-speed and stable transmission of signals.

[0013] The high-speed differential signal transmission composite chip in this invention is based on silicon performance and has a multi-layer composite structure with multi-bit and multi-point signal transmission capabilities. The PCB composite board, high-bandwidth memory chip, GPU chip, and differential signal transmission system work together to reduce the impedance fluctuation of the stripline and improve the stability of signal transmission. The differential microstrip line forms a slow-wave coplanar waveguide periodic structure through the cooperation of the overall carrier, conductor strip, two ground strips, multiple capacitors, multiple inductors, and multiple conductive blocks. This increases the path length of signals and electromagnetic waves, thereby providing the necessary delay matching and reducing electromagnetic interference for high-speed signals. It can ensure the stability and integrity of the internal signal transmission during the signal line and via matching process in the multi-layer PCB board integration process.

[0014] The intra-chip differential signal transmission link configuration method in this invention is a process of configuring and adapting a differential signal transmission system based on the height and length dimensions of the PCB composite board, high-bandwidth memory chip, and GPU chip. This ensures that a high-speed and stable signal transmission structure with reasonable horizontal and vertical configuration is formed between the PCB composite board, high-bandwidth memory chip, and GPU chip, running through all horizontal and vertical positions of the PCB composite board, high-bandwidth memory chip, and GPU chip. The transmission link direction and position meet predetermined requirements and can achieve a standardized and quantifiable configuration process. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the front view structure of the high-speed differential signal transmission composite chip in this invention; Figure 2 This is a top view of the differential microstrip line structure. Figure 3 A schematic diagram of the three-dimensional structure of a differential microstrip line; Figure 4A three-dimensional structural diagram of a differential signal transmission link arranged within a PCB composite board; Figure 5 This is a top view schematic diagram of a differential signal transmission link structure. Figure 6 This is a top view of the differential signal transmission link with the second structural form. Figure 7 This is a side view of the differential signal transmission link with the second structural form. Figure 8 This is a three-dimensional structural diagram of the third type of differential signal transmission link; Figure 9 This is a side view of the high-speed differential signal transmission composite chip. Figure 10 This is a top view of the differential signal transmission link, showing the arrangement of four perforated cylinders. Figure 11 This is a top view of the differential signal transmission link, showing the arrangement of six perforated cylinders. Figure 12 Eye diagram of a high-speed differential signal link interconnect structure containing traditional differential vias; Figure 13 Eye diagram of the high-speed differential signal link interconnect structure after improving the structure of TSV and differential pairs; Figure 14 Eye diagram for simulation of high-speed differential signal link interconnect structure with differential via structure; Figure 15 This is an arrangement diagram of another structural form of differential signal transmission link. In the diagram, the differential microstrip line and the perforated cylinder are arranged in a serpentine pattern and with a 45° oblique outgoing line.

[0016] In the diagram: 1-Perforated cylinder; 1-1-First cylinder; 1-2-Second cylinder; 1-3-Third cylinder; 1-4-Fourth cylinder; 1-5-Fifth cylinder; 1-6-Sixth cylinder; 2-Strip line; 3-Differential microstrip line; 3-1-Total carrier; 3-2-Conductor strip; 3-3-Grounding strip; 3-4-Capacitor; 3-5-Inductor; 3-6-Conductive block; 4-First gap; 5-Second gap; 7-Total substrate; 10-PCB composite board; 10-1-Component layer; 11-High bandwidth memory chip; 11-1-Component sheet; 11-2-Substrate; 12-GPU chip; 13-Conductive copper foil; 14-Disc-shaped wire. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] Specific implementation method one: Combining Figures 1 to 11 This embodiment describes a differential signal transmission link comprising a perforated cylinder 1, a stripline 2, and two differential microstrip lines 3. The perforated cylinder 1 is vertically positioned, and the stripline 2 passes through the perforated cylinder 1 along its axial direction. The two differential microstrip lines 3 are horizontally positioned at both ends of the perforated cylinder 1 from top to bottom. One end of one differential microstrip line 3 is connected to the upper end of the stripline 2, and one end of the other differential microstrip line 3 is connected to the lower end of the stripline 2. Each differential microstrip line 3 includes a carrier plate 3-1, a conductor strip 3-2, two grounding strips 3-3, and multiple capacitors. 3-4, multiple inductors 3-5 and multiple conductive blocks 3-6, the total carrier plate 3-1 is a strip-shaped plate, the conductor strip 3-2 and two grounding strips 3-3 are arranged side by side on the total carrier plate 3-1 along the length direction of the total carrier plate 3-1, the conductor strip 3-2 is arranged between the two grounding strips 3-3, multiple capacitors 3-4, multiple inductors 3-5 and multiple conductive blocks 3-6 are all arranged on the conductor strip 3-2, the multiple capacitors 3-4 and multiple inductors 3-5 are alternately arranged on the conductor strip 3-2 along one side of the conductor strip 3-2, and the multiple conductive blocks 3-6 are evenly arranged on the conductor strip 3-2 along the other side of the conductor strip 3-2.

[0019] In this embodiment, the conductor strip 3-2 is a central conductor strip structure. The two sides of the conductor strip 3-2 are respectively fitted with the two nearby grounding strips 3-3 with gaps, and form a recessed gap with the top surface of the total carrier plate 3-1.

[0020] Furthermore, the conductor strip 3-2 can be an N-shaped, V-shaped, or sinusoidal periodic bending curve, and the grounding metal surfaces on both sides can be the same periodic changing structure as the conductor strip 3-2, or other structures that can prevent electrons from directly hitting the dielectric substrate.

[0021] In this embodiment, stripline 2 is an existing stripline product, specifically a low-loss stripline using Rogers RO4350B dielectric or other striplines, selected according to specific requirements.

[0022] The perforated cylinder 1 of this invention includes an upper ring plate, a cylinder body, and a lower ring plate. The upper and lower ring plates are coaxially and horizontally arranged at both ends of the cylinder body from top to bottom. The perforated cylinder 1 is a signal via structure combining existing through-silicon vias with passive equalizers. This structure can effectively reduce inter-symbol interference (ISI), reduce reflected signals, and suppress crosstalk. It also addresses the signal transmission and integrity issues caused by the matching of signal lines and vias during multilayer PCB integration. This invention provides a multilayer high-frequency PCB and its signal via optimization method. This structural design ensures impedance continuity within the channel, thereby improving signal transmission integrity and optimizing transmission power.

[0023] In this invention, the differential microstrip line 3 comprises a total carrier 3-1, a conductor strip 3-2, two ground strips 3-3, multiple capacitors 3-4, multiple inductors 3-5, and multiple conductive blocks 3-6, which work together to form a slow-wave coplanar waveguide periodic structure. This structure facilitates the extension of the signal and electromagnetic wave path, provides delay matching for high-speed signals, and reduces electromagnetic interference. Its built-in LC resonator has a low-pass filtering function, which can filter high-frequency noise to improve the signal-to-noise ratio, optimize signal integrity and circuit performance, reduce signal reflection, attenuation, and crosstalk, and improve signal transmission quality. The total carrier 3-1 of the differential stripline 3 itself is a three-layer composite structure formed by three vertically positioned structural layers, while the conductor strip 3-2 and the two ground strips 3-3 work together to form another horizontally arranged sandwich composite multilayer structure. The combination of horizontal and vertical multi-directional sandwich structures can effectively suppress stripline impedance fluctuations and enhance signal transmission stability.

[0024] Specific Implementation Method Two: This implementation method is a further limitation of Specific Implementation Method One. In this implementation method, a first gap 4 is formed between one end of each capacitor 3-4 and an adjacent inductor 3-5, and a second gap 5 is formed between two adjacent conductive blocks 3-6. The width of the second gap 5 is smaller than the width of the first gap 4. The width of the recessed gap is larger than the width of the first gap 4, and the width of the recessed gap is larger than the width of the second gap 5.

[0025] Specific Implementation Method 3: This implementation method is a further limitation of Specific Implementation Method 1 or 2. In this implementation method, the length direction of each conductive block 3-6 is in the same direction as the width direction of the total carrier sheet 3-1, and the length of each conductive block 3-6 is less than or equal to half the width of the conductor strip 3-2.

[0026] Specific implementation method four: Combination Figures 1 to 15This embodiment describes a high-speed differential signal transmission composite chip comprising a PCB composite board 10, a high-bandwidth memory chip 11, a GPU chip 12, and a differential signal transmission system. The PCB composite board 10 is horizontally arranged, and the high-bandwidth memory chip 11 and GPU chip 12 are horizontally arranged side-by-side on the PCB composite board 10. A differential signal transmission system is provided between the PCB composite board 10, the high-bandwidth memory chip 11, and the GPU chip 12. The differential signal transmission system includes multiple differential signal transmission links, i.e., the differential signal transmission system includes multiple... The PCB composite board 10 has at least one perforated cylinder 1 along its height direction, the high-bandwidth memory chip 11 has at least one perforated cylinder 1 along its height direction, and the GPU chip 12 has at least one perforated cylinder 1 along its height direction. Each perforated cylinder 1 has a strip line 2 running through it, and a differential microstrip line 3 is horizontally arranged between two adjacent strip lines 2.

[0027] The perforated cylinder 1 in this embodiment is a silicon-based cable routing structure. The perforated cylinder 1 includes an upper ring plate, a cylinder body, and a lower ring plate. The upper and lower ring plates are coaxially and horizontally arranged at both ends of the cylinder body from top to bottom. The perforated cylinder 1 combines the existing silicon through-hole (STI) passive equalizer signal via structure, which effectively reduces ISI inter-symbol interference, reduces reflected signals, and suppresses crosstalk. It also addresses the signal transmission and integrity issues caused by the matching of signal lines and vias during multilayer PCB integration. This provides a multilayer high-frequency PCB and its signal via optimization method. This structural design ensures impedance continuity within the channel, thereby improving signal transmission integrity and optimizing transmission power.

[0028] In this embodiment, stripline 2 is an existing stripline product, specifically a low-loss stripline using Rogers RO4350B dielectric or other striplines, selected according to specific requirements.

[0029] In this embodiment, when the differential microstrip line 3 is positioned horizontally in the PCB composite board 10, the high-bandwidth memory chip 11, and the GPU chip 12, it can be embedded to form a buried structure. The top surface of the differential microstrip line 3 is flush with the horizontal plane of the PCB composite board 10, the high-bandwidth memory chip 11, and the GPU chip 12 where it is located. The differential microstrip line 3 is arranged and placed by processing grooves, thus creating an electromagnetic shield. By changing the electric field distribution, impedance control is achieved, thereby reducing electromagnetic interference.

[0030] In this embodiment, the high-speed differential signal transmission composite chip also incorporates an LC resonator, which exhibits low-pass filtering characteristics. By filtering out high-frequency noise, it improves the signal-to-noise ratio, thereby enhancing signal integrity and overall circuit performance. By slowing down the wave velocity and using filtering functions, signal reflection, attenuation, and crosstalk can be reduced, thus improving signal integrity and reliability.

[0031] The GPU chip 12 in this embodiment is an existing GPU chip, and its structure and working principle are the same as those of existing GPU chips.

[0032] In this embodiment, a conductive copper foil 13 is disposed between two adjacent differential microstrip lines 3. The conductive copper foil 13 is placed in the middle of the differential microstrip lines 3 to form a shielding wall and reduce crosstalk. Below the differential microstrip lines 3 is a hollowed-out core material layer, thereby forming a cavity in the core material that matches the shape of the microstrip line to achieve higher impedance control accuracy. Structures and connection methods not mentioned in this embodiment are the same as in specific embodiments one, two, or three.

[0033] Specific Implementation Method 5: This implementation method is a further limitation of Specific Implementation Method 4. In this implementation method, each differential microstrip line 3 includes a total carrier plate 3-1, a conductor strip 3-2, two grounding strips 3-3, multiple capacitors 3-4, multiple inductors 3-5, and multiple conductive blocks 3-6. The total carrier plate 3-1 is a strip-shaped sheet. The conductor strip 3-2 and the two grounding strips 3-3 are arranged side by side on the total carrier plate 3-1 along the length direction of the total carrier plate 3-1. The conductor strip 3-2 is arranged between the two grounding strips 3-3. The multiple capacitors 3-4, multiple inductors 3-5, and multiple conductive blocks 3-6 are all arranged on the conductor strip 3-2. The multiple capacitors 3-4 and multiple inductors 3-5 are alternately arranged on the conductor strip 3-2 along one side of the conductor strip 3-2, and the multiple conductive blocks 3-6 are evenly arranged on the conductor strip 3-2 along the other side of the conductor strip 3-2.

[0034] Specific Implementation Method Six: This implementation method is a further limitation of Specific Implementation Method Four or Five. In this implementation method, the high-bandwidth memory chip 11 is an existing high-bandwidth memory chip, which includes multiple component wafers 11-1 and a substrate 11-2. The multiple component wafers 11-1 are arranged horizontally on the substrate 11-2 from top to bottom. The composition structure and working principle of the high-bandwidth memory chip 11 are the same as those of existing high-bandwidth memory chips. Two perforated cylinders 1 are provided inside the high-bandwidth memory chip 11 along its height direction. The first cylindrical body 1-1 and the second cylindrical body 1-2 are respectively arranged vertically and alternately inside the high-bandwidth memory chip 11. The first cylindrical body 1-1 is vertically inserted between multiple component chips 11-1 of the high-bandwidth memory chip 11, and the second cylindrical body 1-2 is vertically inserted on the substrate 11-2 of the high-bandwidth memory chip 11. A strip line 2 is inserted inside the first cylindrical body 1-1 and the second cylindrical body 1-2 respectively, and a differential microstrip line 3 is horizontally arranged between the two corresponding strip lines 2 of the first cylindrical body 1-1 and the second cylindrical body 1-2.

[0035] This invention uses a PCB composite board 10 to arrange high-speed channels, providing placement positions for differential signal transmission systems. It adopts corresponding and flexible wiring paths and layout selections, which not only saves costs but also helps to improve the performance indicators of signal integrity, power integrity and electromagnetic compatibility.

[0036] Specific Implementation Method Seven: This implementation method is a further limitation of Specific Implementation Methods Four, Five, or Six. In this implementation method, the PCB composite board 10 includes six constituent layers 10-1, which are horizontally stacked from top to bottom. Four perforated cylinders 1 are inserted into the PCB composite board 10 along its height direction. The four perforated cylinders 1 are a third cylinder 1-3, a fourth cylinder 1-4, a fifth cylinder 1-5, and a sixth cylinder 1-6. The third cylinder 1-3, the fourth cylinder 1-4, the fifth cylinder 1-5, and the sixth cylinder 1-6 are vertically staggered within the PCB composite board 10. The third cylinder 1-3 and the fourth cylinder 1-4 are vertically arranged side-by-side in the upper part of the six constituent layers 10-1. Between the three constituent layers 10-1, a strip line 2 is respectively threaded inside the third cylinder 1-3 and the fourth cylinder 1-4. The fifth cylinder 1-5 and the sixth cylinder 1-6 are vertically arranged side by side between the lower three constituent layers 10-1 of the six constituent layers 10-1. A strip line 2 is respectively threaded inside the fifth cylinder 1-5 and the sixth cylinder 1-6. A differential microstrip line 3 is horizontally arranged between the two strip lines 2 corresponding to the third cylinder 1-3 and the fifth cylinder 1-5. A differential microstrip line 3 is horizontally arranged between the two strip lines 2 corresponding to the fourth cylinder 1-4 and the sixth cylinder 1-6. A differential microstrip line 3 is horizontally arranged between the lower ends of the two strip lines 2 corresponding to the fifth cylinder 1-5 and the sixth cylinder 1-6.

[0037] Furthermore, a main substrate 7 is provided on the top of the PCB composite board 10. The main substrate 7 is bonded and connected to the topmost of the six constituent layers 10-1. The high-bandwidth memory chip 11 and the GPU chip 12 are arranged side by side on the main substrate 7.

[0038] Specific Implementation Method Eight: This implementation method is a further limitation of Specific Implementation Methods Four, Five, Six or Seven. In this implementation method, a differential microstrip line 3 is provided inside the GPU chip 12 along its length direction. The length direction of the differential microstrip line 3 is in the same direction as the length direction of the GPU chip 12. The differential microstrip line 3 is located near the bottom of the GPU chip 12. One end of the differential microstrip line 3 is connected to the upper end of the strip line 2 inside the fourth cylinder 1-4 that is close to it.

[0039] Specific Implementation Method Nine: This implementation method is a further limitation of Specific Implementation Methods Four, Five, Six, Seven or Eight. The upper end of the strip line 2 inside the third cylinder 1-3 is connected to the lower end of the strip line 2 inside the second cylinder 1-2 through a differential microstrip line 3.

[0040] In the six constituent layers 10-1 of the PCB composite board 10, the signal layer, which is the TOP layer, is used to place signal lines. Above it is the main substrate 7, which contains the HBM and Basic Die. The second to fourth layers are the ground layer, the signal layer, and the ground layer, respectively. These three layers together form the "sandwich" structure of the differential stripline 3. The fifth layer is the signal layer, which is used to place power lines and other signal lines. The sixth layer, the Bottom layer, outputs the differential microstrip line 3. The output end of the differential microstrip line 3 is connected to the GPU pads, forming a high-speed signal path.

[0041] Differential microstrip line 3 serves as a signal line to receive signals from HBM and transmits the signals through through-silicon vias to the third signal layer of the PCB. Both sides of the TSV are provided with accompanying ground vias, which can effectively provide a low-impedance return path. After the signal arrives at the third signal layer, it continues to transmit the signal through the differential stripline, and then through the TSV vias all the way to the sixth layer. Finally, the signal is sent to the GPU through differential microstrip line 3.

[0042] In this embodiment, the stacking parameters of the PCB composite board 10 and the parameter design of the transmission lines need to pay attention to the crosstalk between these signal lines and arrange the line layout and component placement reasonably.

[0043] The third signal layer of the PCB composite board 10 has bypass capacitors placed at both ends and bends of the differential stripline, which can effectively filter out high-frequency noise; variable resistors are placed around the power lines to achieve impedance matching.

[0044] In this invention, the differential microstrip line 3 itself, comprising a carrier plate 3-1, a conductor strip 3-2, two grounding strips 3-3, multiple capacitors 3-4, multiple inductors 3-5, and multiple conductive blocks 3-6, forms a slow-wave coplanar waveguide periodic structure. The conductor strip 3-2 and the grounding strips 3-3 on both sides together constitute the coplanar waveguide structure CPW. The periodically arranged metal plates on one side above the conductor strip 3-2 can slow down the speed of electromagnetic waves, thereby achieving slow-wave characteristics; on the other side, the periodically alternating inductors 3-5 and capacitors 3-4 constitute an LC resonator, which can achieve filtering characteristics. These five modules together constitute a slow-wave coplanar waveguide periodic structure with filtering characteristics.

[0045] Specific Implementation Method Ten: Combining Figure 5 , Figure 6 , Figure 7 , Figure 10 and Figure 11 As shown, in this embodiment, the basic connection relationship between the perforated cylinder 1, the strip line 2 and the differential microstrip line 3 is that the strip line 2 passes through the perforated cylinder 1 along the axial direction of the perforated cylinder 1, and a differential microstrip line 3 connects the two strip lines 2.

[0046] Combination Figure 6 and Figure 7 As shown, one type of passive equalizer structure is the PEQ structure, which is a silicon via TSV integrated passive equalizer with PEQ resistors. The PEQ uses a redistribution layer and via connection between the signal TSV and ground GND or TSV. This structure reduces ISI by reducing reflected signals.

[0047] Another structure for passive equalizers is the PEQ structure, which is a TSV integrated passive equalizer with PEQ resistor and PEQ inductor. This structure has the characteristics of a bandpass filter (BPF). At high frequencies, due to the inductance, the impedance of the PEQ is very high, preventing high-frequency spectrum from flowing to the PEQ. By inserting the PEQ, the characteristics of the BPF and the bandwidth with minimized dispersion characteristics are obtained, thereby reducing ISI. Specifically, a differential microstrip line 3 connects two adjacent striplines 2. This differential microstrip line 3 is divided into two segments from the middle, and a disc-shaped conductor 14 is placed between the two segments. The inner center end of the disc-shaped conductor 14 is connected to one of the two segments, and the outer circular end of the disc-shaped conductor 14 is connected to the other segment. The disc-shaped conductor 14 has the same structure as a mosquito coil. Other unmentioned structures and connection relationships are the same as in specific embodiments one, two, three, four, five, six, seven, eight, or nine.

[0048] Detailed Implementation Method Eleven: Combining Figures 1 to 15This embodiment describes the in-chip differential signal transmission link configuration method, which is used to form the above-mentioned high-speed differential signal transmission composite chip. Specifically, it is a process of matching the arrangement height and position of the differential signal transmission system according to the height and length values ​​of the PCB composite board 10, the high-bandwidth memory chip 11, and the GPU chip 12. The differential signal transmission system is divided into three components, with one component each set in the PCB composite board 10, the high-bandwidth storage chip 11, and the GPU chip 12. The process of configuring the components within the PCB composite board 10 is as follows: 2N perforated cylinders 1 are vertically arranged side-by-side according to the height of the PCB composite board 10. Each perforated cylinder 1 contains a strip line 2. The total height of the N perforated cylinders 1 is matched with the height of the PCB composite board 10. A differential microstrip line 3 is horizontally arranged between two adjacent perforated cylinders 1. The length of the differential microstrip line 3 corresponds to the horizontal distance between the two perforated cylinders 1. The differential microstrip line 3 between the two vertically arranged perforated cylinders 1 at the bottom of the PCB composite board 10 is the maximum length differential microstrip line. This ensures that the length of the maximum length differential microstrip line and the length of the PCB composite board 10 meet the predetermined quantity arrangement requirements. The length of the maximum length differential microstrip line ranges from one-fifth to one-third of the length of the PCB composite board 10. The strip lines 2 inside the two vertically arranged perforated cylinders 1 at the bottom of the PCB composite board 10 are connected to the components within the high-bandwidth memory chip 11 and the GPU chip 12, respectively. The process of configuring the components within the high-bandwidth memory chip 11 is as follows: A perforated cylinder 1 is configured according to the height of the high-bandwidth memory chip 11. The height of the perforated cylinder 1 is matched with the height of the high-bandwidth memory chip 11. The perforated cylinder 1 is vertically inserted into the high-bandwidth memory chip 11. A strip line 2 is inserted into the perforated cylinder 1. A differential microstrip line 3 is horizontally arranged between the perforated cylinder 1 and a perforated cylinder 1 on the top of the adjacent PCB composite board 10. The length of the differential microstrip line 3 and the length of the high-bandwidth memory chip 11 meet the arrangement requirements of a predetermined quantity relationship. The length of the differential microstrip line 3 ranges from one-quarter to one-third of the length of the high-bandwidth memory chip 11.

[0049] A differential microstrip line 3 is provided inside the GPU chip 12. The differential microstrip line 3 is connected to a strip line 2 inside a perforated cylinder 1 at the top of the PCB composite board 10. The length of the differential microstrip line 3 is less than or equal to the length of the GPU chip 12.

[0050] In this embodiment, the high-speed differential signal transmission composite chip structure formed by the in-chip differential signal transmission link configuration method includes a PCB composite board 10, a high-bandwidth memory chip 11, a GPU chip 12, and a differential signal transmission system. The PCB composite board 10 is horizontally arranged, and the high-bandwidth memory chip 11 and GPU chip 12 are horizontally arranged side by side on the PCB composite board 10. A differential signal transmission system is provided between the PCB composite board 10, the high-bandwidth memory chip 11, and the GPU chip 12. The differential signal transmission system includes multiple differential signal transmission links, i.e., differential signals... The transmission system includes multiple perforated cylinders 1, multiple strip lines 2, and multiple differential microstrip lines 3. The specific number and composition of the multiple differential signal transmission links are limited according to specific configuration requirements. At least one perforated cylinder 1 is inserted into the PCB composite board 10 along its height direction. At least one perforated cylinder 1 is inserted into the high-bandwidth memory chip 11 along its height direction. At least one perforated cylinder 1 is inserted into the GPU chip 12 along its height direction. A strip line 2 is inserted into each perforated cylinder 1. A differential microstrip line 3 is horizontally arranged between two adjacent strip lines 2.

[0051] In this embodiment, the perforated cylinder 1 is a single-axis cylinder or a double-axis connected cylinder. In the case of a single-axis cylinder, a strip line 2 is inserted inside. The double-axis connected cylinder is composed of two connected single-axis cylinders, which are arranged vertically side by side and connected. Two strip lines 2 are inserted side by side inside the double-axis connected cylinder for the purpose of increasing the transmission of data and for centralized data transmission. The structures and connection relationships not mentioned in this embodiment are the same as those in specific embodiments one, two, three, four, five, six, seven, eight, nine or ten.

[0052] Specific Implementation Method Twelve: This implementation method further defines Specific Implementation Method Eleven. In addition to matching the arrangement height and position of the differential signal transmission system based on the height and length values ​​of the PCB composite board 10, the high-bandwidth memory chip 11, and the GPU chip 12, the method of configuring the intra-chip differential signal transmission link in this implementation method also includes determining the penetration layer thickness of the perforated cylinder 1 in the differential signal transmission system according to predetermined requirements, which is the height of the perforated cylinder 1. It also includes the process of determining the horizontal distance between two adjacent vertically parallel perforated cylinders 1, i.e., the horizontal length arrangement process of the differential microstrip line 3. This is specifically implemented based on the amount of data transmitted and the specific dimensions of the PCB composite board 10, the high-bandwidth memory chip 11, and the GPU chip 12, ensuring that the maximum penetration height of the perforated cylinder 1 is less than or equal to half the total height of the PCB composite board 10, and that the height of the perforated cylinder 1 within the high-bandwidth memory chip 11 is less than or equal to the height of the high-bandwidth memory chip 11.

[0053] Detailed Implementation Method Thirteen: Combining Figure 15As shown, in this embodiment, when planning the routing path of the differential microstrip line 3, both the serpentine and 45° angled outgoing traces of the differential microstrip line 3 are considered. A 45° angled outgoing trace is used to transition between the straight and curved sections of the serpentine line. This combined design can optimize the routing layout and timing matching while meeting signal integrity requirements. Structures and connections not mentioned in this embodiment are the same as in specific embodiments one, two, three, four, five, six, seven, eight, nine, ten, eleven, or twelve.

[0054] Specific Implementation Method Fourteen: Combining Figure 12 , Figure 13 and Figure 14 As shown, in this embodiment, because the signal traces and ground plane are very close, most return paths flow in the ground (GND) region very close to the signal traces. However, since the TSVs are 3-D interconnects, and they share ground TSVs for different signal TSVs, the return paths interfere with each other. This shared return path is a significant problem of increased crosstalk. In the proposed TSV with PEQ, the signal TSV is connected to the target ground (GND) or TSV via the PEQ. Therefore, compared to other ground (GND) or TSVs, the impedance between the target ground (GND) or TSV and the signal TSV is relatively small, so the return path flows directly to the target ground (GND) or TSV. Through this principle, far-end crosstalk (FEXT) and near-end crosstalk (NEXT) can be significantly reduced. The links and composite chips in this invention achieve crosstalk suppression effects, that is, by utilizing the effect of return path separation to alleviate crosstalk.

[0055] analyze Figure 12 The eye diagram of the high-speed differential signal link interconnect structure containing the traditional differential via structure, under the condition of reasonable impedance matching design, shows that the eye diagram generally meets the requirements and the eye width is wide enough. However, the eye height of the eye diagram is not high enough and there is room for optimization. In addition, the jitter is large and the overall eye diagram quality needs to be optimized.

[0056] After improving the structure of TSV and differential pairs, the eye diagram is as follows: Figure 13 As shown, the eye width has been further widened and the eye height has been significantly improved, resulting in better quality than the traditional differential via structure. However, the error change is not significant and further optimization is needed.

[0057] Further optimization of the structural design involves incorporating a slow-wave coplanar waveguide periodic structure and a signal via structure optimization design for the through-silicon via (TSV) integrated passive equalizer (PEQ). The simulated eye diagram is shown below. Figure 14 As shown in the comparison, the eye diagram quality has been significantly improved, with a higher eye height, a wider eye width, and a substantial reduction in jitter. The overall "eye field of view" has become larger, and the overall eye diagram performance is excellent, indicating that the structural improvement is reasonable and adapts to the optimized changes in signal integrity.

Claims

1. A differential signal transmission link, characterized in that: The device includes a perforated cylinder (1), a strip wire (2), and two differential microstrip lines (3). The perforated cylinder (1) is vertically arranged, and the strip wire (2) is inserted into the perforated cylinder (1) along the axial direction. The two differential microstrip lines (3) are arranged horizontally from top to bottom at both ends of the perforated cylinder (1). One end of one of the two differential microstrip lines (3) is connected to the upper end of the strip wire (2), and one end of the other differential microstrip line (3) is connected to the lower end of the strip wire (2). Each differential microstrip line (3) includes a carrier plate (3-1), a conductor strip (3-2), two grounding strips (3-3), multiple capacitors (3-4), and multiple inductors (3-5). -5) and multiple conductive blocks (3-6), the total carrier sheet (3-1) is a strip-shaped sheet, the conductor strip (3-2) and two grounding strips (3-3) are arranged side by side on the total carrier sheet (3-1) along the length direction of the total carrier sheet (3-1), the conductor strip (3-2) is arranged between the two grounding strips (3-3), multiple capacitors (3-4), multiple inductors (3-5) and multiple conductive blocks (3-6) are all arranged on the conductor strip (3-2), the multiple capacitors (3-4) and multiple inductors (3-5) are alternately arranged on the conductor strip (3-2) along one side of the conductor strip (3-2), and the multiple conductive blocks (3-6) are evenly arranged on the conductor strip (3-2) along the other side of the conductor strip (3-2).

2. The differential signal transmission link according to claim 1, characterized in that: A first gap (4) is formed between one end of each capacitor (3-4) and an adjacent inductor (3-5), and a second gap (5) is formed between two adjacent conductive blocks (3-6). The width of the second gap (5) is smaller than the width of the first gap (4).

3. The differential signal transmission link according to claim 1, characterized in that: The length direction of each conductive block (3-6) is in the same direction as the width direction of the total carrier sheet (3-1), and the length of each conductive block (3-6) is less than or equal to half the width of the conductor strip (3-2).

4. A high-speed differential signal transmission composite chip, comprising a differential signal transmission link according to any one of claims 1 to 3, characterized in that: The device includes a PCB composite board (10), a high-bandwidth memory chip (11), a GPU chip (12), and a differential signal transmission system. The PCB composite board (10) is horizontally arranged, and the high-bandwidth memory chip (11) and the GPU chip (12) are horizontally arranged side by side on the PCB composite board (10). A differential signal transmission system is provided between the PCB composite board (10), the high-bandwidth memory chip (11), and the GPU chip (12). The differential signal transmission system includes multiple perforated cylinders (1), multiple strip lines (2), and multiple differential microstrip lines (3). At least one perforated cylinder (1) is provided inside the PCB composite board (10) along its height direction, at least one perforated cylinder (1) is provided inside the high-bandwidth memory chip (11) along its height direction, and at least one perforated cylinder (1) is provided inside the GPU chip (12) along its height direction. A strip line (2) is provided inside each perforated cylinder (1), and a differential microstrip line (3) is horizontally arranged between two adjacent strip lines (2).

5. The high-speed differential signal transmission composite chip according to claim 4, characterized in that: Each differential microstrip line (3) includes a main carrier (3-1), a conductor strip (3-2), two grounding strips (3-3), multiple capacitors (3-4), multiple inductors (3-5), and multiple conductive blocks (3-6). The main carrier (3-1) is a strip-shaped sheet. The conductor strip (3-2) and the two grounding strips (3-3) are arranged side by side on the main carrier (3-1) along the length direction of the main carrier (3-1). The conductor strip (3-2) is arranged between the two grounding strips (3-3). The multiple capacitors (3-4), multiple inductors (3-5), and multiple conductive blocks (3-6) are all arranged on the conductor strip (3-2). The multiple capacitors (3-4) and multiple inductors (3-5) are alternately arranged on the conductor strip (3-2) along one side of the conductor strip (3-2), and the multiple conductive blocks (3-6) are evenly arranged on the conductor strip (3-2) along the other side of the conductor strip (3-2).

6. The high-speed differential signal transmission composite chip according to claim 4 or 5, characterized in that: The high-bandwidth memory chip (11) has two perforated cylinders (1) inserted along its height direction. The two perforated cylinders (1) are the first cylinder (1-1) and the second cylinder (1-2), respectively. The first cylinder (1-1) and the second cylinder (1-2) are arranged vertically and alternately inside the high-bandwidth memory chip (11). The first cylinder (1-1) is vertically inserted between multiple component pieces (11-1) of the high-bandwidth memory chip (11), and the second cylinder (1-2) is vertically inserted on the substrate (11-2) of the high-bandwidth memory chip (11). A strip line (2) is inserted in the first cylinder (1-1) and the second cylinder (1-2), respectively. A differential microstrip line (3) is horizontally arranged between the two strip lines (2) corresponding to the first cylinder (1-1) and the second cylinder (1-2).

7. The high-speed differential signal transmission composite chip according to claim 6, characterized in that: The PCB composite board (10) includes six constituent layers (10-1), which are horizontally stacked from top to bottom. Four perforated cylinders (1) are inserted into the PCB composite board (10) along its height direction. The four perforated cylinders (1) are the third cylinder (1-3), the fourth cylinder (1-4), the fifth cylinder (1-5), and the sixth cylinder (1-6). The third cylinder (1-3), the fourth cylinder (1-4), the fifth cylinder (1-5), and the sixth cylinder (1-6) are vertically staggered within the PCB composite board (10). The third cylinder (1-3) and the fourth cylinder (1-4) are vertically arranged side-by-side between the upper three constituent layers (10-1) of the six constituent layers (10-1). The third cylinder (1-3) and... A strip line (2) is threaded through the fourth cylinder (1-4). The fifth cylinder (1-5) and the sixth cylinder (1-6) are vertically arranged side by side between the lower three constituent layers (10-1) of the six constituent layers (10-1). A strip line (2) is threaded through the fifth cylinder (1-5) and the sixth cylinder (1-6). A differential microstrip line (3) is horizontally arranged between the two strip lines (2) corresponding to the third cylinder (1-3) and the fifth cylinder (1-5). A differential microstrip line (3) is horizontally arranged between the two strip lines (2) corresponding to the fourth cylinder (1-4) and the sixth cylinder (1-6). A differential microstrip line (3) is horizontally arranged between the lower ends of the two strip lines (2) corresponding to the fifth cylinder (1-5) and the sixth cylinder (1-6).

8. The high-speed differential signal transmission composite chip according to claim 7, characterized in that: A differential microstrip line (3) is provided inside the GPU chip (12) along its length direction. The length direction of the differential microstrip line (3) is in the same direction as the length direction of the GPU chip (12). The differential microstrip line (3) is located near the bottom of the GPU chip (12). One end of the differential microstrip line (3) is connected to the upper end of the strip line (2) inside the fourth cylinder (1-4) that is close to it.

9. The high-speed differential signal transmission composite chip according to claim 8, characterized in that: The upper end of the strip line (2) inside the third cylinder (1-3) is connected to the lower end of the strip line (2) inside the second cylinder (1-2) through a differential microstrip line (3).

10. A method for configuring an on-chip differential signal transmission link, used to form a high-speed differential signal transmission composite chip as described in claims 4, 5, 6, 7, 8, or 9, characterized in that: The method for configuring the differential signal transmission link within the chip is to match the arrangement height and position of the differential signal transmission system based on the height and length values ​​of the PCB composite board (10), the high-bandwidth memory chip (11), and the GPU chip (12). The differential signal transmission system is divided into three components, with one component set in each of the PCB composite board (10), the high-bandwidth memory chip (11), and the GPU chip (12); The process of configuring the components in the PCB composite board (10) is as follows: 2N perforated cylinders (1) are vertically arranged in parallel according to the height of the PCB composite board (10). Each perforated cylinder (1) has a strip line (2) inserted in it. The total height of the N perforated cylinders (1) is set in accordance with the height of the PCB composite board (10). A differential microstrip line (3) is arranged horizontally between two adjacent perforated cylinders (1). The length of the differential microstrip line (3) corresponds to the horizontal distance between the two perforated cylinders (1). The differential microstrip line (3) between the two vertically arranged perforated cylinders (1) at the bottom of the PCB composite board (10) is the maximum length differential microstrip line. This ensures that the length of the maximum length differential microstrip line and the length of the PCB composite board (10) meet the arrangement requirements of the predetermined quantity relationship. The strip line (2) in the two vertically arranged perforated cylinders (1) at the bottom of the PCB composite board (10) is connected to the components in the high-bandwidth memory chip (11) and the GPU chip (12) respectively. The process of configuring the components inside the high bandwidth memory chip (11) is as follows: a perforated cylinder (1) is configured according to the height value of the high bandwidth memory chip (11). The height of the perforated cylinder (1) is set to match the height of the high bandwidth memory chip (11). The perforated cylinder (1) is vertically inserted into the high bandwidth memory chip (11). A strip line (2) is inserted into the perforated cylinder (1). A differential microstrip line (3) is horizontally arranged between the perforated cylinder (1) and a perforated cylinder (1) on the top of the PCB composite board (10) that is close to it. The length of the differential microstrip line (3) and the length of the high bandwidth memory chip (11) meet the arrangement requirements of the predetermined quantity relationship. A differential microstrip line (3) is provided inside the GPU chip (12). The differential microstrip line (3) is connected to a strip line (2) inside a perforated cylinder (1) on the top of the PCB composite board (10) that is close to it. The length of the differential microstrip line (3) is less than or equal to the length of the GPU chip (12).

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