Sparse LU decomposition acceleration method for FPGA (Field Programmable Gate Array) with flow-sensing high-bandwidth memory

Abstract

The invention discloses a sparse LU decomposition acceleration method for an FPGA (field programmable gate array) with a flow-sensing high-bandwidth memory, belongs to the technical field of LU decomposition hardware acceleration, and aims to solve the problem of performance bottleneck and efficiency challenge faced by sparse LU decomposition on the FPGA. The acceleration method comprises the following steps of data stream preprocessing, wherein matrix data and metadata are stored and packaged based on a sparse storage format; customizing an FPGA hardware accelerator: carrying out HBM channel allocation and collaborative design of a control unit and memory management; parallel data flow management and scheduling are carried out, and sparse LU decomposition is executed; timely data supply is ensured through a multi-stage pipeline prefetching mechanism; and transmitting the task flow and the data flow to a special parallel processing engine for MAC / DIV calculation in combination with a flow sensing synchronous scheduling strategy.

Description

Technical Field

[0001] This invention belongs to the field of hardware acceleration technology for LU decomposition, specifically relating to a method for accelerating sparse LU decomposition in a flow-aware high-bandwidth memory FPGA. Background Technology

[0002] Solving large sparse linear equation systems Ax = b is a fundamental computational task in scientific and engineering applications, involving circuit simulation, finite element analysis, and power system modeling. In practice, direct solution methods based on sparse LU decomposition are favored over iterative methods due to their reliable accuracy and the elimination of the need to select and adjust preconditioners. As problem size increases, the sparse LU decomposition stage becomes a bottleneck for computation time, making its acceleration a key issue in high-performance computing. Therefore, developing dedicated sparse LU decomposition accelerators is of great significance. Field-programmable gate arrays (FPGAs) offer a highly attractive platform for hardware acceleration through customized parallel architectures and dataflow designs. Compared to central processing units (CPUs) and graphics processing units (GPUs), FPGAs not only achieve lower latency and power consumption but also provide higher resource utilization for sparse matrix workloads. Furthermore, sparse matrix computation is inherently memory-intensive. High-bandwidth memory (HBM) offers higher bandwidth and more independent memory channels compared to traditional double data rate memory (DDR), enabling FPGAs equipped with HBM to effectively address the memory access challenges in the sparse LU decomposition process.

[0003] Sparse LU decomposition, due to its inherent high sparsity and random distribution of non-zero elements, leads to irregular data dependencies and memory access patterns, making efficient acceleration solutions on FPGAs still largely unexplored. Although the high concurrency capabilities of HBM have brought new possibilities for accelerating sparse LU decomposition in recent years, the inherent random dependencies and complex computational patterns of this algorithm make it difficult to achieve efficient bandwidth utilization on the HBM platform.

[0004] The key technical challenges in accelerating sparse LU decomposition on HBM FPGAs mainly include the following four aspects: (1) The mismatch between the existing sparse storage format and the HBM access mode leads to low bandwidth utilization of HBM. The pointer array of CSR (row compression format) / CSC (column compression format) makes it difficult to achieve full-stream access to non-zero elements. The accelerator must access the pointer array before reading non-zero elements. In addition, the highly random distribution of non-zero elements in the sparse matrix hinders effective data merging, thereby reducing bandwidth utilization.

[0005] (2) On-chip memory resource limitations and insufficient data reuse. When dealing with large-scale sparse matrices, a simple on-chip data allocation strategy may lead to the premature removal of memory-dependent data, even if the data still has reuse value later, thereby reducing on-chip memory access efficiency and effective memory utilization.

[0006] (3) High access latency of HBM affects the efficiency of off-chip memory communication. Although HBM provides huge bandwidth, its inherent high access latency limits the performance of sparse LU decomposition. Traditional prefetching strategies may lead to the fetching of data that is not required for computation when faced with irregular off-chip sparse memory access patterns, resulting in inefficient prefetching and unnecessary HBM access, which seriously affects the efficiency of off-chip memory communication.

[0007] (4) Complex data dependencies make parallel scheduling difficult. In sparse LU decomposition, the dependencies between columns are complex and irregular, which makes parallel scheduling on FPGA extremely difficult. Summary of the Invention

[0008] To overcome the shortcomings of existing technologies, the present invention aims to provide a method for accelerating sparse LU decomposition in flow-aware high-bandwidth memory FPGAs, so as to solve the performance bottlenecks and efficiency challenges faced by accelerating sparse LU decomposition on FPGAs.

[0009] The technical problem to be solved by this invention can be achieved through the following specific technical solutions: The aforementioned method for accelerating sparse LU decomposition in a flow-aware high-bandwidth memory FPGA includes the following steps: Data stream preprocessing: Storing and packaging matrix data and metadata based on a sparse storage format; Customized FPGA hardware architecture: Co-design of HBM channel allocation, control unit and memory management; Parallel data stream management and scheduling, performing sparse LU decomposition: ensuring timely data supply through a multi-stage pipeline prefetching mechanism; and transmitting task streams and data streams to a dedicated parallel processing engine for MAC / DIV computation using a stream-aware synchronous scheduling strategy.

[0010] Furthermore, the matrix data uses COO (coordinate format) to explicitly store non-zero elements and their row and column indices. Through vectorized packing, multiple elements are merged into HBM data words. The input data is reordered according to the row index modulus, and each element is assigned to a target slot. If the slot is already occupied, the data word is filled with a dummy element, and a new data word packing cycle is started.

[0011] Furthermore, the metadata includes dependency metadata, which uses the non-zero structure of matrix U obtained by static symbolic decomposition of matrix A to construct a dependency graph. This dependency graph is represented as a directed acyclic graph (DAG). Nodes without dependencies are grouped into the same level based on their dependency depth. The dependencies are organized into the following four linearized arrays: Hierarchy pointer: Stores the starting offset of each hierarchy; Hierarchical column index: Stores the column indexes for each level; Dependency pointer: Stores the offset of each column in the dependency list. The difference between two adjacent entries indicates the number of dependencies of the specified column. Dependency index: Stores the index of the dependent columns of the specified column.

[0012] Furthermore, the metadata also includes matrix metadata, which adopts a data word layout format containing two arrays: data word offset and data word count, which store the starting offset and the data words occupied by each column, respectively.

[0013] Furthermore, FPGA hardware accelerator customization includes channel allocation, control unit, and hierarchical memory modules, among which, Regarding channel allocation: The HBM channel allocation strategy is adopted, and a total of 26 HBM channels are allocated for data transmission; For the control unit: a scheduler is designed, which includes a data prefetcher and a controller to coordinate the data and task flow of the accelerator; the data prefetcher prefetches the requested raw data through the matrix A loader to avoid unnecessary HBM access; at the same time, the controller obtains and organizes metadata from the metadata loader to form processing unit (PE) task packages. For the hierarchical memory module: it includes local memory and shared memory. The local memory is used to provide local access, and the shared memory is used to provide shared storage space. Both local memory and shared memory are managed using a first-in-first-out replacement strategy.

[0014] Furthermore, the multi-stage pipeline manages and processes multiple HBM data prefetch requests simultaneously, carefully dividing HBM access operations into multiple stages to achieve a high degree of temporal overlap.

[0015] Furthermore, the scheduler employs a column index modulo strategy to distribute the column tasks and their corresponding data streams from the initial level (e.g., level 0) to different processing unit groups (PEGs) for parallel processing. Within each PEG, PEs collaboratively resolve dependencies and perform multiply-accumulate (MAC) or divide-by-volume (DIV) operations on the current column. This stream-aware synchronous scheduling strategy strictly adheres to the hierarchical processing order: after all column tasks in the current level have been processed, the scheduler initiates the streaming computation for the next level.

[0016] Furthermore, the MAC operation includes: each processing unit (PE) receives a multiply-accumulate input data packet and performs a multiply-accumulate operation with sparse LU decomposition; the PE performs parallel multiply-accumulate operations using 8 floating-point values ​​and their packing elements through vectorization processing; floating-point multiplication and addition operations utilize the digital signal processing resources inside the FPGA and adopt a deep pipeline design to maximize resource utilization, and achieve an ideal startup interval of 1 through internal loop unrolling optimization.

[0017] Furthermore, the DIV operation includes: after the MAC phase is completed, the PE within PEG will collaboratively process and normalize the diagonal elements of the current column; this operation uses a pipelined floating-point divider to effectively optimize its inherent high latency characteristics, and this process also handles diagonal elements close to zero to ensure numerical stability; after all multiply-accumulate operations are completed, the diagonal elements A of the current column j are normalized. jj Change to U jj Then, the processing unit in the division unit will process all elements A below the diagonal in column j. rj Parallel division by U jj To produce the final L factor L rj , where r > j.

[0018] Compared with the prior art, the present invention has the following advantages: (1) The sparse LU decomposition accelerator (SCLAER) proposed in this invention on HBM FPGA adopts a sparse storage format and merges data through vectorized packing, and customizes a data flow compatible with HBM to improve bandwidth utilization. (2) This invention proposes a two-layer hierarchical memory module to improve data access efficiency and on-chip memory reuse rate by optimizing memory management and reducing redundant transmission; (3) In order to manage the complex dependencies of sparse LU decomposition and maximize parallelism, this invention designs a flow-aware synchronous scheduling strategy to convert irregular dependencies into hierarchical streaming access; combined with a multi-level pipeline data prefetching mechanism, the delay is hidden by overlapping HBM access stages, which improves the efficiency of off-chip communication. Attached Figure Description

[0019] Figure 1 This is an example of the original matrix of the present invention; Figure 2 This is a flowchart of the matrix data storage and packaging process of the present invention (based on an original matrix example); Figure 3 This is a flowchart of the metadata storage and packaging process of the present invention (based on the original matrix example); Figure 4 This is a hardware architecture diagram of the FPGA hardware accelerator of the present invention; Figure 5 This describes the parallel LU decomposition process in the PEG of this invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0021] This invention provides a method for accelerating sparse LU decomposition in flow-aware high-bandwidth memory FPGAs, comprising the following: (a) Data stream preprocessing: Matrix data and metadata are stored and packaged based on sparse storage format.

[0022] Sparse LU decomposition exhibits irregular non-zero distributions and complex column dependencies. Without dedicated storage and packing designs, this leads to low bandwidth utilization and severely limits parallelism. To address this issue, this invention proposes a sparse data format and vectorized packing scheme compatible with HBM, specifically tailoring a sparse storage format for the original matrix and metadata.

[0023] (1) Matrix data storage and packaging For matrix data stream preprocessing, this invention explicitly stores non-zero elements and their row and column indices using a coordinate format. This method can effectively retrieve scattered non-zero elements and is suitable for irregular access patterns in sparse matrices. Figure 1 and Figure 2 As shown, each non-zero element is encoded as 64 bits: a 16-bit column index, a 16-bit row index, and a 32-bit single-precision floating-point value. Multiple 64-bit elements are combined into a 512-bit HBM data word through vectorized packing. To prevent on-chip block random access memory (BRAM) conflicts, the input data is reordered according to the row index modulus, assigning each element to a target slot. If the slot is already occupied, the data word is filled with a dummy element, and a new data word packing cycle is initiated. Despite a slight storage overhead, this strategy ensures conflict-free BRAM access and fixed-time PE processing, which is acceptable considering the performance advantages.

[0024] (2) Metadata storage and packaging Metadata consists of two parts: dependency metadata (hierarchical information and fine-grained dependency lists) and matrix metadata (data word offsets and counts of matrix A and L / U data).

[0025] Dependency on metadata is crucial for guiding computation sequence and maintaining pipeline efficiency in FPGAs. For example... Figure 3 As shown in (a), the non-zero structure of matrix U obtained after static symbolic decomposition of matrix A is used to construct the dependency graph. This dependency graph is represented as a directed acyclic graph (DAG). , where the node set Edge set corresponding to all columns This represents the dependency relationship from column j to column k. For nodes with no dependency relationship, they are grouped into the same level based on their dependency depth. The level of node k is calculated as follows: , in, This represents the row index of all non-diagonal non-zero elements in column k of U (i.e., Considering the irregular storage pattern of the dependency graph used, traversing the dependency graph layer by layer is inefficient in terms of memory utilization and will further lead to non-contiguous data access. Therefore, this invention organizes these dependencies into the following four linearized arrays, such as... Figure 3 As shown in (b), it includes a hierarchy pointer, a hierarchy column index, a dependency pointer, and a dependency index. The hierarchy pointer stores the starting offset of each hierarchy; the hierarchy column index stores the column index in each hierarchy; the dependency pointer stores the offset of each column in the dependency list, and the difference between two adjacent entries represents the number of dependencies of the specified column; the dependency index stores the dependency column index of the specified column.

[0026] To transform the logical structure of a sparse matrix into physically contiguous and efficiently accessible data blocks in HBM, this invention introduces matrix metadata. A data word layout format is adopted, which has two arrays, such as... Figure 3 As shown in (c), the data word offset and data word count store the starting offset and occupied data word for each column, respectively. After this, all metadata entries (32-bit unsigned integers) are packaged into 512-bit HBM data words to optimize HBM transmission efficiency.

[0027] (ii) Custom FPGA hardware accelerator: Co-design of HBM channel allocation, control unit and memory management.

[0028] This invention implements a customized hardware architecture on the FPGA side, designed to efficiently perform sparse LU decomposition and fully utilize the bandwidth of HBM and the parallel processing capabilities of the FPGA. The specific architecture design is as follows: (1) Channel allocation To address potential bandwidth contention issues during HBM access for different data types (matrix A, metadata, and L / U factors), this invention employs a refined HBM channel allocation strategy, allocating a total of 26 HBM channels for data transmission. Since both core computational data types (matrix A and L / U factors) occupy significant space, they are each mapped to 12 HBM channels. To isolate bandwidth contention between metadata access and core computational data, two independent HBM channels are allocated to all metadata (one for scheduling control and matrix A layout information, and the other specifically for L / U factor layout information). The matrix A loader, metadata loader, and L / U writer all support highly concurrent streaming access, ensuring efficient data transfer between HBM and internal FPGA modules.

[0029] (2) Control unit The high access latency and complex data dependencies of HBM pose challenges in sparse LU decomposition. To address these issues, this invention designs a scheduler that includes a data prefetcher (such as...). Figure 4 (as shown in (e)) and controller (as shown in (e)) Figure 4 (as shown in f)) is used to coordinate the data and task flow of the accelerator. The data prefetcher uses the matrix A loader (as shown in f) Figure 4 As shown in (a), the controller efficiently prefetches the requested raw data to avoid unnecessary HBM access. Figure 4 (f) shown in the middle) from the metadata loader (such as Figure 4 As shown in (b) and (c), metadata is acquired and organized to form PE task packages. Finally, the scheduler distributes these tasks and their corresponding column data in parallel to dedicated parallel processing engines (such as...). Figure 4 The 12 processing unit groups (PEGs) in (g) enable efficient sparse LU decomposition by having the MAC and DIV units within each PEG work together to perform numerical column calculations.

[0030] (3) Layered memory modules The L / U factor exhibits random and frequent access patterns in sparse LU decomposition. Relying solely on limited local memory is insufficient to effectively capture all relevant dependency factors, leading to frequent memory misses. Furthermore, achieving efficient cross-PEG direct communication and data forwarding presents significant challenges when the required L / U factor resides in the local memory of different Processing Unit Groups (PEGs). Using an all-to-all cross-connect communication structure for direct data exchange between PEGs is impractical, as this would result in a quadratic increase in circuit complexity, significantly increasing hardware implementation difficulty and reducing operating frequency. However, the high access latency caused by direct access to HBM severely slows down the computational pipeline, impacting overall performance.

[0031] To address the aforementioned issues and effectively improve on-chip data reuse, this invention proposes a two-layer hierarchical memory module. The hierarchical memory module comprises extremely fast local memory and a larger-capacity shared memory. The local memory provides extremely fast local access, while the shared memory provides a large-capacity shared storage space to capture a wider range of dependency factors, thereby improving on-chip data reuse and reducing memory access latency. Both memory units are managed using a first-in, first-out (FIFO) replacement strategy.

[0032] ① Local memory The L / U factor is stored in a sparse column memory entry array constructed from Ultra-Range Random Access Memory (URAM). A column index mapping table (recording the column ID corresponding to each memory slot) and a validity flag array (indicating whether the data in the slot is valid) are stored in corresponding arrays using BRAM. Through a fully partitioned design, each memory slot is mapped to a different physical storage unit (an independent storage bank for BRAM / URAM). Local memory provides extremely fast local access, storing L / U factor columns recently calculated by the PEG or obtained from shared memory / HBM, maximizing computational locality. By leveraging the dual-port feature of BRAM, local memory supports parallel PE access, effectively preventing irregular dependency access conflicts.

[0033] ② Shared memory To avoid retrieving distant dependent data across PEGs, improve overall memory hit rate, and reduce HBM access, shared memory is introduced as a large-capacity cache shared by all PEGs. URAM resources are used to store L / U factors, and BRAM resources are used to store the global column index mapping table and validity flag array; its internal storage units also employ a fully partitioned design to support high-concurrency access and maximize temporal and spatial locality. After computation and storage in local memory, L / U factors are synchronously copied to shared memory and processed via L / U writers (such as...). Figure 4(As shown in (d)) asynchronous write-back to HBM. This HBM write-back operation overlaps with the PEG computation pipeline, hiding the latency.

[0034] (iii) Parallel data stream management and scheduling, and execution of sparse LU decomposition: Ensure timely data supply through a multi-stage pipeline prefetching mechanism; Combine with a stream-aware synchronous scheduling strategy to transmit task streams and data streams to a dedicated parallel processing engine for MAC / DIV calculation.

[0035] This invention proposes an efficient dataflow computation and scheduling strategy aimed at accelerating sparse LU decomposition on HBM FPGAs. Within the PEG, the PE efficiently performs numerical computation for left-look sparse LU decomposition: First, through a series of vectorized MAC operations, the cumulative contribution of the L / U factor products of all left-side decomposed columns is subtracted from the original value of the current column, thereby updating the dense representation of the current column; subsequently, the diagonal elements are normalized through a pipelined DIV, generating the final L / U factors for the elements below the diagonal in the column.

[0036] (1) Prefetching of multi-stage pipeline While HBM offers enormous bandwidth, its inherently high access latency poses a significant bottleneck to the performance of sparse LU decomposition. Traditional prefetch strategies often result in mismatched prefetched data with actual computational needs when faced with irregular off-chip sparse memory access patterns, thus reducing efficiency. To effectively alleviate this problem, this invention proposes a multi-stage pipelined prefetch mechanism. Specifically, the data prefetcher is configured with an asynchronous interface, enabling parallel access to all 12 HBM channels to obtain the original matrix A. Guided by the controller's metadata, it strictly follows the column order of its respective processing level to obtain data, effectively avoiding unnecessary HBM accesses. The multi-stage pipeline manages and processes multiple HBM read requests simultaneously, carefully dividing HBM access operations into multiple stages (e.g., address sending, internal processing, data return) to achieve a high degree of temporal overlap. For example, while the data for the first HBM request is still being processed internally by HBM, the data prefetcher can already send the address for the second request to HBM; when the data for the second request begins to return, the address for the third request may have already been sent. Furthermore, the data prefetcher precisely tracks HBM requests and responses to ensure data integrity. This mechanism ensures that multiple parallel processing columns at the same level can access the required data in a timely manner without causing blockage, enhancing off-chip memory communication and parallelism.

[0037] (2) Flow-aware synchronous scheduling Given the inherent random dependencies in sparse LU decomposition, achieving efficient parallel scheduling is extremely challenging. To maximize concurrent execution efficiency, this invention proposes a stream-aware synchronous scheduling strategy that ensures data stream scheduling strictly follows a predefined hierarchical order. Specifically, the scheduler employs a column index modulo strategy, distributing column tasks and their corresponding data streams from the initial level (e.g., level 0) to different PEGs for parallel processing. Within each PEG, PEs collaboratively resolve dependencies and perform MAC or DIV operations on the current column. This stream-aware synchronous scheduling strategy strictly adheres to the hierarchical processing order: ensuring that streaming computation at the next level can only begin after all column tasks at the current level have been processed. This mechanism guarantees that when a PEG processes a column at its current level, all relevant dependent column data from the previous level has been computed and can be efficiently retrieved through hierarchical memory modules, thus effectively resolving the data dependency problem.

[0038] ① MAC Operation: Each PE receives multiply-accumulate input data packets and performs multiply-accumulate operations based on sparse LU decomposition. The PE performs parallel multiply-accumulate operations using 8 floating-point values ​​and their packet elements through vectorization processing. Floating-point multiplication and addition operations utilize the FPGA's internal digital signal processing (DSP) resources and employ a deep pipeline design to maximize resource utilization. Through internal loop unrolling optimization, an ideal startup interval (II) of 1 is achieved. The core numerical computation process is as follows: Figure 5 As shown, the parallel computation of PE within PEG is as follows: ji ×U ij and L rk ×U kj The product of, and from the corresponding element A of the current column j. jj and A rj Subtract them from the middle to update its dense representation.

[0039] ② DIV Operation: After the MAC phase is complete, the PE within PEG will collaboratively process and normalize the diagonal elements of the current column. This operation uses a pipelined floating-point divider (typically configured with 1 to 2 instances) to effectively optimize its inherent high latency. This process also handles diagonal elements close to zero to ensure numerical stability. After all multiply-accumulate operations are completed, the diagonal elements A of the current column j are normalized. jj Change to U jj Then, the processing unit in the division unit will process all elements A below the diagonal in column j. rj (where r > j) Parallel division by U jj To produce the final L factor L rj .

[0040] (iv) Experiment The sparse LU decomposition accelerator SCALER proposed in this invention is specifically implemented on a Xilinx Alveo U280 FPGA board. Its development utilizes the Xilinx HLS C++ language and is implemented in hardware using the Vitis 2022.1 toolchain. The HLS C++ code is built upon the streaming processing framework TAPA.

[0041] To evaluate the performance of the proposed sparse LU decomposition accelerator, this invention selected seven sparse matrices from the SuiteSparse dataset for evaluation. These matrices cover multiple application areas, including circuit simulation, computational fluid dynamics, and two-dimensional / three-dimensional problems, ensuring the broad applicability of the evaluation results. Table 1 details the key information of these evaluation matrices, including but not limited to their dimensionality, number of non-zero elements, and matrix density.

[0042] Table 1 Information from the evaluation matrix

[0043] To quantitatively evaluate the performance of the SCALER accelerator of this invention, an industry-standard GPU platform is used as a benchmark for comparison. Specifically, benchmark tests are performed on NVIDIA RTX 4090 and NVIDIA Tesla V100 GPUs, utilizing the CUDSS_PHASE_FACTORIZATION and CUDA 12.4 environments of the NVIDIA cuDSS library's secondary application programming interface (API) for sparse LU decomposition computation. cuDSS is widely recognized as a state-of-the-art solution for sparse LU decomposition on current GPUs. On the GPU platform, the execution time of the LU decomposition phase is measured using cudaEventElapsedTime, and power consumption is obtained using the nvidia-smi tool.

[0044] Regarding the SCALER accelerator, kernel execution time was measured using Xilinx Runtime (XRT), and power consumption was obtained using the xbutil tool. To comprehensively evaluate SCALER's performance, this invention employs the following three key metrics: throughput (measured in GFLOP / s, i.e., gigafloat operations per second), bandwidth efficiency (measured in MFLOP / s / (GB / s), i.e., throughput per unit of memory bandwidth), and energy efficiency (measured in MFLOP / s / W, i.e., throughput per watt).

[0045] Table 2 presents a detailed comparison of SCALER with cuDSS running on NVIDIA V100 and RTX 4090 GPUs in terms of throughput, bandwidth efficiency, and energy efficiency. "Performance improvement" is defined as the performance gain of SCALER relative to the best-performing GPU compared to the comparison. Furthermore, Table 3 details the resource utilization of SCALER on the Xilinx Alveo U280 FPGA board.

[0046] Table 2 Comparison of SCLAER and cuDUSS performance on NVIDIA V100 and RTX 4090 GPUs

[0047] Table 3 Resource Utilization of SCALER on Xilinx U280 FPGA Board

[0048] As shown in Table 2, 1) in terms of throughput, the geometric mean throughput gain of the SCALER accelerator proposed in this invention is 2.93 times higher than that of the V100 GPU and 1.68 times higher than that of the RTX 4090 GPU. On matrix "poli4", SCALER's throughput further achieves a peak speedup of up to 2.00 times on these GPUs. Although the frequencies of the RTX 4090 and V100 GPUs are much higher than SCALER (close to or more than 3 times), the SCALER accelerator manages dependencies through flow-aware synchronous scheduling and utilizes on-chip parallelism, compensating for the lower frequency with high-concurrency data processing capabilities, thus achieving a significant improvement in overall throughput, surpassing these two GPUs; 2) SCALER's geometric mean energy efficiency is 6.58 times higher than that of the V100 GPU and 3.48 times higher than that of the RTX 4090 GPU. It can be seen that SCALER achieves higher throughput while maintaining low power consumption. This is primarily due to SCALER's efficient data prefetching and optimized on-chip memory allocation strategies, which significantly reduce high-latency HBM accesses, thereby lowering data movement energy consumption. Bandwidth utilization is crucial for sparse LU decomposition (memory-intensive tasks); 3) SCALER's customized data stream compatible with high-bandwidth memory and dedicated vectorized data packaging make its bandwidth efficiency 6.29 times and 4.57 times higher than NVIDIA V100 GPU and RTX 4090 GPU, respectively.

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for accelerating sparse LU decomposition in a flow-aware high-bandwidth memory FPGA, characterized in that, Includes the following steps: Data stream preprocessing: Storing and packaging matrix data and metadata based on a sparse storage format; Customized FPGA hardware architecture: Co-design of HBM channel allocation, control unit and memory management; Parallel data stream management and scheduling, execution of sparse LU decomposition: ensuring timely data supply through a multi-stage pipeline prefetching mechanism; By combining a stream-aware synchronous scheduling strategy, task streams and data streams are transmitted to a dedicated parallel processing engine for MAC / DIV computation.

2. The method for accelerating sparse LU decomposition in a flow-aware high-bandwidth memory FPGA according to claim 1, characterized in that, The matrix data uses a coordinate format to explicitly store non-zero elements and their row and column indices. Multiple elements are merged into HBM data words through vectorized packing. The input data is reordered according to the row index modulus, and each element is assigned to a target slot. If the slot is already occupied, the data word is filled with a dummy element and a new data word packing cycle is started.

3. The method for accelerating sparse LU decomposition in a flow-aware high-bandwidth memory FPGA according to claim 1, characterized in that, Metadata includes dependency metadata, which uses the non-zero structure of matrix U obtained by static symbolic decomposition of matrix A to construct a dependency graph. This dependency graph is represented as a directed acyclic graph (DAG). Nodes without dependencies are grouped into the same level based on their dependency depth. The dependencies are organized into the following four linearized arrays: Hierarchy pointer: Stores the starting offset of each hierarchy; Hierarchical column index: Stores the column indexes for each level; Dependency pointer: Stores the offset of each column in the dependency list. The difference between two adjacent entries indicates the number of dependencies of the specified column. Dependency index: Stores the index of the dependent columns of the specified column.

4. The method for accelerating sparse LU decomposition in a flow-aware high-bandwidth memory FPGA according to claim 1, characterized in that, The metadata also includes matrix metadata, which uses a data word layout format containing two arrays: data word offset and data word count, which store the starting offset and the number of data words occupied for each column, respectively.

5. The method for accelerating sparse LU decomposition in a flow-aware high-bandwidth memory FPGA according to claim 1, characterized in that, Customized FPGA hardware accelerators include channel allocation, control units, and hierarchical memory modules, among which... Regarding channel allocation: The HBM channel allocation strategy is adopted, and a total of 26 HBM channels are allocated for data transmission; For the control unit: a scheduler was designed, which includes a data prefetcher and a controller to coordinate the data and task flow of the accelerator; the data prefetcher prefetches the requested raw data through the matrix A loader to avoid unnecessary HBM access; at the same time, the controller obtains and organizes metadata from the metadata loader to form PE task packages; For the hierarchical memory module: it includes local memory and shared memory. The local memory is used to provide local access, and the shared memory is used to provide shared storage space. Both local memory and shared memory are managed using a first-in-first-out replacement strategy.

6. The method for accelerating sparse LU decomposition in a flow-aware high-bandwidth memory FPGA according to claim 5, characterized in that, A multi-stage pipeline manages and processes multiple HBM data prefetch requests simultaneously, carefully dividing HBM access operations into multiple stages to achieve a high degree of temporal overlap.

7. The method for accelerating sparse LU decomposition in a flow-aware high-bandwidth memory FPGA according to claim 5, characterized in that, The scheduler employs a column index modulo strategy to distribute the task list of columns at the same level and their corresponding data streams to different PEGs for parallel processing. Within each PEG, PEs work together to resolve dependencies and perform MAC or DIV operations on the current column. The stream-aware synchronous scheduling strategy strictly follows the hierarchical processing order: ensuring that streaming computation at the next level can only be started after all column tasks at the current level have been processed.

8. The method for accelerating sparse LU decomposition in a flow-aware high-bandwidth memory FPGA according to claim 7, characterized in that, The MAC operation includes: each PE receives multiply-accumulate input data packets and performs multiply-accumulate operations with sparse LU decomposition; the PE performs parallel multiply-accumulate operations using 8 floating-point values ​​and their packing elements through vectorization processing; floating-point multiplication and addition operations utilize the digital signal processing resources inside the FPGA and adopt a deep pipeline design to maximize resource utilization. Through internal loop unrolling optimization, an ideal startup interval of 1 is achieved.

9. The method for accelerating sparse LU decomposition in a flow-aware high-bandwidth memory FPGA according to claim 7, characterized in that, The DIV operation includes: after the MAC phase is complete, the PE within PEG will collaboratively process and normalize the diagonal elements of the current column; this operation uses a pipelined floating-point divider to effectively optimize its inherent high latency characteristics, and also processes diagonal elements close to zero to ensure numerical stability; after all multiply-accumulate operations are completed, the diagonal elements A of the current column j are normalized. jj Change to U jj Then, the processing unit in the division unit will process all elements A below the diagonal in column j. rj Parallel division by U jj To produce the final L factor L rj , where r > j.

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