Data processing method and device, equipment and medium

Abstract

The invention relates to the technical field of caching, in particular to a data processing method and device, equipment and a medium, and the method comprises the steps: obtaining a first virtual index and a first physical identifier of a data access request; according to the first virtual index and the first physical identifier, determining whether the request data is hit in the first-level cache; determining whether the same identifier exists in a lookup table according to the first physical identifier, wherein each register in the lookup table stores a uniquely corresponding physical identifier, a virtual index, a cache way number and a significant bit; if the request data are not hit and exist, accessing the corresponding request data from the first-level cache according to the second virtual index and the cache path number in the lookup table; if the first virtual index is not hit and does not exist, sequentially adjusting alias bits of the first virtual index; and accessing the data based on the physical identifier corresponding to each cache path number corresponding to the third virtual index obtained by adjustment in the first-level cache and the first physical identifier. The data access efficiency can be improved.

Description

Technical Field

[0001] The present invention relates to the field of cache technology, and in particular to a data processing method, device, equipment and medium. Background Art

[0002] There are three ways to organize cache: VIVT (virtual Index virtual Tag), VIPT (virtual Index physical Tag), and PIPT (physical Index physical Tag).

[0003] At present, the first-level cache (L1 Cache) mainly uses VIPT, and other levels of cache use PIPT. VIP, the CPU (Central Processing Unit) sends the virtual address to the cache, and the cache performs cache search through the index part of the virtual address. At the same time, the CPU sends the virtual address to the MMU to convert it into a physical address, and the hardware processes it in parallel. The MMU (Memory Management Unit) sends the physical address to the cache, and the cache compares the cache line through the tag part of the physical address. If the cache hits, the data in the cache is used. If it does not hit, the physical address can be used directly to access the memory or the next level of cache. PIPT, the CPU sends the virtual address to the MMU, which is converted into a physical address by the memory management unit and given to the cache. The cache uses the index and tag of the physical address to locate the cache line. If the cache hits, the data in the cache is used. If the cache does not hit, the memory or the next level of cache is directly accessed according to the physical address.

[0004] VIPT-organized caches may have aliasing problems. Different virtual addresses are mapped to the same physical address, but the indexes of these virtual addresses are different, which will cause aliasing. That is, the content of the same physical address is loaded into different cache lines. These different virtual addresses may belong to different processes or the same process. Aliasing occurs when shared internal data is used. The same data block may have different virtual addresses and be loaded into the cache multiple times, which will cause low data search efficiency when accessing data.

[0005] It can be seen that how to improve the efficiency of data access in the presence of aliases is a problem that needs to be solved by those skilled in the art. Summary of the invention

[0006] The purpose of the embodiments of the present invention is to provide a data processing method, apparatus, device and medium, which can improve the efficiency of data access.

[0007] In a first aspect, a data processing method is provided, comprising:

[0008] Acquire a data access request sent by a central processor, wherein the data access request includes: a first virtual index and a first physical identifier;

[0009] Determine whether the requested data is hit in the first level cache based on the virtual cache mode according to the first virtual index and the first physical identifier;

[0010] Determine whether there is an identical physical identifier in a lookup table according to the first physical identifier, wherein the lookup table includes a plurality of registers, each register stores a unique corresponding physical identifier, a virtual index, a cache way number and a valid bit, wherein the virtual index includes: an alias bit and an index low bit;

[0011] If the requested data is not hit and the same physical identifier exists, accessing the corresponding requested data from the first-level cache according to the second virtual index and cache way number corresponding to the first physical identifier in the lookup table;

[0012] If the requested data is not hit and there is no identical physical identifier, the alias bits of the first virtual index are adjusted in sequence to obtain the third virtual index; based on the physical identifiers corresponding to the cache ways corresponding to the third virtual index in the first-level cache and the first physical identifier, the corresponding request data is accessed.

[0013] In a preferred example, the present invention can be further configured as: accessing corresponding request data from the first-level cache according to the second virtual index and cache way number corresponding to the first physical identifier in the lookup table, including:

[0014] If the data access request is a data storage request, the data access request further includes: storing data, writing the stored data into a target cache way corresponding to the first virtual index in the first-level cache, and feeding back a storage result to the central processor;

[0015] If the data access request is a data loading request, the request data is read from the first-level cache according to the second virtual index and the corresponding cache way number, and the read request data is fed back to the central processing unit; and the read request data is written into the target cache way corresponding to the first virtual index in the first-level cache.

[0016] In a preferred example, the present invention can be further configured as follows: after accessing the corresponding request data from the first-level cache according to the second virtual index and cache way number corresponding to the first physical identifier in the lookup table, the configuration further includes:

[0017] Update the second virtual index and the corresponding cache way number in the lookup table to the cache way number corresponding to the first virtual index and the target cache way number, respectively;

[0018] Invalidate data in the first-level cache corresponding to the second virtual index.

[0019] In a preferred example, the present invention can be further configured as follows: the target data includes: storage data, read request data, and writing the target data into the target cache way corresponding to the first virtual index in the first-level cache includes:

[0020] Determine whether there are free cache ways among all cache ways corresponding to the first virtual index in the first-level cache;

[0021] If it exists, writing the target data into the free cache way corresponding to the first virtual index in the first-level cache, and the free cache way is used as the target cache way;

[0022] If not, determine the target cache way of the first virtual index according to a preset rule, write the target data into the target cache way corresponding to the first virtual index in the first-level cache; and write the original data in the target cache way back to the second-level cache.

[0023] In a preferred example, the present invention can be further configured as follows: after writing the original data in the target cache way back to the secondary cache, it also includes:

[0024] Determine whether there is a register with a physical identifier corresponding to the original data in the lookup table;

[0025] If it exists, the valid bit of the register is set to invalid.

[0026] In a preferred example, the present invention can be further configured as follows: adjusting the alias bit of the first virtual index to obtain a third virtual index; accessing corresponding request data based on the physical identifiers corresponding to each cache way corresponding to the third virtual index in the first-level cache and the first physical identifier, including:

[0027] Adjusting the alias bit of the first virtual index to obtain a third virtual index;

[0028] Determine whether the physical identifiers corresponding to all cache ways corresponding to the third virtual index are the same as the first physical identifier;

[0029] If so, accessing the corresponding requested data from the cache way corresponding to the first physical identifier;

[0030] If it does not exist, the alias bit of the first virtual index is adjusted again to obtain a new third virtual index, and the judgment whether the same physical identifier exists is repeated until there is a physical identifier that is the same as the first physical identifier, or, when the alias is adjusted to the maximum value and there is still no physical identifier that is the same as the first physical identifier, the corresponding request data read from the secondary cache based on the physical address is accessed.

[0031] In a preferred example, the present invention may be further configured as follows: after accessing the corresponding request data from the cache way corresponding to the first physical identifier, the method further includes:

[0032] If the data access request is a data storage request, the data access request further includes: storing data, writing the stored data into a target cache way corresponding to the first virtual index in the first-level cache, and feeding back a storage result to the central processor;

[0033] If the data access request is a data load request, the request data is read from the first-level cache according to the second virtual index and the corresponding cache way number, and the read request data is fed back to the central processing unit; and the read request data is written into the target cache way number corresponding to the first virtual index in the first-level cache;

[0034] and / or,

[0035] If there is a register whose valid bit is invalid in the lookup table, the first physical identifier, the first virtual index and the cache way number of the target cache way number corresponding to the first virtual index are written into the register, and the valid bit is set to valid;

[0036] If there is no register whose valid bit is invalid in the lookup table, the register corresponding to the first virtual index is updated according to the cache way number of the target cache way corresponding to the first physical identifier and the first virtual index.

[0037] In a second aspect, a data processing device is provided, comprising:

[0038] A processing module, configured to obtain a data access request sent by a central processing unit, wherein the data access request includes: a first virtual index and a first physical identifier;

[0039] A first-level cache module, configured to determine whether the requested data is hit in the first-level cache based on the virtual cache mode according to the first virtual index and the first physical identifier;

[0040] A lookup table module, used for determining whether there is an identical physical identifier in a lookup table according to the first physical identifier, wherein the lookup table includes a plurality of registers, each register storing a unique corresponding physical identifier, a virtual index, a cache way number and a valid bit, wherein the virtual index includes an alias bit and an index low bit;

[0041] If the requested data is not hit and the same physical identifier exists, the position change module is triggered;

[0042] If the requested data is not hit and there is no identical physical identifier, the read comparison module is triggered;

[0043] The position transformation module is used to access the corresponding request data from the first-level cache according to the second virtual index and cache way number corresponding to the first physical identifier in the lookup table;

[0044] The read comparison module is used to adjust the alias bits of the first virtual index in sequence to obtain a third virtual index; based on the physical identifiers corresponding to the cache ways corresponding to the third virtual index in the first-level cache and the first physical identifier, access the corresponding request data.

[0045] According to a third aspect, an electronic device is provided. The electronic device comprises a memory and a processor. A computer program is stored in the memory. When the processor runs the computer program, the method described in any one of the first aspects is executed.

[0046] In a fourth aspect, a computer-readable storage medium is provided, wherein at least one program code is stored in the computer-readable storage medium, and the program code is loaded and executed by a processor to implement any method as described in the first aspect.

[0047] In a fifth aspect, a computer program product is provided, comprising a computer program or instructions, wherein when the computer program or instructions are executed by a processor, the method described in any one of the first aspects is implemented.

[0048] In summary, the method provided by the present invention includes the following beneficial technical effects:

[0049] In the technical solution of the present invention, after receiving a data access request, by combining the first virtual index and the first physical identifier, a virtual cache method is used to quickly determine whether the requested data is hit in the first-level cache; by using a lookup table to quickly locate whether there is a register with the same physical identifier, the lookup table stores the physical identifier, virtual index, cache way number and valid bit of the physical address stored in the first-level cache, that is, the content of the physical address in the first-level cache corresponds to only one virtual address, and the correct position can be located by the information stored in the lookup table; if there is no hit in the first-level cache and the same physical identifier is found in the lookup table, the virtual index and cache way number stored in the lookup table are directly used to access the data, avoiding the inefficient process of traversing the entire cache to find data, and reducing the data access cycle; if there is no hit in the first-level cache and the same physical identifier is not found in the lookup table, the data is accessed by adjusting the alias bit and comparing the physical identifier, ensuring that the data can be correctly and quickly accessed even when complex virtual addresses are mapped to physical addresses, thereby improving access efficiency.

[0050] In addition, the present invention also provides a data processing device, equipment and medium, all of which have the above-mentioned beneficial technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0052] Figure 1 It is a schematic diagram of the correspondence between virtual address and physical address;

[0053] Figure 2 is a schematic diagram of cache processing in related technology;

[0054] Figure 3 It is a flowchart of a data processing method provided by an embodiment of the present invention;

[0055] Figure 4 is a schematic diagram of the structure of a lookup table provided by an embodiment of the present invention;

[0056] Figure 5 is a structural schematic diagram of a data processing device provided by an embodiment of the present invention;

[0057] Figure 6 is a schematic diagram of a state transition of a lookup table module 230 provided in an embodiment of the present invention;

[0058] Figure 7is a schematic diagram of a state transition of a reading comparison module 250 provided in an embodiment of the present invention;

[0059] Figure 8 is a schematic diagram of the structure of a position transformation module 240 provided in an embodiment of the present invention;

[0060] Fig. 9 is a schematic diagram of a specific example provided by an embodiment of the present invention;

[0061] Fig.10 It is a structural schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0062] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0063] The terms "including" and "having" in the specification of the present invention and the above-mentioned drawings, as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but may include steps or units that are not listed.

[0064] It should be noted that in the optional embodiments of the present invention, the object information and other related data involved, when the embodiments of the present invention are applied to specific products or technologies, need to obtain the permission or consent of the object, and the collection, use and processing of the relevant data need to comply with the relevant laws, regulations and standards of the relevant countries and regions. In other words, if the embodiments of the present invention involve data related to the object, it needs to be obtained with the authorization and consent of the object, the authorization and consent of the relevant department, and in compliance with the relevant laws, regulations and standards of the country and region. If personal information is involved in the embodiments, the acquisition of all personal information needs to obtain the consent of the individual. If sensitive information is involved, the separate consent of the information subject needs to be obtained. The embodiments also need to be implemented with the authorization and consent of the object.

[0065] In addition, the term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article, unless otherwise specified, generally means that the associated objects before and after are in an "or" relationship.

[0066] VIPT-organized caches may have aliasing problems. Different virtual addresses are mapped to the same physical address, but the indexes of these virtual addresses are different, which will cause aliasing. In layman's terms, the content of the same physical address is loaded into different cache lines. These different virtual addresses may belong to different processes or the same process. Aliasing occurs when shared internal data is present. The same data block may have different virtual addresses and be loaded into the cache multiple times. Figure 1 As shown in the figure, if the virtual address index + cache offset is equal to or less than the physical address page offset, there will be no aliasing problem. If it is greater, there will be an aliasing problem. If the aliasing problem is not handled, it will cause cache lines with the same physical address to exist in the cache, and may also cause cache inconsistency problems and cause program errors.

[0067] Currently, effective operating systems also support software solutions to cache aliasing problems, but such solutions are not portable and cannot be used for operating systems that do not support them. Figure 2 As shown. This solution solves the alias problem of the current cache through the current first-level cache (L1 Cache) and the next-level cache (L2 Cache, second-level cache). First, the L2 Cache uses the PIPT organization form, and its index is part of the physical address, so there is no alias problem. The tag queue in the cache way of the L2 Cache always adds an alias signal for each storage space. The cache way of the L1 Cache is no different from that of the ordinary cache.

[0068] The physical address of the L1 Cache loaded or stored by the CPU is not in the L1 Cache, and the alias of the corresponding position in the Tag queue of the L2 Cache is valid as 0. The CPU loads or stores data in the L1 Cache, and the L1 Cache directly loads data from the L2 Cache (and passes the alias to the L2 at the same time). The L2 Cache directly gives the data to the L1 Cache through the data channel and writes the alias to its own alias position for the data Tag queue. At this time, the L1 Cache can give the data to the CPU or store the data given by the CPU in the corresponding position. The physical address of L1 Cache loaded or stored by CPU is in L1 Cache. CPU loads data or stores data in L1 Cache. If there is no hit according to the virtual index query, L1 Cache sends a load command to L2 Cache. L2 Cache sends an invalid signal according to the previously stored alias, which means that the data at the corresponding position of L1 Cache is invalid. L1 Cache sends a storage command to L2 Cache to store the data. L2 Cache then passes the data to L1 Cache through the data channel. L1 Cache stores it in the corresponding position of the virtual index, and the alias in L2 Cache is replaced with the alias of this load request.

[0069] Therefore, for data already in L1 Cache, it is necessary to read it again from L2 Cache, and the delay in the reading process is relatively large. The data already in L1 Cache needs to be invalidated first, and then the data needs to be stored in L2 Cache again to ensure cache consistency. In addition, the data storage format of L2 Cache is changed, which increases the complexity of loading and storing data in L2 Cache.

[0070] Based on this, an embodiment of the present invention provides a data processing method to solve the problem of increased data loading and storage cycles caused by the cache alias problem; further, it can also solve the problem of cache lines with the same physical address existing in the cache caused by the cache alias problem, and solve the cache consistency problem caused by the cache alias problem.

[0071] The present invention no longer solves the alias problem by combining with L2 Cache, but solves the alias problem internally through L1 Cache.

[0072] A table lookup module is added inside the L1 Cache. The table lookup module mainly stores different aliases of the most recent physical addresses in the L1 Cache. When the CPU loads or stores query tags and data queues to the L1 Cache, a table lookup can also be performed. If there is no hit, the table lookup result is used to determine whether the data is stored in the location corresponding to other indexes (that is, whether there are two virtual indexes corresponding to one physical identifier).

[0073] Add multiple tag and data queue read and comparison modules inside the L1 Cache. When the table lookup does not find any other index position with the required physical address, read the tag and data queues of other alias positions except the index transmitted by the CPU to determine whether there is the required physical address. During this process, the required physical address cache line is loaded from the L2 Cache. If the required data is found in the L1 Cache, the data transmitted from the L2 Cache is discarded, and the alias relationship is transmitted to the lookup table module for record.

[0074] Add a position transformation module. If the cache line required for this load or store is in another alias position of the L1 Cache, the data at this position needs to be transferred to the current index position. If there is no empty position at the current position, it is necessary to first write back a cache line of data to the L2 Cache, and then write the data to the current index.

[0075] Specifically, an embodiment of the present invention provides a data processing method, such as Figure 3 As shown, the method provided in the embodiment of the present invention can be executed by an electronic device, and the electronic device is a server. The server can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides cloud computing services. The terminal device can be a smart phone, a tablet computer, a laptop computer, a desktop computer, etc., but is not limited to this. The terminal device and the electronic device can be directly or indirectly connected through wired or wireless communication, and the embodiment of the present invention is not limited here. The method includes:

[0076] S101, obtaining a data access request sent by a central processing unit,

[0077] The data access request includes: a first virtual index and a first physical identifier;

[0078] The data access request may be a data loading request or a data storage request. If it is a data storage request, the data access request also includes storage data.

[0079] In an achievable embodiment, the central processing unit sends a virtual address, and the virtual address is converted into a physical address through the MMU, at which time a first virtual index and a first physical identifier are obtained.

[0080] S102, determining whether the requested data is hit in the first-level cache based on the first virtual index and the first physical identifier and in a virtual cache mode;

[0081] In the embodiment of the present invention, after receiving a data access request, the first-level cache in the CPU uses VIPT to determine whether the requested data is hit from the Cache Way×N modules of the first-level cache.

[0082] If the data is not hit, S104 and S105 are executed. If the data is hit, the subsequent process is executed to access the hit data.

[0083] It is understandable that S102 and S103 may be executed simultaneously, or S102 may be executed first and then S103, which is not limited in the embodiment of the present invention.

[0084] S103, determining whether there is an identical physical identifier in the lookup table according to the first physical identifier;

[0085] The lookup table includes multiple registers, each register stores a unique corresponding physical identifier, a virtual index, a cache way number and a valid bit, and the virtual index includes: an alias bit and an index low bit;

[0086] The embodiment of the present invention is provided with a lookup table module, and the lookup table of the lookup table module is composed of a number of registers, each register contains a physical tag (physical identification), an alias, an index low bit (index low bit), a cache way number (cache way number), and a valid bit. The physical tag is the tag of the physical address of the cache line, the alias is the alias of the virtual address Index storing the current physical address cache line, the index low bit is the low bit of the virtual address Index storing the current physical address cache line excluding the alias, the cache way number records the number of the cache way stored by this physical tag, and the valid bit is whether the data in this register is valid, 0 represents invalid, and 1 represents valid. The structure diagram of the lookup table is shown as follows: Figure 4 .

[0087] In this step, the lookup table module enters the shared physical tag information search state, reads the data in all registers to compare whether there is a register with the same first physical identifier as the shared relationship search input, if so, and the load read and store write do not hit, then the start signal, virtual index signal and cache way code are transmitted to the position transformation module, so as to access the corresponding request data from the first-level cache according to the second virtual index and cache way number corresponding to the first physical identifier in the lookup table; if not, and the load and store do not hit, then the start read comparison signal and the current virtual index and physical tag are sent to the read comparison module to adjust the alias bit of the first virtual index in turn to obtain the third virtual index; based on the physical identifiers corresponding to the cache ways corresponding to the third virtual index in the first-level cache and the first physical identifier, the corresponding request data is accessed.

[0088] S104, if the requested data is not hit and the same physical identifier exists, access the corresponding requested data from the first-level cache according to the second virtual index and cache way number corresponding to the first physical identifier in the lookup table;

[0089] Among them, there is the same physical identifier in the lookup table, but its second virtual index is different from the first virtual index. At this time, the corresponding request data can be directly read from the Cache Way×N module in the first-level cache based on the data.

[0090] S105. If the requested data is not hit and there is no identical physical identifier, the alias bits of the first virtual index are adjusted in sequence to obtain a third virtual index; based on the physical identifiers corresponding to the cache ways corresponding to the third virtual index in the first-level cache and the first physical identifier, the corresponding requested data is accessed.

[0091] If the requested data is not hit and there is no identical physical identifier, it may be an index alias problem, and the alias bits of the first virtual index are adjusted in sequence, and whether there is a hit is determined from the first-level cache.

[0092] In an embodiment of the present invention, after receiving a data access request, by combining the first virtual index and the first physical identifier, a virtual cache method is used to quickly determine whether the requested data is hit in the first-level cache; a lookup table is used to quickly locate whether there is a register with the same physical identifier, and the lookup table stores the physical identifier, virtual index, cache way number and valid bit of the physical address stored in the first-level cache, that is, the content of the physical address in the first-level cache corresponds to only one virtual address, and the correct position can be located by the information stored in the lookup table; if there is no hit in the first-level cache and the same physical identifier is found in the lookup table, the virtual index and cache way number stored in the lookup table are directly used to access the data, avoiding the inefficient process of traversing the entire cache to find data, and reducing the data access cycle; if there is no hit in the first-level cache and the same physical identifier is not found in the lookup table, the data is accessed by adjusting the alias bit and comparing the physical identifier, ensuring that the data can be correctly and quickly accessed even when complex virtual address to physical address mapping is performed, thereby improving access efficiency.

[0093] A possible implementation of the embodiment of the present invention is to access corresponding request data from the first-level cache according to the second virtual index and the cache way number corresponding to the first physical identifier in the lookup table, including:

[0094] If the data access request is a data storage request, the data access request further includes: storing data, writing the stored data into a target cache way corresponding to the first virtual index in the first-level cache, and feeding back the storage result to the central processor;

[0095] If the data access request is a data load request, the request data is read from the first-level cache according to the second virtual index and the corresponding cache way number, and the read request data is fed back to the central processing unit; and the read request data is written to the target cache way number corresponding to the first virtual index in the first-level cache.

[0096] Among them, the data is written into the target cache way corresponding to the first virtual index in the first-level cache, that is, there are multiple cache ways corresponding to the first virtual index in the cache, some of which may store data and some may not store data, and the stored data can be written into the idle cache way (target cache way) from the multiple cache ways; if there is no idle cache way, a target cache way is replaced according to the first-in-first-out / random rules.

[0097] In an embodiment of the present invention, for data storage requests, data is directly stored in the target cache way, ensuring immediate storage and efficient management of data; for data loading requests, not only the requested data is quickly read and fed back, but the read data is also updated to the target cache way, ensuring data consistency.

[0098] Furthermore, in the embodiment of the present invention, the information stored in the lookup table is the latest information, and since the original data is invalid after the data is written to the target cache way, the original data in the first-level cache also needs to be invalidated to ensure data consistency; therefore, a possible implementation method of the embodiment of the present invention, after accessing the corresponding request data from the first-level cache according to the second virtual index and cache way number corresponding to the first physical identifier in the lookup table, also includes: updating the second virtual index and the corresponding cache way number in the lookup table to the cache way number corresponding to the first virtual index and the target cache way, respectively; that is, updating the virtual index and the cache way number so that the information in the lookup table is the latest information; invalidating the data corresponding to the second virtual index in the first-level cache, that is, the data of the second virtual index in the cache is invalid data, and the value of the corresponding data of the Cache Way×N module can be updated to invalid.

[0099] In the embodiment of the present invention, after successfully accessing and processing data, the virtual index and cache way number in the lookup table are updated in time to ensure the accuracy and timeliness of the lookup table. At the same time, the data corresponding to the old virtual index in the first-level cache is invalidated to solve the problem of cache lines with the same physical address in the cache caused by the cache alias problem.

[0100] Specifically, in a possible implementation of the embodiment of the present invention, the target data includes: storage data and read request data, and the target data is written into a target cache way corresponding to the first virtual index in the first-level cache, including:

[0101] Determine whether there is an idle cache way among all cache ways corresponding to the first virtual index in the first-level cache;

[0102] If it exists, the target data is written into the free cache way corresponding to the first virtual index in the first-level cache, and the free cache way is used as the target cache way;

[0103] If not, determine the target cache way of the first virtual index according to a preset rule, write the target data into the target cache way corresponding to the first virtual index in the first-level cache, and write the original data in the target cache way back to the second-level cache.

[0104] In the Cache Way×N module of the first-level cache, each virtual index corresponds to multiple cache ways. If there are free cache ways, any free cache way is selected as the target cache way; if not, the target cache way is determined according to the preset rules (first-in-first-out, random, etc.). Since the data is replaced at this time, the original data can be written back to the second-level cache.

[0105] Furthermore, since the original data is originally stored in the Cache Way×N module of the first-level cache, the corresponding information may exist in the lookup table. Therefore, a possible implementation of the embodiment of the present invention, after writing the original data in the target cache way back to the second-level cache, further includes: determining whether there is a register with a physical identifier corresponding to the original data in the lookup table; if so, setting the valid position of the register to invalid. Among them, the valid position is 1 for valid, and 0 for invalid.

[0106] When no other index position with the required physical address is found in the table query, the tag and data queue of other alias bits except the index transmitted by the CPU are read to determine whether the required physical address is present, so as to determine whether the required data can be found in the L1Cache; therefore, a possible implementation of the embodiment of the present invention is to adjust the alias bit of the first virtual index to obtain a third virtual index; based on the physical identifiers corresponding to the cache ways corresponding to the third virtual index in the first-level cache and the first physical identifier, the corresponding request data is accessed, including:

[0107] Adjust the alias bit of the first virtual index to obtain a third virtual index;

[0108] Determine whether the physical identifiers corresponding to all cache ways corresponding to the third virtual index are the same as the first physical identifier;

[0109] If it exists, access the corresponding requested data from the cache way corresponding to the first physical identifier;

[0110] If it does not exist, the alias bit of the first virtual index is adjusted again to obtain a new third virtual index, and the judgment whether the same physical identifier exists is repeated until there is a physical identifier that is the same as the first physical identifier, or, when the alias is adjusted to the maximum value and there is still no physical identifier that is the same as the first physical identifier, the corresponding request data read from the secondary cache based on the physical address is accessed.

[0111] Specifically, adjust the alias bit of the first virtual index to obtain the third virtual index, and compare all the read physical tag values. If there is a Cache Way that has the same physical tag value as the current Index, record the current Cache Way number; if not, continue to adjust the alias bit. If the highest alias bit of the current read address is the maximum and there is still no physical identifier that is the same as the first physical identifier, access the corresponding request data read from the secondary cache based on the physical address.

[0112] It can be understood that in an embodiment of the present invention, the process of reading data from the secondary cache based on the physical address and the process of adjusting the alias and matching can be performed simultaneously, or the process of reading data from the secondary cache based on the physical address can be performed after the match fails. The embodiment of the present invention no longer limits the execution order.

[0113] A possible implementation of the embodiment of the present invention further includes, after accessing corresponding request data from the cache way corresponding to the first physical identifier:

[0114] If the data access request is a data storage request, the data access request further includes: storing data, writing the stored data into a target cache way corresponding to the first virtual index in the first-level cache, and feeding back the storage result to the central processor;

[0115] If the data access request is a data load request, the request data is read from the first-level cache according to the second virtual index and the corresponding cache way number, and the read request data is fed back to the central processing unit; and the read request data is written into the target cache way number corresponding to the first virtual index in the first-level cache;

[0116] and / or,

[0117] If there is a register whose valid bit is invalid in the lookup table, the first physical identifier, the first virtual index, and the cache way number of the target cache way number corresponding to the first virtual index are written into the register, and the valid bit is set to valid;

[0118] If there is no register whose valid bit is invalid in the lookup table, the register corresponding to the first virtual index is updated according to the first physical identifier and the cache way number of the target cache way number corresponding to the first virtual index.

[0119] Specifically, when the data access request is a data storage request, not only is the storage data written into the target cache way corresponding to the first virtual index in the first-level cache to ensure that the data is correctly stored, but the storage result is also fed back to the central processing unit in a timely manner. For data loading requests, the request data is quickly read from the first-level cache according to the second virtual index and the corresponding cache way number, and the read data is immediately fed back to the central processing unit. In addition, the read request data is written again into the target cache way corresponding to the first virtual index in the first-level cache to ensure data consistency and availability.

[0120] The embodiment of the present invention also introduces dynamic update of the lookup table. If there is a register whose valid bit is invalid in the lookup table, that is, there is an idle register available, the system writes the first physical identifier, the first virtual index, and the cache way number of the target cache way corresponding to the first virtual index into the register, and sets the valid bit to valid. If there is no register whose valid bit is invalid in the lookup table, that is, all registers are occupied, the register corresponding to the first virtual index is updated according to the cache way number of the target cache way corresponding to the first physical identifier and the first virtual index, so as to replace the old data to ensure that the data in the lookup table is always up to date, thereby ensuring the timeliness of the lookup table.

[0121] Furthermore, historical data of data access requests are analyzed regularly, and for each physical tag, the number of times each virtual index is accessed is determined, and a commonly accessed virtual index is selected. It can be predicted that the target virtual index is a commonly accessed index. At this time, the corresponding physical tag register information in the lookup table is fixed as a commonly accessed virtual index for a period of time, and the data corresponding to the physical tag stored in the first-level cache is in the cache way corresponding to the commonly accessed virtual index. The above method can improve data access efficiency.

[0122] Among them, when selecting a commonly accessed virtual index, the commonly accessed virtual index can be selected based on the number of accesses of each virtual index and whether the access is periodic. To determine the periodicity of the access, the access time series of the virtual index can be analyzed to determine whether it is periodic, the length of the periodicity, and the stability of the periodicity, and then the periodicity is quantified based on the above dimensions to obtain a periodicity value; then the number of accesses is quantified to obtain a number value; based on the number value and periodicity value of each virtual index, a commonly accessed virtual index is selected.

[0123] Figure 5 A schematic diagram of the structure of a data processing device provided by an embodiment of the present invention includes:

[0124] The processing module 210 is used to obtain a data access request sent by the central processor, where the data access request includes: a first virtual index and a first physical identifier;

[0125] The first-level cache module 220 is used to determine whether the requested data is hit in the first-level cache based on the virtual cache mode according to the first virtual index and the first physical identifier;

[0126] A lookup table module 230, used to determine whether there is an identical physical identifier in a lookup table according to the first physical identifier, wherein the lookup table includes a plurality of registers, each register storing a unique corresponding physical identifier, a virtual index, a cache way number and a valid bit, wherein the virtual index includes an alias bit and an index low bit;

[0127] If the requested data is not hit and the same physical identifier exists, the position change module 240 is triggered;

[0128] If the requested data is not hit and there is no identical physical identifier, the read comparison module 250 is triggered;

[0129] A position transformation module 240, configured to access corresponding request data from the first-level cache according to the second virtual index and the cache way number corresponding to the first physical identifier in the lookup table;

[0130] The read comparison module 250 is used to adjust the alias bit of the first virtual index in sequence to obtain a third virtual index; based on the physical identifiers corresponding to each cache way corresponding to the third virtual index in the first-level cache and the first physical identifier, access the corresponding request data.

[0131] Among them, the state transition of the lookup table module 230 is as follows: Figure 6 As shown, the implementation process is as follows:

[0132] 11. Initialization state: power on and initialize, configure each register in the lookup table to 0. Enter state 12.

[0133] 12. Idle state. If there is an alias relationship input valid signal, enter state 13. If a write-back module writes back the physical tag value signal, enter state 14. If there is a shared relationship to search for a valid signal, enter state 15.

[0134] 13. Shared physical tag information records the status, read the data in all registers to compare whether there is the same physical tag as the incoming alias relationship signal. If so, replace the virtual index and cache way number in this register with the latest one. If not, find a register with a valid bit of 0, fill the physical tag, virtual index and cache way number into this register and configure the valid bit to 1. If there is no valid bit of 0, find the same virtual index and replace the physical tag and cache way number, and enter state 12.

[0135] 14. Shared physical tag information is in invalid state. Read the data in all registers to see if there is a register with the same physical tag value as the signal sent by the write-back module. If there is, set the valid signal of this register to 0. If not, do nothing. Enter state 12.

[0136] 15. Shared physical tag information search status, read the data in all registers to see if there is a register with the same physical tag value as the shared relationship search. If so, determine whether the load read and store write hit. If so, no processing is done. If not, the start signal, virtual index signal and cache way encoding are sent to the position transformation module; if not, determine whether the load and store hit. If not, send the start signal, virtual index signal and cache way encoding to the read comparison module to start the read comparison signal and the current virtual index and physical tag. If so, no processing is done. Enter state 12.

[0137] The state transition of the read comparison module 250 is as follows: Figure 7 As shown, the implementation process is as follows:

[0138] 21. IDLE state, reset all signals, wait for the read comparison start signal from the lookup table module, and enter state 22.

[0139] 22. The read address Cache is equal to the current index low bit. If this address is equal to the current index, the alias bit of the read address is increased by 1, and the physical tag information of all Cache Ways is read using this address. Enter state 23.

[0140] 23. Compare all the read physical tag values. If there is a cache way with the same physical tag value as the current index, record the current cache way number and enter state 24; if not, enter state 25.

[0141] 24. The position change start signal, the Index value storing the target Tag value, and the Cache Way number are transmitted to the position change module, and the state 26 is entered.

[0142] 25. If the highest alias bit of the current read address is already the largest, enter the IDLE state, otherwise the read address is equal to the current read address plus 1. If this address is equal to the current index, jump to state 25 again. If not, use this address to read the physical tag information of all cache ways. Enter state 23.

[0143] 26. Send L2 return data invalid signal to the miss processing module and enter the IDLE state.

[0144] The state transition of the position transformation module 240 is as follows: Figure 8 As shown, the implementation process is as follows:

[0145] 31. IDLE state, reset all signals, wait for the position change start signal of the comparison module or the position change start signal of the table lookup module, and enter state 32.

[0146] 32. If it is CPU storage processing, the storage data, physical Tag signal, and current Index value are passed to the refill module; if it is CPU loading processing, the data is read out according to the Index and Cache Way number of the target data location, and is given to the refill module together with the physical Tag signal and current Index value;

[0147] If it is CPU loading processing, the read data is also transmitted to the loading control module. Entering state 33.

[0148] 33. Invalidate the data in the position given by the read comparison module (write 0 to the valid bit of this position in the Tag queue). Enter state 34.

[0149] 34. Wait for the Cache Way number returned by the refill module, and pass this number together with the physical Tag value, current Index, and physical Tag shared record signal to the table lookup module. If it is CPU storage processing, transmit the storage completion signal to the storage processing module and enter the IDLE state.

[0150] In one achievable manner, the position transformation module 240 is used to:

[0151] If the data access request is a data storage request, the data access request further includes: storing data, writing the stored data into a target cache way corresponding to the first virtual index in the first-level cache, and feeding back the storage result to the central processor;

[0152] If the data access request is a data load request, the request data is read from the first-level cache according to the second virtual index and the corresponding cache way number, and the read request data is fed back to the central processing unit; and the read request data is written to the target cache way number corresponding to the first virtual index in the first-level cache.

[0153] In an implementable manner, the table lookup module 230 is further used for:

[0154] Update the second virtual index and the corresponding cache way number in the lookup table to the first virtual index and the cache way number corresponding to the target cache way number, respectively;

[0155] The first-level cache module 220 is also used to invalidate the data corresponding to the second virtual index in the first-level cache. In an achievable manner, the target data includes: stored data, read request data,

[0156] The position transformation module 240 is used to:

[0157] Determine whether there is an idle cache way among all cache ways corresponding to the first virtual index in the first-level cache;

[0158] If it exists, the target data is written into the free cache way corresponding to the first virtual index in the first-level cache, and the free cache way is used as the target cache way;

[0159] If not, determine the target cache way of the first virtual index according to a preset rule, write the target data into the target cache way corresponding to the first virtual index in the first-level cache, and write the original data in the target cache way back to the second-level cache.

[0160] In an achievable manner, the table lookup module 230 is further configured to include:

[0161] Determine whether there is a register with a physical identifier corresponding to the original data in the lookup table;

[0162] If it exists, the valid bit of the register is set to invalid.

[0163] In one achievable manner, the reading and comparing module 250 is used to:

[0164] Adjust the alias bit of the first virtual index to obtain a third virtual index;

[0165] Determine whether the physical identifiers corresponding to all cache ways corresponding to the third virtual index are the same as the first physical identifier;

[0166] If it exists, access the corresponding requested data from the cache way corresponding to the first physical identifier;

[0167] If it does not exist, the alias bit of the first virtual index is adjusted again to obtain a new third virtual index, and the judgment whether the same physical identifier exists is repeated until there is a physical identifier that is the same as the first physical identifier, or, when the alias is adjusted to the maximum value and there is still no physical identifier that is the same as the first physical identifier, the corresponding request data read from the secondary cache based on the physical address is accessed.

[0168] In an implementable manner, the position transformation module 240 is further configured to:

[0169] If the data access request is a data storage request, the data access request further includes: storing data, writing the stored data into a target cache way corresponding to the first virtual index in the first-level cache, and feeding back the storage result to the central processor;

[0170] If the data access request is a data load request, the request data is read from the first-level cache according to the second virtual index and the corresponding cache way number, and the read request data is fed back to the central processing unit; and the read request data is written into the target cache way number corresponding to the first virtual index in the first-level cache;

[0171] The lookup table module 230 is further used to: if there is a register with an invalid valid bit in the lookup table, write the first physical identifier, the first virtual index, and the cache way number of the target cache way number corresponding to the first virtual index into the register, and set the valid bit to valid;

[0172] If there is no register whose valid bit is invalid in the lookup table, the register corresponding to the first virtual index is updated according to the first physical identifier and the cache way number of the target cache way number corresponding to the first virtual index.

[0173] Based on this, the embodiment of the present invention provides a specific example, which is applied to the L1 Cache module implemented in FPGA or the L1 Cache module designed in chip. Fig. 9 .

[0174] Cache Way×N module (first level cache) is a module that stores cache line information. Like the Cache Way in L1Cache in the related solution, it receives read and write signals from other modules and outputs the required information to these modules, or stores the data in its own physical tag or data queue (tag and data queue are RAM). There are multiple such CacheWay modules, represented by N here, and N can vary according to design requirements.

[0175] The load processing module is a module that processes data in the CPU load queue. The load signal includes signals such as the virtual address Index (virtual Index), the physical Tag value, and also includes a handshake signal. The load data is the data obtained from the L1 Cache according to these signals or the data obtained from the L2 Cache through the L1 Cache. This module reads the physical Tag information from all CacheWay×N modules according to the virtual Index, and compares the read-back physical Tag information with the physical Tag information passed in by the load queue. If there is a match, it is a hit, and if the match is inconsistent, it is a miss. If it is a hit, the corresponding Cache Way module is read and the data is returned to the load queue. If it is a miss, it is determined based on the result of the table lookup module whether there is other locations that store the same information with the shared Tag information. After obtaining the required data according to the data processing flow of the present invention, it is passed to the load processing module or the data is read back in L2 through the miss processing module and passed to the load processing module.

[0176] The storage processing module is similar to the loading processing module. This module is a module that processes data in the CPU storage queue. The storage signal contains signals such as virtual index and physical tag, and the stored data is the data that needs to be stored. This module reads the physical tag information from all Cache Way modules according to the virtual index, and compares the physical tag information read back with the physical tag information passed in by the loading queue. If there is a match, it is a hit, and if the match is inconsistent, it is a miss. If it is a hit, the data given by the CPU is written to the corresponding position. If it is a miss, the data is written to the Cache Way module according to the data processing flow of the present invention, or the data is written to the Cache Way module through the miss processing module and communicates with the L2 Cache. This module also needs to communicate with the replacement module to determine which positions of the Cache Way are idle when it hits, and if there are no idle positions, they need to be replaced. And the corresponding Cache Line is written back to the L2 Cache.

[0177] The replacement module is a module that records the free positions of each Cache Way and the replacement strategy (first-in-first-out or random replacement), receives replacement query signals from the refill module and the storage processing module, and feeds back the queried information.

[0178] The refill module receives the cache line refill signal from the miss processing module and the position change module, queries the replacement information from the replacement module, and writes the cache line directly to the cache way according to the replacement information, or first sends a read signal to read the data to be replaced to the write back module, and then writes the cache line directly to the cache way.

[0179] The write-back module writes the cache line data that needs to be written back to the L2 cache in the cache way back to the L2 cache through the L2 cache read-write interface, and outputs the written-back cache line information to the table lookup module. The table lookup module will determine whether to invalidate the data in the table based on this data.

[0180] The miss processing module receives the miss information from the load processing module or the storage processing module, and reads the cache line information from the L2 cache based on this information. If the L2 read data invalid signal transmitted to this module by the read comparison module is a high level, this module does not transmit the read data to the load processing module or write the data of the storage processing module into the cache way.

[0181] It can be seen that this solution solves the alias problem inside the L1 Cache by adding a table lookup module, a read comparison module, and a position transformation module. The table lookup module records the most recent alias sharing information, the read comparison module detects the alias sharing that is not recorded by the table lookup module, and the position transformation module transforms the data at the alias sharing position to the current Index. In this solution, if the required data is originally stored in the L1 Cache, the slowest time to complete the search and return is faster than sending a command from the L2 Cache to let the L1 Cache write back the data and then transfer the data back to the L1 Cache. In addition, this design does not change the structure of the L2 Cache and has better portability. By adding a table lookup module, a read comparison module, and a position transformation module, the alias problem is solved inside the L1 Cache, and the memory access efficiency is improved compared to the existing technology, and the design portability is also higher. The point that the present invention wants to protect is the implementation method of the table lookup module, the read comparison module, and the position transformation module.

[0182] Figure 5 The description of the features in the corresponding embodiments can be found in Figure 3 The relevant descriptions of the corresponding embodiments will not be repeated here one by one.

[0183] Fig.10 A structural diagram of an electronic device provided by an embodiment of the present invention, such as Fig.10 As shown, the electronic device includes: a memory 60 for storing a computer program;

[0184] The processor 61 is used to implement the steps of the data processing method in the above embodiment when executing a computer program.

[0185] The electronic device provided in this embodiment may include but is not limited to a smart phone, a tablet computer, a laptop computer or a desktop computer.

[0186] Among them, the processor 61 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 61 can be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 61 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 61 may be integrated with a graphics processing unit (GPU), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 61 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0187] The memory 60 may include one or more computer-readable storage media, which may be non-transitory. The memory 60 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 60 is at least used to store the following computer program 601, wherein the computer program can implement the relevant steps of the data processing method disclosed in any of the aforementioned embodiments after being loaded and executed by the processor 61. In addition, the resources stored in the memory 60 may also include an operating system 602 and data 603, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 602 may include Windows, Unix, Linux, etc.

[0188] In some embodiments, the electronic device may further include a display screen 62 , an input / output interface 63 , a communication interface 64 , a power supply 65 , and a communication bus 66 .

[0189] Those skilled in the art will understand that Fig.10 The structure shown in the figure does not constitute a limitation on the electronic device, and may include more or fewer components than shown in the figure.

[0190] It is understandable that if the data processing method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the current technology, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium to execute all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, magnetic disk or optical disk, etc. Various media that can store program codes.

[0191] Based on this, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned data processing method are implemented.

[0192] Based on this, an embodiment of the present invention further provides a computer program product, including a computer program or instructions, and when the computer program or instructions are executed by a processor, the steps of the above method are implemented.

[0193] The above is a detailed introduction to a data processing method, device, equipment and medium provided by an embodiment of the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0194] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0195] It should be understood that, although the steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

[0196] The above is a detailed introduction to a data processing method, device, equipment and medium provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A data processing method, characterized in that: include: Acquire a data access request sent by a central processor, wherein the data access request includes: a first virtual index and a first physical identifier; Determine whether the requested data is hit in the first level cache based on the virtual cache mode according to the first virtual index and the first physical identifier; Determine whether there is an identical physical identifier in a lookup table according to the first physical identifier, wherein the lookup table includes a plurality of registers, each register stores a unique corresponding physical identifier, a virtual index, a cache way number and a valid bit, wherein the virtual index includes: an alias bit and an index low bit; If the requested data is not hit and the same physical identifier exists, accessing the corresponding requested data from the first-level cache according to the second virtual index and cache way number corresponding to the first physical identifier in the lookup table; If the requested data is not hit and there is no identical physical identifier, the alias bits of the first virtual index are adjusted in sequence to obtain the third virtual index; based on the physical identifiers corresponding to the cache ways corresponding to the third virtual index in the first-level cache and the first physical identifier, the corresponding request data is accessed.

2. The data processing method according to claim 1, characterized in that: Accessing corresponding request data from the first-level cache according to the second virtual index and the cache way number corresponding to the first physical identifier in the lookup table includes: If the data access request is a data storage request, the data access request further includes: storing data, writing the stored data into a target cache way corresponding to the first virtual index in the first-level cache, and feeding back a storage result to the central processor; If the data access request is a data loading request, the request data is read from the first-level cache according to the second virtual index and the corresponding cache way number, and the read request data is fed back to the central processing unit; and the read request data is written into the target cache way corresponding to the first virtual index in the first-level cache.

3. The data processing method according to claim 2, characterized in that: After accessing the corresponding request data from the first-level cache according to the second virtual index and the cache way number corresponding to the first physical identifier in the lookup table, the method further includes: Update the second virtual index and the corresponding cache way number in the lookup table to the cache way number corresponding to the first virtual index and the target cache way number, respectively; Invalidate data in the first-level cache corresponding to the second virtual index.

4. The data processing method according to claim 3, characterized in that: The target data includes: storage data and read request data, and writing the target data into the target cache way corresponding to the first virtual index in the first-level cache includes: Determine whether there are free cache ways among all cache ways corresponding to the first virtual index in the first-level cache; If it exists, writing the target data into the free cache way corresponding to the first virtual index in the first-level cache, and the free cache way is used as the target cache way; If not, determine the target cache way of the first virtual index according to a preset rule, write the target data into the target cache way corresponding to the first virtual index in the first-level cache; and write the original data in the target cache way back to the second-level cache.

5. The data processing method according to claim 4, characterized in that: After writing the original data in the target cache way back to the secondary cache, it also includes: Determine whether there is a register with a physical identifier corresponding to the original data in the lookup table; If it exists, the valid bit of the register is set to invalid.

6. The data processing method according to claim 1 or 2, characterized in that: Adjusting the alias bit of the first virtual index to obtain a third virtual index; and accessing corresponding request data based on the physical identifiers corresponding to each cache way corresponding to the third virtual index in the first-level cache and the first physical identifier, including: Adjusting the alias bit of the first virtual index to obtain a third virtual index; Determine whether the physical identifiers corresponding to all cache ways corresponding to the third virtual index are the same as the first physical identifier; If so, accessing the corresponding requested data from the cache way corresponding to the first physical identifier; If it does not exist, the alias bit of the first virtual index is adjusted again to obtain a new third virtual index, and the judgment whether the same physical identifier exists is repeated until there is a physical identifier that is the same as the first physical identifier, or, when the alias is adjusted to the maximum value and there is still no physical identifier that is the same as the first physical identifier, the corresponding request data read from the secondary cache based on the physical address is accessed.

7. The data processing method according to claim 6, characterized in that: After accessing the corresponding request data from the cache way corresponding to the first physical identifier, the method further includes: If the data access request is a data storage request, the data access request further includes: storing data, writing the stored data into a target cache way corresponding to the first virtual index in the first-level cache, and feeding back a storage result to the central processor; If the data access request is a data load request, the request data is read from the first-level cache according to the second virtual index and the corresponding cache way number, and the read request data is fed back to the central processing unit; and the read request data is written into the target cache way number corresponding to the first virtual index in the first-level cache; and / or, If there is a register whose valid bit is invalid in the lookup table, the first physical identifier, the first virtual index and the cache way number of the target cache way number corresponding to the first virtual index are written into the register, and the valid bit is set to valid; If there is no register whose valid bit is invalid in the lookup table, the register corresponding to the first virtual index is updated according to the cache way number of the target cache way corresponding to the first physical identifier and the first virtual index.

8. A data processing device, characterized in that: include: A processing module, configured to obtain a data access request sent by a central processing unit, wherein the data access request includes: a first virtual index and a first physical identifier; A first-level cache module, configured to determine whether the requested data is hit in the first-level cache based on the virtual cache mode according to the first virtual index and the first physical identifier; A lookup table module, used for determining whether there is an identical physical identifier in a lookup table according to the first physical identifier, wherein the lookup table includes a plurality of registers, each register storing a unique corresponding physical identifier, a virtual index, a cache way number and a valid bit, wherein the virtual index includes an alias bit and an index low bit; If the requested data is not hit and the same physical identifier exists, the position change module is triggered; If the requested data is not hit and there is no identical physical identifier, the read comparison module is triggered; The position transformation module is used to access the corresponding request data from the first-level cache according to the second virtual index and cache way number corresponding to the first physical identifier in the lookup table; The read comparison module is used to adjust the alias bits of the first virtual index in sequence to obtain a third virtual index; based on the physical identifiers corresponding to the cache ways corresponding to the third virtual index in the first-level cache and the first physical identifier, access the corresponding request data.

9. A data processing device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the data processing method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the data processing method according to any one of claims 1 to 7 are implemented.

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