High-density two-port caching technology for chip of system-on-chip

Abstract

The invention discloses a high-density two-port caching technology for a system-on-chip chip, adopts a high-density 4T1T-SRAM (Static Random Access Memory) unit circuit structure, and belongs to the technical field of memories. The structure comprises three NMOS (N-channel Metal Oxide Semiconductor) transistors and two PMOS (P-channel Metal Oxide Semiconductor) transistors, and is provided with independent read-write word lines and bit lines. The circuit design comprises an inverter, a pull-up transistor and a positive feedback structure, and storage nodes Q and QB store a pair of inverted data. The second NMOS transistor is used for reading operation, and the third NMOS transistor and other transistors cooperate to form a writing circuit which is responsible for writing data. The circuit design is comparable with an 8T-SRAM in the aspects of stability and read interference resistance, has the storage density equivalent to that of a 6T-SRAM, and effectively relieves the problem of cache cost in SOC application. Due to the asymmetric structure of the circuit, the 4T1T-SRAM unit is endowed with the characteristic of self-loading 0, and the 4T1T-SRAM unit is particularly suitable for high-sparsity data storage and has the advantage of low write-in power consumption, such as weight sparsity of a neural network model. In combination with the physical connection of the second NMOS transistor, the 4T1T-SRAM unit also supports a transpose read function. The design has high hardware efficiency in the neural network accelerator, and is suitable for application fields with high sparsity, low power consumption, low area overhead and other requirements.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a high-density two-port cache technology for a system-on-chip chip. Background Art

[0002] We are at the peak of the first great wave of computer technology in human history. The vigorous development of cloud services, meta-computing, the Internet of Things, 5G interconnection and other technologies has brought unprecedented convenience and novel experience to people's production and life. At this stage, with the all-round development of productivity driven by computer technology, emerging technologies represented by virtual reality (VR) and augmented reality (AR) are expected to usher in the second computer science and technology civilization.

[0003] Among the many VR / AR hardware devices, the cost of the graphics processing unit (GPU) and central processing unit (CPU) responsible for image processing, rendering and calculation accounts for about 16%. At the same time, in the microprocessor, the area overhead of the static random access memory (SRAM) accounts for more than 50% of the total chip cost and consumes most of the static power consumption of the processor. In short, the cost of SRAM used as the first-level cache and built-in second-level cache inside the CPU is an important part of VR / AR terminal hardware.

[0004] With the evolution of Moore's Law, process nodes are constantly shrinking, and the proportion of memory device costs is increasing. As a memory technology with relatively mature design technology, Static Random Access Memory (SRAM) is a storage medium that is fully compatible with advanced CMOS processes and can be mass-produced. At the same time, compared with various new memories, SRAM has faster operating speed and durability. However, at this stage, SRAM still faces problems such as low storage density and relatively high design complexity.

[0005] Several commonly used SRAM structures include single-port 6T-SRAM, two-port 8T-SRAM, etc. Figure 1 and Figure 2 shown.

[0006] The 6T in the single-port 6T-SRAM means that the storage unit includes 6 MOS transistors, where the first and second PMOS transistors and the first and second NMOS transistors form a pair of inverters connected end to end inside the 6T-SRAM, and the third and fourth NMOS transistors are used as transmission tubes to support read and write operations. Since the read and write operation paths of the 6T-SRAM overlap, the structure faces the problem of read damage caused by read interference, which affects the stability of the 6T-SRAM.

[0007] The 8T in the two-port 8T-SRAM means that the storage unit includes 8 MOS transistors. In addition to the 6 MOS transistors in the 6T-SRAM, the 8T-SRAM adds two NMOS transistors dedicated to read operations, namely the fifth NMOS transistor of the read selection tube and the sixth NMOS transistor of the read pull-down tube. Due to the use of these two NMOS transistors, the 8T-SRAM has the characteristics of read-write separation, which solves the read interference problem faced by the 6T-SRAM and improves the stability of the SRAM structure. However, due to the addition of two NMOS transistors, the 8T-SRAM deteriorates the storage density and leads to a larger area overhead problem. Summary of the invention

[0008] The purpose of the embodiment of the present application is to provide a high-density two-port cache technology for a system-on-chip chip to solve the above problems. The area of ​​a large-capacity storage module is mainly determined by the size of the memory core, so it is key to make the size of the basic storage unit as small as possible. The circuit core of the patent of the present invention adopts a high-storage density two-port 4T1T-SRAM unit circuit with read-write separation, which has high stability and anti-read interference characteristics comparable to the two-port 8T-SRAM, and has a storage density comparable to the single-port 6T-SRAM. In addition, since the P2 tube on the right side of the 4T1T-SRAM unit removes the pull-down tube originally present in the 6T-SRAM unit, it forms a physically asymmetric structure with the left inverter. This asymmetric structure makes the Q (QB) point more inclined to flip to VSS (VDDR) when the 4T1T-SRAM unit is powered on, thus giving the 4T1T-SRAM unit the characteristic of self-loading 0 at the Q point when it is powered on. At the same time, the second NOMS transistor of the read tube with the gate connected to the Q point makes the 4T1T-SRAM unit have the characteristic of transposition reading.

[0009] The objective of the present invention is achieved through the following technical solutions: A high-density two-port cache technology for system-on-chip chips, the circuit technology mainly includes a newly proposed 4T1T-SRAM storage array, a codec circuit required for read and write operations, a drive circuit required for read and write word lines and read and write bit lines, a timing control circuit, an output circuit module composed of a sensitive amplifier circuit, etc. A read-write separated high storage density 4T1T-SRAM unit circuit, the circuit comprises three NMOS transistors and two PMOS transistors, wherein: A power source VDDL is electrically connected to a source of the first PMOS transistor; A power source VDDR is electrically connected to a source of the second PMOS transistor; It is important to mention that the substrates of the first and second PMOS transistors are both electrically connected to VDDL; The drain of the first PMOS transistor is electrically connected to the drain of the first NMOS transistor; The drain of the first PMOS transistor is electrically connected to the gate of the second NMOS transistor; The drain of the first PMOS transistor is electrically connected to the gate of the second PMOS transistor; The drain of the second PMOS transistor is electrically connected to the gate of the first NMOS transistor; The drain of the second PMOS transistor is electrically connected to the drain of the third NMOS transistor; The drain of the second PMOS transistor is electrically connected to the gate of the first PMOS transistor; The ground line VSS is electrically connected to the source of the first NMOS transistor; The source of the second NMOS transistor is electrically connected to the read bit line RBL; The drain of the second NMOS transistor is electrically connected to the read word line RWL; The gate of the third NMOS transistor is electrically connected to the write word line WWL; A source of the third NMOS transistor is electrically connected to the write bit line WBL.

[0010] Based on the connection relationship of the above devices, the first PMOS transistor and the first NMOS transistor form an inverter structure, the second PMOS transistor is used as a pull-up transistor on one side to maintain the data stored at the QB point, and an inverter and a pull-up transistor are connected end to end to form a latch circuit; Specifically, the first and second PMOS transistors are used as a pull-up circuit structure; the first NMOS transistor is used as a pull-down circuit structure; the second NMOS transistor is used as a read operation transistor to realize the read function; the third NMOS transistor is used as a write transmission transistor to realize the write function; Due to the lack of a pull-down transistor on one side of the second PMOS transistor, to improve the stability when the QB point stores a low level, based on the body biasing effect of MOS transistors (i.e., by controlling the voltage difference between the source and the substrate of the MOS transistor to affect the threshold of the MOS transistor), VDDR < VDDL is set to increase the threshold of the second PMOS transistor, thereby suppressing the sub-threshold leakage current of the second PMOS transistor. This structure helps to improve the stability of the 4T1T-SRAM cell, thus avoiding the need for dynamic data refreshing.

[0011] The read operation is completed by the storage node Q controlling the gate of the second NMOS transistor, using the differential current method, i.e., clamping the voltage V LOW at the source of the second NMOS transistor (connected to RWL), and pre-charging the voltage V HIGH to the drain of the second NMOS transistor (connected to RBL). When the storage node Q stores data 1 or 0, due to the voltage difference across the channel of the second NMOS transistor, RBL will generate or not generate a discharge current relative to RWL according to whether the channel of the NMOS transistor is turned on or not, causing the voltage of RBL to be pulled down to V LOW or remain at V HIGH , corresponding to reading out data 1 or 0. There is no direct charge and discharge path between this read operation process and the latch circuit part of the SRAM memory cell, solving the read interference problem faced by 6T-SRAM.

[0012] The write operation is achieved by the third NMOS transistor writing data to the storage node QB, i.e., when the write word line WWL is enabled, the source-drain conductive channel of the third NMOS transistor is turned on, causing a charge or discharge phenomenon between the pre-charged WBL and the storage node QB, realizing the function of writing data to the storage node QB. The write operation adopts a single-sided operation, reducing the use of one NMOS write transfer transistor compared to 8T-SRAM; at the same time, the read operation uses the direct differential current method, reducing the use of one NMOS read transfer transistor; therefore, the structure of 4T1T-SRAM reduces the problem of excessive cell area brought by 8T-SRAM by reducing the number of MOS transistors occupied.

[0013] In addition, by removing a pull-down NMOS transistor that originally existed in the 6T-SRAM cell, the latch structure in the 4T1T-SRAM cell has a physically asymmetric structure. This asymmetric structure makes the Q point more likely to flip to VSS and the QB point more likely to flip to VDDR when the 4T1T-SRAM cell is powered on. This characteristic enables the large-scale SRAM memory array composed of 4T1T-SRAM cells to physically have the function of being all set to 0一次性地、短时间内地、低功耗地 (once, in a short time, with low power consumption).

[0014] At the same time, based on the connection mode of the second NMOS transistor of the read tube, that is, its gate is connected to the internal Q point of the latch, the two-terminal read signal is loaded on the source and drain of the second NMOS transistor respectively, so that the 4T1T-SRAM cell supports the RWL input in the row direction and reads out from the RBL column direction. At the same time, the 4T1T-SRAM cell also supports the RBL input in the column direction and reads out from the RWL row direction.

[0015] It can be seen from the technical solution provided by the present invention that the unit structure uses one less transistor than 6T-SRAM (i.e., 5 transistors are shared), but provides independent functional paths for read and write operations, so it is not affected by read interference and has the same reliability as 8T-SRAM. In addition, it also has the characteristics of transposition read, automatic reset to 0 on power-on, and low write power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings: FIG1 is a schematic diagram of the overall structure of a commonly used 6T-SRAM unit circuit; FIG2 is a schematic diagram of the overall structure of a commonly used two-port 8T-SRAM unit circuit; FIG3 is a schematic diagram of the architecture of a high-density two-port buffer for a system-on-chip chip; FIG4 is a schematic diagram of the overall structure of a read-write separation high storage density 4T1T-SRAM unit circuit provided by an embodiment of the present invention; FIG5 is a timing diagram of the operation of the circuit according to an embodiment of the present invention; FIG6 is a schematic diagram of a 1×1 unit circuit layout of the circuit according to an embodiment of the present invention; FIG. 7 is a schematic diagram of a 1×2 unit circuit layout of the circuit according to an embodiment of the present invention; FIG8 is a 1K-point Monte Carlo simulation diagram of the automatic reset to zero function of the Q point on power-on supported by an embodiment of the present invention; FIG9 is a 1K-point Monte Carlo simulation diagram of the automatic setting function of the QB point upon power-on supported by an embodiment of the present invention; FIG10 is a 1K-point Monte Carlo simulation diagram of the voltage state at point Q after a holding time of 109 seconds (ie, 1 Gs) according to an embodiment of the present invention; FIG11 is a 1K-point Monte Carlo simulation diagram of the voltage state at the QB point after a holding time of 109 seconds (ie, 1 Gs) according to an embodiment of the present invention; FIG. 12 is a diagram comparing the areas of a two-port 4T1T-SRAM cell provided by an embodiment of the present invention and two common single-port 6T-SRAM and two-port 8T-SRAM storage cells.

[0017] Figure 1 In the figure, 111 and 112 are PMOS transistors; 121, 122, 123, and 124 are NMOS transistors; 131 is a word line WL; 141 is a bit line BL; 142 is an anti-bit line BLB; 151 is a storage node Q; and 152 is a storage node QB.

[0018] Figure 2 Among them, 211 and 212 are PMOS tubes; 221, 222, 223, 224, 225, and 226 are NMOS tubes; 231 is a write word line WWL; 232 is a read word line RWL; 241 is a write bit line WBL; 242 is a write anti-bit line WBLB; 243 is a read bit line RBL; 251 is a storage node Q; and 252 is a storage node QB.

[0019] Figure 4 In the figure, 411 and 412 are PMOS transistors; 421, 422, and 423 are NMOS transistors; 431 is a write word line WWL; 432 is a read word line RWL; 441 is a write bit line WBL; 442 is a read bit line RBL; 451 is a storage node Q; and 452 is a storage node QB.

[0020] Figure 6 In the figure, 611 and 612 are PMOS tubes (corresponding to Figure 4 411, 412 in the figure); 621, 622, 623 are NMOS tubes (corresponding to Figure 4 421, 422, 423 in the referenced documents).

[0021] Figure 7 In the figure, 711 and 712 are PMOS tubes of unit 1; 721, 722, and 723 are NMOS tubes of unit 1; 811 and 812 are PMOS tubes of unit 2; 821, 822, and 823 are NMOS tubes of unit 2; unit 1 and unit 2 share the same write word line WWL1 and the same read word line RWL1; unit 1 and unit 2 have separate write bit lines and read bit lines, unit 1 write bit line WBL1, unit 1 read bit line RBL1, unit 2 write bit line WBL2, and unit 2 read bit line RBL2. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the specific implementation methods described herein are only used to illustrate and explain the embodiments of the present application, and are not used to limit the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0023] It should be noted that the technical solutions between the various embodiments of the present application can be combined with each other, but it must be based on the fact that ordinary technicians in the field can implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0024] like Figure 3 The figure shows a schematic diagram of the architecture of a high-density two-port buffer for a system-on-chip chip provided by an embodiment of the present invention. The array structure mainly includes a 4T1T-SRAM storage array, row and column decoders, drive circuits required for read-write word lines and read-write bit lines, and an output circuit module composed of a sensitive amplifier circuit, etc. The 4T1T-SRAM cell structure supports read-write separation functions, which is similar to the two-port 8T-SRAM array structure. The patent of the present invention configures the required drive / precharge circuits for RWL / WWL / RBL / WBL. Among them, when performing a read operation, RWL is clamped to V by a clamper. LOW volts, RBL is precharged to V HIGH When performing a write operation, WWL and WBL will be driven by full swing. Considering the speed drop caused by word line length, capacitance and resistance, the array size recommended by the present invention is between 64Kb and 256Kb. For larger capacity requirements, a hierarchical storage structure can be used to splice multiple storage blocks.

[0025] like Figure 4 The figure shows a schematic diagram of the circuit structure of a high storage density 4T1T-SRAM unit with read-write separation provided by an embodiment of the present invention. The circuit includes three NMOS transistors and two PMOS transistors. The three NMOS transistors are sequentially denoted as 421 to 423, and the two PMOS transistors are sequentially denoted as 411 to 412, wherein: The power source VDDL is electrically connected to the source of the PMOS transistor 411; The power source VDDR is electrically connected to the source of the PMOS transistor 412; It is important to mention that the substrates of transistors 411 and 412 are both electrically connected to VDDL; The drain of the PMOS transistor 411 is electrically connected to the drain of the NMOS transistor 421; The drain of PMOS transistor 411 is electrically connected to the gate of NMOS transistor 422; The drain of PMOS transistor 411 is electrically connected to the gate of PMOS transistor 412; The drain of PMOS transistor 412 is electrically connected to the gate of NMOS transistor 421; The drain of PMOS transistor 412 is electrically connected to the drain of NMOS transistor 423; The drain of PMOS transistor 412 is electrically connected to the gate of PMOS transistor 411; The ground wire VSS is electrically connected to the source of NMOS transistor 421; The source of NMOS transistor 422 is electrically connected to the read bit line 442; The drain of NMOS transistor 422 is electrically connected to the read word line 432; The gate of NMOS transistor 423 is electrically connected to the write word line 431; The source of NMOS transistor 423 is electrically connected to the write bit line 441.

[0026] As Figure 5 shown is the working timing diagram of the circuit according to the embodiment of the present invention. In a specific implementation, based on the circuit: In the hold state, the write word line WWL, the write bit line WBL, the read word line RWL, and the read bit line RBL are all at low level. The latch circuit composed of 411, 412, and 421 is in the latch state, ensuring the stability of the 4T1T-SRAM cell in the hold state; Since there is no pull-down transistor on one side of transistor 412, in order to improve the stability when the QB node stores a low level, based on the body bias effect of the MOS transistor (that is, by controlling the voltage difference between the source and the substrate of the MOS transistor to affect the threshold of the MOS transistor), VDDR < VDDL is set to increase the threshold of transistor 412, thereby suppressing the sub-threshold leakage current of transistor 412. This structure helps to improve the stability of the 4T1T-SRAM cell, thus avoiding the need for dynamic data refreshing.

[0027] In the write operation stage, assuming that the SRAM cell will perform a write 0 operation, at this time, it is required that the QB storage node be written as 1, the write word line WWL is set to high level, and the bit line WBL is set to WrQB 1 volts, and the read word line RWL and the read bit line RBL remain at the original low level unchanged; assuming that the SRAM cell will perform a write 1 operation, at this time, it is required that the QB storage node be written as 0, the write word line WWL is set to high level, and the bit line WBL is set to WrQB 0 volts (usually equivalent to VSS), and the read word line RWL and the read bit line RBL remain at the original low level unchanged, then the operation of writing 1 to the storage node Q can be completed; During the read operation phase, the write word line WWL and write bit line WBL remain at their original low level, and the read word line RWL is set to V LOW Volts, read word line RBL is precharged to V HIGH If the SRAM unit circuit stores data 1 at node Q, the NMOS transistor 422 channel is turned on. At this time, the read bit line RBL discharges to the read word line RWL through the NMOS transistor 422 until the voltage of RBL drops to the same level as RWL and no discharge current is generated, that is, it is at V LOW If the SRAM cell circuit stores data 0 at node Q, the NMOS transistor 422 channel is closed, and no read current flowing to RWL is generated on the read bit line RBL, so the read bit line RBL maintains the precharge voltage V HIGH The sense amplifier SA in the SRAM array reads the data stored in the SRAM unit circuit by detecting the level change of the read bit line RBL, thus completing the read operation.

[0028] In order to more clearly show the scheme of the circuit described in the embodiment of the present invention and the technical effect produced, the following is combined with the accompanying drawings to show the layout of the 4T1T-SRAM unit provided by the embodiment of the present invention, the 1K-point Monte Carlo simulation diagram of the automatic power-on reset function of the Q (QB) point supported by the embodiment of the present invention, the 1K-point Monte Carlo simulation diagram of the voltage state of the Q (QB) point after a holding time of 109 seconds (i.e., 1Gs) in the embodiment of the present invention, and the comparison of the areas of the three storage units of 4T1T-SRAM, 6T-SRAM, and 8T-SRAM, as follows: (1) If Figure 6 and Figure 7 Shown are 1×1 and 1×2 size layouts of the unit circuit provided in the embodiments of the present invention.

[0029] like Figure 6 As shown by the dotted line boundary, the layout of a 4T1T unit is in the shape of a pistol. In order to clearly show the layout structure, the schematic layout only shows the main hierarchical layout below the metal layer M1, that is, it only includes the metal layer M1, the diffusion area Diffusion, the gate Poly, and the vias between the diffusion area or the gate and the metal layer M1. Among them, VSS, VDDL, VDDR, WBL, and RBL use vertical routing, and RWL and WWL use row routing. In order to ensure that the via area of ​​adjacent units at the boundary is shared, each effective contact point is set with a shared via at the boundary of the pistol-shaped unit.

[0030] like Figure 7As shown in the displayed stitching rules, every two centrosymmetric 4T1T cells can be stitched to form a regular rectangle, where the 1×2 size layout shares the same row direction RWL and the same row direction WWL. In order to clearly show the layout structure, the 1×2 size principle layout only shows the main layer layout of the metal layer M1 and below, that is, only includes the metal layer M1, diffusion area Diffusion, gate Poly, diffusion area or gate and metal layer M1 through hole Contact. The 4T1T cell array will be Figure 7 The 1×2 size layout with a regular rectangular structure is used as the basic unit for array splicing.

[0031] (2) FIG. 8 is a 1K-point Monte Carlo simulation diagram of the automatic reset to zero function at Q point power-on supported by an embodiment of the present invention. Fig. 9 This is a 1K-point Monte Carlo simulation diagram of the automatic setting-to-1 function of the QB point upon power-up supported by an embodiment of the present invention.

[0032] based on Figure 5 The timing diagram shown in the figure performs power-on of VDDR and VDDL, and performs a 1K-point Monte Carlo simulation on the voltage of Q and QB nodes after power-on. Here, the voltages of VDDR and VDDL are set to 500mV and 700mV respectively. Figure 8 It can be found that the 1000 simulation results of the Q node voltage are all distributed near the low voltage, and the average value is about 100uV. Fig. 9 It can be found that the 1000 simulation results of the QB node voltage are all distributed near the high voltage, and the average value is about 500mV.

[0033] The Monte Carlo simulation results show that the 4T1T-SRAM cell can provide a stable Q node self-power-on loading 0 function.

[0034] (3) FIG. 10 is a 1K-point Monte Carlo simulation diagram of the voltage state at point Q after a hold time of 109 seconds (i.e., 1Gs) according to an embodiment of the present invention. FIG. 11 is a 1K-point Monte Carlo simulation diagram of the voltage state at point QB after a hold time of 109 seconds (i.e., 1Gs) according to an embodiment of the present invention; based on Figure 4 From the structural diagram of the 4T1T-SRAM cell, we can see that due to the lack of a pull-down tube on one side of the 412 tube, the 4T1T-SRAM cell has a phenomenon of weak storage of 0 and strong storage of 1 at the QB node. Although there is this tendency of strong and weak, as long as the cell structure can stably store data, it can still provide the SRAM function normally. In response to this, we conducted a Monte Carlo simulation to verify whether the 4T1T-SRAM cell can provide a stable data retention function for a long time when the QB node weakly stores 0. Fig.10It can be found that after 109 seconds of continuous tracking simulation, the 1000 simulation results of the Q node voltage are still stable near the high level, and its average value is about 700mV. Fig.11 It can be found that after 109 seconds of continuous tracking simulation, the 1000 simulation results of the QB node voltage are still stably maintained near a low level, and its average value is about 118mV.

[0035] The Monte Carlo simulation results show that the 4T1T-SRAM cell can provide a stable data retention function. In addition, the inventors have verified that when the QB node stores a low level, under the combined subthreshold leakage of the 412 pull-up tube and the 423 write tube in the off state, the static voltage of QB is maintained at around 100mV, which shows that the 4T1T cell can indeed provide the function of SRAM without the need for dynamic data refresh like DRAM.

[0036] (4) If Fig.12 The figure shows the comparison of the areas of the three memory cells of 4T1T-SRAM, 6T-SRAM and 8T-SRAM provided in the embodiment of the present invention. The data is derived from the 28nm process node. Among them, 6T-SRAM refers to the high-density and high-current sizes, and 8T-SRAM refers to the high-current size. The data are all derived from the SRAM cell area statistics provided by the foundry.

[0037] It is worth noting that the contents not described in detail in the embodiments of the present invention belong to the prior art known to professionals in the field. In summary, it is found that the high storage density 4T1T-SRAM unit circuit invention design with read-write separation has high stability and anti-read disturbance characteristics comparable to 8T-SRAM, and has a storage density comparable to 6T-SRAM.

[0038] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims. The information disclosed in the background technology section of this article is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or in any form that the information constitutes prior art known to those skilled in the art.

Claims

1. A high-density two-port cache technology for a system-on-chip chip. Characterized by: Comprising: A set of peripheral circuits supporting the read and write functions of a two-port SRAM, and a high storage density 4T1T-SRAM cell circuit with separated read and write functions.

2. A set of peripheral circuits supporting two-port SRAM read and write functions. It is characterized by: Comprising: The encoding and decoding circuits required for read and write operations; The driving circuits required for read and write word lines and read and write bit lines; The timing control circuit; The output circuit module composed of a sense amplifier circuit; Since the present technology provides a read-one-write-one (1R1W) cell function similar to that of a two-port 8T-SRAM, the peripheral support circuit adopts a peripheral circuit structure similar to that of a two-port 8T-SRAM.

3. A read-write separated high storage density 4T1T-SRAM unit circuit. Characterized by: Comprising: Three NMOS transistors and two PMOS transistors; Wherein: VDDL is electrically connected to the source of the first PMOS transistor; VDDR is electrically connected to the source of the second PMOS transistor; It is worth highlighting that the substrates of the first and second PMOS transistors are both electrically connected to VDDL; The drain of the first PMOS transistor is electrically connected to the drains of the first NMOS transistor, the gate of the second PMOS transistor, and the gates of the second NMOS transistor; The drain of the second PMOS transistor is electrically connected to the gates of the first PMOS transistor, the first NMOS transistor, and the drain of the third NMOS transistor; The source of the first NMOS transistor is electrically connected to VSS; The write word line WWL is electrically connected to the gate of the third NMOS transistor, the write bit line WBL is electrically connected to the source of the third NMOS transistor, the read word line RWL is electrically connected to the source of the second NMOS transistor, and the read bit line RBL is electrically connected to the drain of the second NMOS transistor; Since there is no pull-down transistor on one side of the second PMOS transistor, in order to improve the stability when the QB point stores a low level, based on the body bias effect of the MOS transistor (that is, by controlling the voltage difference between the source and the substrate of the MOS transistor to affect the threshold of the MOS transistor), VDDR < VDDL is set to increase the threshold of the second PMOS transistor, thereby suppressing the subthreshold leakage current of the second PMOS transistor. This structure helps to improve the stability of the 4T1T-SRAM cell, thus avoiding the need for dynamic data refreshing.

4. The high storage density 4T1T-SRAM unit circuit with read-write separation according to claim 3 is characterized in that: Comprising: The third NMOS transistor is used as a read operation transistor for implementing the read function; the fourth NMOS transistor is used as a write transfer transistor for implementing the write function; This SRAM cell circuit adopts a separated read and write method; During the read operation, the source and drain of the second NMOS transistor adopt the voltage difference current mode, that is, the clamping voltage V LOW The source of the second NMOS transistor (connected to RWL) is precharged with voltage V HIGH To the drain of the second NMOS transistor (connected to RBL), when the storage node Q stores data 1 or 0, due to the voltage difference between the two ends of the second NMOS transistor channel, RBL will generate or not generate conduction current relative to RWL according to whether the NMOS tube channel is turned on or off. If the channel is turned on, the discharge will continue until the RBL voltage drops to the same level as RWL, that is, RBL is pulled down to the voltage V LOW If the channel is closed, no read current will flow to RWL on the read bit line RBL, so the read bit line RBL maintains the precharge voltage V HIGH The sensitive amplifier SA in the SRAM array reads the data stored in the SRAM unit circuit by detecting the level change of the read bit line RBL, completing the read operation and reading the corresponding data 1 or 0. LOW and V HIGH is the set value; During the write operation, the gate of the third NMOS transistor is boosted, that is, when the write word line WWL is enabled, the source-drain conductive channel of the third NMOS transistor is turned on, so that a charging or discharging phenomenon occurs between the WBL pulled up or down according to the write data and the storage node QB, realizing the function of writing data to the storage node QB. The control voltage on WWL is X volts, where X is a set value. The pull-up or pull-down voltage on WBL is WrQB1 or WrQB0 volts, where WrQB1 or WrQB0 is a set value for completing the function of writing 1 or 0 to the storage node QB.

5. A read-write separated high storage density 4T1T-SRAM unit circuit according to claim 3 or 4, characterized in that: Comprising: In the hold state, the write word line WWL, the write bit line WBL, the read word line RWL, and the read bit line RBL are all at low levels, the voltage difference across the channel of the second NMOS transistor used for the read operation is 0, so it is in a static state, and the third NMOS transistor used for the write operation is in a closed state; When the SRAM unit circuit performs a write-0 operation, the Q storage node is required to be 0, so the QB storage node is required to be written as 1, the write word line WWL is set to a high level, the bit line WBL is set to WrQB1 volt, and the read word line RWL and the read bit line RBL remain at the original low level, and the write-0 operation to the storage node Q can be completed; at this time, the third NMOS transistor used as a write transmission tube is in an on state, and the second NMOS transistor used as a read operation tube is in a static state; When the SRAM unit circuit performs a write 1 operation, the Q storage node is required to be 1, so the QB storage node is required to be written to 0, the write word line WWL is set to a high level, the bit line WBL is set to WrQB0 volts, and the read word line RWL and the read bit line RBL remain at the original low level, and the write 1 operation to the storage node Q can be completed; at this time, the third NMOS transistor used as a write transmission tube is in an open state, and the second NMOS transistor used as a read operation tube is in a static state; When the SRAM unit circuit performs a read operation, the write word line WWL and the write bit line WBL remain at their original low level, and the read word line RWL is set to V LOW Volts, read word line RBL is precharged to V HIGH If the SRAM unit circuit stores data 1 at node Q, the second NMOS transistor channel is turned on. At this time, the read bit line RBL discharges to the read word line RWL through the second NMOS transistor until the RBL voltage drops to the same level as RWL and no discharge current is generated, that is, it is at V LOW If the SRAM cell circuit stores data 0 at node Q, the second NMOS transistor channel is closed. At this time, no read current flows to RWL on the read bit line RBL, so the read bit line RBL maintains the precharge voltage V HIGH The sense amplifier SA in the SRAM array reads the data stored in the SRAM unit circuit by detecting the level change of the read bit line RBL, thus completing the read operation.

6. The 4T1T-SRAM unit circuit with an asymmetric latch structure according to claim 3, characterized in that: include: The first PMOS transistor and the first NMOS transistor form an inverter, the second PMOS transistor forms a pull-up transistor, and an inverter and a pull-up transistor form the latch part of the SRAM unit circuit; In addition, since the second PMOS transistor on the right removes the pull-down tube originally present in the 6T-SRAM cell, it forms a physically asymmetric structure with an inverter formed by the first PMOS transistor and the first NMOS transistor on the left. This asymmetric structure makes the Q point of the 4T1T-SRAM cell more inclined to flip to VSS and the QB point more inclined to flip to VDDR when it is powered on. In other words, this process gives the 4T1T-SRAM cell the characteristic of automatically loading 0 at the Q point when it is powered on. Looking at the SRAM array level, the ability of the 4T1T cell to write 0 on power-up can make the entire large-scale SRAM array all set to 0 at once, in a short time, and with low power consumption when it is powered on. It is worth noting that in order to improve the stability of self-power-on 0, VDDL can be set to power on one clock cycle later than VDDR to further help the trend of QB (Q) point biasing towards VDDR (VSS) during power-on.

7. The 4T1T-SRAM unit circuit capable of transposition reading according to claim 5, characterized in that: include: The second NMOS transistor of the read tube supports the RWL input in the row direction and reads out from the RBL column direction. At the same time, the second NMOS transistor of the read tube also supports the RBL input in the column direction and reads out from the RWL row direction; This feature is suitable for application scenarios that require the memory to provide transposed readout, such as in-memory computing neural network accelerators that provide on-chip training capabilities, or TCAM applications that require bidirectional search.

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