Chip design text storage method and system

Abstract

The invention provides a chip design text storage method and system which are applied to the technical field of chip storage, and the method comprises the steps: obtaining a data structure, parameters, configuration and other information required for defining chip design; representing the information in a proper serialization format; writing the integrated serialized format information into a database through a binary format; compared with the prior art, delay is reduced, so that higher bandwidth and faster response time are achieved, which is particularly important for applications (such as databases, virtualization environments and high-performance computing) needing to quickly read and write a large amount of data, the optimized task scheduling and load balancing strategy can ensure that the utilization rates of all channels are balanced, a certain channel is prevented from being overloaded or idle, and the service life of the channels is prolonged. The efficient resource management can reduce the I / O bottleneck, improve the overall efficiency of the system, enable storage resources to be utilized more fully, and further improve the performance of the whole storage system.

Description

Technical Field

[0001] The present application relates to the field of chip storage technology, and in particular to a text storage method and system for chip design. Background Art

[0002] In chip design, text storage usually refers to text format files used to store and manage design data. These files can contain various information, such as circuit design descriptions, test vectors, configuration parameters, constraints, etc. The main advantages of text storage are strong readability, easy editing and version control;

[0003] Languages ​​such as VHDL or Verilog are used to describe the structure and behavior of digital circuits and are usually stored in the form of text files. For example, SDC (Synopsys Design Constraints) files define design rules such as timing constraints and pin assignments and are usually stored in text format. Text files used to store test cases and input signals for use in simulation and verification processes. Some chip design tools and environments use text files to store configuration parameters and user settings. Design documents, comments, and other auxiliary information are also often stored in text format to facilitate communication and collaboration among team members.

[0004] Text files are typically larger than binary files, and reading and parsing text files is slower, which can affect performance, especially when dealing with large amounts of data. In particular, text files are prone to manual editing, which can lead to grammatical errors, spelling errors, or incorrect formatting that can cause design issues or simulation failures. Summary of the invention

[0005] The present application aims to solve the technical problem that text files are usually larger than binary files, and the speed of reading and parsing text files is slow, which may affect performance, especially when processing large amounts of data. In particular, text files are easy to edit manually, which may lead to grammatical errors, spelling errors or incorrect formats, thereby causing design problems or simulation failures. A chip design text storage method and system are provided.

[0006] This application adopts the following technical means to solve the technical problem: a chip design text storage method and system,

[0007] A chip design text storage method and system, the method comprising:

[0008] Obtain the data structures, parameters, configurations, and other information needed to define the chip design;

[0009] Represent the above information in a suitable serialization format;

[0010] The integrated serialized format information is written into the database in binary format.

[0011] Furthermore, in the step of obtaining the data structure, parameters, configuration and other information required to define the chip design,

[0012] Obtain the processing speed, power consumption, frequency, bandwidth, latency, size and cost conditions of the chip design;

[0013] Define the data structure, collect the corresponding parameter configuration and verify whether the data is suitable.

[0014] Further, if the corresponding parameter configuration is adapted to the data verification, the data of the chip design is correspondingly defined by a serialized format;

[0015] If the corresponding parameter configuration and data validation do not match, the data is recalculated.

[0016] Furthermore, in the step of representing the above information in a suitable serialization format,

[0017] Use protocol buffers to represent chip design data structures.

[0018] Furthermore, in the step of writing the integrated serialized format information into the database in binary format,

[0019] The chip design data structure is obtained and serialized into binary format.

[0020] Furthermore, after the step of obtaining the chip design data structure and serializing it into a binary format,

[0021] When you need to read the data, you can use deserialization to convert the binary data back to the original data structure.

[0022] Further, after the step of selecting the binary format to write the chip design data,

[0023] Use hybrid storage architecture and tiered storage architecture to improve data reading and writing;

[0024] The hybrid storage architecture uses both SLC and TLC storage, with SLC used to store frequently accessed data and TLC used to store large-capacity cold data;

[0025] The tiered storage architecture stores data in tiers, with hot data stored in SLC or MLC and cold data stored in TLC or QLC.

[0026] Further, after the step of writing the chip design data in the rotating binary format,

[0027] Set up a multi-channel master control design, read and write through electronic sequences, and perform parallel processing.

[0028] The present application provides a chip design text storage method and system, which has the following beneficial effects:

[0029] By using multiple channels for data transmission at the same time, the system can significantly improve the data reading and writing speed. Parallel processing of multiple data streams can reduce the load of a single channel and reduce latency, thereby achieving higher bandwidth and faster response time. This is especially important for applications that need to quickly read and write large amounts of data (such as databases, virtualized environments, and high-performance computing);

[0030] Optimized task scheduling and load balancing strategies can ensure balanced utilization of all channels and avoid overloading or idleness of a channel. This efficient resource management can reduce I / O bottlenecks, improve the overall efficiency of the system, make better use of storage resources, and thus improve the performance of the entire storage system.

[0031] By properly managing hot and cold data, the system can reduce frequent write operations and lower the write amplification effect, thereby extending the service life of the storage media. In addition, the master controller can implement efficient garbage collection and error recovery mechanisms to ensure data integrity and reliability. This improved durability is especially important for enterprise-level storage solutions, helping to reduce maintenance costs and improve data security. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A flowchart of an embodiment of a text storage method and system for chip design of the present application.

[0033] The implementation, functional features and advantages of the present application will be further described in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0034] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0035] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0036] It should be noted that the terms "include", "comprises" and "have" and any variations thereof in the specification and claims of the present application and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices. In the claims, specification and drawings of the present application, relational terms such as "first" and "second" are merely used to distinguish one entity / operation / object from another entity / operation / object, and do not necessarily require or imply any such actual relationship or order between these entities / operations / objects.

[0037] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0038] Reference Figure 1 , is a flow chart of a chip design text storage method and system in one embodiment of the present application;

[0039] Embodiment 1

[0040] A chip design text storage method and system, the method comprising:

[0041] Obtain the data structures, parameters, configurations, and other information needed to define the chip design;

[0042] Represent the above information in a suitable serialization format;

[0043] The integrated serialized format information is written into the database in binary format.

[0044] In this embodiment,

[0045] In the step of obtaining the data structure, parameters, configuration and other information required to define the chip design,

[0046] Obtain the processing speed, power consumption, frequency, bandwidth, latency, size and cost conditions of the chip design;

[0047] Define the data structure, collect the corresponding parameter configuration and verify whether the data is suitable.

[0048] If the corresponding parameter configuration and data verification are compatible, the chip design data is defined in a serialized format accordingly;

[0049] If the corresponding parameter configuration and data validation do not match, the data is recalculated.

[0050] Specifically, obtain the preset parameters of the chip design, such as the processing speed required by the chip (the number of instructions processed per second or the data transmission rate), set the power consumption requirements of the chip in different operating modes, the operating frequency range, the data transmission bandwidth, the maximum allowable delay, the chip's power consumption size and packaging type.

[0051] In this embodiment, in the step of representing the above information in a suitable serialization format,

[0052] Use protocol buffers to represent chip design data structures.

[0053] In the step of writing the integrated serialized format information into the database in binary format,

[0054] The chip design data structure is obtained and serialized into binary format.

[0055] Specifically,

[0056] Use Protocol Buffers to define chip design data structures:

[0057]

[0058]

[0059] After defining the data structure, you can use the corresponding library to serialize the data into binary format. Example code for serialization using Python and Protocol Buffers:

[0060]

[0061]

[0062]

[0063] When you need to read the data, you can use deserialization to convert the binary data back to the original data structure:

[0064]

[0065] In this embodiment, after the step of obtaining the chip design data structure and serializing it into a binary format,

[0066] When you need to read the data, you can use deserialization to convert the binary data back to the original data structure.

[0067] Specifically,

[0068]

[0069]

[0070] Therefore, by defining the data structure through Protocol Buffers, various information required for chip design can be represented, and serialization and deserialization operations can be performed, which improves data storage efficiency and simplifies data transmission and processing.

[0071] After the step of selecting the binary format to write the chip design data,

[0072] Use hybrid storage architecture and tiered storage architecture to improve data reading and writing;

[0073] The hybrid storage architecture uses both SLC and TLC storage, with SLC used to store frequently accessed data and TLC used to store large-capacity cold data;

[0074] The tiered storage architecture stores data in tiers, with hot data stored in SLC or MLC and cold data stored in TLC or QLC.

[0075] After the step of writing the chip design data in the rotating binary format,

[0076] Set up a multi-channel master control design, read and write through electronic sequences, and perform parallel processing.

[0077] Embodiment 2

[0078] A chip design text storage method and system, the method comprising:

[0079] Obtain the data structures, parameters, configurations, and other information needed to define the chip design;

[0080] Represent the above information in a suitable serialization format;

[0081] The integrated serialized format information is written into the database in binary format.

[0082] In the step of obtaining the data structure, parameters, configuration and other information required to define the chip design,

[0083] Obtain the processing speed, power consumption, frequency, bandwidth, latency, size and cost conditions of the chip design;

[0084] Define the data structure, collect the corresponding parameter configuration and verify whether the data is suitable.

[0085] If the corresponding parameter configuration and data verification are compatible, the chip design data is defined in a serialized format accordingly;

[0086] If the corresponding parameter configuration and data validation do not match, the data is recalculated.

[0087] In the step of representing the above information in a suitable serialization format,

[0088] Use protocol buffers to represent chip design data structures.

[0089] In the step of writing the integrated serialized format information into the database in binary format,

[0090] The chip design data structure is obtained and serialized into binary format.

[0091] After the step of obtaining the chip design data structure and serializing it into a binary format,

[0092] When you need to read the data, you can use deserialization to convert the binary data back to the original data structure.

[0093] In this embodiment, after the step of selecting the binary format to write the chip design data,

[0094] Use hybrid storage architecture and tiered storage architecture to improve data reading and writing;

[0095] The hybrid storage architecture uses both SLC and TLC storage, with SLC used to store frequently accessed data and TLC used to store large-capacity cold data;

[0096] The tiered storage architecture stores data in tiers, with hot data stored in SLC or MLC and cold data stored in TLC or QLC.

[0097] Specifically,

[0098] Storage architecture selection

[0099] Hybrid storage architecture:

[0100] SLC storage (capacity: 1TB):

[0101] Store frequently accessed design data and key configuration files;

[0102] For example:

[0103] Design documents: 500MB (such as specifications, design process documents)

[0104] Simulation results: 200MB (latest design simulation results)

[0105] Key algorithm code: 300MB (such as image processing algorithm, signal processing algorithm)

[0106] TLC storage (capacity: 4TB):

[0107] Store large amounts of cold data

[0108] For example:

[0109] Historical test data: 1TB (test results for the past 6 months)

[0110] Version control backup: 2TB (old version code and design documents)

[0111] Infrequently used documents: 1TB (such as outdated design documents, market research reports)

[0112] Tiered storage architecture:

[0113] Hot data (stored in SLC or MLC):

[0114] Current development codebase: 500MB (active codebase, frequently updated)

[0115] Latest test results: 300MB (test results of the current version, need quick access)

[0116] Cold data (stored in TLC or QLC):

[0117] Outdated design documents: 1TB (design documents from 6 months ago)

[0118] Old version code: 1TB (past code version, no longer used).

[0119] After the step of writing the chip design data in the rotating binary format,

[0120] Set up a multi-channel master control design, read and write through electronic sequences, and perform parallel processing;

[0121] Specifically,

[0122] Writing data in rotating binary format

[0123] Before starting a multi-channel master design, you first need to ensure that the chip design data is successfully written in a rotating binary format. This process usually includes the following steps:

[0124] Converting design data into a rotated binary format;

[0125] Use a dedicated writing algorithm to write the converted data to the storage medium

[0126] Set up multi-channel master control design

[0127] Hardware architecture design

[0128] Multi-channel controller:

[0129] Design a multi-channel controller that can manage multiple data channels simultaneously to achieve parallel read and write operations;

[0130] The controller can be designed using FPGA or ASIC, with enough I / O interfaces to support multiple channels;

[0131] Channel division:

[0132] Divide the data channel into multiple independent channels, each channel is responsible for a specific data block;

[0133] For example, suppose there are 8 channels, each of which can process 256MB of data simultaneously;

[0134] Electronic serial read and write

[0135] Design electronic sequence control logic to ensure that there is no conflict between channels when writing and reading data;

[0136] Use the state machine to control the read and write status of each channel;

[0137] Data reading and writing process:

[0138] Divide the data into blocks and distribute them by channels;

[0139] Send a write command to the controller, specifying the target channel and data block;

[0140] The controller writes the data into the storage medium through the corresponding channel;

[0141] Reading process:

[0142] Send a read command to the controller, specifying the target channel and data block;

[0143] The controller reads data from the storage medium and transmits it to the specified output port;

[0144] Parallel Data Processing:

[0145] In a multi-channel controller, parallel processing logic is implemented so that multiple channels can read and write data simultaneously;

[0146] For example, if the read and write speed of each channel is 100MB / s, 8 channels can achieve a data processing speed of up to 800MB / s;

[0147] After the data is read, a data integration module is designed to merge the data from different channels to form a complete design data set;

[0148] This module can be implemented in FPGA or microcontroller and is responsible for synchronizing and integrating data from multiple channels.

[0149] Embodiment 3

[0150] A chip design text storage method and system, the method comprising:

[0151] Obtain the data structures, parameters, configurations, and other information needed to define the chip design;

[0152] Represent the above information in a suitable serialization format;

[0153] The integrated serialized format information is written into the database in binary format.

[0154] In the step of obtaining the data structure, parameters, configuration and other information required to define the chip design,

[0155] Obtain the processing speed, power consumption, frequency, bandwidth, latency, size and cost conditions of the chip design;

[0156] Define the data structure, collect the corresponding parameter configuration and verify whether the data is suitable.

[0157] If the corresponding parameter configuration and data verification are compatible, the chip design data is defined in a serialized format accordingly;

[0158] If the corresponding parameter configuration and data validation do not match, the data is recalculated.

[0159] In the step of representing the above information in a suitable serialization format,

[0160] Use protocol buffers to represent chip design data structures.

[0161] In the step of writing the integrated serialized format information into the database in binary format,

[0162] The chip design data structure is obtained and serialized into binary format.

[0163] After the step of obtaining the chip design data structure and serializing it into a binary format,

[0164] When you need to read the data, you can use deserialization to convert the binary data back to the original data structure.

[0165] After the step of selecting the binary format to write the chip design data,

[0166] Use hybrid storage architecture and tiered storage architecture to improve data reading and writing;

[0167] The hybrid storage architecture uses both SLC and TLC storage, with SLC used to store frequently accessed data and TLC used to store large-capacity cold data;

[0168] The tiered storage architecture stores data in tiers, with hot data stored in SLC or MLC and cold data stored in TLC or QLC.

[0169] After the step of writing the chip design data in the rotating binary format,

[0170] Set up a multi-channel master control design, read and write through electronic sequences, and perform parallel processing;

[0171] In summary,

[0172] By using multiple channels for data transmission at the same time, the system can significantly improve the data reading and writing speed. Parallel processing of multiple data streams can reduce the load of a single channel and reduce latency, thereby achieving higher bandwidth and faster response time. This is especially important for applications that need to quickly read and write large amounts of data (such as databases, virtualized environments, and high-performance computing);

[0173] Optimized task scheduling and load balancing strategies can ensure balanced utilization of all channels and avoid overloading or idleness of a channel. This efficient resource management can reduce I / O bottlenecks, improve the overall efficiency of the system, make better use of storage resources, and thus improve the performance of the entire storage system.

[0174] By properly managing hot and cold data, the system can reduce frequent write operations and lower the write amplification effect, thereby extending the service life of the storage media. In addition, the master controller can implement efficient garbage collection and error recovery mechanisms to ensure data integrity and reliability. This improved durability is especially important for enterprise-level storage solutions, helping to reduce maintenance costs and improve data security.

[0175] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0176] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems) and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the process in the flowchart. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0177] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0178] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0179] Although the embodiments of the present application have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the appended claims and their equivalents.

Claims

1. A chip design text storage method and system, characterized in that: The method comprises: Obtain the data structures, parameters, configurations, and other information needed to define the chip design; Represent the above information in a suitable serialization format; The integrated serialized format information is written into the database in binary format.

2. The chip design text storage method and system according to claim 1, characterized in that: In the step of obtaining the data structure, parameters, configuration and other information required to define the chip design, Obtain the processing speed, power consumption, frequency, bandwidth, latency, size and cost conditions of the chip design; Define the data structure, collect the corresponding parameter configuration and verify whether the data is suitable.

3. The chip design text storage method and system according to claim 2, characterized in that: If the corresponding parameter configuration and data verification are compatible, the chip design data is defined in a serialized format accordingly; If the corresponding parameter configuration and data validation do not match, the data is recalculated.

4. The chip design text storage method and system according to claim 1, characterized in that: In the step of representing the above information in a suitable serialization format, Use protocol buffers to represent chip design data structures.

5. The chip design text storage method and system according to claim 1, characterized in that: In the step of writing the integrated serialized format information into the database in binary format, The chip design data structure is obtained and serialized into binary format.

6. The chip design text storage method and system according to claim 5, characterized in that: After the step of obtaining the chip design data structure and serializing it into a binary format, When you need to read the data, you can use deserialization to convert the binary data back to the original data structure.

7. The chip design text storage method and system according to claim 1, characterized in that: After the step of selecting the binary format to write the chip design data, Use hybrid storage architecture and tiered storage architecture to improve data reading and writing; The hybrid storage architecture uses both SLC and TLC storage, with SLC used to store frequently accessed data and TLC used to store large-capacity cold data; The tiered storage architecture stores data in tiers, with hot data stored in SLC or MLC and cold data stored in TLC or QLC.

8. The chip design text storage method and system according to claim 1, characterized in that: After the step of writing the chip design data in the rotating binary format, Set up a multi-channel master control design, read and write through electronic sequences, and perform parallel processing.

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