Display device and vehicle system including the same

Abstract

The present disclosure provides a display device and a vehicle system including the same. The display device includes: a display panel including a plurality of sub-pixels; a gate driving circuit configured to provide a scanning signal and an emission signal to the display panel through a plurality of gate lines; a converter configured to convert a first level circuit power supply provided from a host system to a second level circuit power supply; a logic gate configured to generate a power supply check signal based on an interface data signal transmitted through the interface line and a second level circuit power supply; and a timing controller configured to control a transmission start signal supplied to the gate driving circuit in accordance with the power supply check signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0174009 filed on December 5, 2023, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0003] Embodiments of the present disclosure relate to a display device and a vehicle system, and more particularly, to a display device and a vehicle system capable of preventing an accident due to an error in a display panel. Background Art

[0004] The development of a smart society has led to an increased demand for the use of image display devices and various types of display devices such as liquid crystal displays, organic light emitting displays, etc.

[0005] Among these display devices, an organic light emitting display device uses a self-emitting organic light emitting diode, providing advantages such as fast response and better contrast, light emitting efficiency, brightness, and viewing angle.

[0006] The display device may include light emitting elements respectively arranged in a plurality of sub-pixels provided on a display panel, and light emitting diodes are made to emit light by controlling a voltage applied to the light emitting elements, thereby displaying an image while controlling the brightness of each sub-pixel.

[0007] Recently, the use fields of display devices have gradually expanded to include not only portable computers but also desktop computer monitors, vehicle displays, and wall-mounted televisions.

[0008] Such a display device can provide various functions according to the purpose of the electronic device on which the display panel is mounted. For example, for a vehicle display device, a navigation function can be called an essential function.

[0009] Meanwhile, the display device may be abnormally shut down due to impact or overcurrent during the driving process. In this case, if screen flickering or display errors such as horizontal stripes occur during the abnormal shut down process of the display device such as the navigation device, there is a possibility that an accident may occur due to the sudden reaction of the driver. Summary of the invention

[0010] Therefore, the inventors of the present disclosure have invented a display device and a vehicle system that can prevent an accident caused by a display error when a display panel is abnormally turned off.

[0011] Embodiments of the present disclosure may provide a display device and a vehicle system that can eliminate display errors by blocking an emission control transistor that controls a light emitting element when a display panel is abnormally turned off.

[0012] Embodiments of the present disclosure may provide a display device and a vehicle system that may prevent accidents caused by display errors by determining whether a display panel is abnormally shut down by detecting changes in an interface data signal and a power supply voltage.

[0013] An embodiment of the present disclosure may provide a display device, comprising: a display panel including a plurality of sub-pixels, a gate driving circuit configured to provide a scanning signal and an emission signal to the display panel through a plurality of gate lines, a converter configured to convert a first-level circuit power provided from a host system into a second-level circuit power, a logic gate configured to generate a power check signal based on an interface data signal transmitted through an interface line and the second-level circuit power, and a timing controller configured to control an emission start signal provided to the gate driving circuit according to the power check signal.

[0014] An embodiment of the present disclosure may provide a vehicle system, comprising: a display panel including a plurality of sub-pixels, a gate drive circuit configured to provide a scan signal and an emission signal to the display panel through a plurality of gate lines, a converter configured to convert a first-level circuit power provided from a host system into a second-level circuit power, a logic gate configured to generate a power check signal based on an interface data signal transmitted through an interface line and the second-level circuit power, and a timing controller configured to control an emission start signal provided to the gate drive circuit according to the power check signal.

[0015] According to the embodiments of the present disclosure, an accident due to a display error when a display panel is abnormally turned off can be prevented.

[0016] According to an embodiment of the present disclosure, display errors can be eliminated and power consumption can be reduced by blocking an emission control transistor that controls a light emitting element when a display panel is abnormally turned off.

[0017] According to an embodiment of the present disclosure, it is possible to prevent accidents caused by display errors by determining whether a display panel is abnormally shut down by detecting changes in an interface data signal and a power supply voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0019] Figure 1is a view showing an example interior of a vehicle system according to an embodiment of the present disclosure;

[0020] Figure 2 is a view schematically showing a display device for a vehicle system according to an embodiment of the present disclosure;

[0021] Figure 3 is an exemplary system diagram showing a display device according to an embodiment of the present disclosure;

[0022] Figure 4 is a view showing a structure for receiving an interface data signal from a host system using a low voltage differential signaling interface in a display device for a vehicle system according to an embodiment of the present disclosure;

[0023] Figure 5 is a diagram showing a waveform of an interface data signal transmitted from a host system to a display device in a vehicle system according to an embodiment of the present disclosure;

[0024] Figure 6 is a block diagram showing an example gate driving circuit including a scan driving circuit and an emission driving circuit in a display device according to an embodiment of the present disclosure;

[0025] Figure 7 is a view showing an example sub-pixel circuit in a display device according to an embodiment of the present disclosure;

[0026] Figure 8 is a diagram showing an example power waveform provided to a host system of a display device according to an embodiment of the present disclosure;

[0027] Fig. 9 is a diagram illustrating an example signal error when power supplied to a host system is abnormally cut off in a display device according to an embodiment of the present disclosure;

[0028] Fig.10 is a circuit block diagram for controlling emission of a display panel by detecting changes in circuit power and interface data signals in a display device according to an embodiment of the present disclosure;

[0029] Fig.11 A table showing logic gates for comparing second level circuit power and interface data signals in a display device according to an embodiment of the present disclosure;

[0030] Fig.12 shows waveforms of a power check signal and a transmission start signal depending on a circuit power supply and an interface data signal in a display device according to an embodiment of the present disclosure; and

[0031] Fig.13is a view showing an example screen state of a display panel when the display device is abnormally shut down. DETAILED DESCRIPTION

[0032] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to exemplary drawings. In the following description of the examples or embodiments of the present disclosure, reference will be made to the drawings, wherein specific examples or embodiments that can be implemented are shown by way of illustration, and wherein even when the same or similar parts are shown in drawings that are different from each other, the same reference numerals and symbols can be used to represent the same or similar parts. In addition, in the following description of the examples or embodiments of the present disclosure, when it is determined that the description of the known functions and parts incorporated herein may make the subject matter in some embodiments of the present disclosure unclear, its detailed description will be omitted. Terms such as "including", "having", "containing", "constituting", "consisting of ... " and "formed by ... " used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only". As used herein, the singular form is intended to include the plural form, unless the context clearly indicates otherwise.

[0033] Terms such as "first", "second", "A", "B", "(A)" or "(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to define the nature, order, sequence or quantity of the elements, etc., but is only used to distinguish the corresponding element from other elements.

[0034] When it is mentioned that a first element is “connected or coupled”, “contacted or overlapped”, etc. with a second element, it should be interpreted that not only the first element can be “directly connected or coupled” or “directly contacted or overlapped” with the second element, but also a third element can be “inserted” between the first and second elements, or the first and second elements can be “connected or coupled”, “contacted or overlapped”, etc. with each other via a fourth element. Here, the second element can be included in at least one of the two or more elements that are “connected or coupled”, “contacted or overlapped”, etc. with each other.

[0035] When time relative terms such as “after,” “subsequently,” “next,” “before,” etc. are used to describe a process or operation of an element or configuration, or a flow or step in an operation, process, or method of manufacture, these terms may be used to describe non-sequential or non-sequential processes or operations unless the terms “directly” or “immediately” are used together.

[0036] Furthermore, when referring to any dimension, relative size, etc., it should be considered that the numerical value of an element or feature, or corresponding information (e.g., level, range, etc.) includes a tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.) even when no relevant description is specified. In addition, the term "may" fully encompasses all meanings of the term "can".

[0037] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0038] Figure 1 is a view showing an example interior of a vehicle according to an embodiment of the present disclosure.

[0039] refer to Figure 1 The vehicle system 1000 according to an embodiment of the present disclosure may include a driver seat, a passenger seat, a dashboard located in front of the driver seat and the passenger seat and on which various instruments required for driving are arranged, and a center fascia having a control panel of electronic devices.

[0040] The instrument panel may include a first display panel 111 that displays information required for driving, including a speedometer. The first display panel 111 may be referred to as an instrument panel display panel.

[0041] The first display panel 111 is a display panel capable of safely driving the vehicle system 1000 by transmitting information about the driving state of the vehicle system 1000 and the operations of various electronic devices provided in the vehicle system 1000 to the driver. A speedometer indicating a driving speed, an odometer indicating a driving distance, a tachometer indicating the revolutions per meter (RPM) of an engine, a fuel gauge, a water temperature gauge, an engine temperature gauge, and various warning lights located behind a steering wheel relative to a driver's seat may be displayed through the first display panel 111.

[0042] The central instrument panel is located between the driver's seat and the passenger seat, and may correspond to the area where the instrument panel and the shift lever meet vertically, and may be provided with audio, air conditioning, heater controls, navigation, blower, cigar jack, ashtray, cup holder, etc. In addition, the central instrument panel may include a second display panel 112 .

[0043] The second display panel 112 may guide a route to a destination or display a map image corresponding to a current location, and display a user interface related to control of various electronic devices installed in the vehicle system 1000. In addition, when the vehicle system 1000 and a mobile terminal are connected, a screen provided by the mobile terminal may be displayed.

[0044] The second display panel 112 located between the driver seat and the passenger seat of the vehicle system 1000 may be referred to as a center instrument panel display panel.

[0045] In addition, for the convenience of the passengers in the passenger seat, the third display panel 113 may be additionally installed on the front surface of the passenger seat. The third display panel 113 located in the passenger seat may be referred to as a passenger seat display panel.

[0046] In addition, the display panel 110 may include at least one of a front window display panel, a side mirror display panel, a rearview mirror display panel, and a side window display panel in addition to the instrument panel display panel 111, the central instrument panel display panel 112, and the passenger seat display panel 113. In addition, various types of display panels may be installed.

[0047] The front window display panel may be a display panel that projects a virtual image onto the front window and is capable of observing a partial area in front of the vehicle system 1000. By displaying the vehicle's speed, remaining fuel, route direction information, etc. via the front window display panel, unnecessary changes in the driver's gaze in different directions can be minimized.

[0048] The side mirror display panel may be a display panel capable of displaying an image of the side surface captured by the side camera in a partial area or the entire area of ​​the side mirror formed to observe the side surface of the vehicle system 1000. Therefore, the driver can recognize not only the image of the side surface reflected by the side mirror but also the image of the side surface captured by the side camera through the side mirror display panel.

[0049] The rearview mirror display panel may be a display panel capable of displaying an image of the rear captured by the rear camera in a partial area or the entire area of ​​the rearview mirror formed to observe the rear of the vehicle system 1000. Therefore, the driver can recognize not only the rear image reflected by the rearview mirror but also the rear image captured by the rear camera through the rearview mirror display panel.

[0050] The side window display panel may be a display panel that projects a virtual image onto a partial area of ​​a side surface of the side window where the vehicle system 1000 can be observed. A lot of information about the vehicle system may be displayed through the side window display panel.

[0051] Figure 2 is a view schematically illustrating a display device for a vehicle system according to an embodiment of the present disclosure.

[0052] refer to Figure 2 , the display device 100 according to an embodiment of the present disclosure may include a display panel 110 , a gate driving circuit 120 , a data driving circuit 130 , a timing controller 140 , and a level shifter 180 .

[0053] In the display panel 110 , a plurality of data lines DL and a plurality of gate lines GL may intersect each other, and sub-pixels SP may be arranged in a matrix form in each intersecting region, thereby forming a sub-pixel array.

[0054] In the case of a liquid crystal display device, the display panel 110 may include a liquid crystal layer formed between two substrates, and may operate in any known mode, such as a twisted nematic (TN) mode, a vertical alignment (VA) mode, an in-plane switching (IPS) mode, or a fringe field switching (FFS) mode. In the case of an organic light emitting display device, the display panel 110 may be implemented in a top emission scheme, a bottom emission scheme, or a dual emission scheme.

[0055] One sub-pixel SP may include, for example, a thin film transistor (TFT) disposed in a region formed by one data line DL and one gate line GL, a light emitting element that emits light according to a data voltage, and a storage capacitor electrically connected to the light emitting element to maintain a voltage. The thin film transistor may include a driving transistor and one or more switching transistors, and may be implemented as a P-type transistor or an N-type transistor. Alternatively, it may be implemented in a hybrid form of a hybrid P-type transistor and an N-type transistor.

[0056] For example, when the display device 100 having a resolution of 2160×3840 includes four sub-pixels SP of white (W), red (R), green (G), and blue (B), 3840 data lines DL may be connected to 2160 gate lines GL and four sub-pixels WRGB, and thus 3840×4=15360 data lines DL may be provided. Each sub-pixel SP is disposed in a region formed by the gate line GL and the data line DL.

[0057] The timing controller 140 may receive the interface data signal IFD from the host system 200 through a predetermined interface scheme and may convert it into the image data DATA for internal use.

[0058] In the case of the display device 100 for a vehicle system, the host system 200 and the display device 100 may use a low voltage differential signaling (LVDS) interface. In this case, the interface data signal IFD transmitted from the host system 200 to the display device 100 through the low voltage differential signaling (LVDS) interface may be referred to as a low voltage differential data signal.

[0059] The low voltage differential signaling (LVDS) interface is a standard interface defined by ANSI / TIA / EIA-644 and is used in areas where high-speed data transmission, low power consumption, and noise immunity are required. When the low voltage differential signaling (LVDS) interface is used, the interface data signal IFD is transmitted as a differential input signal with a swing width of approximately 350mV, so it has strong noise immunity and is capable of high-speed data transmission.

[0060] The timing controller 140 may correct the image data DATA to compensate for a driving deviation of the sub-pixel SP based on a sensing result of a characteristic value of the sub-pixel (eg, a threshold voltage or mobility of a driving transistor), and then transmit it to the data driving circuit 130 .

[0061] The timing controller 140 may receive timing signals such as a vertical synchronization signal, a horizontal synchronization signal, and a data enable signal and an interface data signal IFD from the host system 200. The timing controller 140 generates a source control signal SCS for controlling the operation timing of the data driving circuit 130 and a timing control signal TCS for controlling the operation timing of the gate driving circuit 120 based on the timing signals input from the host system.

[0062] The source control signal SCS includes a source sampling clock, a source output enable signal, etc. The source sampling clock is a clock for controlling the sampling timing of the image data DATA in the data driving circuit 130 based on a rising edge or a falling edge. The source output enable signal is a signal for controlling the output timing of the analog data voltage applied to the display panel 110.

[0063] The data driving circuit 130 may include a plurality of source driving integrated chips SDIC. The data driving circuit 130 receives the image data DATA from the timing controller 140. The data driving circuit 130 generates a data voltage by converting the image data DATA into a gamma compensation voltage in response to a source control signal SCS transmitted from the timing controller 140, synchronizes the data voltage with a scan signal of the gate driving circuit 120, and provides it to the data line DL of the display panel 110.

[0064] The data driving circuit 130 may be connected to the data lines DL of the display panel 110 through a chip on glass (COG) process or a tape automated bonding (TAB) process.

[0065] The display device 100 may include a level shifter 180 that generates a gate control signal GCS using a timing control signal TCS output from the timing controller 140 and provides the generated gate control signal GCS to the gate driving circuit 120. The level shifter 180 may be located inside the gate driving circuit 120, or may be located on a source printed circuit board on which the data driving circuit 130 is disposed.

[0066] The level shifter 180 may convert a transistor-transistor-logic (TTL) level voltage of a timing control signal (TCS) input from the timing controller 140 into a voltage capable of switching an on level and an off level of a transistor formed on the display panel 110. Then, the level shifter 180 provides a gate control signal GCS to the gate driving circuit 120.

[0067] The timing control signal TCS may include an on-clock, an off-clock, an alternating control pulse, and the like.

[0068] The gate control signal GCS may include a gate start signal, a gate clock, an even-numbered alternating current (AC) voltage, an odd-numbered AC voltage, a line selection signal, a reset signal, and a panel turn-on signal. The gate clock may be composed of N (where N is a natural number) phase clocks having different phases. When the gate drive circuit 120 includes a scan drive circuit and an emission drive circuit, the gate start signal may include a scan start signal and an emission start signal, and the gate clock may include a scan clock and an emission clock.

[0069] For example, in a display device 100 having a resolution of 2160×3840, for 2160 gate lines GL, the case where gate signals are sequentially output from the first gate line to the 2160th gate line can be referred to as 2160-phase drive. Alternatively, the case where gate signals are sequentially output on the basis of every four gate lines GL, similar to the case where gate signals are sequentially output from the first gate line to the fourth gate line and then from the fifth gate line to the eighth gate line, is referred to as four-phase drive. In other words, the case where gate signals are sequentially output for every N gate lines GL can be referred to as N-phase drive.

[0070] When the gate driving circuit 120 includes a scan driving circuit and an emission driving circuit, the gate signal may include a scan signal and an emission signal.

[0071] Furthermore, the gate driving circuit 120 may include one or more gate driving integrated circuits GDIC.

[0072] Based on the gate control signal GCS input from the level shifter 180 and one or more power supply voltages GVDD and GVSS input from the power management circuit (not shown), the gate driving circuit 120 can output a display gate signal during a display driving period and output a sensing gate signal for sensing a characteristic value of a sub-pixel SP during a blanking period.

[0073] The gate driving circuit 120 may be directly formed on the substrate of the display panel 110 in a gate-in-panel (GIP) manner.

[0074] The gate driving circuit 120 may be formed in a border region where no image is displayed on the display panel 110, but is not limited thereto. The gate driving circuit 120 may be formed in a double bank structure, wherein a first gate driving circuit 120a is disposed in a first border region of the display panel 110, and a second gate driving circuit 120b is disposed in a second border region of the display panel 110, to minimize distortion of a gate signal due to signal delay.

[0075] The timing controller 140 may control the display driving operation and the sensing driving operation of the subpixel rows of the display panel 110 based on the source control signal SCS and the timing control signal TCS, thereby sensing the characteristic values ​​of the subpixels SP in real time even in a period of displaying an image.

[0076] Here, the sub-pixel row refers to a set of sub-pixels SP of the number of one row adjacent to each other in the horizontal direction.

[0077] The sensing driving operation refers to an operation of sensing a characteristic value of a corresponding subpixel SP by applying sensing data to the subpixel SP disposed in a specific subpixel row, and updating a compensation value for compensating for a change in the characteristic value of the corresponding subpixel SP based on the sensing result.

[0078] The display device 100 may include a power management circuit that provides various voltages or currents to the display panel 110 , the gate driving circuit 120 , the data driving circuit 130 , etc., or controls various voltages or currents to be provided.

[0079] The power management circuit generates power required to drive the display panel 110 , the gate driving circuit 120 , and the data driving circuit 130 by regulating a direct current (DC) voltage provided from an external host system.

[0080] The display device 100 may be one of various types of devices, such as a liquid crystal display, an organic light emitting diode display, or a plasma display panel.

[0081] Figure 3 is an exemplary system diagram illustrating a display device according to an embodiment of the present disclosure.

[0082] Figure 3 The following example is shown: in which, in the display device 100 according to an embodiment of the present disclosure, the data driving circuit 130 is implemented by a chip-on-film (COF) type among various types (e.g., TAB, COG, and COF), and the gate driving circuit 120 is implemented by a gate-in-panel (GIP) type among various types (e.g., TAB, COG, COF, and GIP).

[0083] When the gate driving circuit 120 is implemented in a GIP type, a plurality of gate driving integrated circuits GDICa and GDICb included in the gate driving circuit 120 may be directly formed in the bezel region of the display panel 110. In this case, the gate driving integrated circuits GDICa and GDICb may receive various signals (e.g., gate clocks, gate high signals, gate low signals, etc.) required to generate gate signals through gate driving-related signal lines provided in the bezel region.

[0084] Likewise, one or more source driver integrated circuits SDIC included in the data driver circuit 130 may be mounted on the source film SF, and one side of the source film SF may be electrically connected to the display panel 110. Signal lines for electrically connecting the source driver integrated circuits SDIC and the display panel 110 may be provided on the source film SF.

[0085] The display device 100 may include at least one source printed circuit board SPCB for circuit connection between a plurality of source driving integrated circuits SDIC and other devices, and a control printed circuit board CPCB for mounting control parts and various electrical devices.

[0086] The other side of the source film SF on which the source driver integrated circuit SDIC is mounted may be connected to at least one source printed circuit board SPCB. In other words, one side of the source film SF on which the source driver integrated circuit SDIC is mounted may be electrically connected to the display panel 110, and the other side thereof may be electrically connected to the source printed circuit board SPCB.

[0087] The timing controller 140 and the power management circuit 150 may be mounted on the control printed circuit board CPCB. The timing controller 140 may control the operations of the data driving circuit 130 and the gate driving circuit 120. The power management circuit 150 may provide a driving voltage or current to the display panel 110, the data driving circuit 130, and the gate driving circuit 120, and control the provided voltage or current.

[0088] At least one source printed circuit board SPCB and a control printed circuit board CPCB may be circuit-connected by at least one connecting member. The connecting member may include, for example, a flexible printed circuit FPC or a flexible flat cable FFC. At least one source printed circuit board SPCB and a control printed circuit board CPCB may be integrated into a single printed circuit board.

[0089] The display device 100 may further include a setting board 170 electrically connected to the control printed circuit board CPCB. In this case, the setting board 170 may also be referred to as a power distribution board. A main power management circuit 160 for managing the total power of the display device 100 may exist on the setting board 170. The main power management circuit 160 may interact with the power management circuit 150.

[0090] In the display device 100 having the above configuration, a driving voltage is generated in the setting board 170 and transmitted to the power management circuit 150 in the control printed circuit board CPCB. The power management circuit 150 transmits the driving voltage required for display driving or characteristic value sensing to the source printed circuit board SPCB through the flexible printed circuit FPC or the flexible flat cable FFC. The driving voltage transmitted to the source printed circuit board SPCB is provided to emit light or sense a specific sub-pixel SP in the display panel 110 through the source drive integrated circuit SDIC.

[0091] Each sub-pixel SP arranged in the display panel 110 in the display device 100 may include a light emitting element and a circuit element for driving an organic light emitting diode, such as a driving transistor.

[0092] The type and number of circuit elements constituting each sub-pixel SP may vary depending on the functions to be provided and the design scheme.

[0093] According to the configuration of the sub-pixel SP, the gate driving circuit 120 may be formed of a scan driving circuit that outputs a scan signal, or may include a scan driving circuit that outputs a scan signal and an emission driving circuit that outputs an emission signal.

[0094] Figure 4 is a view showing a structure of receiving an interface data signal from a host system using a low voltage differential signaling interface in a display device for a vehicle system according to an embodiment of the present disclosure.

[0095] refer to Figure 4 According to an embodiment of the present disclosure, the timing controller 140 of the display device 100 for a vehicle system may include a receiver (RX) 145 configured to receive an interface data signal IFD, and the host system 200 may include a transmitter (TX) 205 configured to transmit the interface data signal IFD.

[0096] The transmitter 205 converts the single-ended signal into an interface data signal IFD of a differential signal. The interface data signal IFD of the differential signal is transmitted to the timing controller 140 having the receiver 145 via the interface line 108 .

[0097] The interface line 108 includes two signal lines. The reception resistor Rt provided on the receiver 145 side is a terminal resistor and has a resistance value corresponding to the characteristic impedance of the interface line 108 .

[0098] The receiving resistor Rt according to the standard of the low voltage differential signaling (LVDS) interface may have a resistance value of 100Ω. The interface data signal IFD transmitted from the transmitter 205 may be a differential current having a range of ±2.5mA. When the interface data signal IFD flows through the receiving resistor Rt of 100Ω in the form of a differential current, a differential voltage signal converted within a range of 250mV (1.075V to 1.325V) is transmitted to the receiver 145.

[0099] The receiver 145 of the timing controller 140 detects the differential voltage signal and converts it into image data DATA of a single-ended signal. The image data DATA of the single-ended image data DATA generated by the receiver 145 is transmitted to the data driving circuit 130 .

[0100] Figure 5 is a view showing a waveform of an interface data signal transmitted from a host system to a display device in a vehicle system according to an embodiment of the present disclosure.

[0101] refer to Figure 5 The interface data signal IFD transmitted from the host system 200 to the display device 100 in the vehicle system 1000 according to an embodiment of the present disclosure may be a signal whose polarity is changed by a switching element of the transmitter 205 .

[0102] For example, the interface data signal IFD may include a first polarity voltage VOH swinging between 1.075V and 1.325V and a second polarity voltage VOL swinging between 1.075V and 1.325V and having an opposite phase to the first polarity voltage VOH.

[0103] Therefore, the common mode voltage Vcm of the interface data signal IFD may have a range between 1.075V and 1.325V, and may have an average value of 1.2V.

[0104] At this time, the swing margin of the output signal in the transmitter 205 may be reduced due to the parasitic resistance. Therefore, the interface data signal IFD transmitted through the interface line 108 must be able to swing with a sufficient margin within the range of 1.075V to 1.375V level. Therefore, it is desirable to minimize the parasitic resistance by making the area of ​​the receiver 145 sufficient to accurately and reliably detect the interface data signal IFD.

[0105] Meanwhile, a constant current of 2.5 mA and a receiving resistor Rt of 100 Ω can be used for the low voltage differential signaling (LVDS) interface, but it can be changed within the standard range (250 mV to 400 mV).

[0106] Figure 6 is a block diagram illustrating an example gate driving circuit including a scan driving circuit and an emission driving circuit in a display device according to an embodiment of the present disclosure.

[0107] refer to Figure 6 According to an embodiment of the present disclosure, the gate driving circuit 120 of the display device 100 may include a plurality of scan driving circuits SCD1-SCD4 that output scan signals SCAN[1]-SCAN[4] for controlling switching transistors included in a plurality of sub-pixels SP1-SP4, and a plurality of emission driving circuits EMD1-EMD4 that generate emission signals for controlling emission control transistors included in the plurality of sub-pixels SP1-SP4.

[0108] In this case, the scan driving circuit and the emission driving circuit may be collectively referred to as a gate driving integrated circuit.

[0109] When the gate driving circuit 120 is implemented in a gate-in-panel (GIP) type, the scan driving circuit SCD and the emission driving circuit EMD may be provided in a plurality of stages ST1 , ST2 , ST3 , ST4 in a bezel area of ​​the display panel 110 .

[0110] The emission driving circuit EMD may generate row emission signals EM[1], EM[2], EM[3], EM[4] by operating based on the emission clock ECLKs, the emission start signal EVST, the low potential emission voltage VEL, and the high potential emission voltage VEH.

[0111] In this case, the emission driving circuit EMD1 of the first row can generate the first row emission signal EM[1] using the emission start signal EVST, and the emission driving circuit EMD2 of the second row can generate the second row emission signal EM[2] using the first row emission signal EM[1] output from the emission driving circuit EMD1 of the first row. As described above, from the emission driving circuit EMD2 of the second row, the row emission signal generated by the front emission driving circuit can be used as the emission start signal.

[0112] The row emission signals EM[1], EM[2], EM[3], EM[4] may be provided to the display panel 110 through their respective corresponding sub-pixel rows, and each of the row emission signals EM[1], EM[2], EM[3], EM[4] may include one or more emission signals according to the structure of the sub-pixel SP.

[0113] The scan driving circuit SCD may generate row scan signals SCAN[1], SCAN[2], SCAN[3], SCAN[4] by operating based on the scan clock SCLKs, the scan start signal SVST, the low potential scan voltage VSL, and the high potential scan voltage VSH.

[0114] In this case, the scan driving circuit SCD1 of the first row can generate the first row scan signal SCAN[1] using the scan start signal SVST, and the scan driving circuit SCD2 of the second row can generate the second row scan signal SCAN[2] using the first row scan signal SCAN[1] output from the scan driving circuit SCD1 of the first row. As described above, from the scan driving circuit SCD2 of the second row, the row scan signal generated by the previous scan driving circuit can be used as the scan start signal.

[0115] The row scan signals SCAN[1], SCAN[2], SCAN[3], SCAN[4] may be provided to the display panel 110 through their respective corresponding sub-pixel rows, and each of the row scan signals SCAN[1], SCAN[2], SCAN[3], SCAN[4] may include one or more scan signals according to the structure of the sub-pixel SP.

[0116] Figure 7 is a view showing an example sub-pixel circuit in a display device according to an embodiment of the present disclosure.

[0117] refer to Figure 7 , a sub-pixel circuit of the display device 100 according to an embodiment of the present disclosure may include a light emitting element ED, a driving transistor DRT, a plurality of switching transistors T1 - T5 , and a storage capacitor Cst.

[0118] The driving transistor DRT and the plurality of switching transistors T1 - T5 included in the sub-pixel circuit may be implemented as PMOS-type low temperature polysilicon (LTPS) transistors, thereby ensuring desired response characteristics.

[0119] Alternatively, at least one of the plurality of switch transistors T1-T5 may be implemented as an NMOS type or PMOS type oxide transistor having good leakage current characteristics when turned off, and the remaining switch transistors may be implemented as PMOS type LTPS transistors having good response characteristics.

[0120] The light emitting element ED emits light by a driving current adjusted according to the gate-source voltage Vgs of the driving transistor DRT. An anode electrode of the light emitting element ED is connected to the fourth node P4, and a cathode electrode of the light emitting element ED is connected to the low potential pixel voltage EVSS.

[0121] When the light emitting element ED is an organic emission diode, an organic compound layer is provided between an anode electrode and a cathode electrode.

[0122] The organic compound layer may include a hole injection layer HIL, a hole transport layer HTL, an emission layer EML, an electron transport layer ETL, and an electron injection layer EIL. For example, two or more organic compound layers emitting light of different colors may be stacked according to a tandem structure.

[0123] When a driving current flows through the light emitting element ED, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL move to the emission layer EML to form excitons, and as a result, the emission layer EML may emit visible light.

[0124] The driving transistor DRT controls the current flowing through the light emitting element ED according to the gate-source voltage Vgs. The gate electrode of the driving transistor DRT is connected to the second node P2, the drain electrode (or source electrode) is connected to the driving voltage line providing the high potential pixel voltage EVDD, and the source electrode (or drain electrode) is connected to the third node P3.

[0125] The sub-pixel circuit may include first to fifth switching transistors T1 to T5 capable of sampling the gate-source voltage Vgs and a storage capacitor Cst for compensating for a threshold voltage or mobility of the driving transistor DRT.

[0126] The first switching transistor T1 is connected between the data line DL and the first node P1 and is switched according to the first scan signal SCAN1. The gate electrode of the first switching transistor T1 is connected to the first gate line to which the first scan signal SCAN1 is applied, the drain electrode (or source electrode) is connected to the data line DL, and the source electrode (or drain electrode) is connected to the first node P1.

[0127] The second switching transistor T2 is connected between the second node P2 and the third node P3 and is switched according to the second scan signal SCAN2. The gate electrode of the second switching transistor T2 is connected to the second gate line to which the second scan signal SCAN2 is applied, the drain electrode (or source electrode) is connected to the third node P3, and the source electrode (or drain electrode) is connected to the second node P2.

[0128] Because one electrode of the second switch transistor T2 is connected to the gate electrode of the driving transistor DRT, the second switch transistor T2 preferably has good off-current characteristics. Therefore, the second switch transistor T2 can be designed as a double-gate structure to suppress leakage current when turned off.

[0129] In the dual gate structure, the first gate electrode and the second gate electrode are connected to each other to have the same potential, and the channel length is longer than that of the single gate structure. As the channel length increases, the resistance increases, and the leakage current decreases when turned off, so that the stability of the operation can be ensured. However, the second switch transistor T2 can be implemented as a single gate structure, and in this case, the second switch transistor T2 can be implemented as an oxide transistor.

[0130] The third switching transistor T3 is connected between the first node P1 and a reference voltage line to which a reference voltage Vref is applied, and is switched according to the emission signal EM. A gate electrode of the third switching transistor T3 is connected to a third gate line to which the emission signal EM is applied, a drain electrode (or a source electrode) is connected to the first node P1, and a source electrode (or a drain electrode) is connected to the reference voltage line.

[0131] The fourth switching transistor T4 is connected between the third node P3 and the fourth node P4 which is the anode electrode of the light emitting element ED, and is switched according to the emission signal EM. The gate electrode of the fourth switching transistor T4 is connected to the third gate line to which the emission signal EM is applied, the drain electrode (or source electrode) is connected to the third node P3, and the source electrode (or drain electrode) is connected to the fourth node P4. Since the fourth switching transistor T4 controls the driving current flowing through the light emitting element ED, it can be called an emission control transistor.

[0132] The fifth switching transistor T5 is connected between the fourth node P4 and the reference voltage line and is switched according to the second scan signal SCAN2. The gate electrode of the fifth switching transistor T5 is connected to the second gate line to which the second scan signal SCAN2 is applied, the drain electrode (or source electrode) is connected to the fourth node P4, and the source electrode (or drain electrode) is connected to the reference voltage line.

[0133] The storage capacitor Cst is connected between the first node P1 and the second node P2.

[0134] The display device 100 according to the present disclosure may operate a driving circuit and a display panel using power provided from a host system.

[0135] Figure 8 is a view showing an example power waveform provided to a host system of a display device according to an embodiment of the present disclosure.

[0136] refer to Figure 8 The display device 100 according to an embodiment of the present disclosure may operate a driving circuit such as a timing controller 140 and a power management circuit 150 using a first power supply VCC provided from a host system 200 , and may drive a display panel 110 using a second power supply VDD provided from the host system 200 .

[0137] The first power VCC provided from the host system 200 to operate the driving circuits such as the timing controller 140 and the power management circuit 150 may be referred to as a circuit power supply, and the first power VCC may be 3.3 V. In addition, the second power VDD provided from the host system 200 to drive the display panel 110 may be referred to as a panel power supply, and the second power VDD may be 20 V.

[0138] In this case, in order to normally turn on the display device 100, it is preferred that the driving circuit is first operated by the first power source VCC, and after the turn-on delay time d1 has elapsed, the display panel 110 is then driven by the second power source VDD.

[0139] In addition, in order to normally shut down the display device 100, it is preferred that the second power source VDD is cut off to shut down the display panel 110, and after the shut-down delay time d2 has elapsed, the first power source VCC is cut off to shut down the driving circuit.

[0140] However, when the first power source VCC and the second power source VDD supplied from the host system 200 are abnormally cut off due to a battery failure or the like, a gate signal may be applied before the display panel 110 is turned off, so that a display error may occur.

[0141] Fig. 9 is a view illustrating an example signal error when power supplied to a host system is abnormally cut off in a display device according to an embodiment of the present disclosure.

[0142] refer to Fig. 9 In order to normally shut down the display device 100 according to an embodiment of the present disclosure, it is necessary to shut down the second power supply VDD for driving the display panel 110, and then shut down the first power supply VCC for operating the driving circuit after a predetermined shutdown delay time d2.

[0143] However, when the host system is abnormally cut off, such as when the battery power is turned off, the first power source VCC for operating the driving circuit may be cut off in a state in which the second power source VDD is turned on.

[0144] When the second power source VDD is turned on, the high potential pixel voltage EVDD for driving the display panel 110 also maintains an on state. Therefore, some of the image data DATA transmitted through the interface data signal IFD may be provided to the display panel 110.

[0145] In this case, when the gate control signal GCS provided to the gate driving circuit 120 through the level shifter 180 is cut off, a display error in which some sub-pixels SP emit light may occur due to the emission signal EM provided to the display panel 110 .

[0146] For example, when the emission control transistor ( Figure 7 When T4 in FIG. 1 is a PMOS transistor, the emission control transistor emits light by the low-level emission signal EM, and thus a display error occurs, in which a partial area of ​​the display panel 110 emits light by the low-level emission signal EM applied when the gate control signal GCS is cut off.

[0147] When the power of the host system 200 is abnormally cut off, the display device 100 according to the present disclosure detects this and cuts off the emission control transistor of the display panel 110 , thereby preventing an accident caused by a display error.

[0148] Fig.10 is a block diagram of a circuit for controlling emission of a display panel by detecting changes in circuit power and interface data signals in a display device according to an embodiment of the present disclosure.

[0149] refer to Fig.10 According to an embodiment of the present disclosure, a display device 100 may include: a converter 102, which is configured to convert a first level circuit power VCC provided from a host system 200 into a second level circuit power VCCL corresponding to the level of an interface data signal IFD; a logic gate 104, which is configured to generate a power check signal PC according to the interface data signal IFD and the second level circuit power VCCL; and a timing controller 140, which is configured to generate an emission start signal EVST for controlling the emission of the display panel 110 based on the power check signal PC.

[0150] In order to calculate the circuit power supply VCC and the interface data signal IFD in the logic gate 104, the circuit power supply VCC needs to be supplied at the same voltage level as the interface data signal IFD.

[0151] The circuit power supply VCC provided from the host system 200 is a power supply voltage for operating a driving circuit such as the timing controller 140 and the power management circuit 150, and may be 3.3 V. In contrast, in the case of a low voltage differential signaling (LVDS) interface, a common mode voltage Vcm of an interface data signal IFD transmitted through the interface line 108 may have an average value of 1.2 V.

[0152] Therefore, it is effective that the converter 102 converts the first level circuit power VCC having a relatively high level into the level of the second level circuit power VCCL which is the same as the interface data signal IFD of a low level.

[0153] At this time, when the output voltage of converter 102 suddenly increases, a voltage drop in the battery may occur due to the inrush current, which may cause malfunction of other circuits constituting vehicle system 1000. In order to reduce this problem, converter 102 may be configured with an LDO regulator (low dropout regulator) having a soft start function to smoothly change the output voltage and reduce the inrush current.

[0154] The LDO regulator can generate an output voltage having a potential level proportional to the potential level of the reference voltage. Therefore, when the reference voltage gradually increases in the form of a ramp waveform, the second level circuit power VCCL generated from the converter 102 also gradually increases to achieve soft start. The soft start time can be controlled by the slope of the reference voltage.

[0155] On the other hand, when the host system 200 is abnormally shut down, for example, when the battery power is turned off, the circuit power VCC and the interface data signal IFD for operating the driving circuit may be turned off while the panel power VDD is turned on.

[0156] Therefore, the logic gate 104 may be configured to generate the power check signal PC by detecting that the second level circuit power VCCL and the interface data signal IFD are simultaneously turned off.

[0157] Fig.11 A table showing logic gates comparing second-stage circuit power and interface data signals in a display device according to an embodiment of the present disclosure is shown.

[0158] refer to Fig.11 , the display device 100 according to an embodiment of the present disclosure can detect a situation when the circuit power VCC and the interface data signal IFD for operating the driving circuit are turned off to a low level due to the host system 200 being abnormally cut off (case 1).

[0159] Therefore, the logic gate 104 may be configured as a NOR gate that generates the power check signal PC at a high level when the circuit power supply VCC and the interface data signal IFD are at a low level.

[0160] The timing controller 140 may control the emission start signal EVST provided to the display panel 110 by using the power check signal PC generated from the logic gate 104 .

[0161] That is, when the power check signal PC at a high level is transferred from the logic gate 104 , the timing controller 140 may determine that the host system 200 is abnormally shut down and may generate the emission start signal EVST at a shut-down level for blocking emission of the display panel 110 .

[0162] At this time, the converter 102 and the logic gate 104 may be implemented together on a control printed circuit board provided with the timing controller 140 , or may be included inside the timing controller 140 in the form of an integrated circuit.

[0163] Fig.12 The waveforms of the power check signal and the transmission start signal depending on the circuit power and the interface data signal in the display device according to the embodiment of the present disclosure are shown. In addition, Fig.13 is a view showing an example screen state of a display panel when the display device is abnormally shut down.

[0164] refer to Fig.12 and Fig.13 When the display device 100 according to an embodiment of the present disclosure is normally turned off, the panel power VDD driving the display panel 110 is turned off, and after a predetermined turn-off delay time, the circuit power VCC operating the driving circuit is turned off.

[0165] However, when the host system is abnormally shut down, for example when the battery power is cut off, in a state where the high-potential pixel voltage EVDD for driving the display panel 110 is turned on, the circuit power VCC for operating the driving circuit can be reduced to a ground voltage GND less than or equal to a threshold and the interface data signal IFD transmitted through the interface line 108 can be blocked.

[0166] As described above, when the circuit power supply VCC provided from the host system is abnormally reduced, the high potential scanning voltage and the scanning start signal SVST that interact with the circuit power supply VCC may also be reduced. As a result, the PMOS type switching transistor (e.g., Figure 7 T1 and T2) can be turned on.

[0167] However, the display device 100 of the present disclosure transmits the circuit power VCC at the off level and the power check signal PC corresponding to the interface data signal IFD to the timing controller 140, and the timing controller 140 can maintain the emission start signal EVST at the off level (high level). As a result, the PMOS type emission control transistor (e.g., Figure 7 T4) to reduce display errors.

[0168] In other words, when abnormal power off occurs due to battery failure or the like, the display device 100 of the present disclosure may generate the emission start signal EVST at a turn-off level by detecting changes in the circuit power source VCC and the interface data signal IFD.

[0169] As a result, although the conventional display device 100 of the vehicle system 1000 may experience a Fig.13 The display error on the display panel 110 shown in (a) of FIG. 1 is shown in FIG. 1 , but the display device 100 according to the present disclosure can also be displayed as shown in FIG. 1 even though the circuit power supply VCC is abnormally turned off. Fig.13 (b) shows that by turning off the emission control transistor ( Figure 7 T4) to reduce display errors and accidents on the display panel 110.

[0170] The embodiments of the present disclosure described above are briefly described below.

[0171] The display device of the present disclosure may include: a display panel, the display panel including a plurality of sub-pixels; a gate driving circuit, the gate driving circuit being configured to provide a scanning signal and an emission signal to the display panel through a plurality of gate lines; a converter, the converter being configured to convert a first-level circuit power provided from a host system into a second-level circuit power; a logic gate, the logic gate being configured to generate a power check signal based on an interface data signal transmitted through an interface line and the second-level circuit power; and a timing controller, the timing controller being configured to control an emission start signal provided to the gate driving circuit according to the power check signal.

[0172] The sub-pixel includes a light-emitting element, a driving transistor that controls a current flowing to the light-emitting element according to a gate-source voltage, a first switching transistor connected between a data line and a first node and switched according to a first scanning signal, a second switching transistor connected between a second node and a third node and switched according to a second scanning signal, a third switching transistor connected between the first node and a reference voltage line and switched according to the emission signal, a fourth switching transistor connected between the third node and an anode electrode of the light-emitting element and switched according to the emission start signal, a fifth switching transistor connected between the anode electrode and the reference voltage line and switched according to the second scanning signal, and a storage capacitor connected between the first node and the second node.

[0173] The driving transistor is a PMOS type low temperature polysilicon (LTPS) transistor.

[0174] At least one of the first to fifth switch transistors is a PMOS type oxide transistor.

[0175] The gate driving circuit includes a first scanning driving circuit configured to generate a first row scanning signal using the scanning start signal, one or more subsequent scanning driving circuits configured to generate subsequent row scanning signals using the row scanning signal transmitted from the previous scanning driving circuit, a first emission driving circuit configured to generate a first emission signal using the emission start signal, and one or more subsequent emission driving circuits configured to generate subsequent emission signals using the emission signal transmitted from the previous emission driving circuit.

[0176] The first level circuit power source is a power source for driving the timing controller.

[0177] The interface data signal is a low voltage differential data signal transmitted through a low voltage differential signaling (LVDS) interface.

[0178] The second-level circuit power has the same level as a common mode voltage of the low voltage differential data signal.

[0179] The converter is an LDO regulator (low dropout regulator) with a soft-start function.

[0180] The logic gate is a NOR gate.

[0181] When the first level circuit power and the interface data signal are at a turn-off level, the emission start signal is generated at a level that turns off a display panel.

[0182] The converter, the logic gates and the timing controller are implemented on a control printed circuit board.

[0183] In addition, the vehicle system of the present disclosure may include: a display panel, the display panel including multiple sub-pixels; a gate drive circuit, the gate drive circuit being configured to provide a scan signal and an emission signal to the display panel through multiple gate lines; a converter, the converter being configured to convert a first-level circuit power provided from a host system into a second-level circuit power; a logic gate, the logic gate being configured to generate a power check signal based on an interface data signal transmitted through an interface line and the second-level circuit power; and a timing controller, the timing controller being configured to control an emission start signal provided to the gate drive circuit according to the power check signal.

[0184] The above description has been presented to enable any person skilled in the art to make and use the technical concept of the present disclosure, and the above description has been provided in the context of a specific application and its requirements. Various modifications, additions and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. The above description and accompanying drawings provide examples of the technical concept of the present disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concept of the present disclosure.

Claims

1. A display device, comprising: A display panel, the display panel comprising a plurality of sub-pixels; a gate driving circuit configured to provide a scanning signal and an emission signal to the display panel through a plurality of gate lines; a converter configured to convert a first level circuit power supplied from a host system into a second level circuit power; a logic gate configured to generate a power check signal based on an interface data signal transmitted through an interface line and the second level circuit power; as well as A timing controller is configured to control an emission start signal provided to the gate driving circuit according to the power supply check signal.

2. The display device according to claim 1, wherein: The sub-pixel comprises: Light emitting element; a driving transistor that controls a current flowing to the light emitting element according to a gate-source voltage; a first switch transistor connected between the data line and the first node and switched according to a first scan signal; a second switch transistor connected between the second node and the third node and switched according to a second scan signal; a third switch transistor, the third switch transistor being connected between the first node and a reference voltage line and being switched according to the transmission signal; a fourth switch transistor, the fourth switch transistor being connected between the third node and the anode electrode of the light emitting element and being switched according to the emission start signal; a fifth switching transistor connected between the anode electrode and the reference voltage line and switched according to the second scanning signal; and A storage capacitor is connected between the first node and the second node.

3. The display device according to claim 2, wherein: The driving transistor is a PMOS type low temperature polysilicon (LTPS) transistor.

4. The display device according to claim 2, wherein: At least one of the first to fifth switch transistors is a PMOS type oxide transistor.

5. The display device according to claim 1, wherein: The gate drive circuit comprises: a first scan driving circuit configured to generate a first row scan signal using the scan start signal; one or more subsequent scanning driving circuits configured to generate subsequent row scanning signals using the row scanning signals transmitted from the previous scanning driving circuit; a first transmit driving circuit configured to generate a first transmit signal using the transmit start signal; and One or more subsequent transmit driver circuits are configured to generate subsequent transmit signals using the transmit signal transmitted from the previous transmit driver circuit.

6. The display device according to claim 1, wherein: The first level circuit power source is a power source for driving the timing controller.

7. The display device according to claim 1, wherein: The interface data signal is a low voltage differential data signal transmitted through a low voltage differential signaling (LVDS) interface.

8. The display device according to claim 7, wherein: The second-level circuit power has the same level as a common mode voltage of the low voltage differential data signal.

9. The display device according to claim 1, wherein: The converter is an LDO regulator (low dropout regulator) with a soft-start function.

10. The display device according to claim 1, wherein: The logic gate is a NOR gate.

11. The display device according to claim 1, wherein: When the first level circuit power and the interface data signal are at an off level, the emission start signal is generated at a level that turns off the display panel.

12. The display device according to claim 1, wherein: The converter, the logic gates and the timing controller are implemented on a control printed circuit board.

13. The display device according to claim 2, wherein: The timing controller is configured to turn off the fourth switching transistor by generating the transmission start signal at a turn-off level when the host system is abnormally shut down.

14. A vehicle system comprising: A display panel, the display panel comprising a plurality of sub-pixels; a gate driving circuit configured to provide a scanning signal and an emission signal to the display panel through a plurality of gate lines; a converter configured to convert a first level circuit power supplied from a host system into a second level circuit power; a logic gate configured to generate a power check signal based on an interface data signal transmitted through an interface line and the second level circuit power; as well as A timing controller is configured to control an emission start signal provided to the gate driving circuit according to the power supply check signal.

15. The vehicle system according to claim 14, wherein: The first level circuit power source is a power source for driving the timing controller.

16. The vehicle system of claim 14, wherein: The interface data signal is a low voltage differential data signal transmitted through a low voltage differential signaling (LVDS) interface.

17. The vehicle system according to claim 16, wherein: The second-level circuit power has the same level as a common mode voltage of the low voltage differential data signal.

18. The vehicle system of claim 14, wherein: The converter is an LDO regulator (low dropout regulator) with a soft-start function.

19. The vehicle system of claim 14, wherein: The logic gate is a NOR gate.

20. The vehicle system of claim 14, wherein: When the first level circuit power and the interface data signal are at an off level, the emission start signal is generated at a level that turns off the display panel.

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