Semiconductor structure, memory system and preparation method of semiconductor structure

Abstract

The invention provides a semiconductor structure, a storage system and a preparation method of the semiconductor structure, relates to the technical field of semiconductor chips, and aims to solve the problem of complex wiring between bit lines and a sensing amplification circuit. The semiconductor structure includes a first semiconductor structure. The first semiconductor structure has a first memory region. The first semiconductor structure comprises a first bit line and a first lead-out contact positioned on one side of the first bit line; the first lead-out contact is in contact with the first bit line. At least part of the first bit line is located in the first storage area; the first lead-out contact is located in the first storage area. The semiconductor structure is applied to a storage system so as to realize data reading and writing operation.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure, a storage system, and a method for preparing the semiconductor structure. Background Art

[0002] Planar semiconductor devices (such as memory systems) are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of semiconductor devices approaches the lower limit, planar processes and manufacturing technologies become challenging and costly. 3D semiconductor device architectures can address density limitations in some planar semiconductor devices, such as flash memory devices.

[0003] 3D semiconductor devices can be formed by stacking semiconductor wafers or dies and interconnecting them vertically. Compared with conventional planar semiconductor devices, 3D semiconductor devices have smaller sizes and higher densities to achieve improved performance. Summary of the invention

[0004] Embodiments of the present disclosure provide a semiconductor structure, a storage system, and a method for manufacturing the semiconductor structure, aiming to solve the problem of complex wiring of an interconnect structure coupled to a bit line.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] In one aspect, a semiconductor structure is provided. The semiconductor structure includes a first semiconductor structure. The first semiconductor structure has a first storage area. The first semiconductor structure includes a first bit line and a first lead contact located on one side of the first bit line; the first lead contact contacts the first bit line. At least a portion of the first bit line is located in the first storage area; the first lead contact is located in the first storage area.

[0007] By arranging the first lead-out contact in the first storage area, the interconnection structure can be led out from the first lead-out contact in the first storage area, and part of the interconnection structure can connect the first lead-out contact to the circuit structure in the first storage area without winding the wire to the peripheral area. In this way, the wiring of the interconnection structure can be simplified, and the overlap of the interconnection structure coupled to the adjacent first bit line in the peripheral area and / or the storage area can be reduced, and the mutual influence can be reduced. The length of the interconnection structure can be shortened, and the number of layers of the interconnection structure can be reduced. First, it is beneficial to compress the size of the semiconductor structure in the second direction (for example, the extension direction of the first bit line) and the first direction (for example, the direction intersecting with the plane where the lateral surface of the first semiconductor structure is located); second, it can increase the flexibility of the interconnection structure when arranging; third, it can make the inductive coupling of the interconnection structure smaller, which is beneficial to improving the sensing margin.

[0008] In some embodiments, the semiconductor structure further includes a second semiconductor structure. The second semiconductor structure is located on one side of the first semiconductor structure and is connected to the first semiconductor structure. The second semiconductor structure includes a peripheral circuit. The first bit line is coupled to the peripheral circuit through the first lead contact.

[0009] In some embodiments, the peripheral circuit includes a plurality of sensing amplifier circuits. The first bit line is coupled to the sensing amplifier circuit via a first lead contact. The orthographic projection of the first storage area on the second semiconductor structure overlaps with the region where the plurality of sensing amplifier circuits are located; and the orthographic projection of the first lead contact on the second semiconductor structure is located within the overlap.

[0010] In some embodiments, there are a plurality of first lead lines, and the plurality of first lead lines are arranged in parallel. There are a plurality of first lead contacts. The first lead contacts are in contact with the first lead lines. Any two adjacent first lead contacts are staggered along the second direction, and the second direction is the extension direction of the first lead lines.

[0011] In some embodiments, two ends of the plurality of first bit lines along the second direction are flush.

[0012] In some embodiments, the first semiconductor structure also includes a plurality of first storage cells located in a first storage area; the first bit line is located on one side of the plurality of first storage cells along a first direction; wherein a projection of the first lead contact along the first direction overlaps with a projection of a first storage cell along the first direction.

[0013] In some embodiments, the first bit line is located in the first storage region.

[0014] In some embodiments, the number of first bit lines is multiple, and the multiple first bit lines include a first group of bit lines. The number of first lead contacts is multiple, and the multiple first lead contacts include a first group of lead contacts. The first group of bit lines is coupled to the sense amplifier circuit through the first group of lead contacts. The area where the sense amplifier circuit coupled to the first group of bit lines is located and the orthographic projection of the first storage area on the second semiconductor structure have a first overlapping area. The orthographic projection of the first group of lead contacts on the second semiconductor structure is located in the first overlapping area.

[0015] In some embodiments, the first semiconductor structure further includes a first interconnect layer and a second interconnect layer. The first interconnect layer is located on a side of the first lead-out contact away from the first bit line; the first interconnect layer includes a plurality of first interconnect lines; the plurality of first interconnect lines include a first group of first interconnect lines. The second interconnect layer is located on a side of the first interconnect layer away from the first lead-out contact; the second interconnect layer includes a plurality of second interconnect lines; the plurality of second interconnect lines include a first group of second interconnect lines. The first group of lead-out contacts is coupled to the sense amplifier circuit through the first group of first interconnect lines and the first group of second interconnect lines.

[0016] In some embodiments, the sensing amplifier circuit includes a first sub-sensing amplifier circuit located in the first overlap region. The first group of bit lines includes a first sub-bit line coupled to the first sub-sensing amplifier circuit. The first group of first interconnection lines coupled to the first sub-bit line and the first group of second interconnection lines coupled to the first sub-bit line have an orthographic projection on the second semiconductor structure located in the first overlap region.

[0017] In some embodiments, the sense amplifier circuit coupled to the first group of bit lines further includes a second sub-sense amplifier circuit. The first group of bit lines further includes a second sub-bit line coupled to the second sub-sense amplifier circuit. The first group of first interconnect lines coupled to the second sub-bit lines have an orthographic projection on the second semiconductor structure located in the first overlapping region. The first group of second interconnect lines coupled to the second sub-bit lines extend to within the orthographic projection of the second sub-sense amplifier circuit on the first semiconductor structure.

[0018] In some embodiments, the second interconnect layer further includes a first shielding line. The first shielding line is located between two adjacent first group second interconnecting lines coupled to the second sub-bit line. The first shielding line is coupled to the second semiconductor structure.

[0019] In some embodiments, the first semiconductor structure further has a second storage area arranged along a second direction with the first storage area, and the first semiconductor structure further includes a second group of bit lines, and a second group of lead contacts located on one side of the second group of bit lines and in contact with the second group of bit lines. At least part of the second group of bit lines is located in the second storage area; the second direction is the extension direction of the first bit lines. The second group of bit lines is coupled to the sensing amplifier circuit through the second group of lead contacts; and the second group of bit lines and the first group of bit lines are coupled to the same sensing amplifier circuit. The area where the sensing amplifier circuit coupled to the second group of bit lines is located and the orthographic projection of the second storage area on the second semiconductor structure have a second overlapping area; the orthographic projection of the second group of lead contacts on the second semiconductor structure is located in the second overlapping area.

[0020] In some embodiments, the plurality of first interconnection lines further include a second group of first interconnection lines. The plurality of second interconnection lines further include a second group of second interconnection lines. The second group of lead-out contacts are coupled to the sense amplifier circuit through the second group of first interconnection lines and the second group of second interconnection lines.

[0021] In some embodiments, the sensing amplifier circuit includes a second sub-sense amplifier circuit located in the second overlap region. The second group of bit lines includes a third sub-bit line coupled to the second sub-sense amplifier circuit. The second group of first interconnection lines coupled to the third sub-bit line and the second group of second interconnection lines coupled to the third sub-bit line are located in the second overlap region in the orthographic projection of the second semiconductor structure.

[0022] In some embodiments, the sensing amplifier circuit further includes a first sub-sense amplifier circuit located in the first overlap region. The second group of bit lines further includes a fourth sub-bit line coupled to the first sub-sense amplifier circuit. The second group of first interconnect lines coupled to the fourth sub-bit line extends to within the orthographic projection of the first overlap region on the first semiconductor structure. The second group of second interconnect lines coupled to the fourth sub-bit line has an orthographic projection on the second semiconductor structure located in the first overlap region.

[0023] In some embodiments, the first interconnect layer further includes a second shielding line. The second shielding line is located between two adjacent second group first interconnecting lines coupled to the fourth sub-bit line. The second shielding line is coupled to the second semiconductor structure.

[0024] In some embodiments, the first semiconductor structure further includes a third interconnect layer located between the first interconnect layer and the second interconnect layer. The third interconnect layer includes a plurality of interconnect contacts. The first interconnect line is coupled to the second interconnect line through the interconnect contacts.

[0025] In some embodiments, the second semiconductor structure includes a first bonding layer, the first bonding layer includes a plurality of first bonding contacts. The first semiconductor structure includes a second bonding layer, the second bonding layer includes a plurality of second bonding contacts. The second interconnect line is coupled to the sense amplifier circuit through the second bonding contacts and the first bonding contacts.

[0026] On the other hand, a storage system is provided, comprising: a semiconductor structure and a controller, wherein the semiconductor structure is the semiconductor structure described above, and the controller is coupled to the semiconductor structure to control the semiconductor structure to store data.

[0027] It can be understood that the beneficial effects that can be achieved by the storage system provided by the above embodiments of the present disclosure can be referred to the beneficial effects of the semiconductor structure described above, and will not be repeated here.

[0028] In another aspect, a method for preparing a semiconductor structure is provided, comprising forming a first semiconductor structure, wherein the first semiconductor structure has a first storage area. Forming the first semiconductor structure comprises: forming a first bit line, wherein at least a portion of the first bit line is located in the first storage area. Forming a first lead contact on one side of the first bit line; the first lead contact contacts the first bit line. The first lead contact is located in the first storage area.

[0029] It can be understood that the beneficial effects that can be achieved by the method for preparing the semiconductor structure provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor structure described above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0031] Figure 1A A top view of a first semiconductor structure provided according to some embodiments;

[0032] Figure 1B A top view of a dielectric layer provided with a bit line according to some embodiments;

[0033] Figure 1C is a cross-sectional structural diagram of a first semiconductor structure provided according to some embodiments;

[0034] Figure 2A is another top view of the first semiconductor structure provided according to some embodiments;

[0035] Figure 2B A cross-sectional structural diagram of a semiconductor structure provided according to some embodiments;

[0036] Figure 2C Another top view of the first semiconductor structure provided according to some embodiments;

[0037] Figure 2D is another cross-sectional structural diagram of a first semiconductor structure provided according to some embodiments;

[0038] Figure 2E is another cross-sectional structural diagram of a first semiconductor structure provided according to some embodiments;

[0039] Figure 3A is a structural diagram of a storage system according to some embodiments;

[0040] Figure 3B is a structural diagram of a storage system according to some other embodiments;

[0041] Figure 4 is a structural diagram of an electronic device according to some embodiments;

[0042] Figure 5A A cross-sectional structure diagram corresponding to step S1.1 in a method for preparing a semiconductor structure according to some embodiments;

[0043] Figure 5BA cross-sectional structure diagram corresponding to step S1.2 in a semiconductor structure preparation method provided according to some embodiments;

[0044] Figure 5C A cross-sectional structure diagram corresponding to steps S1.3 to S1.4 in a semiconductor structure preparation method provided according to some embodiments;

[0045] Figure 5D A cross-sectional structure diagram corresponding to step S1.5 in a semiconductor structure preparation method provided according to some embodiments;

[0046] Figure 5E A cross-sectional structure diagram corresponding to step S2 in a method for preparing a semiconductor structure provided according to some embodiments;

[0047] Fig. 5F A cross-sectional structure diagram corresponding to step S3 in a method for preparing a semiconductor structure provided according to some embodiments;

[0048] Figure 5G A cross-sectional structure diagram corresponding to step S4 in a method for preparing a semiconductor structure according to some embodiments;

[0049] Figure 6 The present invention is a flow chart of a method for preparing a first semiconductor structure according to some embodiments. DETAILED DESCRIPTION

[0050] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0051] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0052] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0053] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0054] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0055] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0056] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0057] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0058] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0059] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0060] In the context of this disclosure, the meanings of “on,” “above,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “above” or “over” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0061] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0062] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0063] The term "three-dimensional memory" refers to a semiconductor device formed by a memory cell transistor string (referred to herein as a "memory cell string", such as a NAND memory cell string) arranged in an array on a main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertical / vertically" means nominally perpendicular to the main surface (i.e., lateral surface) of the substrate or source layer.

[0064] It should be noted that the labels "A to B" appearing in the drawings mean that structure / region A belongs to structure / region B, that is, the structure referred to by the labels is both structure A and structure B. For example, Figure 2BThe "233-231" in the figure means that the structure indicated by the reference numeral is the second electrode 233, and the second electrode 233 belongs to the storage capacitor 231. The reference numeral "A / B" in the figure means that the structure / region A and the structure / region B can be referred to by the same structure / region, for example, Figure 2D The “ 261 / 214 ” in the figure means that both the first group of first interconnection lines 261 and the first interconnection lines 214 can be referred to by this structure.

[0065] As used in the present disclosure, whether a component (e.g., layer, structure, or device) is "on," "over," or "under" another component (e.g., layer, structure, or device) of a semiconductor device (e.g., semiconductor structure) is determined relative to a substrate of the semiconductor device in a first direction X when the substrate is located in the lowest plane of the semiconductor device in the first direction X. The same concept is applied throughout the present disclosure to describe spatial relationships.

[0066] In some semiconductor structures, a first semiconductor structure including a memory cell and a second semiconductor structure including a peripheral circuit are stacked to save wafer area and increase memory cell density. For example, direct bonding technology has been proposed to manufacture some three-dimensional NAND memory devices (e.g., having 96 layers or more) by bonding peripheral devices and memory cells on different substrates in a face-to-face manner.

[0067] Among them, the peripheral circuit includes a plurality of sensing amplifier circuits. Sensing amplifier circuits are widely used in storage devices, especially as an important component of volatile memories such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory). The sensing amplifier circuit can be composed of cross-coupled transistors, and its function is to use the principle of differential amplification to sense and amplify the small voltage changes on the target bit line, thereby realizing operations such as signal reading, writing and refreshing.

[0068] Figure 1A FIG. 1 is a possible layout diagram of the lead-out contacts 112 contacting the bit lines 111 in some implementation modes. Figure 1B FIG. 1 is a possible top view of the dielectric layer 101 with the bit line 111 formed thereon in some implementation modes. Figure 1C FIG. 1 is a possible layout diagram of the interconnection structure between the bit line 111 and the sense amplifier circuit in some embodiments. Figure 1A to Figure 1CIn the figure, the first direction X is a direction intersecting with the plane where the lateral surface of the first semiconductor structure 110 is located; the first direction X is, for example, a direction perpendicular to the plane where the lateral surface of the first semiconductor structure 110 is located. The second direction Y intersects with the third direction Z, and the second direction Y and the third direction Z are, for example, two orthogonal directions in the plane where the lateral surface of the first semiconductor structure 110 is located: the second direction Y is, for example, an extension direction of the bit line 111, and the third direction Z is, for example, an extension direction of the word line 113. Moreover, for a clearer description, Figure 1C It is a structural diagram when a plurality of bit lines 111 and a first interconnection line 114 , a second interconnection line 115 and a third interconnection line 116 located on one side of the plurality of bit lines 111 are arranged in the same cross section.

[0069] In some implementations, reference Figure 1A to Figure 1B , the first semiconductor structure 110 includes a storage area 102 and a peripheral area 103; a storage unit (not shown in the figure) is located in the storage area 102. The lead-out contact 112 in contact with the bit line 111 is located in the peripheral area 103 and does not overlap with the storage area 102. In this case, when it is necessary to connect the bit line 111 to a circuit structure (for example, a sensing amplifier circuit) or a device structure through an interconnection structure, the interconnection structure needs to be led out from the lead-out contact 112 located in the peripheral area 103, and cannot be led out from the storage area 102. In this way, the interconnection structure wiring is more complicated, and the interconnection structures of adjacent bit lines 111 overlap in the peripheral area 103 and / or the storage area 102, affecting each other, so that the length of the interconnection structure is longer and the number of layers is more. In this way, on the one hand, since the lead contact 112 is located in the peripheral area 103, the bit line 111 needs to extend to the peripheral area 103, which is not conducive to the compression of the size of the semiconductor structure 100 in the second direction Y; on the other hand, due to the large number of layers, the interconnection structure occupies more space in the first direction X, which is not conducive to the compression of the size of the semiconductor structure 100 in the first direction X.

[0070] For example, refer to Figure 1C The orthographic projection of the region where the sensing amplifier circuit is located on the first semiconductor structure 110 is as follows: Figure 1C As shown in the dashed box 106, the area where the contacts (not shown in the figure) where the interconnect structure is coupled to the sensing amplifier circuit can be divided into a first sub-area and a second sub-area. The orthographic projection of the first sub-area on the first semiconductor structure 110 is shown in FIG. Figure 1C As shown in the dashed box 104, the orthographic projection of the second sub-region on the first semiconductor structure 110 is as follows: Figure 1CAs shown in the dashed box 105. It is worth noting that the orthographic projection of the first sub-region on the first semiconductor structure 110 and the orthographic projection of the second sub-region on the first semiconductor structure 110 are both located in the storage area 102. Since the lead-out contact 112 is located in the peripheral area 103 and does not overlap with the storage area 102, when it is necessary to connect the bit line 111 to the sense amplifier circuit, the interconnection structure between the bit line 111 and the sense amplifier circuit is relatively complex, for example, the interconnection structure includes a first interconnection line 114, a second interconnection line 115 and a third interconnection line 116. Figure 1C From the wiring of the first interconnection line 114, the second interconnection line 115 and the third interconnection line 116, it can be seen that the interconnection structures of adjacent bit lines 111 overlap in the peripheral area 103 and / or the storage area 102 and affect each other, so that the length of the interconnection structure is longer and the number of layers is larger, which is not conducive to the compression of the size of the semiconductor structure 100 in the first direction X and the second direction Y.

[0071] Based on this, some embodiments of the present disclosure provide a semiconductor structure, a storage system, and a method for preparing a semiconductor structure to overcome the above problems. The semiconductor structure, the storage system, and the method for preparing a semiconductor structure provided by some embodiments of the present disclosure are introduced below. The semiconductor structure can be a memory or a part of a memory.

[0072] Figure 2A A possible arrangement diagram of the first lead-out contact 212 in some embodiments of the present disclosure; Figure 2B A cross-sectional structural diagram of a semiconductor structure 200 provided for some embodiments of the present disclosure. The semiconductor structure 200 includes a first semiconductor structure 210, the first semiconductor structure 210 has a first storage area 220, the first semiconductor structure 210 includes a first bit line 211, and a first lead contact 212 located on one side of the first bit line 211; the first lead contact 212 contacts the first bit line 211. At least a portion of the first bit line 211 is located in the first storage area 220; the first lead contact 212 is located in the first storage area 220.

[0073] Here, at least a portion of the first bit line 211 is located in the first storage area 220, which means that at least a portion of each first bit line 211 is located in the first storage area 220. In some examples, a portion of the first bit line 211 is located in the first storage area 220, and another portion extends to the peripheral area 203. In other examples, the first bit line 211 is located in the first storage area 220 and does not extend to the peripheral area 203. It should be understood that when at least a portion of the first bit line 211 is located in the first storage area 220, the first bit line 211 can be coupled to a structure in the first storage area 220 (for example, the first storage unit 217 described in detail below).

[0074] In some examples, reference Figure 2A The first semiconductor structure 210 includes a storage area 202 and a peripheral area 203; the first storage area 220 belongs to the storage area 202. A portion of the first lead-out contact 212 is located in a first storage sub-area 220A in the first storage area 220, and another portion is located in a second storage sub-area 220B in the first storage area 220. Moreover, the first storage sub-area 220A and the second storage sub-area 220B do not overlap with the peripheral area 203.

[0075] It can be understood that, based on the above structure, when it is necessary to connect the first bit line 211 to a circuit structure (e.g., a sensing amplifier circuit) or a device structure through the interconnection structure 235, the interconnection structure 235 can be led out from the first lead-out contact 212 located in the first storage area 202. In this way, compared with some implementations in which the first lead-out contact 112 is located in the peripheral area 103 of the first semiconductor structure 110 (see Figure 1C ), part of the interconnect structure 235 can connect the first lead contact 212 to the circuit structure in the first storage area 220 without winding to the peripheral area 203, which can simplify the wiring of the interconnect structure 235, reduce the overlap of the interconnect structure 235 coupled to the adjacent first bit line 211 in the peripheral area 203 and / or the storage area 202, reduce mutual influence, shorten the length of the interconnect structure 235, and reduce the number of layers of the interconnect structure 235. First, it is beneficial to compress the size of the semiconductor structure 200 in the second direction Y and the first direction X; second, it can increase the flexibility of the layout of the interconnect structure 235; third, it can make the inductive coupling of the interconnect structure 235 smaller, which is beneficial to improve the sensing margin.

[0076] In some embodiments, the first semiconductor structure 210 further includes a semiconductor layer 221, and the first storage region 220 is located in the semiconductor layer 221. Exemplarily, the material of the semiconductor layer 221 may include silicon, such as amorphous silicon, polycrystalline silicon, or single crystal silicon.

[0077] In some embodiments, reference Figure 2B The first semiconductor structure 210 further includes a plurality of first storage units 217 located in the first storage area 220 , and the plurality of first storage units 217 may be arranged in an array. Figure 2B FIG. 4 shows a cross-sectional structure of a plurality of first storage units 217 arranged along the second direction Y. FIG.

[0078] In some examples, reference Figure 2B, the first storage unit 217 includes a first type transistor 223. In the case where a plurality of first storage units 217 can be arranged in an array, the first type transistor 223 is arranged in an array. Each first type transistor 223 includes a channel portion 224, a source 225, a drain 226 and a gate 227. The source 225 and the drain 226 are respectively located at opposite ends of the channel portion 224 along the thickness direction of the first semiconductor structure 210; the gate 227 is located on one side of the channel portion 224.

[0079] In practical applications, the first type of transistor 223 has a vertical channel or a vertical channel (i.e., the channel portion 224). The source 225 is located at the first end of the channel portion 224, and the drain 226 is located at the second end of the channel portion 224. The first end and the second end are respectively two opposite ends of the channel portion 224 along the thickness direction of the first semiconductor structure 210. Moreover, the positions of the source 225 and the drain 226 are interchangeable, that is, the first end and the second end are respectively two opposite ends of the channel portion 224 in the thickness direction of the first semiconductor structure 210 that can be interchanged.

[0080] For example, the thickness direction of the first semiconductor structure 210 may be Figure 2B The channel portion 224 , the source electrode 225 , and the drain electrode 226 may be arranged along the first direction X.

[0081] In practical applications, the first type of transistor 223 can be an N-type transistor or a P-type transistor. When the first type of transistor 223 is an N-type transistor, the doping types of the source 225 and the drain 226 are both N-type doping. When the first type of transistor 223 is a P-type transistor, the doping types of the source 225 and the drain 226 are both P-type doping.

[0082] By way of example, the material of the gate 227 includes, but is not limited to, polysilicon, a conductive metal, or a conductive alloy. The conductive metal may include tungsten or copper, etc. The material of the channel portion 224 may include, for example, polysilicon.

[0083] In some examples, reference Figure 2B , two adjacent first-type transistors 223 are symmetrically arranged along the second direction Y. When the channel portions 224 of two adjacent first-type transistors 223 are located on opposite sides, the channel portions 224 of the two first-type transistors 223 are separated by the first dielectric layer 228. Exemplarily, the material of the first dielectric layer 228 includes but is not limited to silicon oxide.

[0084] In some embodiments, reference Figure 2BA gate oxide layer 230 is further provided between the gate 227 and the channel portion 224 for electrically isolating the channel portion 224 from the gate 227. Here, the material of the gate oxide layer 230 may include but is not limited to silicon oxide. Specifically, the gate oxide layer 230 may be used to sense different electric fields and apply them to the surface of the channel portion 224, so that the minority carriers of the semiconductor layer 221 are adsorbed to the surface of the channel portion 224 and accumulated and inverted, so that the gate oxide layer 230 may become the same as the source 225 and the drain 226, thereby achieving conduction between the source 225 and the drain 226.

[0085] In some embodiments, reference Figure 2B , the first bit line 211 is coupled to the drain 226 of a row of first type transistors 223 arranged along the second direction Y. Moreover, the first storage unit 217 further includes a storage capacitor 231, a second electrode 233 of the storage capacitor 231 is coupled to the peripheral circuit 281, a first electrode of the storage capacitor 231 is coupled to the source 225 of the first type transistor 223, and the storage capacitor 231 is used to store data written into the first storage unit 217.

[0086] Exemplarily, the material of the first electrode may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The material of the second electrode 233 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof.

[0087] In some examples, reference Figure 2B , the source 225 of the first type transistor 223 is reused as the first electrode of the storage capacitor 231; in other examples, the first electrode of the storage capacitor 231 is coupled to the source 225 through a storage capacitor contact (not shown in the figure). In some examples, multiple storage capacitors 231 share a second electrode 233. In some examples, a dielectric layer 234 is provided between the first electrode and the second electrode 233.

[0088] In practical applications, the storage capacitor 231 can have a variety of structures. In some embodiments, the storage capacitor 231 can be a cup-shaped, cylindrical or pillar-shaped capacitor. In other words, the storage capacitor 231 can be any one of a cup-shaped capacitor, a cylindrical capacitor and a pillar-shaped capacitor. Among them, the cup-shaped capacitor, the cylindrical capacitor and the pillar-shaped capacitor all include a bottom electrode, a top electrode and a dielectric layer located between the bottom electrode and the top electrode.

[0089] Based on the above structure, the working process of the first storage unit 217 can be: the drain 226 of the first type transistor 223 is coupled to the first bit line 211, the source 225 of the first type transistor 223 is coupled to the first electrode of the storage capacitor 231, and the gate 227 of the first type transistor 223 is coupled to the word line (WL, Word Line); the first type transistor 223 is controlled to be turned on or off by applying a voltage through the word line, and the first bit line 211 is used to perform a read or write operation on the first type transistor 223 when the first type transistor 223 is turned on.

[0090] In order to make the above-mentioned working process controllable, in addition to being coupled to the drains 226 of the corresponding multiple first-type transistors 223, the first bit line 211 is also coupled to the circuit structure (for example, the sensing amplifier circuit described in detail below) through the first lead contact 212 and the interconnection structure 235 to realize the transmission of signals (for example, sensing signals).

[0091] In some examples, reference Figure 2B , the first semiconductor structure 210 also includes a front interconnect layer 222 located on a side of the first bit line 211 away from the first storage area 220. The above-mentioned first lead contact 212 and the interconnect structure 235 may be located on the front interconnect layer 222. Exemplarily, the front interconnect layer 222 may include a plurality of interlayer dielectric (ILD) layers (also referred to as "intermetal dielectric (IMD) layers") and one or more redistribution layers on the ILD layer. The ILD layer may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant (low-k) dielectric, or any combination thereof. The redistribution layer may include a conductive material, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof. Although in Figure 2B Although not shown in the figure, it should be understood that the redistribution layer can be patterned to form various types of interconnect structures, for example, Figure 2B The first lead contact 212 may be formed by forming a plurality of through contact holes on the ILD layer (e.g., one or more) and filling the contact holes with one or more conductive materials. Exemplarily, the first lead contact 212 includes one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN). In some embodiments, the first lead contact 212 also includes an insulator (e.g., a dielectric layer) to electrically insulate the first lead contact 212 from the ILD layer.

[0092] In some embodiments, reference Figure 2BThe semiconductor structure 200 further includes a second semiconductor structure 280. The second semiconductor structure 280 is located at one side of the first semiconductor structure 210 and is connected to the first semiconductor structure 210. The second semiconductor structure 280 includes a peripheral circuit 281. The first bit line 211 is coupled to the peripheral circuit 281 through a first lead contact 212.

[0093] In some embodiments, reference Figure 2B The second semiconductor structure 280 further includes a substrate 282, and the peripheral circuit 281 is located on the substrate 282. The first semiconductor structure 210 is connected to the second semiconductor structure 280, and the connection method may be bonding, for example.

[0094] The material of the substrate 282 may be, for example, single crystal silicon, or other suitable materials, such as silicon germanium, germanium, or silicon-on-insulator film.

[0095] The peripheral circuit 281 is configured to control and sense the first semiconductor structure 210. The peripheral circuit 281 may be any suitable digital, analog, and / or mixed signal control and sensing circuit for supporting the operation (or work) of the first semiconductor structure 210, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuit 281 may also include any other circuit compatible with advanced logic processes, including logic circuits (e.g., Programmable Logic Device, PLD for short, processors and programmable logic devices), or storage circuits (e.g., Static random-Access Mmemory, SRAM for short, static random access memory).

[0096] Reference Figure 2B , the peripheral circuit 281 may include a second type of transistor 283 (e.g., a plurality of transistors) formed on a substrate 282. All or a portion of the second type of transistor 283 is formed in the substrate 282 (e.g., below the top surface of the substrate 282) and / or directly on the substrate 282. An isolation region 284 (e.g., a region where the shallow trench isolation 285 is located) and a doped region 286 (e.g., a source region and a drain region of the second type of transistor 283) may also be formed on the substrate 282.

[0097] In some embodiments, reference Figure 2B, the semiconductor structure 200 further includes a peripheral interconnect layer 236 located on one side of the semiconductor layer 221. The peripheral interconnect layer 236 may include one or more ILD layers located on the first semiconductor structure 210 and one or more redistribution layers on the ILD layer. Figure 2B Although not shown in the figure, it should be understood that the redistribution layer can be patterned to form various types of peripheral interconnect structures, for example, Figure 2B In some examples, the peripheral interconnect layer 236 may further include a passivation layer 232 located on a side of the peripheral interconnect layer 236 away from the first semiconductor structure 210 , and the passivation layer 232 serves as an outermost layer for passivating and protecting the semiconductor structure 200 .

[0098] It is understandable that when the first bit line 211 is coupled to the peripheral circuit 281 through the first lead contact 212, the peripheral circuit 281 can control and sense the first bit line 211 to achieve the purpose of controlling and sensing the first semiconductor structure 210. For example, the peripheral circuit 281 can sense a small voltage change on the target bit line and amplify it, thereby achieving operations such as signal reading, writing, and refreshing.

[0099] Exemplarily, the first lead contact 212 and the peripheral circuit 281 may be coupled via an interconnection structure 235 . The arrangement of the interconnection structure 235 may be set according to actual needs, and the embodiments of the present disclosure do not specifically limit this.

[0100] In some embodiments, reference Figure 2B , the peripheral circuit 281 includes a plurality of sense amplifier circuits 287. The first bit line 211 is coupled to the sense amplifier circuit 287 via the first lead contact 212. The orthographic projection of the first storage area 220 on the second semiconductor structure 280 overlaps with the region where the plurality of sense amplifier circuits 287 are located; the orthographic projection of the first lead contact 212 on the second semiconductor structure 280 is located in the overlap region.

[0101] Exemplarily, the sensing amplifier circuit 287 includes a plurality of second-type transistors 283 , and the sensing amplifier circuit 287 can be configured to sense and amplify small voltage changes on the target bit line using the principle of differential amplification, thereby realizing operations such as signal reading, writing, and refreshing.

[0102] In some examples, reference Figure 2A, the overlapping region includes a first overlapping region and a third overlapping region arranged along the second direction Y, the orthographic projection of the overlapping region on the first semiconductor structure 210 is shown as 206 in the figure, the orthographic projection of the first overlapping region on the first semiconductor structure 210 is shown as the dotted box 204 in the figure, and the orthographic projection of the third overlapping region on the first semiconductor structure 210 is shown as the dotted box 207 in the figure, and the first lead contact 212 is located within the orthographic projection 206 of the overlapping region on the first semiconductor structure 210, that is, the orthographic projection of the first lead contact 212 on the second semiconductor structure 280 is located within the overlapping region. It should be understood that in this case, the first storage sub-region 220A described above can overlap with the orthographic projection 204 of the first overlapping region on the first semiconductor structure 210, and the second storage sub-region 220B described above can overlap with the orthographic projection 207 of the third overlapping region on the first semiconductor structure 210.

[0103] It should be noted that Figure 2A 2 shows that the lead-out contact of the word line 213 is located outside the first storage area 220. In practical applications, the lead-out contact of the word line 213 can be located outside the first storage area 220 or inside the first storage area 220, which is not limited here.

[0104] It can be understood that when the orthographic projection of the first lead contact 212 on the second semiconductor structure 280 is located in the overlapping area, the first lead contact 212 is directly opposite to the area where the sensing amplifier circuit 287 is located. In this way, the wiring of the interconnection structure 235 can be simplified, the length of the interconnection structure 235 can be shortened, and the number of layers of the interconnection structure 235 can be reduced. First, it is conducive to the compression of the size of the semiconductor structure 200 in the second direction Y and the first direction X; second, it can increase the flexibility of the arrangement of the interconnection structure 235; third, it can make the inductive coupling of the interconnection structure 235 smaller, which is conducive to improving the sensing margin. Moreover, when the first lead contact 212 is coupled to the sensing amplifier circuit 287 directly opposite to it, the first lead contact 212 and the sensing amplifier circuit 287 can be coupled through a shorter interconnection structure 235 and a fewer number of interconnection structures 235, which further improves the feasibility of compressing the size of the semiconductor structure 200 in the second direction Y and the first direction X, and is conducive to improving the sensing margin.

[0105] In some embodiments, reference Figure 2A The number of the first bit lines 211 is multiple, and the multiple first bit lines 211 are arranged in parallel. The number of the first lead contacts 212 is multiple. The first lead contacts 212 are in contact with the first bit lines 211. Any two adjacent first lead contacts 212 are staggered along the second direction Y, and the second direction Y is the extension direction of the first bit lines 211.

[0106] In some examples, reference Figure 2A, the first bit line 211 and the first lead contact 212 may be in one-to-one contact. In other examples, one first bit line 211 may be in contact with a plurality of first lead contacts 212. In still other embodiments, the first bit line 211 is not provided with a first lead contact 212 in contact with the first bit line 211, and in this case, the first bit line 211 is a virtual bit line. In other words, the manner in which the first lead contact 212 and the first bit line 211 are in corresponding contact may be set according to actual needs, and the embodiments of the present disclosure do not specifically limit this.

[0107] It is understandable that when any two adjacent first lead contacts 212 are staggered along the second direction Y, the distribution integration of the first lead contacts 212 in the third direction Z can be reduced, and the inductive coupling between adjacent first lead contacts 212 and adjacent interconnect structures 235 can be reduced.

[0108] It should be noted that any two adjacent first lead-out contacts 212 are staggeredly arranged along the second direction Y, which means that any two adjacent first lead-out contacts 212 are not directly opposite in the third direction Z.

[0109] In some implementations, reference Figure 1B , a portion (e.g., odd-numbered bit lines 111) of the plurality of bit lines 111 coupled to the plurality of memory cells in the same memory area extend to the peripheral area 103 on one side of the memory area, and another portion (e.g., even-numbered bit lines 111) extend to the peripheral area 103 on the other side of the memory area (not shown in the figure). In this case, the two ends of the plurality of bit lines 111 along the second direction Y are not flush.

[0110] Figure 2C The arrangement diagram of the plurality of first bit lines 211 provided in some embodiments of the present disclosure. Both ends of the plurality of first bit lines 211 along the second direction Y are flush.

[0111] It is understandable that when the first bit lines 211 are aligned at both ends along the second direction Y, the space occupied by the first bit lines 211 is smaller in the second direction Y, which is beneficial to compressing the size of the semiconductor structure 200 in the second direction Y.

[0112] In some embodiments, reference Figure 2B The first semiconductor structure 210 also includes a plurality of first storage units 217 located in the first storage area 220; the first bit line 211 is located on one side of the plurality of first storage units 217 along the first direction X; wherein the projection of the first lead contact 212 along the first direction X overlaps with the projection of a first storage unit 217 along the first direction X.

[0113] It can be understood that, based on the above structure, when it is necessary to connect the first bit line 211 to a circuit structure (for example, a sensing amplifier circuit) or a device structure through the interconnection structure 235, the interconnection structure 235 can be led out from the first lead contact 112 located on one side of the first storage unit 217. This is beneficial to the compression of the size of the semiconductor structure 200 in the second direction Y and the first direction X; at the same time, it can increase the flexibility of the arrangement of the interconnection structure 235; and it can make the inductive coupling of the interconnection structure 235 smaller, which is beneficial to improve the sensing margin.

[0114] In some embodiments, reference Figure 2B and Figure 2C , the first bit line 211 is located in the first storage area 220 .

[0115] It can be understood that when the first bit line 211 is located in the first storage area 220, it can avoid occupying additional space in the peripheral area 203. In this way, the size of the peripheral area 203 adjacent to the first storage area 220 in the second direction Y can be reduced, which is beneficial to the compression of the size of the semiconductor structure 200 in the second direction Y.

[0116] In some examples, when the plurality of bit lines 111 extend to the peripheral region 103 (see Figure 1B ), the size of the peripheral region 103 adjacent to the first storage region 220 in the second direction Y is 1.38 μm. When the first bit lines 211 are all located in the storage region 202 (refer to Figure 2C ), the size of the peripheral area 203 adjacent to the first storage area 220 in the second direction Y is 1.18 μm. It can be seen that through the above configuration, the size of the peripheral area 203 adjacent to the first storage area 220 in the second direction Y can be reduced by 0.20 μm.

[0117] Figure 2D A layout diagram of an interconnection structure 235 between a first bit line 211 and a sense amplifier circuit 287 provided for some embodiments of the present disclosure. The number of first bit lines 211 is multiple, and the multiple first bit lines 211 include a first group of bit lines 241. The number of first lead contacts 212 is multiple, and the multiple first lead contacts 212 include a first group of lead contacts 251. The first group of bit lines 241 is coupled to the sense amplifier circuit 287 through the first group of lead contacts 251. The area where the sense amplifier circuit 287 coupled to the first group of bit lines 241 is located and the orthographic projection of the first storage area 220 on the second semiconductor structure 280 have a first overlapping area. The orthographic projection of the first group of lead contacts 251 on the second semiconductor structure 280 is located in the first overlapping area.

[0118] In some examples, the first group of bit lines 241 may include a plurality of odd-numbered first bit lines 211; in other examples, the first group of bit lines 241 may include a plurality of even-numbered first bit lines 211; in still other examples, the first group of bit lines 241 may be a portion of the first bit lines 211 selected in other ways. In other words, the first group of bit lines 241 is a portion of the plurality of first bit lines 211, and the screening method of the first group of bit lines 241 may be set according to actual needs, and the embodiments of the present disclosure do not specifically limit this.

[0119] Figure 2E A layout diagram of the interconnection structure 235 between the first bit line 211 and the sense amplifier circuit 287 provided for some embodiments of the present disclosure. The first group of bit lines 241 includes a plurality of odd-numbered first bit lines 211; in this case, the plurality of first bit lines 211 also includes a third group of bit lines 243, the third group of bit lines 243 includes a plurality of even-numbered first bit lines 211, and the third group of bit lines 243 is coupled to the sense amplifier circuit 287 through a third group of lead-out contacts 253. In other words, the first group of bit lines 241 and the third group of bit lines 243 are arranged alternately. In this way, the first group of lead-out contacts 251 coupled to the first group of bit lines 241 and the interconnection structure 235, and the third group of lead-out contacts 253 coupled to the third group of bit lines 243 and the interconnection structure 235 can be arranged in an alternating manner; in this way, the flexibility of the arrangement of the first lead-out contacts 212 and the interconnection structure 235 can be increased; at the same time, the inductive coupling of the interconnection structure 235 can be made smaller, which is conducive to improving the sensing margin.

[0120] In some examples, reference Figure 2A and Figure 2E , the orthographic projection of the first storage area 220 on the second semiconductor structure 280 overlaps with the areas where the two sensing amplifier circuits are located. Among them, the orthographic projection of the first storage area 220 on the second semiconductor structure 280 has a first overlapping area with the area where the first sensing amplifier circuit (the sensing amplifier circuit coupled to the first group of bit lines 241) is located, and has a third overlapping area with the area where the second sensing amplifier circuit (the sensing amplifier circuit coupled to the third group of bit lines 243) is located. The orthographic projection of the first group of lead-out contacts 251 on the second semiconductor structure 280 is located in the first overlapping area, that is, the orthographic projection of the first group of lead-out contacts 251 on the first semiconductor structure 210 (such as Figure 2A and Figure 2E The orthographic projection of the third group of lead-out contacts 253 on the second semiconductor structure 280 is located in the third overlapping region, that is, the orthographic projection of the third group of lead-out contacts 253 on the first semiconductor structure 210 is located in the third overlapping region (as shown in the dashed box 204). Figure 2A and Figure 2E (shown in the dashed box 207).

[0121] It can be understood that when the orthographic projection of the first group of lead-out contacts 251 on the second semiconductor structure 280 is located within the first overlapping region, the first group of lead-out contacts 251 and a portion of the sensing amplifier circuit 287 (for example, the first sensing amplifier circuit) coupled thereto are directly opposite to each other along the first direction X; in this way, at least a portion of the first group of lead-out contacts 251 can be coupled to the sensing amplifier circuit 287 through a shorter interconnection structure 235 and an interconnection structure 235 with fewer layers, further improving the feasibility of compressing the size of the semiconductor structure 200 in the second direction Y and the first direction X, and at the same time helping to improve the sensing margin.

[0122] In some embodiments, reference Figure 2D The first semiconductor structure 210 further includes a first interconnection layer 260 and a second interconnection layer 270. The first interconnection layer 260 is located on a side of the first lead-out contact 212 away from the first bit line 211; the first interconnection layer 260 includes a plurality of first interconnection lines 214; the plurality of first interconnection lines 214 include a first group of first interconnection lines 261. The second interconnection layer 270 is located on a side of the first interconnection layer 260 away from the first lead-out contact 212; the second interconnection layer 270 includes a plurality of second interconnection lines 215; the plurality of second interconnection lines 215 include a first group of second interconnection lines 271. The first group of lead-out contacts 251 is coupled to the sense amplifier circuit 287 through the first group of first interconnection lines 261 and the first group of second interconnection lines 271.

[0123] It can be understood that when the first group of lead-out contacts 251 is coupled to the sense amplifier circuit 287 through the first group of first interconnection lines 261 and the first group of second interconnection lines 271, the number of layers of the interconnection structure 235 coupled to the first group of lead-out contacts 251 is two layers, compared with the interconnection structure between the bit line 111 and the sense amplifier circuit in some implementations including the first interconnection line 114, the second interconnection line 115 and the third interconnection line 116 (see Figure 1C ), the number of layers of the interconnect structure 235 can be reduced, which is beneficial to the compression of the size of the semiconductor structure 200 in the first direction X.

[0124] Exemplarily, the first group of lead-out contacts 251 and the first group of first interconnection lines 261, and / or the first group of first interconnection lines 261 and the first group of second interconnection lines 271, and / or the first group of second interconnection lines 271 and the sensing amplifier circuit 287 can be coupled by direct contact or by indirect connection, which can be set according to actual needs, and the embodiments of the present disclosure do not specifically limit this.

[0125] Exemplarily, the material of the first interconnection line 214 may include a conductive material, and the material of the second interconnection line 215 may include a conductive material, the conductive material including but not limited to W, Co, Cu, Al, silicide, or any combination thereof.

[0126] In some embodiments, reference Figure 2D The sensing amplifier circuit includes a first sub-sensing amplifier circuit located in the first overlapping region. The first group of bit lines 241 includes a first sub-bit line 241A coupled to the first sub-sensing amplifier circuit. The first group of first interconnection lines 261 coupled to the first sub-bit line 241A and the first group of second interconnection lines 271 coupled to the first sub-bit line 241A have an orthographic projection on the second semiconductor structure 280 located in the first overlapping region.

[0127] In order to more clearly describe the location of the first overlapping region and / or the region where the first sub-sense amplifier circuit is located in some embodiments, the following is used: Figure 2D The dashed box 204 in the figure represents the orthographic projection of the first overlapping region and / or the region where the first sub-sense amplifier circuit is located on the first semiconductor structure 210 .

[0128] It can be understood that when the orthographic projections of the first group of first interconnection lines 261 coupled to the first sub-bit line 241A and the first group of second interconnection lines 271 coupled to the first sub-bit line 241A on the second semiconductor structure 280 are both located in the first overlapping region, the interconnection structure 235 between the first sub-bit line 241A and the first sub-sensing amplifier circuit can be simplified, and the first sub-bit line 241A can be coupled to the first sub-sensing amplifier circuit through a shorter interconnection structure 235 and an interconnection structure 235 with fewer layers, which can improve the feasibility of compressing the size of the semiconductor structure 200 in the second direction Y and the first direction X, and at the same time can improve the sensing margin.

[0129] In some embodiments, reference Figure 2D , the sense amplifier circuit coupled to the first group of bit lines 241 further includes a second sub-sense amplifier circuit. The first group of bit lines 241 further includes a second sub-bit line 241B coupled to the second sub-sense amplifier circuit. The first group of first interconnection lines 261 coupled to the second sub-bit line 241B, the orthographic projection on the second semiconductor structure 280, is located in the first overlapping region. The first group of second interconnection lines 271 coupled to the second sub-bit line 241B extends to within the orthographic projection of the second sub-sense amplifier circuit on the first semiconductor structure 210.

[0130] In order to more clearly describe the location of the second sub-sense amplifier circuit in some embodiments, the Figure 2DThe dashed box 205 represents the positive projection of the area where the second sub-sensing amplifier circuit is located on the first semiconductor structure 210. It should be understood that the first sub-sensing amplifier circuit and the second sub-sensing amplifier circuit are arranged along the second direction Y.

[0131] For example, the first sub-bit line 241A and the second sub-bit line 241B are arranged alternately. In this way, the first group of lead-out contacts 251 and the interconnection structure 235 coupled to the first sub-bit line 241A and the first group of lead-out contacts 251 and the interconnection structure 235 coupled to the second sub-bit line 241B can be arranged in a staggered manner, so that the flexibility of the arrangement of the first group of lead-out contacts 251 and the interconnection structure 235 can be increased; at the same time, the inductive coupling of the interconnection structure 235 can be reduced, which is conducive to improving the sensing margin.

[0132] It can be understood that when the orthographic projection of the first group of first interconnection lines 261 coupled to the second sub-bit line 241B on the second semiconductor structure 280 is located in the first overlapping region, the second sub-bit line 241B can be coupled to the first group of second interconnection lines 271 through the shorter interconnection structure 235, which can improve the feasibility of compressing the size of the semiconductor structure 200 in the second direction Y, and is conducive to improving the sensing margin. When the first group of second interconnection lines 271 coupled to the second sub-bit line 241B extends to the orthographic projection of the second sub-sensing amplifier circuit on the first semiconductor structure 210, the end of the first group of second interconnection lines 271 away from the first group of first interconnection lines 261 can be opposite to the second sub-sensing amplifier circuit, so that the wiring between the first group of second interconnection lines 271 and the second sub-sensing amplifier circuit can be simplified.

[0133] In some embodiments, reference Figure 2D The second interconnect layer 270 further includes a first shielding line 275 . The first shielding line 275 is located between two adjacent first group second interconnecting lines 271 coupled to the second sub-bit line 241B. The first shielding line 275 is coupled to the second semiconductor structure 280 .

[0134] It can be understood that, due to the long length of the first group of second interconnection lines 271 coupled to the second sub-bit line 241B, inductive coupling is easily generated between two adjacent first group of second interconnection lines 271. By configuring the second interconnection layer 270 to include the first shielding line 275, a shielding effect can be formed between the first group of second interconnection lines 271 to reduce inductive coupling. Moreover, by coupling the first shielding line 275 to the second semiconductor structure 280, a fixed voltage can be provided to the first shielding line 275 using the peripheral circuit 281 to improve the reliability of the first shielding line 275 in performing the shielding function.

[0135] In some examples, reference Figure 2D and Figure 2E, at least a portion of the first shielding line 275 is located in the peripheral area 203 . In this way, the first shielding line 275 can at least form a shielding effect between the portions of the first group of second interconnection lines 271 located in the peripheral area 203 .

[0136] Exemplarily, the material of the first shielding line 275 may include a conductive material, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof.

[0137] In some embodiments, reference Figure 2C and Figure 2D The first semiconductor structure 210 also has a second storage area 218 arranged along the second direction Y with the first storage area 220. The first semiconductor structure 210 also includes a second group of bit lines 242, and a second group of lead contacts 252 located on one side of the second group of bit lines 242 and in contact with the second group of bit lines 242. At least part of the second group of bit lines 242 is located in the second storage area 218; the second direction Y is the extension direction of the first bit line 211. The second group of bit lines 242 is coupled to the sensing amplifier circuit through the second group of lead contacts 252; and the second group of bit lines 242 and the first group of bit lines 241 are coupled to the same sensing amplifier circuit. The area where the sensing amplifier circuit coupled to the second group of bit lines 242 is located and the orthographic projection of the second storage area 218 on the second semiconductor structure have a second overlapping area; the orthographic projection of the second group of lead contacts 252 on the second semiconductor structure 280 is located in the second overlapping area.

[0138] In some examples, reference Figure 2C , the first semiconductor structure 210 also includes a plurality of second bit lines 229 located in the second storage area 218, a plurality of second lead contacts are provided on one side of the plurality of second bit lines 229, and the plurality of second bit lines 229 are coupled to the sensing amplifier circuit through the plurality of second lead contacts. It should be understood that the second group of bit lines 242 is the portion of the plurality of second bit lines 229 coupled to the first sensing amplifier circuit; the second group of lead contacts 252 is a portion of the plurality of second lead contacts. Here, the description of the second storage area 218, the second bit lines 229, and the second lead contacts can refer to the relevant descriptions in the first storage area 220, the first bit line 212, and the first lead contacts, which will not be repeated here. It should be noted that the “first” and “second” in the first storage area and the second storage area are relative concepts and are only used for descriptive purposes to make the relative position relationship between the two adjacent storage areas clearer. In actual applications, the first storage area and the second storage area may be any two adjacent storage areas in the first semiconductor structure, and, depending on the position of the other storage area being described, a storage area may be either the first storage area or the second storage area.

[0139] It should be understood that the second storage area 218 is a storage area adjacent to the first storage area 220, and the second group of bit lines 242 located in the second storage area 218 and the first group of bit lines 241 located in the first storage area 220 are coupled to the same sensing amplifier circuit (for example, the first sensing amplifier circuit described above), that is, the second group of bit lines 242 and the first group of bit lines 241 share the sensing amplifier circuit. Moreover, the sensing amplifier circuit and the orthographic projection of the second storage area 218 on the second semiconductor structure 280 have a second overlapping area, and the orthographic projection of the first storage area 220 on the second semiconductor structure 280 has a first overlapping area. That is to say, the area where the sensing amplifier circuit is located includes the first overlapping area and the second overlapping area. In order to more clearly describe the position of the second overlapping area in some embodiments, the sensing amplifier circuit is used. Figure 2D The dashed box 205 in the figure represents the positive projection of the second overlapping region on the first semiconductor structure 210.

[0140] In some examples, the first group of bit lines 241 and the second group of bit lines 242 are arranged in a one-to-one correspondence along the second direction Y; that is, each first group of bit lines 241 is aligned with one second group of bit lines 242 in the second direction Y. For example, when the first group of bit lines 241 includes odd-numbered first bit lines 211 , the second group of bit lines 242 includes odd-numbered second bit lines 229 .

[0141] In some examples, a first group of bit lines 241 and a second group of bit lines 242 are connected to the same sense amplifier module in the sense amplifier circuit. One of the first group of bit lines 241 and the second group of bit lines 242 is a target bit line and the other is a reference bit line. The sense amplifier module is configured to sense and amplify a voltage difference signal between the target bit line and the reference bit line.

[0142] It can be understood that when the orthographic projection of the second group of lead-out contacts 252 on the second semiconductor structure 280 is located within the second overlapping region, the second group of lead-out contacts 252 and a portion of the sensing amplifier circuit coupled thereto (for example, the first sensing amplifier circuit) are directly opposite to each other along the first direction X; in this way, at least a portion of the second group of lead-out contacts 252 can be coupled to the sensing amplifier circuit through a shorter interconnect structure 235 and an interconnect structure 235 with fewer layers, further improving the feasibility of compressing the size of the semiconductor structure 200 in the second direction Y and the first direction X, and at the same time helping to improve the sensing margin.

[0143] In some embodiments, the plurality of first interconnection lines 214 further include a second group of first interconnection lines 262. The plurality of second interconnection lines 215 further include a second group of second interconnection lines 272. The second group of extraction contacts 252 is coupled to the sense amplifier circuit through the second group of first interconnection lines 262 and the second group of second interconnection lines 272.

[0144] It can be understood that when the second group of lead contacts 252 is coupled to the sense amplifier circuit through the second group of first interconnection lines 262 and the second group of second interconnection lines 272, the number of layers of the interconnection structure 235 coupled to the second group of lead contacts 252 is two layers, compared with some implementations in which the interconnection structure between the bit line 111 and the sense amplifier circuit includes the first interconnection line 114, the second interconnection line 115 and the third interconnection line 116 (see Figure 1C ), the number of layers of the interconnect structure 235 can be reduced, which is beneficial to the compression of the size of the semiconductor structure 200 in the first direction X.

[0145] Exemplarily, the second group of lead-out contacts 252 and the second group of first interconnection lines 262, and / or the second group of first interconnection lines 262 and the second group of second interconnection lines 272, and / or the second group of second interconnection lines 272 and the sensing amplifier circuit can be coupled by direct contact or by indirect connection, which can be set according to actual needs, and the embodiments of the present disclosure do not specifically limit this.

[0146] In some embodiments, reference Figure 2D The sensing amplifier circuit includes a second sub-sense amplifier circuit located in the second overlapping region. The second group of bit lines 242 is coupled to a third sub-bit line 242A of the second sub-sense amplifier circuit. The second group of first interconnection lines 262 coupled to the third sub-bit line 242A and the second group of second interconnection lines 272 coupled to the third sub-bit line 242A are located in the second overlapping region in the orthographic projection of the second semiconductor structure 280.

[0147] In order to more clearly describe the location of the second overlapping region and / or the region where the second sub-sense amplifier circuit is located in some embodiments, the following is used: Figure 2D The dashed box 205 in FIG. 2 represents the positive projection of the second overlapping region and / or the second sub-sense amplifier circuit on the first semiconductor structure 210 .

[0148] It can be understood that when the orthographic projections of the second group of first interconnection lines 262 coupled to the third sub-bit line 242A and the second group of second interconnection lines 272 coupled to the third sub-bit line 242A on the second semiconductor structure 280 are both located in the second overlapping region, the interconnection structure 235 between the third sub-bit line 242A and the second sub-sensing amplifier circuit can be simplified, and the third sub-bit line 242A can be coupled to the second sub-sensing amplifier circuit through a shorter interconnection structure 235 and an interconnection structure 235 with fewer layers, which can improve the feasibility of compressing the size of the semiconductor structure 200 in the second direction Y and the first direction X, and at the same time can improve the sensing margin.

[0149] In some embodiments, reference Figure 2D, the sensing amplifier circuit further includes a first sub-sensing amplifier circuit located in the first overlap region. The second group of bit lines 242 further includes a fourth sub-bit line 242B coupled to the first sub-sensing amplifier circuit. The second group of first interconnect lines 262 coupled to the fourth sub-bit line 242B extends to within the orthographic projection 204 of the first overlap region on the first semiconductor structure 210. The second group of second interconnect lines 272 coupled to the fourth sub-bit line 242B has an orthographic projection in the second semiconductor structure 280 located in the first overlap region.

[0150] It should be understood that the first group of bit lines 241 and the second group of bit lines 242 are coupled to the same sense amplifier circuit, and the sense amplifier circuit includes a first sub-sense amplifier circuit and a second sub-sense amplifier circuit arranged along the second direction Y. In this case, the first group of bit lines 241 includes a first sub-bit line 241A coupled to the first sub-sense amplifier circuit and a second sub-bit line 241B coupled to the second sub-sense amplifier circuit. Correspondingly, the second group of bit lines 242 includes a third sub-bit line 242A coupled to the second sub-sense amplifier circuit and a fourth sub-bit line 242B coupled to the first sub-sense amplifier circuit.

[0151] For example, the third sub-bit line 242A and the fourth sub-bit line 242B are arranged alternately. In this way, the second group of lead-out contacts 252 and the interconnection structure 235 coupled to the third sub-bit line 242A and the second group of lead-out contacts 252 and the interconnection structure 235 coupled to the fourth sub-bit line 242B can be arranged in a staggered manner, which can increase the flexibility of the arrangement of the second group of lead-out contacts 252 and the interconnection structure 235; at the same time, the inductive coupling of the interconnection structure 235 can be reduced, which is conducive to improving the sensing margin.

[0152] It can be understood that when the second group of first interconnection lines 262 coupled to the fourth sub-bit line 242B extends to within the orthographic projection 204 of the first overlapping region on the first semiconductor structure 210, the end of the second group of first interconnection lines 262 away from the second group of lead-out contacts 252 can be directly opposite to the first sub-sensing amplifier circuit; when the second group of second interconnection lines 272 coupled to the fourth sub-bit line 242B has an orthographic projection on the second semiconductor structure 280 located in the first overlapping region, the second group of first interconnection lines 262 can be coupled to the first sub-sensing amplifier circuit through a shorter interconnection structure 235. In this way, the wiring between the fourth sub-bit line 242B and the first sub-sensing amplifier circuit can be simplified, the feasibility of compressing the size of the semiconductor structure 200 in the first direction X and the second direction Y can be improved, and at the same time, it is beneficial to improve the sensing margin.

[0153] In some embodiments, reference Figure 2DThe first interconnect layer 260 further includes a second shielding line 265. The second shielding line 265 is located between two adjacent second group first interconnect lines 262 coupled to the fourth sub-bit line 242B. The second shielding line 265 is coupled to the second semiconductor structure 280.

[0154] It can be understood that, due to the long length of the second group of first interconnection lines 262 coupled to the fourth sub-bit line 242B, inductive coupling is easily generated between two adjacent second group of first interconnection lines 262. By providing the first interconnection layer 260 with the second shielding line 265, a shielding effect can be formed between the second group of first interconnection lines 262 to reduce inductive coupling. Moreover, by coupling the second shielding line 265 with the second semiconductor structure 280, a fixed voltage can be provided to the second shielding line 265 using the peripheral circuit 281 to improve the reliability of the second shielding line 265 in performing the shielding function.

[0155] In some examples, reference Figure 2D and Figure 2E At least part of the second shielding line 265 is located in the peripheral area 203 . In this way, the second shielding line 265 can at least form a shielding effect between the parts of the second group of first interconnection lines 262 located in the peripheral area 203 .

[0156] Exemplarily, the material of the second shielding line 265 may include a conductive material, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof.

[0157] The above is an exemplary description of the first group of bit lines 241 located in the first storage area 220 and the second group of bit lines 242 located in the second storage area coupled to the sensing amplifier circuit (for example, the first sensing amplifier circuit). Based on the above embodiments, some implementation methods of the interconnection structure, lead contacts, bit lines and storage units coupled to the same sensing amplifier circuit provided by the present disclosure can be understood. In order to make the technical solutions in some embodiments of the present disclosure clearer and more complete, the first storage area will be taken as an example below to exemplarily describe the bit lines, lead contacts, interconnection structures and sensing amplifier circuits coupled to multiple storage units located in the same storage area.

[0158] It should be understood that reference Figure 2EIn addition to the first sensing amplifier circuit described in detail above, the sensing amplifier circuit coupled to the plurality of first storage cells 217 located in the first storage area 220 also includes a second sensing amplifier circuit. In addition to the first group of bit lines 241 described in detail above, the plurality of first bit lines 211 located in the first storage area 220 also include a third group of bit lines 243. In addition to the first group of lead contacts 251 described in detail above, the plurality of first lead contacts 212 located on one side of the plurality of first bit lines 211 also include a third group of lead contacts 253. The third group of bit lines 243 is coupled to the second sensing amplifier circuit through the third group of lead contacts 253. The region where the second sensing amplifier circuit is located and the orthographic projection of the first storage area 220 on the second semiconductor structure 280 have a third overlapping region. The orthographic projection of the third group of lead contacts 253 on the second semiconductor structure 280 is located in the third overlapping region.

[0159] In order to more clearly describe the location of the third overlapping region in some embodiments and / or the region where the third sub-sense amplifier circuit described in detail below is located, the following is used. Figure 2E The dashed box 207 in the figure represents the positive projection of the third overlapping region and / or the region where the third sub-sense amplifier circuit is located on the first semiconductor structure.

[0160] In some examples, reference Figure 2E , the first group of bit lines 241 includes a plurality of even-numbered first lines; the third group of bit lines 243 includes a plurality of odd-numbered first lines. In other examples, the first group of bit lines 241 includes a plurality of odd-numbered first lines; the third group of bit lines 243 includes a plurality of even-numbered first lines. In still other examples, the first group of bit lines 241 and the third group of bit lines 243 may be classified in other ways. That is, the screening method of the first group of bit lines 241 and the third group of bit lines 243 may be set according to actual needs, and the embodiments of the present disclosure do not specifically limit this.

[0161] Exemplarily, the first sensing amplifier circuit and the second sensing amplifier circuit are arranged along the second direction Y.

[0162] In some examples, reference Figure 2EThe first semiconductor structure 210 also has a third storage area 219 arranged along the second direction Y with the first storage area 220. The first semiconductor structure 210 also includes a fourth group of bit lines 244, and a fourth group of lead contacts 254 on one side of the fourth group of bit lines 244 and in contact with the fourth group of bit lines 244. At least part of the fourth group of bit lines is located in the third storage area 219; and the second storage area and the third storage area 219 are respectively located on both sides of the first storage area 220. The fourth group of bit lines 244 is coupled to the second sensing amplifier circuit through the fourth group of lead contacts 254; and the fourth group of bit lines 244 and the third group of bit lines 243 are both coupled to the second sensing amplifier circuit. The area where the second sensing amplifier circuit is located and the orthographic projection of the third storage area 219 on the second semiconductor structure 280 have a fourth overlapping area; the orthographic projection of the fourth group of lead contacts 254 on the second semiconductor structure 280 is located in the fourth overlapping area.

[0163] In order to more clearly describe the location of the fourth overlapping region in some embodiments and / or the region where the fourth sub-sense amplifier circuit described in detail below is located, Figure 2E The dashed box 208 in the figure represents the positive projection of the fourth overlapping region and / or the region where the fourth sub-sense amplifier circuit described in detail below is located on the first semiconductor structure.

[0164] In some examples, the first semiconductor structure 210 further includes a plurality of third bit lines, and a plurality of third lead contacts are disposed on one side of the plurality of third bit lines, and the plurality of third bit lines are coupled to the sensing amplifier circuit through the plurality of third lead contacts. At least part of the third bit lines is located in the third storage area. It should be understood that the fourth group of bit lines 244 is a portion of the plurality of third bit lines coupled to the second sensing amplifier circuit; the fourth group of lead contacts 254 is a portion of the plurality of third lead contacts. Here, for the description of the third storage area, the third bit line, and the third lead contact, please refer to the relevant description of the first storage area, the first bit line, and the first lead contact, which will not be repeated here. It should be noted that the “first”, “second” and “third” in the first storage area, the second storage area and the third storage area are relative concepts and are only used for descriptive purposes to make the relative position relationship of the three adjacent storage areas clearer. In actual applications, the first storage area, the second storage area and the third storage area may be any three adjacent storage areas in the first semiconductor structure, and, depending on the positions of the other storage areas described, a storage area may be the first storage area, the second storage area or the third storage area.

[0165] In some examples, reference Figure 2EThe plurality of first interconnection lines further include a third group of first interconnection lines 263. The plurality of second interconnection lines further include a third group of second interconnection lines 273. The third group of lead-out contacts 253 is coupled to the second sense amplifier circuit through the third group of first interconnection lines 263 and the third group of second interconnection lines 273.

[0166] In some examples, reference Figure 2E The second sense amplifier circuit includes a third sub-sense amplifier circuit located in the third overlap region. The third group of bit lines 243 includes a fifth sub-bit line 243A coupled to the third sub-sense amplifier circuit. The third group of first interconnection lines 263 coupled to the fifth sub-bit line 243A and the third group of second interconnection lines 273 coupled to the fifth sub-bit line 243A are located within the orthographic projection 207 of the third overlap region on the first semiconductor structure.

[0167] The second sense amplifier circuit coupled to the third group of bit lines 243 further includes a fourth sub-sense amplifier circuit. The third group of bit lines 243 further includes a sixth sub-bit line 243B coupled to the fourth sub-sense amplifier circuit. The third group of first interconnect lines 263 coupled to the sixth sub-bit line 243B extends to within the orthographic projection 208 of the fourth overlapping region on the first semiconductor structure. The third group of second interconnect lines 273 coupled to the sixth sub-bit line 243B is located within the orthographic projection 208 of the fourth overlapping region on the first semiconductor structure.

[0168] In some examples, reference Figure 2E The first interconnection layer 260 further includes a third shielding line 266. The third shielding line 266 is located between two adjacent third group first interconnection lines 263 coupled to the sixth sub-bit line 243B. The third shielding line 266 is coupled to the second semiconductor structure.

[0169] In some examples, the plurality of first interconnection lines further include a fourth group of first interconnection lines 264. The plurality of second interconnection lines further include a fourth group of second interconnection lines 274. The fourth group of lead-out contacts 254 is coupled to the second sense amplifier circuit through the fourth group of first interconnection lines 264 and the fourth group of second interconnection lines 274.

[0170] In some examples, the fourth group of bit lines 244 includes a seventh sub-bit line 244A coupled to the fourth sub-sense amplifier circuit. A fourth group of first interconnect lines 264 coupled to the seventh sub-bit line 244A and a fourth group of second interconnect lines 274 coupled to the seventh sub-bit line 244A are located within the orthographic projection 208 of the fourth overlap region on the first semiconductor structure.

[0171] The fourth group of bit lines 244 also includes an eighth sub-bit line 244B coupled to the third sub-sense amplifier circuit. The fourth group of first interconnection lines 264 coupled to the eighth sub-bit line 244B is located within the orthographic projection 208 of the fourth overlapping region on the first semiconductor structure. The fourth group of second interconnection lines 274 coupled to the eighth sub-bit line 244B extends to within the orthographic projection 207 of the third overlapping region on the first semiconductor structure.

[0172] In some examples, reference Figure 2E The second interconnect layer 270 further includes a fourth shielding line 276. The fourth shielding line 276 is located between two adjacent fourth group second interconnecting lines 274 coupled to the eighth sub-bit line 244B. The fourth shielding line 276 is coupled to the second semiconductor structure.

[0173] It should be noted that, for the description of the third shielding wire 266 and the fourth shielding wire 276, reference can be made to the relevant description of the first shielding wire 275 and the second shielding wire 265, which will not be repeated here.

[0174] In some embodiments, reference Figure 2D and Figure 2E The first semiconductor structure 210 further includes a third interconnect layer 290 located between the first interconnect layer 260 and the second interconnect layer 270. The third interconnect layer 290 includes a plurality of interconnect contacts 291. The first interconnect line 214 and the second interconnect line 215 are coupled through the interconnect contacts 291.

[0175] In some examples, reference Figure 2D and Figure 2E , multiple interconnection contacts 291 are located in the storage area 202.

[0176] By setting a third interconnect layer 290 between the first interconnect layer 260 and the second interconnect layer 270, and setting a plurality of interconnect contacts 291 in the third interconnect layer 290, the first interconnect line 214 and the second interconnect line 215 can be connected by using the interconnect contacts 291. In this way, the coupling of the first interconnect line 214 and the second interconnect line 215 can be achieved, thereby improving the process feasibility of coupling the first interconnect line 214 and the second interconnect line 215.

[0177] In some examples, the third interconnect layer 290 may correspond to the position of the ILD layer between the first interconnect layer 260 and the second interconnect layer 270, and the interconnect contact 291 may be prepared by forming a plurality of through contact holes on the ILD layer and filling the contact holes with one or more conductive materials. Exemplarily, the interconnect contact 291 includes one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN). In some embodiments, the interconnect contact 291 also includes an insulator (e.g., a dielectric layer) to electrically insulate the interconnect contact 291 from the ILD layer.

[0178] In some embodiments, reference Figure 2B The second semiconductor structure 280 includes a first bonding layer 288, and the first bonding layer 288 includes a plurality of first bonding contacts 289. The first semiconductor structure 210 includes a second bonding layer 238, and the second bonding layer 238 includes a plurality of second bonding contacts 239. The second interconnection line 215 is coupled to the sense amplifier circuit 287 through the second bonding contacts 239 and the first bonding contacts 289.

[0179] For example, refer to Figure 2B , the first bonding layer 288 can be located above the peripheral circuit 281. The first bonding layer 288 can also include a dielectric that electrically isolates the first bonding contact 289. The first bonding contact 289 can include a conductive material, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof. The remaining area of ​​the first bonding layer 288 can be formed with a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. The first bonding contact 289 in the first bonding layer 288 and the surrounding dielectric can be used for hybrid bonding.

[0180] Correspondingly, refer to Figure 2B , the second bonding layer 238 may be located above the first bonding layer 288. The second bonding layer 238 may also include a dielectric that electrically isolates the second bonding contact 239. The second bonding contact 239 may include a conductive material, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof. The remaining area of ​​the second bonding layer 238 may be formed with a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. The second bonding contact 239 in the second bonding layer 238 and the surrounding dielectric may be used for hybrid bonding. In some embodiments, the second bonding contact 239 contacts the first bonding contact 289. Among them, hybrid bonding (also referred to as "metal / dielectric hybrid bonding") is a direct bonding technology (e.g., forming a bond between surfaces without using an intermediate layer (e.g., solder or adhesive)) and can simultaneously obtain metal-metal bonding and dielectric-dielectric bonding.

[0181] In the case where the second interconnection line 215 is coupled to the sense amplifier circuit 287 through the second bonding contact 239 and the first bonding contact 289, Figure 2B , the first bit line 211 can be coupled to the sense amplifier circuit 287 through a metal wiring. The metal wiring includes a first lead-out contact 212, a first interconnection line 214, a second interconnection line 215, a second bonding contact 239, and a first bonding contact 289. By wiring in this way, the total resistance of the metal wiring can be reduced, and the process feasibility of coupling the first bit line 211 with the sense amplifier circuit 287 can be improved.

[0182] Some embodiments of the present disclosure also provide a storage system 1000. Figure 3A and Figure 3B As shown, the storage system 1000 includes: a controller 300 and a semiconductor structure 200 provided by any of the above embodiments. The controller 300 is coupled to the semiconductor structure 200 to control the semiconductor structure 200 to store data.

[0183] In some embodiments, reference Figure 3A , the storage system 1000 includes: a semiconductor structure 200, and the storage system 1000 can be integrated into a memory card.

[0184] Memory cards include, for example, PC cards (Personal Computer Memory Card International Association, PCMCIA), Compact Flash (CF) cards, Smart Media (SM) cards, memory sticks, Multimedia Cards (MMC), Secure Digital (SD) cards, and UFS.

[0185] The storage system 1000 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 1000 may be applied to and packaged into different types of electronic products, for example, mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0186] In other embodiments, reference Figure 3B The storage system 1000 includes: a controller 300 and a plurality of semiconductor structures 200. The storage system 1000 is integrated into a solid state drive (SSD).

[0187] In the storage system 1000, in some embodiments, the controller 300 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0188] In other embodiments, the controller 300 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, notebooks, and enterprise storage arrays.

[0189] In some embodiments, the controller 300 may be configured to manage data stored in the semiconductor structure 200 and communicate with an external device (eg, a host).

[0190] In some embodiments, the controller 300 may also be configured to control operations of the semiconductor structure 200 , such as read, erase, and program operations.

[0191] In some embodiments, the controller 300 may also be configured to manage various functions regarding data stored or to be stored in the semiconductor structure 200 , including at least one of bad block management, garbage collection, logical to physical address translation, and wear leveling.

[0192] In some embodiments, the controller 300 is further configured to process error correction codes regarding data read from or written to the semiconductor structure 200 .

[0193] Of course, the controller 300 may also perform any other suitable functions, such as formatting the semiconductor structure 200 ; for example, the controller 300 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0194] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0195] The embodiment of the present disclosure also provides an electronic device 10000, referring to Figure 4 , the electronic device 10000 includes a storage system 1000.

[0196] The electronic device 10000 includes but is not limited to any one of a mobile phone, a tablet computer, a laptop computer, a television, a personal digital assistant (PDA), an ultra-mobile personal computer (UMPC), a netbook, a wearable device (such as a smart watch, a smart bracelet, smart glasses), etc. The embodiments of the present application do not limit the type of electronic device.

[0197] The electronic device may include the storage system 1000 described above, and may also include at least one of a central processing unit (CPU) and a cache.

[0198] In some embodiments, reference Figure 4 The electronic device 10000 further includes a printed circuit board 2000 , and the printed circuit board 2000 is coupled to the storage system 1000 .

[0199] Figure 5A to Figure 5G A process for preparing a semiconductor structure is provided for some embodiments of the present disclosure. Figure 6 The following is a flow chart of a method for preparing a first semiconductor structure 210 provided in some embodiments of the present disclosure. Figure 5A to Figure 5G and Figure 6It should be understood that the operations shown in the preparation method are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, they may be performed simultaneously or in a manner similar to that of the embodiment of the present invention. Figure 6 Some of the operations are performed in a different order as shown.

[0200] Some embodiments of the present disclosure further provide a method for preparing a semiconductor structure 200 , including S1 .

[0201] S1 : forming a first semiconductor structure 210 , wherein the first semiconductor structure 210 has a first storage region 220 .

[0202] For example, refer to Figure 6 , forming the first semiconductor structure 210 includes S1.1 to S1.4.

[0203] S1.1: Reference Figure 5A , forming a plurality of first storage units 217 located in the first storage area 220.

[0204] Exemplarily, forming a plurality of first storage units 217 includes S1.1.1 to S1.1.5.

[0205] S1.1.1: Provide a semiconductor layer 221 , in which at least one active pillar extending along the thickness direction of the semiconductor layer 221 and gates 227 located on both sides of the active pillar are formed.

[0206] In some examples, the semiconductor layer 221 includes a substrate 294. The material of the substrate 294 may include silicon (Si), germanium (Ge), silicon germanium (SiGe), etc.; in some specific embodiments, the substrate 294 may also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI); in practical applications, the substrate 294 may be formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, etc.

[0207] By way of example, the semiconductor layer 221 may be etched by a dry etching process, for example, a plasma etching process or a reactive ion etching process, so as to form active pillars on the semiconductor layer 221 .

[0208] In some examples, S1.1.1 also includes: forming a gate oxide layer 230 on both sides of the active column; wherein the gate oxide layer 230 can be used to suppress the short channel effect. In addition, setting the thickness of the gate oxide layer 230 to oxide layers of different thicknesses can solve the matching problem of the semiconductor structure 200 under different voltage requirements. Here, the thickness of the gate oxide layer 230 can be set according to the actual requirements of the first type of transistor 223. Next, a gate 227 is formed on the side of the gate oxide layer 230 away from the active column.

[0209] Exemplarily, the gate 227 is formed by methods including but not limited to PVD, CVD, ALD, etc.

[0210] S1.1.2: Etching the active pillar to form a first groove; the first groove divides the active pillar into a first sub-active pillar and a second sub-active pillar.

[0211] Exemplarily, a method of etching the active pillar to form the first groove includes but is not limited to dry plasma etching.

[0212] S1.1.3: Fill the first groove to form a first dielectric layer 228 .

[0213] Exemplarily, the method of filling the first groove and forming the first dielectric layer 228 includes but is not limited to PVD, CVD, ALD and other processes.

[0214] S1.1.4: The source 225 and the drain 226 of the first type-one transistor 223 and the second type-one transistor 223 are respectively formed at the two opposite ends of the first sub-active pillar and the second sub-active pillar along the thickness direction of the semiconductor layer 221; the first sub-active pillar and the second sub-active pillar between the source 225 and the drain 226 constitute the channel portion 224 of the first type-one transistor 223 and the second type-one transistor 223 respectively.

[0215] Exemplarily, S1.1.4 further includes: thinning the semiconductor layer 221 from the surface of the semiconductor layer 221 and in a direction perpendicular to the semiconductor layer 221 to expose the first ends of the first sub-active pillar and the second sub-active pillar. Ion implantation is performed at the first ends of the first sub-active pillar and the second sub-active pillar to form the source 225 of the first first-type transistor 223 and the second first-type transistor 223.

[0216] Exemplarily, the doping method of the source 225 and the drain 226 includes an ion implantation process or a diffusion process, but is not limited thereto.

[0217] Illustratively, the process of thinning the semiconductor layer 221 includes, but is not limited to, an etching process and a chemical mechanical polishing process.

[0218] S1.1.5: Forming storage capacitor 231.

[0219] Exemplarily, forming the storage capacitor 231 may include the following steps: forming a storage cell contact hole on the source 225; filling a metal material in the storage cell contact hole to form a storage cell contact; forming a storage cell hole on the storage cell contact; and forming the storage capacitor 231 in the storage cell hole.

[0220] S1.2: Reference Figure 5B , forming a first bit line 211 ; at least a portion of the first bit line 211 is located in the first storage area 220 .

[0221] Exemplarily, forming the first bit line 211 may include the following steps: forming the first bit line 211 by forming a metal line at a preset bit line position. The metal line includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.

[0222] S1.3: Reference Figure 5C A first lead contact 212 is formed on one side of the first bit line 211 ; the first lead contact 212 contacts the first bit line 211 . The first lead contact 212 is located in the first storage area 220 .

[0223] Exemplarily, the process of forming the first lead contact 212 may be: first, dry etching and / or wet etching (such as reactive ion etching (RIE)) is used to etch a contact opening (such as a trench) through the ILD layer. Then, one or more thin film deposition processes (including but not limited to CVD, PVD, ALD or any combination thereof) may be used to deposit a conductive material on the ILD layer and into the contact opening to form an adhesive / barrier layer and a contact core filling each contact opening.

[0224] In some examples, reference Figure 5C , after S1.3, also includes S1.4.

[0225] S1.4: forming an interconnection structure 235 on a side of the first lead-out contact 212 away from the first bit line 211 .

[0226] For example, refer to Figure 2B The interconnect structure 235 includes a plurality of first interconnect lines 214 and a plurality of second interconnect lines 215; when the first semiconductor structure 210 includes a first shielding line 275, the first shielding line 275 is formed while the plurality of second interconnect lines 215 are formed; when the first semiconductor structure 210 includes a second shielding line 265, the second shielding line 265 is formed while the plurality of first interconnect lines 214 are formed.

[0227] For example, the process of forming the plurality of first interconnect lines 214 may be: firstly, dry etching and / or wet etching (such as reactive ion etching (RIE)) is used to etch through the ILD layer to form patterned grooves, and then one or more thin film deposition processes (including but not limited to CVD, PVD, ALD or any combination thereof) may be used to deposit a conductive material on the ILD layer and into the grooves to form the first interconnect lines 214.

[0228] Exemplarily, when the interconnect structure 235 includes a plurality of first interconnect lines 214 and a plurality of second interconnect lines 215, forming the interconnect structure 235 includes: first forming the first interconnect lines 214 on one ILD layer, and then forming the second interconnect lines 215 on another ILD layer. The process of forming the second interconnect lines 215, the first shielding lines 275, and the second shielding lines 265 can refer to the process of forming the first interconnect lines 214, which will not be described again here.

[0229] In some examples, reference Figure 5D , after S1.4, S1.5 is also included.

[0230] S1.5: forming a plurality of second bonding contacts 239 on a side of the interconnect structure 235 away from the first lead-out contact 212 .

[0231] Exemplarily, the process of forming the plurality of second bonding contacts 239 may be: first, using dry etching and / or wet etching (such as reactive ion etching (RIE)) to etch contact openings (such as trenches) through the ILD layer. Then, one or more thin film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof) may be used to deposit conductive material on the ILD layer and into the contact openings to form an adhesive / barrier layer and a contact core filling each contact opening. In some embodiments, a planarization process (such as etching and / or CMP) is performed to remove excess conductive material and planarize the top surface of the ILD layer and the second bonding contacts 239.

[0232] In some examples, after S1, S2 to S4 are also included.

[0233] S2: forming a second semiconductor structure 280 .

[0234] In some examples, reference Figure 5E Forming the second semiconductor structure 280 includes: forming a peripheral circuit 281 on a substrate 282, wherein the peripheral circuit 281 includes a sensing amplifier circuit.

[0235] Exemplarily, the process of forming the peripheral circuit 281 having the plurality of second-type transistors 283 on the substrate 282 may be photolithography, etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable process.

[0236] Exemplarily, forming the second semiconductor structure 280 further includes: forming a plurality of first bonding contacts 289 on a side of the peripheral circuit 281 away from the substrate 282 .

[0237] Here, for the description of forming the plurality of first bonding contacts 289 , reference may be made to the above description of the second bonding contacts, which will not be repeated here.

[0238] S3: Reference Fig. 5F , connecting the second semiconductor structure 280 to the first semiconductor structure 210 , and coupling the first bonding contact 289 to the second bonding contact 239 during the connection.

[0239] For example, the process of connecting the first semiconductor structure 210 and the second semiconductor structure 280 may be: bonding the first semiconductor structure 210 and the second semiconductor structure 280 in a face-to-face manner so that the first storage area 220 is above the peripheral circuit 281. The bonding may include hybrid bonding.

[0240] In some examples, reference Figure 5A After S1.1.5, the method further includes: connecting the first semiconductor structure 210 to the carrier wafer 293 so that the storage capacitor 231 is closer to the carrier wafer 293 than the first type transistor 223. After the first semiconductor structure 210 is connected to the second semiconductor structure 280, refer to Fig. 5F , also including removal of the carrier wafer.

[0241] S4: Reference Figure 5G A peripheral interconnection layer 236 is formed on a side of the first semiconductor structure 210 away from the second semiconductor structure 280 .

[0242] For example, in the case where the peripheral interconnect layer 236 includes a contact pad 237, the process of forming the contact pad 237 may be: first, dry etching and / or wet etching (such as reactive ion etching (RIE)) is used to etch a contact pad opening (such as a trench) through the ILD layer. Then, one or more thin film deposition processes (including but not limited to CVD, PVD, ALD or any combination thereof) may be used to deposit a conductive material on the ILD layer and into the contact pad opening to form an adhesive / barrier layer and a contact pad core filling the contact pad opening.

[0243] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, It is characterized in that include: A first semiconductor structure having a first storage area; the first semiconductor structure comprises a first bit line and a first lead contact located at one side of the first bit line; The first lead-out contact contacts the first bit line; at least a portion of the first bit line is located in the first storage area; and the first lead-out contact is located in the first storage area.

2. The semiconductor structure according to claim 1, It is characterized in that Also includes: a second semiconductor structure, located on one side of the first semiconductor structure and connected to the first semiconductor structure; The second semiconductor structure includes a peripheral circuit; The first bit line is coupled to the peripheral circuit through the first lead contact.

3. The semiconductor structure according to claim 2, It is characterized in that The peripheral circuit includes a plurality of sensing amplifier circuits; the first bit line is coupled to the sensing amplifier circuit through the first lead contact; The orthographic projection of the first storage area on the second semiconductor structure and the area where the multiple sensing amplifier circuits are located have an overlapping area; the orthographic projection of the first lead-out contact on the second semiconductor structure is located in the overlapping area.

4. The semiconductor structure according to claim 1, It is characterized in that There are a plurality of first bit lines, and the plurality of first bit lines are arranged in parallel; there are a plurality of first lead contacts; The first lead-out contacts are in corresponding contact with the first bit lines; any two adjacent first lead-out contacts are arranged alternately along a second direction, and the second direction is an extension direction of the first bit lines.

5. The semiconductor structure according to claim 4, It is characterized in that Two ends of the plurality of first bit lines along the second direction are flush.

6. The semiconductor structure according to claim 1, It is characterized in that The first semiconductor structure further comprises a plurality of first storage cells located in the first storage area; the first bit line is located at one side of the plurality of first storage cells along the first direction; The projection of the first lead contact along the first direction overlaps with the projection of one of the first storage units along the first direction.

7. The semiconductor structure according to claim 1, It is characterized in that The first bit line is located in the first storage area.

8. The semiconductor structure according to claim 3, It is characterized in that The number of the first bit lines is a plurality, and the plurality of first bit lines comprises a first group of bit lines; The number of the first lead-out contacts is multiple, and the multiple first lead-out contacts include a first group of lead-out contacts; the first group of bit lines are coupled to the sensing amplifier circuit through the first group of lead-out contacts; the area where the sensing amplifier circuit coupled to the first group of bit lines is located and the orthographic projection of the first storage area on the second semiconductor structure have a first overlapping area; the orthographic projection of the first group of lead-out contacts on the second semiconductor structure is located in the first overlapping area.

9. The semiconductor structure according to claim 8, It is characterized in that The first semiconductor structure further comprises: A first interconnection layer is located at a side of the first lead-out contact away from the first bit line; the first interconnection layer comprises a plurality of first interconnection lines; the plurality of first interconnection lines comprises a first group of first interconnection lines; A second interconnection layer is located at a side of the first interconnection layer away from the first lead-out contact; the second interconnection layer comprises a plurality of second interconnection lines; the plurality of second interconnection lines comprises a first group of second interconnection lines; The first group of lead-out contacts is coupled to the sensing amplifier circuit through the first group of first interconnection lines and the first group of second interconnection lines.

10. The semiconductor structure according to claim 9, It is characterized in that The sense amplifier circuit includes a first sub-sense amplifier circuit located in the first overlap region; the first group of bit lines includes a first sub-bit line coupled to the first sub-sense amplifier circuit; Orthographic projections of the first group of first interconnection lines coupled to the first sub-bit line and the first group of second interconnection lines coupled to the first sub-bit line on the second semiconductor structure are located in the first overlapping region.

11. The semiconductor structure according to claim 10, It is characterized in that The sense amplifier circuit coupled to the first group of bit lines further includes a second sub-sense amplifier circuit; the first group of bit lines further includes a second sub-bit line coupled to the second sub-sense amplifier circuit; The orthographic projection of the first group of first interconnection lines coupled to the second sub-bit line on the second semiconductor structure is located in the first overlapping region; the first group of second interconnection lines coupled to the second sub-bit line extends into the orthographic projection of the second sub-sense amplifier circuit on the first semiconductor structure.

12. The semiconductor structure according to claim 11, It is characterized in that The second interconnect layer further includes a first shielding line; the first shielding line is located between two adjacent first group second interconnecting lines coupled to the second sub-bit line; the first shielding line is coupled to the second semiconductor structure.

13. The semiconductor structure according to claim 9, It is characterized in that The first semiconductor structure further has a second storage area arranged along a second direction with the first storage area, and the first semiconductor structure further includes a second group of bit lines, and a second group of lead contacts located on one side of the second group of bit lines and in contact with the second group of bit lines; wherein at least a portion of the second group of bit lines is located in the second storage area; and the second direction is an extension direction of the first bit lines; The second group of bit lines is coupled to the sense amplifier circuit through the second group of lead contacts; and the second group of bit lines and the first group of bit lines are coupled to the same sense amplifier circuit; The area where the sensing amplifier circuit coupled to the second group of bit lines is located and the orthographic projection of the second storage area on the second semiconductor structure have a second overlapping area; the orthographic projection of the second group of lead contacts on the second semiconductor structure is located in the second overlapping area.

14. The semiconductor structure according to claim 13, It is characterized in that The plurality of first interconnection lines further include a second group of first interconnection lines; the plurality of second interconnection lines further include a second group of second interconnection lines; the second group of lead-out contacts are coupled to the sensing amplifier circuit through the second group of first interconnection lines and the second group of second interconnection lines.

15. The semiconductor structure according to claim 14, It is characterized in that The sense amplifier circuit includes a second sub-sense amplifier circuit located in the second overlap region; the second group of bit lines includes a third sub-bit line coupled to the second sub-sense amplifier circuit; The second group of first interconnection lines coupled to the third sub-bit line and the second group of second interconnection lines coupled to the third sub-bit line are located in the second overlapping region in an orthographic projection of the second semiconductor structure.

16. The semiconductor structure according to claim 15, It is characterized in that The sensing amplifier circuit further includes a first sub-sensing amplifier circuit located in the first overlapping region; the second group of bit lines further includes a fourth sub-bit line coupled to the first sub-sensing amplifier circuit; a second group of first interconnect lines coupled to the fourth sub-bit line, extending into an orthographic projection of the first overlapping region on the first semiconductor structure; A second group of second interconnection lines coupled to the fourth sub-bit line has an orthographic projection on the second semiconductor structure located in the first overlapping region.

17. The semiconductor structure according to claim 16, It is characterized in that The first interconnect layer further includes a second shielding line; the second shielding line is located between two adjacent second-group first interconnecting lines coupled to the fourth sub-bit line; and the second shielding line is coupled to the second semiconductor structure.

18. The semiconductor structure according to any one of claims 9 to 17, It is characterized in that The first semiconductor structure further includes a third interconnect layer located between the first interconnect layer and the second interconnect layer, the third interconnect layer including a plurality of interconnect contacts, and the first interconnect line and the second interconnect line are coupled through the interconnect contacts.

19. The semiconductor structure according to any one of claims 9 to 17, It is characterized in that The second semiconductor structure includes a first bonding layer, the first bonding layer includes a plurality of first bonding contacts; The first semiconductor structure includes a second bonding layer, the second bonding layer includes a plurality of second bonding contacts; The second interconnection line is coupled to the sense amplifier circuit through the second bonding contact and the first bonding contact.

20. A storage system, It is characterized in that include: A semiconductor structure, wherein the semiconductor structure is the semiconductor structure according to any one of claims 1 to 19; The controller is coupled to the semiconductor structure to control the semiconductor structure to store data.

21. A method for preparing a semiconductor structure, It is characterized in that include: forming a first semiconductor structure having a first storage region; The forming of the first semiconductor structure comprises: forming a first bit line; at least a portion of the first bit line is located in the first storage area; A first lead contact is formed at one side of the first bit line; the first lead contact is in contact with the first bit line; Wherein, the first lead contact is located in the first storage area.

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