Stacked memory device communicating via data packets

Abstract

The invention relates to a stacked memory device communicating via data packets. The stacked memory device includes a base chip and a core chip stacked with and electrically connected to the base chip. In the present disclosure, a base chip includes: a transmission / reception circuit configured to receive write data, a write effective signal, and transmit a write clock signal; a serialization / parallelization circuit configured to receive write data based on the write valid signal in synchronization with transmitting the write clock signal, and to generate a parallelized input data packet from the write data; and a data transfer control circuit configured to decode the parallelized input data packet to extract, from the parallelized input data packet, first internal data stored in the core chip when a write operation is performed on the core chip.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0174966, filed on December 5, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Some embodiments of the present disclosure relate to stacked memory devices that communicate in data packets. Background Art

[0004] Stacked memory systems such as high bandwidth memory (HBM) systems are used in a wide range of applications due to their excellent bandwidth and energy efficiency. Unlike existing memory systems that use parallel data buses, stacked memory systems include stacked memory devices consisting of a base chip and multiple memory chips interconnected by through silicon vias (TSVs, hereinafter referred to as "vias"). Stacked memory devices communicate with processors using physical interfaces such as PHYs, and PHYs need to be designed to ensure high-speed data transmission and efficient communication. Summary of the invention

[0005] According to an embodiment of the present disclosure, a stacked memory device may include a base chip and a core chip stacked with the base chip and electrically connected to the base chip. In the present disclosure, the base chip may include: a sending / receiving circuit configured to receive write data, a write valid signal, and a transmission write clock signal; a serialization / parallelization circuit configured to receive write data based on the write valid signal in synchronization with the transmission write clock signal, and generate a parallelized input data packet from the write data; and a data transmission control circuit configured to decode the parallelized input data packet to extract the first internal data stored in the core chip when a write operation is performed on the core chip from the parallelized input data packet.

[0006] According to another embodiment of the present disclosure, a stacked memory device may include: a serialization / parallelization circuit, which is configured to receive write data when a write valid signal is activated in synchronization with a transmission write clock signal, and generate a parallelized input data packet from the write data; and a data transmission control circuit, which is configured to decode the parallelized input data packet, generate an internal row control signal and an internal column control signal, extract first internal data from the parallelized input data packet when a write operation is performed on the core chip based on the internal row control signal and the internal column control signal, receive data output from the core chip as second internal data when a read operation is performed on the core chip based on the internal row control signal and the internal column control signal, and generate an output data packet based on the second internal data and header information.

[0007] According to another embodiment of the present disclosure, a stacked memory device may include a plurality of core chips connected to each other through one or more through holes and stacked with a base chip. In the present disclosure, the base chip may include: a sending / receiving circuit configured to receive write data, a write valid signal, and a transmission write clock signal; a serialization / parallelization circuit configured to receive write data based on a write valid signal in synchronization with the transmission write clock signal, and to generate a parallelized input data packet from the write data; a memory controller configured to generate a control command and an address based on the parallelized input data packet; and an interface conversion circuit configured to convert the control command and the address into an internal row control signal for row series operations for multiple core chips and an internal column control signal for column series operations for multiple core chips.

[0008] According to another embodiment of the present disclosure, the method may include: when a write valid signal is activated in synchronization with a transmission write clock signal, receiving serial write data by a base chip; generating an input data packet by parallelizing the serial write data; and when a write operation is performed on a core chip, decoding the input data packet to generate at least two control signals, and extracting first internal data based on the at least two control signals to store the first internal data in the core chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating a stacked memory device according to an embodiment of the present disclosure.

[0010] Figure 2 is a block diagram illustrating an embodiment of a base chip included in a stacked memory device.

[0011] Figure 3 is a timing diagram showing the timing of a write operation of a stacked memory device according to an embodiment of the present disclosure.

[0012] Figure 4 is a table identifying data transferred during input and output operations for a data packet according to an embodiment of the present disclosure.

[0013] Figure 5 and Figure 6 is a diagram showing an example of a data packet format according to an embodiment of the present disclosure.

[0014] Figure 7 is a block diagram illustrating a stacked memory device according to another embodiment of the present disclosure.

[0015] Figure 8 is a block diagram illustrating an embodiment of a base chip included in a stacked memory device.

[0016] Fig. 9is a block diagram illustrating a stacked memory device according to another embodiment of the present disclosure.

[0017] Fig.10 is a block diagram illustrating a stacked memory system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] In the following description of the embodiments, when a parameter is referred to as "predetermined", the value of the parameter may be predetermined when the parameter is used in a process or algorithm. The value of the parameter may be determined at the beginning of the process or algorithm, or may be determined during the execution of the process or algorithm.

[0019] Although the terms "first", "second", "third", etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element and are not intended to imply the order or quantity of the elements. Therefore, the first element in some embodiments may be referred to as the second element in other embodiments without departing from the teachings of the present disclosure.

[0020] When an element is referred to as being “connected” or “coupled” to another element, the element may be directly connected or coupled to the other element, or intervening elements may be present. When an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements.

[0021] Logical "high" levels and logical "low" levels can be used to describe the logical levels of electrical signals. A signal at a logical "high" level is different from a signal at a logical "low" level. For example, when a signal at a first voltage corresponds to a signal at a logical "high" level, a signal at a second voltage corresponds to a signal at a logical "low" level. In an embodiment, a logical "high" level can be a voltage level that is higher than a voltage level at a logical "low" level. The logical levels of a signal can be set to be different or opposite depending on the embodiment. For example, a signal that is at a logical "high" level in one embodiment can be at a logical "low" level in another embodiment.

[0022] The term "logical bit group" may include a combination of logic levels of bits included in a signal. When the logic level of each bit included in the signal changes, the logic bit group of the signal may be different. For example, if the signal includes two bits, when the logic level of each of the two bits included in the signal is "logic low level, logic low level", the logic bit group of the signal may be a first logic bit group, and when the logic level of each of the two bits included in the signal is "logic low level and logic high level", the logic bit group of the signal may be a second logic bit group.

[0023] Various embodiments of the present disclosure are described in more detail with reference to the accompanying drawings. The embodiments are described for illustrative purposes only and are not intended to limit the scope of the present disclosure.

[0024] Figure 1 is a block diagram showing a stacked memory device 10 according to an embodiment of the present disclosure. Figure 1 As shown, the stacked memory device 10 includes a base chip 101 and a core chip 103. The core chip 103 may be disposed on the base chip 101, disposed together with the base chip 101, or disposed above the base chip 101. The core chip 103 may include a plurality of (L) core chips 103-1 to 103-L. Each of the plurality of core chips 103-1 to 103-L may be connected to one or more through holes (e.g., Fig.10 The core chip 103 may receive various signals from the base chip 101 and exchange data with the base chip 101 through one or more through holes.

[0025] The basic chip 101 includes a transmission / reception circuit (Rx Tx) 111 , a serialization / deserialization circuit (SERDES) 113 , a data transmission control circuit (DATATR CTR) 115 , and a core control circuit (CORE CTR) 119 .

[0026] For write operations and read operations to the core chip 103, the send / receive circuit 111 receives data from a processor (eg, Fig.10 When the core chip 103 is read, the sending / receiving circuit 111 sends the read data RDATA, the read valid signal RVALID, and the transmission read clock signals RCK-t and RCK-c to the external device.

[0027] The serialization / parallelization circuit 113 receives the write data WDATA and generates a parallelized input data packet (eg, Figure 2 BI in the serialization / parallelization circuit 113), and when the write valid signal WVALID is activated in synchronization with the transmission write clock signals WCK-t and WCK-c, the parallelized input data packet is provided to the data transmission control circuit 115. When a read operation is performed on the core chip 103, the serialization / parallelization circuit 113 generates an output data packet (for example, Figure 2 BO) in the transmission / reception circuit 111 extracts the serialized read data RDATA and the read valid signal RVALID, and provides the serialized read data RDATA and the read valid signal RVALID to the transmission / reception circuit 111.

[0028] When a write operation is performed on the core chip 103, the data transfer control circuit 115 processes the input data packet (eg Figure 2 The data transmission control circuit 115 decodes the internal data IDQ extracted from the input data packet BI to check whether any error is detected in the internal data IDQ extracted from the input data packet BI, and stores the internal data IDQ in the core chip 103 through the core control circuit 119. When a read operation is performed on the core chip 103, the data transmission control circuit 115 checks whether any error is detected in the internal data IDQ output from the core chip 103, and stores the output data packet (e.g. Figure 2 The internal data IDQ extracted from the input data packet BI when a write operation is performed on the internal data IDQ and the internal data IDQ output from the core chip 103 when a read operation is performed on the core chip 103 may be separate signals transmitted through the same signal line.

[0029] When a write operation is performed on the core chip 103, the core control circuit 119 receives the internal data IDQ and controls the core chip 103 so that the internal data IDQ is stored in the core chip 103. When a read operation is performed on the core chip 103, the core control circuit 119 receives the internal data IDQ output from the core chip 103 to provide the internal data IDQ to the data transfer control circuit 115.

[0030] The stacked memory device 10 configured as described above uses data packets (eg, Figure 2 BI and BO in ), thereby improving scalability and performing high-speed operations when applied to or used in stacked memory systems.

[0031] Figure 2 It is shown as Figure 1 FIG. 1 is a block diagram of an embodiment of a basic chip 101 shown in FIG. Figure 2 As shown, the basic chip 101 includes a sending / receiving circuit 111 , a serialization / parallelization circuit 113 , a data transmission control circuit 115 , and a core control circuit 119 .

[0032] The transmission / reception circuit 111 includes reception buffers 111-1, 111-2, and 111-3 and transmission drivers 112-1, 112-2, 112-3, and 112-4. The reception buffer 111-1 buffers the write data WDATA serially received from the external device based on the reference voltage VREF, and provides the buffered write data WDATA to the serialization / parallelization circuit 113. The reception buffer 111-2 receives and buffers the write valid signal WVALID based on the reference voltage VREF, and provides the buffered write valid signal WVALID to the serialization / parallelization circuit 113. The reception buffer 111-3 receives and buffers the transmission write clock signals WCK-t and WCK-c, and provides the buffered transmission write clock signals WCK-t and WCK-c to the serialization / parallelization circuit 113. The transmission driver 112-1 transmits the read data RDATA serially received from the serialization / parallelization circuit 113 to the external device. The transmission driver 112-2 transmits the read valid signal RVALID received from the serialization / parallelization circuit 113 to the external device. The transmission drivers 112-3 and 112-4 transmit the transmission read clock signals RCK-t and RCK-c received from the serialization / parallelization circuit 113 to the external device.

[0033] The serialization / parallelization circuit 113 includes a parallelization circuit 121 and a serialization circuit 123 .

[0034] The parallelization circuit 121 is electrically connected to the receiving buffers 111-1, 111-2 and 111-3, and receives the write data WDATA, the write valid signal WVALID and the transmission write clock signals WCK-t and WCK-c. When the write valid signal WVALID is activated in synchronization with the transmission write clock signals WCK-t and WCK-c, the parallelization circuit 121 receives the write data WDATA to generate and output the parallelized input data packet BI. The parallelization circuit 121 outputs the transmission write clock signals WCK-t and WCK-c as the buffer write clock signal BWCK / B. The parallelization circuit 121 is electrically connected to the data transmission control circuit 115, and provides the input data packet BI and the buffer write clock signal BWCK / B to the data transmission control circuit 115. The input data packet BI can be implemented or formatted as a data packet used in the fast peripheral component interconnect (PCIe) and fast computing link (CXL) protocols. PCIe and CXL are high-speed interface standards for interconnecting various hardware components (such as graphics cards, storage devices, and network cards, etc.). The input data packet BI may include header information (which includes information such as the destination and data packet type), information about internal control signals that control internal operations, data information stored in the core chip 103, error control information for detecting errors, and security information for preventing data sharing, etc.

[0035] The serialization circuit 123 is electrically connected to the data transmission control circuit 115, and receives the output data packet BO and the buffer read clock signal BRCK / B from the data transmission control circuit 115. The serialization circuit 123 extracts the read data RDATA and the read valid signal RVALID from the output data packet BO in synchronization with the buffer read clock signal BRCK / B, so as to provide the serialized read data RDATA to the transmission driver 112-1 and the read valid signal RVALID to the transmission driver 112-2. The serialization circuit 123 generates the transmission read clock signals RCK-t and RCK-c from the buffer read clock signal BRCK / B, and provides the transmission read clock signals RCK-t and RCK-c to the transmission drivers 112-3 and 112-4, respectively.

[0036] The data transfer control circuit 115 includes a write error check circuit (EC WT) 131 , a data packet decoder (PACDEC) 133 , a read error check circuit (EC RD) 135 , and a data packet encoder (PAC ENC) 137 .

[0037] The write error check circuit 131 is electrically connected to the parallelization circuit 121 and receives the input data packet BI from the parallelization circuit 121. The write error check circuit 131 generates a write error check code WEC based on the input data packet BI. The write error check circuit 131 can apply a cyclic redundancy check (CRC) algorithm to generate the write error check code WEC as a checksum that can be used to check errors in the internal data IDQ.

[0038] The data packet decoder 133 is electrically connected to the parallelization circuit 121 and the write error check circuit 131, receives the input data packet BI and the buffer write clock signal BWCK / B from the parallelization circuit 121, and receives the write error check code WEC from the write error check circuit 131. The data packet decoder 133 checks whether there is any error in the input data packet BI based on the write error check code WEC. When at least one error is detected in the input data packet BI based on the write error check code WEC during the write operation to the core chip 103, the data packet decoder 133 may receive the input data packet BI from the parallelization circuit 121 again. The data packet decoder 133 decodes the input data packet BI in synchronization with the buffer write clock signal BWCK / B to generate an internal row control signal IRA and an internal column control signal ICA. The internal row control signal IRA may be a signal used in a row series operation such as an activation operation and a precharge operation to the core chip 103, and the internal column control signal ICA may be a signal used in a column series operation such as a read operation and a write operation to the core chip 103. The data packet decoder 133 generates an internal write clock signal IWCK / B based on the buffer write clock signal BWCK / B. For example, the internal write clock signal IWCK / B can be implemented in the same manner as the buffer write clock signal BWCK / B. The present disclosure is not limited to this example. When a write operation is performed on the core chip 103, the data packet decoder 133 decodes the input data packet BI to extract the header information HB and the internal data IDQ. The input data packet BI may include header information HB (which includes information such as the destination and the data packet type), data information including control signals for controlling the operation, and error safety information for error detection or safety, etc. The data packet decoder 133 is electrically connected to the core control circuit 119 and provides the internal data IDQ to the core control circuit 119 so that the internal data IDQ is stored in the core chip 103 when a write operation is performed on the core chip 103.

[0039] The read error check circuit 135 is electrically connected to the core control circuit 119 and receives the internal data IDQ from the core control circuit 119. The read error check circuit 135 generates a read error check code REC based on the internal data IDQ. The read error check circuit 135 may apply a cyclic redundancy check (CRC) algorithm to generate the read error check code REC as a checksum that can be used to check errors in the internal data IDQ.

[0040] The data packet encoder 137 is electrically connected to the data packet decoder 133, the read error check circuit 135, and the core control circuit 119, and receives the header information HB from the data packet decoder 133, receives the read error check code REC from the read error check circuit 135, and receives the internal read clock signal IRCK / B from the core control circuit 119. When a read operation is performed on the core chip 103, the data packet encoder 137 receives the internal data IDQ from the core control circuit 119. The data packet encoder 137 checks whether there is any error in the internal data IDQ received during the read operation on the core chip 103 based on the read error check code REC. When at least one error is detected in the internal data IDQ based on the read error check code REC during the read operation on the core chip 103, the data packet encoder 137 may receive the internal data IDQ from the core chip 103 again through the core control circuit 119. The data packet encoder 137 generates an output data packet BO based on the header information HB and the internal data IDQ. The output data packet BO may be a data packet used in the PCle and CXL protocols. The data packet encoder 137 generates a buffer read clock signal BRCK / B based on the internal read clock signal IRCK / B. For example, the buffer read clock signal BRCK / B may be implemented in the same manner as the internal read clock signal IRCK / B. The present disclosure is not limited to this example.

[0041] The core control circuit 119 is electrically connected to the data packet decoder 133, and receives the internal row control signal IRA, the internal column control signal ICA, the internal write clock signal IWCK / B, and the internal data IDQ from the data packet decoder 133. When a write operation is performed on the core chip 103 based on the internal row control signal IRA and the internal column control signal ICA, the core control circuit 119 receives the internal write clock signal IWCK / B and the internal data IDQ from the data packet decoder 133. The core control circuit 119 controls the core chip 103 so that the internal data IDQ is synchronized with the internal write clock signal IWCK / B and is stored in the core chip 103 when the write operation is performed on the core chip 103. When a read operation is performed on the core chip 103, the core control circuit 119 provides the internal data IDQ as data output from the core chip 103 to the data packet encoder 137. When a read operation is performed on the core chip 103, the core control circuit 119 provides the internal read clock signal IRCK / B to the data packet encoder 137.

[0042] The operation of the stacked memory device 10 configured as described above is described below with respect to two examples, namely, an example of performing a write operation on the core chip 103 and an example of performing a read operation on the core chip 103 .

[0043] For the write operation to the core chip 103, the parallelization circuit 121 receives the write data WDATA, the write valid signal WVAID, and the transmission write clock signals WCK-t and WCK-c from the receiving buffers 111-1, 111-2, and 111-3, and receives the write data WDATA when the write valid signal WVALID is activated in synchronization with the transmission write clock signals WCK-t and WCK-c to generate the parallelized input data packet BI. The data packet decoder 133 checks whether there is any error in the input data packet BI based on the write error check code WEC, and receives the input data packet BI again when at least one error is detected in the input data packet BI. The data packet decoder 133 decodes the input data packet BI to generate the internal row control signal IRA and the internal column control signal ICA. When a write operation is performed on the core chip 103 based on the internal row control signal IRA and the internal column control signal ICA, the core control circuit 119 receives the internal write clock signal IWCK / B and the internal data IDQ from the data packet decoder 133, and controls the core chip 103 so that the internal data IDQ is synchronized with the internal write clock signal IWCK / B and is stored in the core chip 103.

[0044] For a read operation on the core chip 103, the parallelization circuit 121 receives the write data WDATA, the write valid signal WVALID, and the transmission write clock signals WCK-t and WCK-c from the receiving buffers 111-1, 111-2, and 111-3, and receives the write data WDATA when the write valid signal WVALID is activated in synchronization with the transmission write clock signals WCK-t and WCK-c to generate a parallelized input data packet BI. The data packet decoder 133 checks whether there is any error in the input data packet BI based on the write error check code WEC, and receives the input data packet BI again when there is at least one error in the input data packet BI. The data packet decoder 133 can decode the input data packet BI to generate header information HB, internal row control signal IRA, and internal column control signal ICA. When a read operation is performed on the core chip 103 based on the internal row control signal IRA and the internal column control signal ICA, the core control circuit 119 can output the data output from the core chip 103 as internal data IDQ. The read error check circuit 135 may generate a read error check code REC based on the internal data IDQ. The data packet encoder 137 may check whether there is any error in the internal data IDQ based on the read error check code REC, and receive the internal data IDQ again when at least one error is detected in the internal data IDQ. The data packet encoder 137 may generate an output data packet BO based on the header information HB and the internal data IDQ. The serialization circuit 123 extracts the read data RDATA and the read valid signal RVALID from the output data packet BO in synchronization with the buffer read clock signal BRCK / B to provide the serialized read data RDATA to the transmission driver 112-1, and the read valid signal RVALID to the transmission driver 112-2. The serialization circuit 123 generates transmission read clock signals RCK-t and RCK-c from the buffer read clock signal BRCK / B, and provides the transmission read clock signals RCK-t and RCK-c to the transmission drivers 112-3 and 112-4. The transmission drivers 112 - 1 , 112 - 2 , 112 - 3 , and 112 - 4 provide read data RDATA, a read valid signal RVALID, and transmission read clock signals RCK-t and RCK-c to an external device.

[0045] Figure 3 It is shown in Figure 1 The stacked memory device 10 is shown as a timing diagram of a write operation in which write data WDATA is transmitted in synchronization with a write valid signal WVALID during a write operation.

[0046] Reference Figure 2 and Figure 3, when a write operation is performed in the stacked memory device 10, based on the transmission write clock signal WCK-t and the write valid signal WVALID, the write data WDATA is received by the transmission / receiving circuit 111. More specifically, when the write valid signal WVALID is first activated in synchronization with the transmission write clock signal WCK-t from the time period T11 to T12, the first byte (1st Byte) of the write data WDATA is received, and when the write valid signal WVALID is second activated in synchronization with the transmission write clock signal WCK-t from the time period T12 to T13, the second byte (2nd Byte) of the write data WDATA is received. In one example, during a preset time period for receiving the write data WDATA, the write valid signal WVALID is activated at a logic "high" level, but the present disclosure is not limited to this example.

[0047] Figure 4 is a table identifying data transmitted during operations of inputting packets and outputting packets according to an embodiment of the present disclosure. Figure 4 The operation of inputting and outputting a data packet consisting of 64 bytes through 16 pins (PINs) is described. The pins can be any form of electrical connection between devices, such as between the basic chip 101 and the core chip 103.

[0048] During the first burst length (BL0-7) period, the first 16 bytes B0 to B15 are input and output through the first pin PIN0 to the sixteenth pin PIN15. During the second burst length (BL8-15) period, the second 16 bytes B16 to B31 are input and output through the first pin PIN0 to the sixteenth pin PIN15. During the third burst length (BL16-23) period, the third 16 bytes B32 to B47 are input and output through the first pin PIN0 to the sixteenth pin PIN15. During the fourth burst length (BL24-31) period, the fourth 16 bytes B48 to B63 are input and output through the first pin PIN0 to the sixteenth pin PIN15. Data input and output operations can be performed according to the following steps: Figure 4 The order of the top row to the bottom row of the table or in a different order. In this example, the operation of inputting and outputting a data packet consisting of 64 bytes through 16 pins during 4 burst length periods (BL0-31) is described, but the present disclosure is not limited to this example.

[0049] Figure 5 and Figure 6 is a diagram showing an example of a data packet format according to an embodiment of the present disclosure.

[0050] like Figure 5As shown, according to the example, the data packet consists of 192 bytes, including three blocks, each of which consists of 64 bytes. The first block in the data packet includes 2 bytes of header information HB1 and HB2 and 62 bytes of information DB1. The second block in the data packet includes 4 bytes of header information HB3, HB4, HB5 and HB6, 2 bytes of error control information CB1 and CB2, and 58 bytes of information DB2. The third block in the data packet includes 2 bytes of header information HB7 and HB8, 2 bytes of error control information CB3 and CB4, and 60 bytes of information DB2 and DB3.

[0051] like Figure 6 As shown, a data packet according to another example is composed of 256 bytes, including 4 blocks, each of which is composed of 64 bytes. The first block included in the data packet may include 2 bytes of header information HB1 and HB2 and 62 bytes of information DB1. The second block included in the data packet may include 64 bytes of information DB2. The third block included in the data packet may include 64 bytes of information DB3. The fourth block included in the data packet may include 10 bytes of reserved information RSV, 4 bytes of error control information CB3 and CB4, and 50 bytes of information DB4. The reserved information RSV may include information that is protected or reserved for subsequent use.

[0052] The configuration of the above-mentioned data packet is only an example, and the number of bytes included in the data packet, the number of bytes included in the block, and the arrangement of the header information, error control information, and internal control signals can be implemented in various ways according to the embodiment.

[0053] Figure 7 2 is a block diagram showing a stacked memory device 20 according to another embodiment of the present disclosure. Figure 7 As shown, the stacked memory device 20 includes a base chip 201 and a core chip 203. The core chip 203 may be disposed on the base chip 201, disposed together with the base chip 201, or disposed above the base chip 201. The core chip 203 may include a plurality of core chips 203-1 to 203-L. Each of the plurality (L) of core chips 203-1 to 203-L may be connected to the base chip 201 through one or more through holes (e.g., Fig.10 The core chip 203 may receive various signals from the base chip 201 and exchange data with the base chip 201 through one or more through holes.

[0054] The basic chip 201 includes a transmission / reception circuit (Rx Tx) 211 , a serialization / deserialization circuit (SERDES) 213 , a memory controller (MC) 215 , an interface conversion circuit (IF CVT) 217 ​​, and a core control circuit (CORE CTR) 219 .

[0055] For write operations and read operations to the core chip 203, the send / receive circuit 211 receives data from a processor (e.g., Fig.10 The external device 403 in receives the write data WDATA, the write valid signal WVALID and the transmission write clock signals WCK-t and WCK-c. For the read operation of the core chip 203, the send / receive circuit 211 sends the read data RDATA, the read valid signal RVALID and the transmission read clock signals RCK-t and RCK-c to the external device.

[0056] The serialization / parallelization circuit 213 receives the write data WDATA to generate a parallelized input data packet (eg, Figure 8 BI in ), and when the write valid signal WVALID is activated in synchronization with the transmission write clock signals WCK-t and WCK-c, the input data packets (for example, Figure 8 BI in the memory controller 215. When a read operation is performed, the serialization / parallelization circuit 213 generates an output data packet (eg, Figure 8 BO) in the transmission / reception circuit 211 extracts the serialized read data RDATA and the read valid signal RVALID, and provides the serialized read data RDATA and the read valid signal RVALID to the transmission / reception circuit 211.

[0057] The memory controller 215 receives the data packet (eg Figure 8 BI in the core chip 203) to generate a control command for controlling the internal operation of the core chip 203 (for example, Figure 8 act, ras, cas, and we) and addresses (e.g., Figure 8 When a write operation is performed on the core chip 203, the memory controller 215 receives the input data packet (eg, Figure 8 BI in the extract control data (e.g. Figure 8 When a read operation is performed on the core chip 203, the memory controller 215 generates a read operation based on the internal output data (eg, Figure 8 IDOUT in the IO generates an output packet (for example, Figure 8 BO in) and read error check code (for example, Figure 8 REC in the ).

[0058] The interface conversion circuit 217 converts the control command (eg Figure 8 ACT, RAS, CAS and WE) into internal row control signals (e.g. Figure 8 IRA in the ) and internal column control signals (such as Figure 8 When a write operation is performed on the core chip 203, the interface conversion circuit 217 converts the control data CDQ into internal data IDQ via the interface with the memory controller 215, and provides the internal data IDQ via the interface with the core control circuit 219 to perform an operation on the core chip 203. When a read operation is performed on the core chip 203, the interface conversion circuit 217 converts the internal data IDQ into internal output data IDOUT via the interface with the control circuit 219, and provides the internal output data IDOUT to the interface with the memory controller 215.

[0059] When a write operation is performed on the core chip 203, the core control circuit 219 receives the internal data IDQ from the interface conversion circuit 217 and stores the internal data IDQ in the core chip 203. When a read operation is performed on the core chip 203, the core control circuit 219 receives the internal data IDQ output from the core chip 203 and provides the internal data IDQ to the interface conversion circuit 217.

[0060] The stacked memory device 20 configured as described above uses data packets (eg, Figure 8 BI and BO in the stack memory device 20), thereby improving scalability and performing high-speed operation when applied to or used in a stack memory system. In addition, the stack memory device 20 can be provided with a memory controller 215 that operates with different interfaces through an interface conversion circuit 217, thereby providing high-speed operation of the system on chip.

[0061] Figure 8 It is shown as Figure 7 FIG. 2 is a block diagram of an embodiment of a basic chip 201 shown in FIG. Figure 8 As shown, the basic chip 201 includes a transmitting / receiving circuit 211 , a serializing / parallelizing circuit 213 , a memory controller 215 , an interface conversion circuit 217 and a core control circuit 219 .

[0062] The transmission / reception circuit 211 includes reception buffers 211-1, 211-2, and 211-3 and transmission drivers 212-1, 212-2, 212-3, and 212-4. The reception buffer 211-1 buffers the write data WDATA serially received from the external device based on the reference voltage VREF, and provides the buffered write data WDATA to the serialization / parallelization circuit 213. The reception buffer 211-2 receives and buffers the write valid signal WVALID based on the reference voltage VREF, and provides the buffered write valid signal WVALID to the serialization / parallelization circuit 213. The reception buffer 211-3 receives and buffers the transmission write clock signals WCK-t and WCK-c, and provides the buffered transmission write clock signals WCK-t and WCK-c to the serialization / parallelization circuit 213. The transmission driver 212-1 transmits the read data RDATA serially received from the serialization / parallelization circuit 213 to the external device. The transmission driver 212-2 transmits the read valid signal RVALID received from the serialization / parallelization circuit 213 to the external device. The transmission drivers 212-3 and 212-4 transmit the transmission read clock signals RCK-t and RCK-c received from the serialization / parallelization circuit 213 to the external device.

[0063] The serialization / parallelization circuit 213 includes a parallelization circuit 221 and a serialization circuit 223 .

[0064] The parallelization circuit 221 is electrically connected to the receiving buffers 211-1, 211-2, and 211-3, and receives the write data WDATA, the write valid signal WVALID, and the transmission write clock signals WCK-t and WCK-c. When the write valid signal WVALID is activated in synchronization with the transmission write clock signals WCK-t and WCK-c, the parallelization circuit 221 receives the write data WDATA to generate and output the parallelized input data packet BI. The parallelization circuit 221 outputs the transmission write clock signals WCK-t and WCK-c as the buffer write clock signal BWCK / B. The parallelization circuit 221 is electrically connected to the memory controller 215, and provides the input data packet BI and the buffer write clock signal BWCK / B to the memory controller 215. The input data packet BI can be implemented or formatted as a data packet used in the PCIe and CXL protocols.

[0065] The serialization circuit 223 is electrically connected to the memory controller 215 and receives an output data packet BO, a buffer read clock signal BRCK / B, and a read error check code REC from the memory controller 215. When at least one error is detected in the output data packet BO based on the read error check code REC, the serialization circuit 223 may receive the output data packet BO from the memory controller 215 again. The serialization circuit 223 extracts the read data RDATA and the read valid signal RVALID from the output data packet BO in synchronization with the buffer read clock signal BRCK / B, and provides the serialized read data RDATA to the transmission driver 212-1 and the read valid signal RVALID to the transmission driver 212-2. The serialization circuit 223 generates transmission read clock signals RCK-t and RCK-c from the buffer read clock signal BRCK / B, and provides the transmission read clock signals RCK-t and RCK-c to the transmission drivers 212-3 and 212-4, respectively. The output data packet BO may be implemented or formatted as a data packet used in the PCle and CXL protocols.

[0066] The memory controller 215 is electrically connected to the serialization / parallelization circuit 213 and the interface conversion circuit 217, receives the input data packet BI and the buffer write clock signal BWCK / B from the serialization / parallelization circuit 213, and receives the internal output data IDOUT and the internal output clock signal IDOCK / B from the interface conversion circuit 217. The memory controller 215 generates control commands act, ras, cas and we and address add for controlling the internal operation of the core chip 203 based on the input data packet BI and the buffer write clock signal BWCK / B. The internal operation of the core chip 203 includes an activation operation, a read operation, a write operation, and a precharge operation. When performing a write operation on the core chip 203, the memory controller 215 extracts the control data CDQ from the input data packet BI, generates the control clock signal CCLK from the buffer write clock signal BWCK / B, and provides the control data CDQ and the control clock signal CCLK to the interface conversion circuit 217. When a read operation is performed on the core chip 203, the memory controller 215 provides an output data packet BO generated based on the internal output data IDOUT and the internal output clock signal IDOCK / B, a buffer read clock signal BRCK / B and a read error check code REC to the serialization / parallelization circuit 213. The read error check code REC can be generated based on a cyclic redundancy check (CRC) algorithm.

[0067] The interface conversion circuit 217 is electrically connected to the memory controller 215 and the core control circuit 219, and receives control commands act, ras, cas, and we, address add, control data CDQ, and control clock signal CCLK from the memory controller 215, and receives internal data IDQ and output clock signal OCK / B from the core control circuit 219. The interface conversion circuit 217 converts the control commands act, ras, cas, and we and address add into internal row control signals IRA and internal column control signals ICA, and provides the internal row control signals IRA and internal column control signals ICA to the core control circuit 219. The control commands act, ras, cas, and we and address add may be provided by an interface with the memory controller 215, and the internal row control signals IRA and internal column control signals ICA may be provided by an interface with the core control circuit 219 that operates the core chip 203 using the internal row control signals IRA and internal column control signals ICA. The method by which the control commands act, ras, cas, and we and address add are converted into the internal row control signals IRA and internal column control signals ICA may be determined in various ways according to the embodiment.

[0068] When a write operation is performed on the core chip 203, the interface conversion circuit 217 converts the control data CDQ and the control clock signal CCLK into the internal data IDQ and the input clock signal INCK / B, and provides the internal data IDQ and the input clock signal INCK / B to the core control circuit 219. Based on the operation with the core chip 203, the control data CDQ and the control clock signal CCLK can be provided by the interface with the memory controller 215, and the internal data IDQ and the input clock signal INCK / B can be provided by the interface with the core control circuit 219. The method by which the control data CDQ and the control clock signal CCLK are converted into the internal data IDQ and the input clock signal INCK / B can be determined in various ways according to the embodiment. When a read operation is performed on the core chip 203, the interface conversion circuit 217 converts the internal data IDQ and the output clock signal OCK / B into the internal output data IDOUT and the internal output clock signal IDOCK / B, and provides the internal output data IDOUT and the internal output clock signal IDOCK / B to the memory controller 215. The internal data IDQ and the output clock signal OCK / B may be provided by an interface with the core control circuit 219 based on the operation with the core chip 203, and the internal output data IDOUT and the internal output clock signal IDOCK / B may be provided by an interface with the memory controller 215. The method by which the internal data IDQ and the output clock signal OCK / B are converted into the internal output data IDOUT and the internal output clock signal IDOCK / B may be determined in various ways according to the embodiment.

[0069] When a write operation is performed on the core chip 203 based on the internal row control signal IRA and the internal column control signal ICA, the core control circuit 219 receives the internal data IDQ and the input clock signal INCK / B from the interface conversion circuit 217. The core control circuit 219 controls the core chip 203 so that when a write operation is performed on the core chip 203, the internal data IDQ is synchronized with the input clock signal INCK / B and is stored in the core chip 203. When a read operation is performed on the core chip 203, the core control circuit 219 provides the data output from the core chip 203 as the internal data IDQ to the interface conversion circuit 217. When a read operation is performed on the core chip 203, the core control circuit 219 provides the output clock signal OCK / B to the interface conversion circuit 217.

[0070] The operation of the stacked memory device 20 configured as described above is described below with respect to two examples, namely, an example of performing a write operation on the core chip 203 and an example of performing a read operation on the core chip 203 .

[0071] For the write operation to the core chip 203, the parallelization circuit 221 receives the write data WDATA, the write valid signal WVALID, and the transmission write clock signals WCK-t and WCK-c from the receiving buffers 211-1, 211-2, and 211-3, and receives the write data WDATA when the write valid signal WVALID is activated in synchronization with the transmission write clock signals WCK-t and WCK-c to generate the parallelized input data packet BI. The memory controller 215 generates the control commands act, ras, cas, and we and the address add based on the input data packet BI and the buffer write clock signal BWCK / B, extracts the control data CDQ from the input data packet BI, and generates the control clock signal CCLK from the buffer write clock signal BWCK / B. The interface conversion circuit 217 converts the control commands act, ras, cas, and we into the internal row control signal IRA and the internal column control signal ICA, and converts the control data CDQ and the control clock signal CCLK into the internal data IDQ and the input clock signal INCK / B, respectively. The core control circuit 219 controls the core chip 203 so that the internal data IDQ is synchronized with the input clock signal INCK / B and is stored in the core chip 203 .

[0072] For the read operation of the core chip 203, the parallelization circuit 221 receives the write data WDATA, the write valid signal WVALID and the transmission write clock signals WCK-t and WCK-c from the receiving buffers 211-1, 211-2 and 211-3, and receives the write data WDATA when the write valid signal WVALID is activated in synchronization with the transmission write clock signals WCK-t and WCK-c to generate the parallelized input data packet BI. The memory controller 215 generates the control commands act, ras, cas and we and the address add based on the input data packet BI and the buffer write clock signal BWCK / B, extracts the control data CDQ from the input data packet BI, and generates the control clock signal CCLK from the buffer write clock signal BWCK / B. The interface conversion circuit 217 converts the control commands act, ras, cas, we into the internal row control signal IRA and the internal column control signal ICA. The core control circuit 219 outputs the data output from the core chip 203 as internal data IDQ, and outputs the output clock signal OCK / B based on the internal row control signal IRA and the internal column control signal ICA. The interface conversion circuit 217 converts the internal data IDQ and the output clock signal OCK / B into internal output data IDOUT and the internal output clock signal IDOCK / B. The memory controller 215 generates an output data packet BO, a buffer read clock signal BRCK / B, and a read error check code REC based on the internal output data IDOUT and the internal output clock signal IDOCK / B. When at least one error is detected in the output data packet BO based on the read error check code REC, the serialization circuit 223 receives the output data packet BO from the memory controller 215 again. The serialization circuit 223 extracts the read data RDATA and the read valid signal RVALID from the output data packet BO in synchronization with the buffer read clock signal BRCK / B, and provides the serialized read data RDATA to the transmission driver 212-1 and the read valid signal RVALID to the transmission driver 212-2. The serialization circuit 223 generates transmission read clock signals RCK-t and RCK-c from the buffer read clock signal BRCK / B, and provides the transmission read clock signals RCK-t and RCK-c to the transmission drivers 212-3 and 212-4, respectively. The transmission drivers 212-1, 212-2, 212-3, 212-4 can transmit the read data RDATA, the read valid signal RVALID, and the transmission read clock signals RCK-t and RCK-c to the external device.

[0073] Fig. 9 is a block diagram showing a stacked memory device 30 according to another embodiment of the present disclosure. Fig. 9As shown, the stacked memory device 30 includes a base chip 301 and a core chip 303. The core chip 303 may be disposed on the base chip 301, disposed together with the base chip 301, or disposed above the base chip 301. The core chip 303 may include a plurality of (L) core chips 303-1 to 303-L. Each of the plurality of core chips 303-1 to 303-L may be connected to the base chip 301 through one or more through holes (e.g., Fig.10 The core chip 303 may receive various signals from the base chip 301 and exchange data with the base chip 301 through one or more through holes.

[0074] The base chip 301 includes a transmission / reception circuit (Rx Tx) 311 , a serialization / parallelization circuit (SERDES) 313 , a memory controller (MC) 315 , a calculation circuit (CPT LOG) 316 , an interface conversion circuit (IF CVT) 317 , and a core control circuit (CORE CTR) 319 .

[0075] The calculation circuit 316 is electrically connected to the serialization / parallelization circuit 313 and the memory controller 315, and performs the calculation operation of the serialization / parallelization circuit 313 and the calculation operation of the memory controller 315. In addition to the calculation circuit 316, Fig. 9 The stacked memory device 30 shown may be Figure 7 Therefore, the transmission / reception circuit 311, the serialization / parallelization circuit 313, the memory controller 315, the interface conversion circuit 317 and the core control circuit 319 can be implemented in the same manner as previously described. Figure 7 The transmitting / receiving circuit 211, the serializing / parallelizing circuit 213, the memory controller 215, the interface conversion circuit 217 and the core control circuit 219 are implemented in the same manner as described.

[0076] Fig.10 is a block diagram showing a stacked memory system 40 according to an embodiment of the present disclosure. Fig.10 As shown, the stacked memory system 40 includes a stacked memory device 401 , a processor 403 , an interposer 405 , and a substrate 407 .

[0077] The interposer 405 may be disposed on, with, or above the substrate 407, and the stacked memory device 401 and the processor 403 may be disposed on, with, or above the interposer 405. The interposer 405 may electrically connect the substrate 407, the stacked memory device 401, and the processor 403 to each other. The spacing difference between the substrate 407, the stacked memory device 401, and the processor 403 is large, so that the substrate 407, the stacked memory device 401, and the processor 403 can be electrically connected to each other using the interposer 405 including a plurality of formed wires or other conductive connection devices.

[0078] The processor 403 includes a processor interface circuit (PPHY) 421. The processor 403 provides a write control signal and an address including commands for controlling various internal operations of the stacked memory device 401 to the stacked memory device 401 through the processor interface circuit 421, and receives a read control signal from the stacked memory device 401 through the processor interface circuit 421. The write control signal may include write data WDATA, a write valid signal WVALID, and transmission write clock signals WCK-t and WCK-c, such as Figure 1 , Figure 7 and Fig. 9 The read control signal may include read data RDATA, a read valid signal RVALID, and transmission read clock signals RCK-t and RCK-c, as shown in FIG. Figure 1 , Figure 7 and Fig. 9 shown.

[0079] The stacked memory device 401 includes a base chip 411 and core chips 414, 415, 417, and 419. The stacked memory device 401 may be similar to Figure 1 The stacked memory device 10 shown, Figure 7 The stacked memory device 20 and / or Fig. 9 The stacked memory device 30 shown is implemented.

[0080] The core chips 414 , 415 , 417 , and 419 may be sequentially stacked on, together with, or over the base chip 411 , and receive various signals from the base chip 411 through one or more vias 441 .

[0081] The base chip 411 includes a core interface circuit (CPHY) 431 and an operation control circuit (OP CTR) 433. The core interface circuit 431 enables communication with the processor interface circuit 421 to transmit a write control signal sent from the processor 403 to the operation control circuit 433, and provides a read control signal generated by the operation control circuit 433 to the processor 403. The core interface circuit 431 can be used Figure 1 The transmission / reception circuit 111, the serialization / parallelization circuit 113 and the data transmission control circuit 115 are shown. Figure 7 The transmission / reception circuit 211 and the serialization / parallelization circuit 213 shown, and / or Fig. 9 The transmission / reception circuit 311 and the serialization / parallelization circuit 313 shown in the figure are implemented. The operation control circuit 433 can be used Figure 1 The core control circuit 119 shown, Figure 7 The memory controller 215, the interface conversion circuit 217 and the core control circuit 219 shown, and / or Fig. 9 The embodiment is implemented by the memory controller 315, computing circuit 316, interface conversion circuit 317 and core control circuit 319 shown.

[0082] Concepts are disclosed in conjunction with the various embodiments described above. It will be appreciated by those skilled in the art that various modifications, additions and substitutions are possible without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed in this specification should not be considered from a restrictive perspective, but from an illustrative perspective. The scope of the present disclosure is not limited to the above description, and all different features within the equivalent range should be interpreted as being included in the present disclosure.

Claims

1. A stacked memory device, comprising: Basic chip; as well as a core chip, which is stacked with the base chip and electrically connected to the base chip, Wherein, the basic chip includes: a sending / receiving circuit that receives write data, a write valid signal, and a transmission write clock signal; a serialization / parallelization circuit that receives the write data based on the write valid signal in synchronization with the transmission write clock signal and generates a parallelized input data packet from the write data; and The data transmission control circuit decodes the parallelized input data packet to extract first internal data stored in the core chip when a write operation is performed on the core chip.

2. The stacked memory device according to claim 1, wherein: When the write valid signal is activated, the transmission / reception circuit receives the write data serially input during a burst length period.

3. The stacked memory device according to claim 1, wherein: The parallelized input data packets are formatted as data packets used in the PCIe protocol and the CXL protocol, PCIe refers to Peripheral Component Interconnect Express, and CXL refers to Compute Link Express.

4. The stacked memory device according to claim 1, wherein: The data transmission control circuit generates a write error check code based on the parallelized input data packet, and receives the parallelized input data packet again from the serialization / parallelization circuit when at least one error is detected in the parallelized input data packet based on the write error check code.

5. The stacked memory device according to claim 1, wherein: The data transmission control circuit decodes the parallelized input data packet to generate an internal row control signal for a row series operation and an internal column control signal for a column series operation for the core chip. 6 . The stacked memory device of claim 1 , further comprising a core control circuit that controls the core chip so that the first internal data is stored in the core chip when the write operation is performed. 7 . The stacked memory device of claim 1 , further comprising a core control circuit which outputs second internal data output from the core chip when a read operation is performed on the core chip.

8. The stacked memory device according to claim 7, wherein: When performing the read operation, the data transfer control circuit generates an output data packet based on the second internal data.

9. The stacked memory device according to claim 8, wherein: The output data packets are formatted as data packets used in the PCIe protocol and the CXL protocol, PCIe refers to Peripheral Component Interconnect Express, and CXL refers to Compute Link Express.

10. The stacked memory device according to claim 8, wherein: When the read operation is performed on the core chip, the data transmission control circuit generates a read error check code based on the second internal data, and when at least one error is detected in the second internal data based on the read error check code, the data transmission control circuit receives the second internal data from the core control circuit again.

11. The stacked memory device according to claim 7, wherein: The data transfer control circuit extracts read data and a read valid signal from the output data packet.

12. The stacked memory device according to claim 11, wherein: The transmission / reception circuit transmits the read data and the read valid signal.

13. A stacked memory device comprising: a serialization / parallelization circuit that: receives write data when a write valid signal is activated in synchronization with a transmission write clock signal, and generates a parallelized input data packet from the write data; and A data transmission control circuit, which: decodes the parallelized input data packet; generates an internal row control signal and an internal column control signal; extracts first internal data from the parallelized input data packet when a write operation is performed on the core chip based on the internal row control signal and the internal column control signal; receives data output from the core chip as second internal data when a read operation is performed on the core chip based on the internal row control signal and the internal column control signal; and generates an output data packet based on the second internal data and header information.

14. The stacked memory device according to claim 13, wherein: The serialization / deserialization circuit extracts read data and a read valid signal from the output data packet.

15. The stacked memory device according to claim 14, further comprising a transmission / reception circuit that receives the write data, the write valid signal and the transmission write clock signal, and transmits the read data, the read valid signal and the transmission read clock signal.

16. The stacked memory device according to claim 13, wherein: The serialization / deserialization circuit generates the deserialized input data packets formatted as data packets used in the PCIe protocol and the CXL protocol, PCIe refers to Peripheral Component Interconnect Express, and CXL refers to Compute Link Express.

17. The stacked memory device according to claim 13, wherein: The data transfer control circuit generates the output data packet formatted as a data packet used in a PCIe protocol and a CXL protocol, PCIe refers to Peripheral Component Interconnect Express, and CXL refers to Compute Link Express.

18. The stacked memory device according to claim 13, wherein: When at least one error is detected in the parallelized input data packet according to a write error check code generated based on the parallelized input data packet during the write operation, the data transfer control circuit receives the parallelized input data packet from the serialization / parallelization circuit again.

19. The stacked memory device according to claim 13, wherein: When at least one error is detected in the second internal data according to a read error check code generated based on the second internal data during the read operation, the data transfer control circuit receives the second internal data from the core control circuit again.

20. A stacked memory device comprising a plurality of core chips connected to each other through one or more through-holes and stacked with a base chip, in, The basic chip comprises: a sending / receiving circuit that receives write data, a write valid signal, and a transmission write clock signal; a serialization / parallelization circuit that receives the write data based on the write valid signal in synchronization with the transmission write clock signal and generates a parallelized input data packet from the write data; a memory controller that generates control commands and addresses based on the parallelized input data packets; and An interface conversion circuit converts the control command and the address into an internal row control signal for row series operation for the plurality of core chips and an internal column control signal for column series operation for the plurality of core chips.

21. The stacked memory device according to claim 20, wherein: The interface conversion circuit converts the control command and the address into the internal row control signal and the internal column control signal through a first interface with the memory controller, and provides the internal row control signal and the internal column control signal via a second interface to perform operations on the core chip.

22. The stacked memory device according to claim 20, in, When performing a write operation on the core chip, the memory controller extracts control data from the parallelized input data packet, and The interface conversion circuit converts the control data into internal data stored in the core chip.

23. The stacked memory device according to claim 20, wherein: When a read operation is performed on the core chip, the interface conversion circuit receives data output from the core chip and converts the internal data into internal output data.

24. The stacked memory device according to claim 23, wherein: The memory controller generates an output data packet and a read error check code based on the internal output data.

25. The stacked memory device according to claim 20 further includes a computing circuit, which is electrically connected to the serialization / parallelization circuit and the memory controller, and the computing circuit performs computing operations of the serialization / parallelization circuit and computing operations of the memory controller.

26. A method comprising: When the write valid signal is activated in synchronization with the transmission write clock signal, the serial write data is received by the basic chip; generating an input data packet by parallelizing the serial write data; as well as When a write operation is performed on the core chip, the input data packet is decoded to generate at least two control signals, and first internal data is extracted based on the at least two control signals to store the first internal data in the core chip.

27. The method according to claim 26, wherein: The at least two control signals include an internal row control signal and an internal column control signal, and the method further includes: When a read operation is performed on the core chip based on the internal row control signal and the internal column control signal, receiving data output from the core chip as second internal data, and An output data packet is generated based on the second internal data.

Images