Storage unit, memory, electronic equipment and data read-write method

Abstract

A memory cell, a memory, an electronic device, and a data read-write method, the memory cell including: a write transistor including a first electrode, a second electrode, and a first gate electrode; a read transistor including a third electrode, a fourth electrode, and a second gate electrode; a switching transistor including a fifth electrode, a sixth electrode, and a third gate electrode; a storage node; wherein the fourth electrode is connected with the second electrode; the first electrode is connected with the storage node, and the first gate electrode is connected with the writing word line; the third electrode is connected with the first bit line, and the second gate electrode is connected with the storage node; the fifth electrode is connected with the fourth electrode and the second electrode, the sixth electrode is connected with the second bit line, and the third gate electrode is connected with the read word line; the write transistor is used for controlling storage data to be written into the storage node, and the read transistor is used for controlling reading of the storage data. The storage unit provided by the embodiment of the invention is convenient to realize read-write operation, simple in structure, easy to manufacture and small in occupied area.

Description

Technical Field

[0001] The embodiments of the present application relate to but are not limited to the field of design and manufacture of semiconductor devices, and in particular to a storage unit, a memory, an electronic device, and a data reading and writing method. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0005] The embodiments of the present application provide a storage unit, a memory, an electronic device and a data reading and writing method. The storage unit facilitates reading and writing operations, has a simple structure, is easy to manufacture, and occupies a small area.

[0006] An embodiment of the present application provides a storage unit, the storage unit comprising:

[0007] A write transistor including a first electrode, a second electrode and a first gate electrode;

[0008] a read transistor including a third electrode, a fourth electrode, and a second gate electrode;

[0009] a switching transistor comprising a fifth electrode, a sixth electrode and a third gate electrode;

[0010] Storage nodes;

[0011] Wherein, the fourth electrode is connected to the second electrode;

[0012] The first electrode is connected to the storage node, and the first gate electrode is connected to a write word line;

[0013] The third electrode is connected to the first bit line, and the second gate electrode is connected to the storage node;

[0014] The fifth electrode is connected to the fourth electrode and the second electrode, the sixth electrode is connected to the second bit line, and the third gate electrode is connected to the read word line;

[0015] The write transistor is used to control the writing of storage data into the storage node, and the read transistor is used to control the reading of storage data.

[0016] Exemplarily, the switch transistor remains in an on state at least part of the time during the data writing phase to write the high voltage of the second bit line into the storage node.

[0017] Exemplarily, the switch transistor remains turned on during a data reading phase to write the low voltage of the second bit line into the fourth electrode.

[0018] An embodiment of the present application also provides a memory, which includes at least one storage unit provided in the above embodiment of the present application.

[0019] Exemplarily, the memory includes:

[0020] A plurality of storage units are arrayed along a first direction and a second direction; the first direction intersects the second direction;

[0021] a plurality of the write word lines and a plurality of read word lines extending along the first direction;

[0022] A plurality of the first bit lines and a plurality of second bit lines extend along the second direction.

[0023] Exemplarily, the third gate electrodes of the plurality of memory cells spaced apart and distributed along the first direction are connected to the same read word line.

[0024] Exemplarily, the first gate electrodes of the plurality of memory cells spaced apart and distributed along the first direction are connected to the same write word line.

[0025] Exemplarily, the third electrodes of the plurality of memory cells spaced apart and distributed along the second direction are connected to the same first bit line.

[0026] Exemplarily, the sixth electrodes of the plurality of memory cells spaced apart and distributed along the second direction are connected to the same second bit line.

[0027] An embodiment of the present application also provides an electronic device, which includes the memory provided in the above embodiment of the present application.

[0028] The embodiment of the present application further provides a data reading and writing method, which is performed based on the storage unit or the memory provided in the embodiment of the present application; the data reading and writing method includes:

[0029] Data reading phase:

[0030] Supplying a high voltage to a read word line so that the read transistor is turned on when the storage node stores data "1" and is turned off when the storage node stores data "0";

[0031] Data writing phase:

[0032] Provide a high voltage to the write word line and a low voltage to the read word line, so that the switch transistor is turned off and the write transistor is turned on;

[0033] A data voltage is provided to the first bit line so that the voltage of the storage node is V data +V th , V data is the data voltage, V th is the threshold voltage of the read transistor.

[0034] Exemplarily, in the data reading phase, the data reading and writing method further includes: providing a low voltage to the second bit line, providing a low voltage to the write word line, and reading the stored data voltage through the first bit line.

[0035] Exemplarily, in the data reading phase, the data reading and writing method further includes: providing a low voltage to the first bit line, providing a low voltage to the write word line, and reading the stored data voltage through the second bit line.

[0036] Exemplarily, in the data writing stage, before providing a low voltage to the read word line, the data reading and writing method further includes: providing a high voltage to the read word line, providing a high voltage to the write word line, and providing a voltage V to the second bit line. pre , the storage node is charged to V by the second bit line pre .

[0037] For example, V pre >V data"1” +V th , V data"1” is the data voltage of the first bit line when the written data is "1".

[0038] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or understood by practicing the present application. The objects and advantages of the present application can be realized and obtained by the structures particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0040] Figure 1A logic circuit diagram of a storage unit provided in some embodiments of the present application;

[0041] Figure 2 A logic circuit diagram of a memory provided in some embodiments of the present application;

[0042] Figure 3 A timing diagram of a memory cell according to some embodiments of the present application;

[0043] Figure 4 A timing diagram of a memory cell according to some embodiments of the present application;

[0044] Figure 5 A timing diagram of a memory cell according to some embodiments of the present application;

[0045] Figure 6 A timing diagram of a memory cell according to some embodiments of the present application;

[0046] Figure 7 Schematic diagram of an IV curve of a read transistor of a memory cell in a data reading phase according to some embodiments of the present application. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solution and advantages of the present application more clear, the embodiments of the present application will be described in detail with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.

[0048] The embodiments of the present application are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present application are not limited to the shapes or values ​​shown in the drawings.

[0049] The ordinal numbers such as "first" and "second" in this application are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0050] In this application, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on this application. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

[0051] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0052] In the present application, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.

[0053] In the present application, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or a change in the direction of current during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present application, unless otherwise specified, the "source electrode" and the "drain electrode" may be interchanged.

[0054] In the present application, "electrical connection" or "connection" includes the situation where the components are connected together through an element with some electrical function, such as electrical signal connection (coupled connection, such as coupled to), or physical direct connection. There is no particular limitation on "element with some electrical function" as long as it can transfer electrical signals between the connected components. Examples of "element with some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0055] T2T2 An embodiment of the present application provides a storage unit.

[0056] Figure 1 A logic circuit diagram of a storage unit provided in some embodiments of the present application. Figure 1 As shown, the storage unit includes: a write transistor T1, a read transistor T2, a switch transistor T3 and a storage node SN;

[0057] The write transistor T1 includes a first electrode P1, a second electrode P2 and a first gate electrode G1;

[0058] The read transistor T2 includes a third electrode P3, a fourth electrode P4 and a second gate electrode G2;

[0059] The switch transistor T3 includes a fifth electrode P5, a sixth electrode P6 and a third gate electrode G3;

[0060] Wherein, the fourth electrode P4 is connected to the second electrode P2;

[0061] The first electrode P1 is connected to the storage node SN, and the first gate electrode G1 is connected to the write word line W_WL;

[0062] The third electrode P3 is connected to the first bit line BL1, and the second gate electrode G2 is connected to the storage node SN;

[0063] The fifth electrode P5 is connected to the fourth electrode P4 and the second electrode P2, the sixth electrode P6 is connected to the second bit line BL2, and the third gate electrode G3 is connected to the read word line R_WL;

[0064] The write transistor T1 is used to control the writing of storage data into the storage node SN, and the read transistor T2 is used to control the reading of storage data.

[0065] Through the above configuration, the write transistor T1 can control the controllable connection between the second gate electrode G2 and the fourth electrode. When the two are connected, the storage data can be written into the storage node SN through the first bit line BL1. At this time, the read transistor T2 is connected in a diode manner, and the write voltage is V data +V th , therefore, reading the V of transistor T2 th be compensated.

[0066] By setting the switch transistor T3, the high voltage or low voltage of the second bit line BL2 can be controllably written into the storage node SN or the read transistor T2 to better cooperate with the read and write operations.

[0067] Exemplarily, the second gate electrode G2 is shared as a storage node SN.

[0068] Exemplarily, the switch transistor T3 remains in an on state at least part of the time during the data writing phase to write the high voltage of the second bit line BL2 into the storage node SN. The above configuration can controllably charge the high voltage of the second bit line into the storage node in advance, so that the read transistor T2 can be kept turned on during the data writing phase, facilitating writing storage data to the storage node.

[0069] Exemplarily, the switch transistor T3 remains turned on during the data reading phase to write the low voltage of the second bit line BL2 into the fourth electrode P4. The above configuration enables the read transistor T2 to be turned on and off accordingly during the data reading phase to achieve data reading.

[0070] Exemplarily, the storage unit may be a 3T0C structure.

[0071] An embodiment of the present application also provides a memory, which includes at least one storage unit provided in the above embodiment of the present application.

[0072] Figure 2 The logic circuit diagram of the memory provided by the exemplary embodiment of the present application. Figure 2 As shown, the memory includes:

[0073] A plurality of storage units distributed in an array along a first direction and a second direction;

[0074] a plurality of write word lines W_WL and a plurality of read word lines R_WL extending along the first direction;

[0075] A plurality of first bit lines BL1 and a plurality of second bit lines BL2 extend along the second direction.

[0076] For example, Figure 2 As shown, the third gate electrodes G3 of the plurality of memory cells spaced apart and distributed along the first direction may be connected to the same read word line R_WL.

[0077] For example, Figure 2 As shown, the first gate electrodes G1 of the plurality of memory cells spaced apart and distributed along the first direction may be connected to the same write word line W_WL;

[0078] For example, Figure 2 As shown, the third electrodes P3 of the plurality of memory cells spaced apart and distributed along the second direction are connected to the same first bit line BL1.

[0079] For example, Figure 2 As shown, the sixth electrodes P6 of the plurality of memory cells spaced apart and distributed along the second direction are connected to the same second bit line BL2.

[0080] The first direction intersects with the second direction, for example, they may be perpendicular to each other. Figure 2 The X direction shown, the second direction can be as follows Figure 2 Y direction shown.

[0081] like Figure 2 As shown, one end of the first bit line BL1 is controllably connected to the voltage signal terminal VPRE through a switch transistor, and the other end of the first bit line BL1 is connected to the sense amplifier circuit SA; in the data writing stage, the sense amplifier circuit SA is used to provide the data voltage V to the first bit line BL1 data In the data reading phase, the sense amplifier circuit SA is used to sense the data voltage V stored in the storage node SN. data ; For BL1, the data voltage V dataThe voltage other than the voltage is provided by the voltage signal terminal VPRE; the input end of the second bit line BL2 includes two branches, the first branch is controllably connected to the voltage signal terminal Vcom through a switching transistor, and the second branch is controllably connected to the voltage signal terminal VPRE through a switching transistor. In the data writing stage, the voltage signal terminal VPRE is used to provide a voltage signal to the second bit line BL2; in the data reading stage, the voltage signal terminal Vcom is used to provide a voltage signal to the second bit line BL2.

[0082] Exemplarily, the memory may further include a substrate, and the first direction and the second direction are both parallel to the substrate.

[0083] Exemplarily, the memory may be a 3D memory, such as a 3D DRAM or other memory. The storage unit of the 3D memory may be a 3T0C structure.

[0084] An embodiment of the present application also provides an electronic device, which includes the memory provided in the above embodiment of the present application.

[0085] Exemplarily, the electronic device may be: a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply, etc. The storage device may include a memory in a computer, etc., which is not limited here.

[0086] The embodiment of the present application also provides a data reading and writing method, and the data reading and writing method is performed based on the storage unit or the memory provided by the embodiment of the present application.

[0087] The following embodiments of the present application take the case where the switch transistor, the write transistor, and the read transistor are all N-type transistors as an example to illustrate the data reading and writing method of the embodiments of the present application. The case where one or more of the above transistors are P-type transistors and the change of the data reading and writing method caused by the change of the transistor type also falls within the protection scope of the present application.

[0088] Before the data write operation, the storage node SN is precharged with a high voltage through the second bit line BL2. In order to achieve V th Compensation, V th is the threshold voltage of the read transistor, the data voltage V data It flows through the source and drain electrodes of the read transistor, enters the write transistor through the bypass, and is finally written into the second gate electrode of the read transistor (which can work as the storage node SN). In this process, the read transistor is connected in a diode manner, and the write voltage is V data +V th Therefore, reading the transistor's V th be compensated.

[0089] The embodiment of the present application further provides a data reading and writing method, which is performed based on the storage unit or the memory provided in the embodiment of the present application; the data reading and writing method includes:

[0090] Data reading phase:

[0091] Supplying a high voltage to the read word line so that the read transistor is turned on when the storage node stores data "1" and is turned off when the storage node stores data "0";

[0092] Data writing phase:

[0093] Provide a high voltage to the write word line and a low voltage to the read word line, so that the switch transistor is turned off and the write transistor is turned on;

[0094] A data voltage is provided to the first bit line so that the voltage of the storage node is V data +V th , V data is the data voltage, V th is the threshold voltage of the reading transistor.

[0095] Exemplarily, in the data reading phase, the data reading and writing method further includes: providing a low voltage to the second bit line, providing a low voltage to the write word line, and reading the stored data voltage through the first bit line.

[0096] Exemplarily, in the data reading phase, the data reading and writing method further includes: providing a low voltage to the first bit line, providing a low voltage to the write word line, and reading the stored data voltage through the second bit line.

[0097] Exemplarily, in the data writing stage, before providing a low voltage to the read word line, the data reading and writing method further includes: providing a high voltage to the read word line, providing a high voltage to the write word line, and providing a voltage V to the second bit line. pre , the voltage of the storage node is charged to V by the second bit line pre .

[0098] For example, V pre >V data"1” +V th , V data"1” is the data voltage of the first bit line when the written data is "1".

[0099] Figure 3 A timing diagram of a memory cell according to some embodiments of the present application; Figure 4 1 is a timing diagram of a storage unit of some embodiments of the present application. Figure 3 and Figure 4 For example, the data reading and writing method includes:

[0100] Data reading phase:

[0101] Providing a low voltage (eg, ground voltage) to the second bit line BL2;

[0102] A high voltage is provided to the read word line R_WL. At this time, the switch transistor T3 is turned on, the write transistor T1 is turned off, and the second gate electrode G2 of the read transistor T2 stores a voltage (V data +V th ), the source electrode (fourth electrode P4) of the read transistor T2 writes the low voltage V of the second bit line BL2 low , so at this time, the voltage difference V between the second gate electrode G2 and the source electrode (fourth electrode P4) of the transistor T2 is read GS =V data +V th -V low .

[0103] When the storage node SN stores data "1" (V GS >0) is turned on, and the stored data is “0” (V GS <0), at this time, the stored data voltage V can be obtained by reading the voltage on the first bit line BL1. data Is it "1" or "0"?

[0104] Data writing phase:

[0105] The second bit line BL2 is precharged to a voltage of V pre , V pre >V data"1” +V th ; V data"1” The data voltage of the first bit line BL1 when the written data is "1";

[0106] A high voltage is provided to the write word line W_WL and the read word line R_WL, so that the switch transistor T3 and the write transistor T1 are turned on, and the storage node SN is charged to V by the second bit line BL2. pre Then, the high voltage of the write word line W_WL is maintained, a low voltage is provided to the read word line R_WL, the write transistor T1 remains turned on, and the switch transistor T3 is turned off;

[0107] A given data voltage is provided to the first bit line BL1, because the read transistor T2 is in a diode connection state at this time, so that the storage node SN is discharged to V data +V th , V th Get compensated.

[0108] exist Figure 3 and Figure 4In the example, the different potentials of the first bit line BL1 are used to determine whether the data is "1" or "0". In addition, the roles of BL1 and BL2 can be interchanged during the data reading phase, and a low voltage (such as ground voltage) can be provided to the first bit line BL1, thereby using the different voltages output by the second bit line BL2 to determine whether the data is "1" or "0". Figure 5 and Figure 6 As shown in the timing diagram.

[0109] Figure 3 and Figure 4 In contrast, during the data writing phase, Figure 3 The time when W_WL in the voltage change phase of BL1 ends the high voltage is later than that in the voltage change phase of BL1, so that the coupling on the storage node SN is small; because at this time, in order to keep the read transistor T2 off and not affect the data written in the previous period, the BL1 signal can only jump from low to high. At this time, extending the time when W_WL keeps the high voltage can delay the turning off of the write transistor T1, so that the storage node SN is still connected to the external circuit through T1, so that the coupling on the storage node SN is small; Figure 4 The W_WL in the voltage change phase of BL1 ends the high voltage earlier, which can make the data reading more accurate because the V of the compensated read transistor T2 th The BL1 side is used as the source, so in principle, the BL1 side should still be used as the source when reading data. You can increase V th The accuracy of compensation; in this way, the potential of BL1 may need to jump from high to low after writing. Figure 3 The solution cannot be adopted. Figure 5 and Figure 6 The difference between Figure 3 and Figure 4 The difference is the same.

[0110] In an exemplary embodiment of the present application, the state of the read transistor T2 when reading data "1" and "0" can be as follows: Figure 7 As shown (this figure takes an N-type read transistor and an N-type write transistor as an example), wherein the abscissa is the voltage difference V between the second gate electrode and the source electrode (eg, the fourth electrode P4) of the read transistor T2. GS , the vertical axis is the current I of the drain electrode (for example, the third electrode P3), 0 means when the written data is "0", 1 means when the written data is "1", LV means that during the data reading process, the first bit line BL1 outputs a first voltage (for example, it can be a low voltage for an N-type transistor), HV means that during the data reading process, the first bit line BL1 outputs a second voltage (that is, a high voltage), that is, at this time during the data reading process, the output voltage on the first bit line BL1 changes from the first voltage to the second voltage, for example, for an N-type transistor, it means changing from a low voltage to a high voltage.

[0111] Although the embodiments disclosed in this application are as above, the contents described are only embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any technician in the field to which this application belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be based on the scope defined in the attached claims.

Claims

1. A storage unit, It is characterized in that include: A write transistor including a first electrode, a second electrode and a first gate electrode; a read transistor including a third electrode, a fourth electrode, and a second gate electrode; a switching transistor comprising a fifth electrode, a sixth electrode and a third gate electrode; Storage nodes; Wherein, the fourth electrode is connected to the second electrode; The first electrode is connected to the storage node, and the first gate electrode is connected to a write word line; The third electrode is connected to the first bit line, and the second gate electrode is connected to the storage node; The fifth electrode is connected to the fourth electrode and the second electrode, the sixth electrode is connected to the second bit line, and the third gate electrode is connected to the read word line; The write transistor is used to control the writing of storage data into the storage node, and the read transistor is used to control the reading of storage data.

2. The storage unit according to claim 1, It is characterized in that The switch transistor remains in an on state at least part of the time during the data writing phase to write the high voltage of the second bit line into the storage node.

3. The storage unit according to claim 1 or 2, It is characterized in that The switch transistor remains turned on during a data reading phase to write the low voltage of the second bit line into the fourth electrode.

4. A memory, It is characterized in that Comprising at least one storage unit according to any one of claims 1 to 3.

5. The memory according to claim 4, It is characterized in that include: A plurality of storage units distributed in an array along a first direction and a second direction; The first direction intersects the second direction; a plurality of the write word lines and a plurality of read word lines extending along the first direction; A plurality of the first bit lines and a plurality of second bit lines extend along the second direction.

6. The memory according to claim 5, It is characterized in that The third gate electrodes of the switch transistors of the plurality of memory cells spaced apart and distributed along the first direction are connected to the same read word line; and / or, The first gate electrodes of the plurality of memory cells spaced apart and distributed along the first direction are connected to the same write word line.

7. The memory according to claim 5 or 6, It is characterized in that The third electrodes of the plurality of memory cells spaced apart and distributed along the second direction are connected to the same first bit line; and / or, The sixth electrodes of the switch transistors of the plurality of memory cells spaced apart and distributed along the second direction are connected to the same second bit line.

8. An electronic device, It is characterized in that Comprising a memory according to any one of claims 4 to 7.

9. A method for reading and writing data, It is characterized in that Based on the storage unit according to any one of claims 1 to 3 or the memory according to any one of claims 4 to 7; The data reading and writing method comprises: Data reading phase: Providing a high voltage to the read word line so that the read transistor is turned on when the storage node stores data "1" and is turned off when the storage node stores data "0"; Data writing phase: Provide a high voltage to the write word line and a low voltage to the read word line, so that the switch transistor is turned off and the write transistor is turned on; A data voltage is provided to the first bit line so that the voltage of the storage node is V data +V th , V data is the data voltage, V th is the threshold voltage of the read transistor.

10. The data reading and writing method according to claim 9, It is characterized in that In the data reading phase, the method further includes: providing a low voltage to the second bit line, providing a low voltage to the write word line, and reading the stored data voltage through the first bit line.

11. The data reading and writing method according to claim 9, It is characterized in that In the data reading phase, the method further includes: providing a low voltage to the first bit line, providing a low voltage to the write word line, and reading the stored data voltage through the second bit line.

12. The data reading and writing method according to claim 10 or 11, It is characterized in that In the data writing phase, before providing a low voltage to the read word line, the step further includes: providing a high voltage to the read word line, providing a high voltage to the write word line, and providing a voltage V to the second bit line. pre , the voltage of the storage node is charged to V by the second bit line pre .

13. The data reading and writing method according to claim 12, It is characterized in that V pre >V data"1” +V th , V data"1” is the data voltage of the first bit line when the written data is "1".

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