Storage unit, memory, electronic device, and data read / write method

Abstract

A storage unit, a memory, an electronic device and a data read-write method, the storage unit comprising: a write transistor comprising a first electrode, a second electrode and a first gate electrode; a read transistor comprising a third electrode, a fourth electrode and a second gate electrode; a switch transistor comprising a fifth electrode, a sixth electrode and a third gate electrode; a storage node; wherein the fourth electrode is connected with the second electrode; the first electrode is connected with the storage node, and the first gate electrode is connected with a write word line; the third electrode is connected with a first bit line, and the second gate electrode is connected with the storage node; the fifth electrode is connected with the fourth electrode and the second electrode, the sixth electrode is connected with a second bit line, and the third gate electrode is connected with a read word line; the write transistor is used for controlling storage data to be written into the storage node, and the read transistor is used for controlling the storage data to be read. The storage unit of the embodiment of the application is convenient for realizing read-write operation, has simple structure, is easy to manufacture, and occupies small area.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to, but are not limited to, the field of design and manufacture of semiconductor devices, and in particular to a memory cell, a memory, an electronic device and a data read-write method. BACKGROUND

[0002] With the development of integrated circuit technology, the critical dimension of a device is increasingly reduced, and the types and quantities of devices contained in a single chip are increased, so that any slight difference in the process production can affect the performance of the device.

[0003] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs. SUMMARY

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of protection of the present application.

[0005] Embodiments of the present application provide a memory cell, a memory, an electronic device and a data read-write method, which facilitate the implementation of read-write operations, have simple structure, are easy to manufacture, and have small area occupation.

[0006] Embodiments of the present application provide a memory cell, which comprises:

[0007] a write transistor comprising a first electrode, a second electrode and a first gate electrode;

[0008] a read transistor comprising a third electrode, a fourth electrode and a second gate electrode;

[0009] a switch transistor comprising a fifth electrode, a sixth electrode and a third gate electrode;

[0010] a storage node;

[0011] The fourth electrode is connected to the second electrode.

[0012] The first electrode is connected to the storage node, and the first gate electrode is connected to a write word line.

[0013] The third electrode is connected to a first bit line, and the second gate electrode is connected to the storage node.

[0014] The fifth electrode is connected to the fourth electrode and the second electrode, the sixth electrode is connected to a second bit line, and the third gate electrode is connected to a read word line.

[0015] The write transistor is configured to control writing of stored data to the storage node, and the read transistor is configured to control reading of the stored data.

[0016] In an example, the switch transistor is kept in an on state at least for part of a data writing phase to write a high voltage of the second bit line to the storage node.

[0017] In an example, the switch transistor is kept in an on state at least for part of a data reading phase to write a low voltage of the second bit line to the fourth electrode.

[0018] Embodiments of the present application also provide a memory, which includes at least one memory cell as provided in embodiments of the present application.

[0019] In an example, the memory includes:

[0020] a plurality of memory cells arranged in a first direction and a second direction, the first direction intersecting the second direction;

[0021] a plurality of write word lines and a plurality of read word lines extending in the first direction;

[0022] a plurality of first bit lines and a plurality of second bit lines extending in the second direction.

[0023] In an example, the third gate electrodes of the plurality of memory cells arranged in the first direction are connected to a same read word line.

[0024] In an example, the first gate electrodes of the plurality of memory cells arranged in the first direction are connected to a same write word line.

[0025] In an example, the third electrodes of the plurality of memory cells arranged in the second direction are connected to a same first bit line.

[0026] In an example, the sixth electrodes of the plurality of memory cells arranged in the second direction are connected to a same second bit line.

[0027] Embodiments of the present application also provide an electronic device, which includes a memory as provided in embodiments of the present application.

[0028] Embodiments of the present application also provide a data read-write method, which is based on a memory cell or a memory as provided in embodiments of the present application; the data read-write method includes:

[0029] a data reading phase;

[0030] A high voltage is supplied to the read word line so that the read transistor is turned on when the data "1" is stored in the memory node and turned off when the data "0" is stored.

[0031] Data writing phase:

[0032] A high voltage is supplied to the write line and a low voltage is supplied to the read line, causing the switching transistor to turn off and the write transistor to turn on;

[0033] A data voltage is provided to the first bit line, such that the voltage of the storage node is V. data +V th V data For data voltage, V th This is the threshold voltage for reading the transistor.

[0034] For example, during the data reading phase, the data read / write method further includes: providing a low voltage to the second bit line, providing a low voltage to the write word line, and reading the stored data voltage through the first bit line.

[0035] For example, during the data reading phase, the data read / write method further includes: providing a low voltage to the first bit line, providing a low voltage to the write word line, and reading the stored data voltage through the second bit line.

[0036] For example, in the data writing phase, before providing a low voltage to the read word line, the data read / write method further includes: providing a high voltage to the read word line, providing a high voltage to the write word line, and providing a voltage V to the second bit line. pre The storage node is charged to V by the second bit line. pre .

[0037] For example, V pre >V data"1” +V th V data"1” The data voltage of the first bit line when the written data is "1".

[0038] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and advantages of this application may be realized and obtained by means of the structures particularly pointed out in the description and the accompanying drawings. Attached Figure Description

[0039] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0040] Figure 1A logic circuit diagram of a memory cell provided for some embodiments of this application;

[0041] Figure 2 A logic circuit diagram of a memory provided for some embodiments of this application;

[0042] Figure 3 This is a timing diagram of the storage units in some embodiments of this application;

[0043] Figure 4 This is a timing diagram of the storage units in some embodiments of this application;

[0044] Figure 5 This is a timing diagram of the storage units in some embodiments of this application;

[0045] Figure 6 This is a timing diagram of the storage units in some embodiments of this application;

[0046] Figure 7 This is a schematic diagram of the IV curve of the read transistor of the storage cell in some embodiments of this application during the data reading phase. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0048] The embodiments described in this application are not necessarily limited to the dimensions shown in the accompanying drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments described in this application are not limited to the shapes or values ​​shown in the drawings.

[0049] The ordinal numbers such as "first" and "second" in this application are used to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0050] In this application, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of this specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this application. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the application is not limited to the terms described in the disclosure and may be appropriately replaced as appropriate.

[0051] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0052] In this application, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode.

[0053] In this application, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, unless otherwise specified, in this application, the "source electrode" and "drain electrode" can be interchanged.

[0054] In this application, "electrical connection" or "connection" includes situations where constituent elements are connected together by a component having some electrical function, such as an electrical signal connection (coupled connection, e.g., coupled to), or a physical direct connection. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0055] T2T2 This application provides a storage unit.

[0056] Figure 1 This is a logic circuit diagram of a memory cell provided for some embodiments of this application. For example... Figure 1 As shown, the storage unit includes: a write transistor T1, a read transistor T2, a switch transistor T3, and a storage node SN;

[0057] The write transistor T1 includes a first electrode P1, a second electrode P2, and a first gate electrode G1;

[0058] The read transistor T2 includes a third electrode P3, a fourth electrode P4, and a second gate electrode G2;

[0059] The switching transistor T3 includes a fifth electrode P5, a sixth electrode P6, and a third gate electrode G3;

[0060] The fourth electrode P4 is connected to the second electrode P2;

[0061] The first electrode P1 is connected to the memory node SN, and the first gate electrode G1 is connected to the write word line W_WL.

[0062] The third electrode P3 is connected to the first bit line BL1, and the second gate electrode G2 is connected to the memory node SN.

[0063] The fifth electrode P5 is connected to the fourth electrode P4 and the second electrode P2, the sixth electrode P6 is connected to the second bit line BL2, and the third gate electrode G3 is connected to the read word line R_WL.

[0064] Write transistor T1 is used to control the writing of stored data to storage node SN, and read transistor T2 is used to control the reading of stored data.

[0065] With the above settings, the write transistor T1 can control the controllable connection between the second gate electrode G2 and the fourth electrode. When the two are connected, the stored data can be written to the storage node SN through the first bit line BL1. At this time, the read transistor T2 is connected in diode mode, and the write voltage is V. data +V th Therefore, the V of transistor T2 is read. th They were compensated.

[0066] By setting the switching transistor T3, the high or low voltage of the second bit line BL2 can be controllably written to the memory node SN or read from the transistor T2 to better coordinate read and write operations.

[0067] For example, the second gate electrode G2 is shared as a storage node SN.

[0068] For example, the switching transistor T3 remains on for at least a portion of the data writing phase to write the high voltage of the second bit line BL2 into the memory node SN. This configuration allows the high voltage of the second bit line to be pre-charged into the memory node, thereby keeping the read transistor T2 on during the data writing phase and facilitating the writing of stored data into the memory node.

[0069] For example, switching transistor T3 remains on during the data read phase to write the low voltage of the second bit line BL2 to the fourth electrode P4. This configuration allows read transistor T2 to be turned on and off accordingly during the data read phase to achieve data reading.

[0070] For example, the storage unit can be a 3TOC structure.

[0071] This application also provides a memory, which includes at least one storage unit as provided in the above embodiments of this application.

[0072] Figure 2 A logic circuit diagram of a memory provided for an exemplary embodiment of this application. (e.g.)Figure 2 As shown, the memory includes:

[0073] The plurality of said storage cells are arrayed along a first direction and a second direction;

[0074] Multiple writing lines W_WL and multiple reading lines R_WL extending along the first direction;

[0075] Multiple first bit lines BL1 and multiple second bit lines BL2 extending along the second direction.

[0076] For example, such as Figure 2 As shown, the third gate electrode G3 of the plurality of memory cells spaced apart along the first direction can be connected to the same read word line R_WL.

[0077] For example, such as Figure 2 As shown, the first gate electrode G1 of the plurality of memory cells spaced apart along the first direction can be connected to the same write word line W_WL;

[0078] For example, such as Figure 2 As shown, the third electrodes P3 of the plurality of memory cells spaced apart along the second direction are connected to the same first bit line BL1.

[0079] For example, such as Figure 2 As shown, the sixth electrode P6 of the plurality of memory cells spaced apart along the second direction is connected to the same second bit line BL2.

[0080] The first direction intersects the second direction; for example, they can be perpendicular to each other. For instance, the first direction could be as follows: Figure 2 The X direction shown can be the second direction as follows: Figure 2 Y direction shown.

[0081] like Figure 3 As shown, one end of the first line BL1 is controllably connected to the voltage signal terminal VPRE via a switching transistor, and the other end of the first line BL1 is connected to the sensing amplifier circuit SA; during the data writing phase, the sensing amplifier circuit SA is used to provide the data voltage V to the first line BL1. data During the data reading phase, the sensing amplifier circuit SA is used to sense the data voltage V stored in the storage node SN. data ; and for BL1, except for the data voltage V dataThe voltage other than that provided is supplied by the voltage signal terminal VPRE; the input terminal of the second bit line BL2 includes two branches. The first branch is controllably connected to the voltage signal terminal Vcom through a switching transistor, and the second branch is controllably connected to the voltage signal terminal VPRE through a switching transistor. During the data writing stage, the voltage signal terminal VPRE is used to provide a voltage signal to the second bit line BL2; during the data reading stage, the voltage signal terminal Vcom is used to provide a voltage signal to the second bit line BL2.

[0082] For example, the memory may further include a substrate, wherein both the first direction and the second direction are parallel to the substrate.

[0083] For example, the memory can be a 3D memory, such as 3D DRAM. The storage cells of the 3D memory can be of a 3TOC structure.

[0084] This application also provides an electronic device, which includes the memory provided in the above-described embodiments of this application.

[0085] For example, the electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0086] This application also provides a data read / write method, which is based on the storage unit or memory provided in this application.

[0087] The following embodiments of this application illustrate the data read / write method using N-type transistors as an example where the switching transistor, writing transistor, and reading transistor are all N-type transistors. The application also protects cases where one or more of the transistors are P-type transistors, and cases where changes in the data read / write method occur due to variations in transistor type.

[0088] Before the data write operation, the storage node SN is pre-charged with a high voltage via the second bit line BL2. This is to achieve V during the write operation. th Compensation, V th To read the threshold voltage of the transistor, the data voltage V data The current flows through the source and drain electrodes of the read transistor, bypasses to the write transistor, and is finally written to the second gate electrode of the read transistor (which can function as a storage node SN). During this process, the read transistor is connected as a diode, and the write voltage is V. data +V th Therefore, the V of the transistor is read. th They were compensated.

[0089] This application embodiment also provides a data read / write method, which is based on the storage unit or memory provided in this application embodiment; the data read / write method includes:

[0090] Data reading phase:

[0091] A high voltage is supplied to the read word line so that the read transistor is turned on when the data "1" is stored in the memory node and turned off when the data "0" is stored.

[0092] Data writing phase:

[0093] A high voltage is supplied to the write line and a low voltage is supplied to the read line, causing the switching transistor to turn off and the write transistor to turn on;

[0094] A data voltage is provided to the first bit line, such that the voltage of the storage node is V. data +V th V data For data voltage, V th This is to read the threshold voltage of the transistor.

[0095] For example, during the data reading phase, the data read / write method further includes: providing a low voltage to the second bit line, providing a low voltage to the write word line, and reading the stored data voltage through the first bit line.

[0096] For example, during the data reading phase, the data read / write method further includes: providing a low voltage to the first bit line, providing a low voltage to the write word line, and reading the stored data voltage through the second bit line.

[0097] For example, in the data writing phase, before providing a low voltage to the read word line, the data read / write method further includes: providing a high voltage to the read word line, providing a high voltage to the write word line, and providing a voltage V to the second bit line. pre The voltage of the storage node is charged to V by the second bit line. pre .

[0098] For example, V pre >V data"1” +V th V data"1” The data voltage of the first bit line when the written data is "1".

[0099] Figure 4 This is a timing diagram of the storage units in some embodiments of this application; Figure 3 This is a timing diagram of storage units in some embodiments of this application. Figure 4 and Figure 3 For example, the data read / write method includes:

[0100] Data reading phase:

[0101] Provide a low voltage (e.g., ground voltage) to the second bit line BL2;

[0102] When a high voltage is supplied to the read word line R_WL, the switching transistor T3 turns on, the write transistor T1 turns off, and the second gate electrode G2 of the read transistor T2 stores the voltage (V). data +V th The low voltage V of the second bit line BL2 is written to the source electrode (fourth electrode P4) of transistor T2. low Therefore, at this time, the voltage difference V between the second gate electrode G2 and the source electrode (fourth electrode P4) of transistor T2 is read. GS =V data +V th -V low .

[0103] This causes the read transistor T2 to store data "1" at memory node SN (V GS >0) is enabled, storing data "0" (V GS When <0), it is turned off. At this time, the stored data voltage V can be obtained by reading the voltage on the first bit line BL1. data Is it "1" or "0"?

[0104] Data writing phase:

[0105] The second bit line BL2 is precharged to a voltage of V. pre V pre >V data"1” +V th V data"1” This is the data voltage of the first line BL1 when the data written is "1";

[0106] A high voltage is supplied to the write word line W_WL and the read word line R_WL, causing the switching transistor T3 and the write transistor T1 to turn on, and the memory node SN is charged to V by the second bit line BL2. pre Then, continue to maintain a high voltage on the write line W_WL, provide a low voltage to the read line R_WL, keep the write transistor T1 on, and turn off the switching transistor T3.

[0107] The given data voltage is supplied to the first bit line BL1 because the read transistor T2 is in diode-connected state at this time, causing the storage node SN to discharge to V. data +V th V th They received compensation.

[0108] exist Figure 4 and Figure 5In this system, the difference in potential of the first bit line BL1 is used to determine whether the data is "1" or "0". Alternatively, the roles of BL1 and BL2 can be reversed during the data reading phase. A low voltage (e.g., ground voltage) can be supplied to the first bit line BL1, and the difference in voltage output from the second bit line BL2 can then be used to determine whether the data is "1" or "0". Figure 6 and Figure 3 The timing diagram is shown.

[0109] Figure 4 and Figure 3 In contrast, during the data writing phase, Figure 4 In the W_WL phase, the high voltage ends later than in the BL1 voltage change phase. This reduces the coupling of the storage node SN. At this time, in order to keep the read transistor T2 off and not affect the previously written data, the BL1 signal can only transition from low to high. Extending the high voltage time of W_WL can delay the turn-off of the write transistor T1, allowing the storage node SN to remain connected to the external circuit through T1, thus reducing the coupling of the storage node SN. Figure 3 In the voltage change phase of W_WL relative to BL1, the high voltage ends earlier, which allows for more accurate data reading because the compensated read transistor T2's V... th This refers to the BL1 side as the source, so in principle, data should still be read from the BL1 side as the source. This can be achieved by increasing V... th The accuracy of the compensation; thus, after the BL1 potential is written, it may need to jump from high to low, at which point... Figure 5 Therefore, the proposed solution cannot be adopted. Figure 6 and Figure 3 The difference and Figure 4 and Figure 7 The differences are the same.

[0110] In an exemplary embodiment of this application, the state of the read transistor T2 when reading data "1" and "0" can be as follows: ​ As shown in the figure (this diagram uses an N-type read transistor and an N-type write transistor as examples), the horizontal axis represents the voltage difference V between the second gate electrode and the source electrode (e.g., the fourth electrode P4) of the read transistor T2. GS The vertical axis represents the current I of the drain electrode (e.g., the third electrode P3). 0 indicates that the data written is "0", 1 indicates that the data written is "1", LV indicates that during the data reading process, the first line BL1 outputs the first voltage (e.g., low voltage for N-type transistors), and HV indicates that during the data reading process, the first line BL1 outputs the second voltage (i.e., high voltage). That is, during the data reading process, the output voltage on the first line BL1 changes from the first voltage to the second voltage. For example, for N-type transistors, it means changing from low voltage to high voltage.

[0111] While the embodiments disclosed in this application are as described above, the content is merely for the purpose of facilitating understanding of this application and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A storage unit, characterized in that, include: A write transistor, including a first electrode, a second electrode, and a first gate electrode; Read the transistor, including the third electrode, the fourth electrode, and the second gate electrode; A switching transistor, comprising a fifth electrode, a sixth electrode, and a third gate electrode; Storage nodes; The fourth electrode is connected to the second electrode; The first electrode is connected to the memory node, and the first gate electrode is connected to the write line; The third electrode is connected to the first bit line, and the second gate electrode is connected to the memory node; The fifth electrode is connected to the fourth electrode and the second electrode, the sixth electrode is connected to the second bit line, and the third gate electrode is connected to the read word line; The write transistor is used to control the writing of stored data to the storage node, and the read transistor is used to control the reading of stored data.

2. The storage unit according to claim 1, characterized in that, The switching transistor remains on for at least a portion of the data writing phase to write the high voltage of the second bit line into the memory node.

3. The storage unit according to claim 1 or 2, characterized in that, The switching transistor remains on during the data read phase to write the low voltage of the second bit line to the fourth electrode.

4. A memory, characterized in that, It includes at least one storage unit according to any one of claims 1 to 3.

5. The memory according to claim 4, characterized in that, include: The plurality of said storage cells are arrayed along a first direction and a second direction; The first direction intersects with the second direction; The plurality of writing lines and the plurality of reading lines extending along the first direction; A plurality of first bit lines and a plurality of second bit lines extending along the second direction.

6. The memory according to claim 5, characterized in that, The third gate electrode of the switching transistors of the plurality of memory cells spaced apart along the first direction is connected to the same read word line; and / or, The first gate electrode of the plurality of memory cells spaced apart along the first direction is connected to the same write word line.

7. The memory according to claim 5 or 6, characterized in that, The third electrodes of the plurality of memory cells spaced apart along the second direction are connected to the same first bit line; and / or, The sixth electrode of the switching transistor of the plurality of memory cells spaced apart along the second direction is connected to the same second bit line.

8. An electronic device, characterized in that, Includes the memory according to any one of claims 4 to 7.

9. A data read / write method, characterized in that, Based on the storage unit according to any one of claims 1 to 3 or the memory according to any one of claims 4 to 7; The data read / write method includes: Data reading phase: A high voltage is provided to the read word line so that the read transistor is turned on when the data "1" is stored in the memory node and turned off when the data "0" is stored. Data writing phase: A high voltage is supplied to the write line and a low voltage is supplied to the read line, causing the switching transistor to turn off and the write transistor to turn on; A data voltage is provided to the first bit line, such that the voltage of the storage node is V. data +V th V data For data voltage, V th This is the threshold voltage for reading the transistor.

10. The data read / write method according to claim 9, characterized in that, The data reading stage also includes: providing a low voltage to the second bit line, providing a low voltage to the write word line, and reading the stored data voltage through the first bit line.

11. The data read / write method according to claim 9, characterized in that, The data reading stage also includes: providing a low voltage to the first bit line, providing a low voltage to the write word line, and reading the stored data voltage through the second bit line.

12. The data read / write method according to claim 10 or 11, characterized in that, The data writing phase, before providing a low voltage to the read word line, further includes: providing a high voltage to the read word line, providing a high voltage to the write word line, and providing a voltage V to the second bit line. pre The voltage of the storage node is charged to V by the second bit line. pre .

13. The data read / write method according to claim 12, characterized in that, V pre >V data"1” +V th V data"1” The data voltage of the first bit line when the data written is "1".

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