Write compensation circuit and memory

Abstract

The invention provides a write compensation circuit and a memory. The write compensation circuit comprises a decoding circuit and a compensation circuit, the decoding circuit determines the compensation amount corresponding to the current working mode according to the mode selection signal and the mode register instruction and outputs an odd-even indication signal and a plurality of enable signals; and when the automatic pre-charging enable signal is valid, the compensation circuit compensates an internal write-in command obtained based on the external write-in command according to the parity indication signal, the plurality of enable signals and the corresponding compensation amount, so that the external write-in command completes preset delay amount delay in different modes. According to the scheme, flexible write compensation can be realized.

Description

Technical Field

[0001] The present disclosure relates to memory technology, and more particularly to a write compensation circuit and a memory. Background Art

[0002] With the development of memory technology, memory is widely used in various fields. For example, dynamic random access memory (DRAM) is widely used.

[0003] In actual applications, the memory performs sampling and decoding according to the input signal of the command / address pin to implement related command operations. Under this design, when the chip is in a write (WriteAutoPrecharge) command operation including automatic precharge, it is necessary to perform delay compensation on the internal write command, and the compensation time is different in different working modes, so a flexible write compensation solution is needed. Summary of the invention

[0004] Embodiments of the present disclosure provide a write compensation circuit and a memory.

[0005] According to some embodiments, the first aspect of the present disclosure provides a write compensation circuit, including: a decoding circuit and a compensation circuit; the decoding circuit receives a mode selection signal and a mode register instruction, and is used to determine the compensation amount corresponding to the current working mode and output a parity indication signal and multiple enable signals according to the mode selection signal and the mode register instruction, and different enable signals correspond to different offsets; wherein, among the enable signals, only the enable signal corresponding to the offset corresponding to the compensation amount corresponding to the current working mode is valid, and the parity indication signal represents that the compensation amount corresponding to the current working mode is an odd or even multiple of the external clock cycle; the compensation circuit is coupled to the decoding circuit, and is used to compensate the internal write command obtained based on the external write command according to the parity indication signal and the multiple enable signals according to the corresponding compensation amount when the automatic pre-charge enable signal is valid, so that the external write command completes the preset delay amount in different modes, and the compensation amount is obtained by superimposing the odd offset or the even offset on the offset corresponding to the compensation amount.

[0006] According to some embodiments, a second aspect of the present disclosure provides a memory, comprising: a memory array, and a write compensation circuit as described in any of the previous examples.

[0007] The write compensation circuit and memory provided by the embodiment of the present disclosure include a decoding circuit and a compensation circuit. The decoding circuit determines the compensation amount of this time according to the mode selection signal and the mode register instruction, and outputs a parity indication signal used to characterize that the compensation amount of this time is an odd or even multiple of the external clock cycle and an enable signal corresponding to each offset, wherein only the enable signal corresponding to the offset corresponding to the current working mode is valid, and the compensation circuit performs delay compensation for the internal write command according to the parity indication signal and the enable signal according to the compensation amount of this time when the automatic precharge enable signal is valid. The specific compensation is to apply the delay of the offset corresponding to the current working mode to the internal write command, and further superimpose the delay of applying the odd offset or even offset. This scheme is for different working modes. By applying an odd offset or even offset on the basis of the corresponding offset, the internal write command is delayed and compensated, thereby satisfying the signal timing relationship required when the chip is in a write command operation including automatic precharge, and realizing a flexible write compensation scheme. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the description, serve to explain the principles of the embodiments of the present disclosure.

[0009] Figure 1 An example diagram of an exemplary memory architecture;

[0010] Figure 2 is a structural example diagram of an exemplary storage unit;

[0011] Figure 3 A timing diagram of a write command operation including automatic pre-charging;

[0012] Figure 4 is a structural schematic diagram of an exemplary write compensation circuit;

[0013] Figure 5 is a structural example diagram of an exemplary write compensation circuit;

[0014] Figure 6 is a structural example diagram of an exemplary processing circuit;

[0015] Figure 7 is a structural example diagram of an exemplary processing circuit;

[0016] Figure 8 is a structural example diagram of an output circuit of an example;

[0017] Fig. 9 is a structural example diagram of an exemplary clock generation circuit;

[0018] Fig.10is a structural example diagram of an output circuit of an example;

[0019] Fig.11 is a schematic structural diagram of a decoding circuit of an example;

[0020] Fig.12 is a schematic structural diagram of a decoding circuit of an example;

[0021] Fig.13 is a structural example diagram of an exemplary timing matching circuit;

[0022] Fig.14 A structural diagram of a memory device of an example;

[0023] Fig.15 FIG. 4 is a timing diagram of an example.

[0024] The above drawings show clear embodiments of the present disclosure, which will be described in more detail below. These drawings and text descriptions are not intended to limit the scope of the present disclosure in any way, but to illustrate the concepts of the present disclosure to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0025] Here, exemplary embodiments will be described in detail, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are only examples of devices and methods consistent with some aspects of the present disclosure.

[0026] The terms "including" and "having" in this disclosure are used to express an open-ended inclusive meaning, and mean that in addition to the listed elements / components / etc., there may be other elements / components / etc.; the logical symbol " / " is used to express the logical meaning of "or"; the terms "first" and "second" are used only as markings or distinctions, and are not intended to limit the order or quantity of their objects. In addition, the different elements and regions in the drawings are only shown schematically, and are therefore not limited to the sizes or distances shown in the drawings. The "connection" in this disclosure can be a direct connection or an indirect connection.

[0027] The technical solution is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present disclosure will be described below in conjunction with the accompanying drawings.

[0028] Figure 1 An example diagram of the memory architecture is shown in FIG. Figure 1As shown, taking DRAM as an example, it includes data input / output buffer, row decoder, column decoder, sense amplifier and storage array. Among them, the data input / output buffer belongs to the peripheral area circuit, and the sense amplifier, row decoder, column decoder and storage array belong to the array area circuit. The storage array is mainly composed of word lines, bit lines and storage cells. The word lines in the storage array extend in the row direction, and the bit lines in the storage array extend in the column direction. The intersection of the word lines and the bit lines is the storage cell of the storage array.

[0029] Each storage unit is used to store one bit of data. Figure 2 As shown, Figure 2 : is a structural example diagram of an exemplary memory cell, and the memory cell is mainly composed of a transistor switch M and a capacitor C. Among them, the capacitor is used to store data, and the transistor switch is used to turn off or on according to the selected state.

[0030] A certain storage cell can be activated by controlling the word line and the bit line to access the storage cell. Take the read scenario as an example: when the data in the storage cell needs to be read, the word line of the row where the storage cell is located can be selected through the row decoder, and accordingly, the transistor M in the diagram is turned on, and the state of the capacitor C at this time can be sensed by sensing and amplifying the bit line signal. For example, if the bit data stored in the storage cell is 1, then after the transistor M is turned on, 1 will be read from the bit line of the storage cell, and vice versa. In addition, take the write scenario as an example: when bit data needs to be written to a certain storage cell, such as writing 1. The word line of the row where the storage cell is located can be selected through the row decoder, and the corresponding transistor M in the diagram is turned on, and by setting the logic level of the bit line to 1, the capacitor C is charged, that is, 1 is written to the storage cell. Conversely, if 0 is to be written, the logic level of the bit line is set to 0, so that the capacitor C is discharged, that is, 0 is written to the storage cell.

[0031] In actual applications, the memory performs sampling and decoding according to the input signal of the command / address (CA) pin to implement related command operations. Taking the write (WriteAutoPrecharge) command operation example including automatic pre-charging, after the write leveling internal cycle calibration (WriteLevelingInternalCycleAlignment) is set through the memory's mode register (such as the data OP<3:0> in MR3), it is also necessary to perform timing delay compensation on the internal write command obtained based on the external write command to meet the external write command. After a certain time requirement, the chip will perform automatic pre-charging. The time requirements here include the column address strobe write delay (ColumnAddressStrobeWriteLatency, referred to as CWL) and data transmission time (that is, the sum of half of the burst length (BurstLength, referred to as BL)), and write recovery time (WriteRecoveryTime, referred to as tWR). In order to understand the above timing more intuitively, Figure 3 The timing diagram of the write command operation including automatic precharge is shown in FIG. Figure 3 As shown, taking the design of double rate synchronous dynamic random access memory (DDR) as an example, after the activation command (ACT in the figure), after the delay time from row enable to column enable (Row to Column Delay, tRCD for short), responding to the external write command (automatic pre-charge write command, WR in the figure) after the delay CWL, it starts to take BL / 2 clock cycles to store the write data (DATA in the figure) in the storage array of the memory, and then responds to the pre-charge command (PRE in the figure) after tWR for pre-charging, and after the row pre-charge time (Row Pre-charge Time, tRP for short) The execution of a write command operation including automatic pre-charging is completed.

[0032] Combined with the above technical background, in order to ensure that the timing of the clock and data selection pulse (Data Strobe Signal, referred to as DQS signal) of each memory is consistent, write leveling (Write Leveling) processing will be performed. Specifically, after the external write leveling (External Write Leveling) training operation is completed, the data selection pulse and the clock signal are aligned at the pin. Then, during the internal write leveling, a negative offset will be applied to the data selection pulse. For example, the reference point of the internal write leveling pulse (Internal Write Leveling Pulse) can be aligned by setting the memory mode register MR3OP<3:0>, and the negative offset can be increased to reduce the delay from the write command to the internal write pulse until the data selection pulse and the internal write pulse are aligned. After completing the write leveling process, the internal write command needs to compensate for the negative offset in the write leveling process to meet the delay required by the aforementioned external write command, that is, CWL+BL / 2, and then the chip automatically performs a pre-charge operation after the tWR time delay. Therefore, in order to make the external write command meet the above delay, it is necessary to compensate the internal write command of the memory. The internal write command here is a signal obtained after the external write command is delayed internally. Under different modes and different MR3 settings, the internal delay is different. Therefore, the duration to be compensated is different in different working modes, and the amount to be compensated may also be an odd or even multiple of the external clock cycle, so it is necessary to provide a flexible write compensation scheme. Some aspects of the embodiments of the present disclosure relate to the above considerations. The following is an example introduction of the scheme in conjunction with some embodiments.

[0033] In some embodiments, Figure 4 FIG. 1 is a schematic diagram of a structure of an exemplary write compensation circuit. Figure 4 As shown, the write compensation circuit includes: a decoding circuit 11 and a compensation circuit 12;

[0034] The decoding circuit 11 receives the mode selection signal D4_P<…> and the mode register instruction MR3<…>, and is used to determine the compensation amount corresponding to the current working mode according to the mode selection signal D4_P<…> and the mode register instruction MR3<…>, and output a parity indication signal SW and a plurality of enable signals P<…>, wherein different enable signals P<…> correspond to different offsets; wherein, among the enable signals P<…>, only the enable signal corresponding to the offset corresponding to the compensation amount corresponding to the current working mode is valid, and the parity indication signal SW indicates whether the compensation amount corresponding to the current working mode is an odd or even multiple of the external clock cycle;

[0035] The compensation circuit 12 is coupled to the decoding circuit 11, and is used to compensate the internal write command INT_WRCMD obtained based on the external write command according to the parity indication signal SW and multiple enable signals P<…> according to the corresponding compensation amount when the automatic pre-charge enable signal AP_EN is valid, so that the external write command can complete the preset delay amount in different modes. The compensation amount is obtained by superimposing the odd offset or the even offset on the offset corresponding to the compensation amount.

[0036] In practical applications, the circuit provided in this embodiment can be applied to various memories. As an example, it can be applied to, including but not limited to, double data rate synchronous dynamic random access memory (DDR DRAM for short). Among them, the automatic precharge enable signal AP_EN is obtained based on "the CA10 signal of the write command is low level in the second cycle (ie AP = L)", that is, the signal received by the CA10 pin in the second cycle under the write command. Among them, the mode selection signal is used to determine the current working mode. Further, in combination with the foregoing content, the duration of the internal delay in different working modes is different. As an example, the working mode of the memory can be determined according to the transmission frequency of the memory. For example, the exemplary working mode may include a first mode, a second mode and a third mode; the transmission rate corresponding to the first mode is not greater than the preset value and the preamble of the data selection signal is 4 external clock cycles, the transmission rate corresponding to the second mode is not greater than the preset value and the preamble of the data selection signal is 2 or 3 external clock cycles; the transmission frequency corresponding to the third mode is greater than the preset value. Combined with the example in Table 1, Table 1 is an example of the time delay amount in different working modes, including D4TYPE_PRE4 mode, D4TYPE_PRE2 / 3 mode and D5TYPE mode. The time delay amount in Table 1 is the time difference between the external write command and the internal write command. Similarly, the object of compensation in this scheme is the internal write command mentioned in this scheme. Specifically, the transmission rate of the memory in the D4TYPE_PRE4 working mode is not greater than 3200Mbps (Mbps is million bits per second) and the preamble of the data selection signal is 4 external clock cycles; the transmission rate of the memory in the D4TYPE_PRE2 / 3 working mode is also not greater than 3200Mbps and the preamble of the data selection signal is 2 or 3 external clock cycles; the transmission rate of the memory in the D5TYPE working mode is greater than 3200Mbps. In practical applications, the current working mode can be determined based on the transmission rate and preamble of the memory.

[0037] Table 1

[0038]

[0039] Among them, internal write leveling is not required in D4TYPE_PRE4 mode and D4TYPE_PRE2 / 3 mode, and internal write leveling is involved in D5TYPE mode. It can be understood that in different working modes, the time difference between the external write command and the internal write command is different, for example, CWL+2 in D4TYPE_PRE4 mode, CWL+3 in D4TYPE_PRE2 / 3 mode, and CWL+4-MR3 in D5TYPE. It should be noted that the numbers in the above table represent the duration equivalent to the number of times the external clock cycle, such as CWL+2, which means that the time delay is the sum of CWL and 2 times the external clock cycle, and MR3 represents the absolute value of the offset represented by the parameter value in the mode register MR3. The parameter value in the mode register MR3 is determined by internal write leveling. Combined with the time delay amount of the above example, that is to say, the memory has delayed the external write command by the above time delay amount to obtain the internal write command, so this solution needs to further delay the internal write command on this basis to meet the time difference between the compensated internal write command and the external write command is CWL+BL / 2. Specifically, this solution can be applied to compensate the internal write command in different working modes. Among them, the amount of compensation for the internal write command can be determined according to the time difference between the external write command and the decoded internal write command in different working modes. Taking the D4TYPE_PRE4 mode as an example, it can be seen that the time delay amount is CWL+2, and the total delay time is CWL+BL / 2, so the amount of compensation for the internal write command is CWL+BL / 2-(CWL+2). Taking BL as 16 as an example, it can be determined that in D4TYPE_PRE4 mode, the amount of compensation required for the internal write command is 6 external clock cycles. For another example, in D4TYPE_PRE2 / 3 mode, the amount of compensation required for the internal write command is 5 external clock cycles. In D5TYPE mode, the amount of compensation required for the internal write command is the sum of 4 external clock cycles and the offset represented by the parameter value in MR3. Among them, the offset represented by the parameter value in MR3 can also be represented by an external clock cycle, for example, an odd or even number of external clock cycles. In combination with the above, in one example, the preset delay amount is the sum of the number of external clock cycles corresponding to the column address strobe pulse write delay and half of the burst length; the compensation amount corresponding to the first mode is six external clock cycles; the compensation amount corresponding to the second mode is five external clock cycles; the compensation amount corresponding to the third mode is the sum of four external clock cycles and the absolute value of the offset represented by the mode register instruction.

[0040] In practical applications, the above-mentioned working modes can be determined by the mode selection signal D4_P<…>. As an example, Table 2 is an example of the functional description of different mode selection signals. As shown in Table 2, D4_P <0> The value of is used to select D4TYPE mode or D5TYPE mode. The D4TYPE mode includes D4TYPE_PRE4 mode and D4TYPE_PRE2 / 3 mode. As an example, D4_P <0> 0 means D5TYPE mode is adopted, D4_P <0> 1 indicates that D4TYPE mode is used. <0> When D4_P is 1, <1> 1 means D4TYPE_PRE2 / 3 mode is adopted, D4_P <1> 0 indicates that the D4TYPE_PRE4 mode is adopted, thereby realizing the current working mode being determined based on the mode selection signal.

[0041] Table 2

[0042] Mode selection signal Functional Description D4_P <0> Select D4 / D5TYPE; when D4_P0=1, select D4_TYPE D4_P <1> Select Preamble mode; when D4_P1=1, select Preamble2 / 3

[0043] In this solution, two-level compensation is used to achieve the compensation amount required for the internal write command according to the current working mode. Specifically, in order to compensate the internal write command, the decoding circuit 11 determines the current working mode according to the current mode selection signal D4_P<…> and the mode register instruction MR3<…> (including the parameter value set in the mode register), thereby determining the delay amount of the internal write command (INT_WRCMD) relative to the external write command, and then combining the total delay amount required by the external write command, determining how much time the internal write command needs to be delayed to reach the total delay amount, that is, the amount of compensation required for the internal write command in this solution, that is, the compensation amount corresponding to the current working mode. Correspondingly, the decoding circuit 11 outputs a parity indication signal SW and multiple enable signals P<…>. Among them, the compensation amount may be an odd or even multiple of the external clock cycle. For example, combined with the above example, the compensation amount corresponding to the D4TYPE_PRE4 mode is 6 external clock cycles, that is, an even multiple; the compensation amount corresponding to the D4TYPE_PRE2 / 3 mode is 5 external clock cycles, which is an odd multiple.

[0044] In combination with the two-stage compensation scheme, the multiple enable signals P<…> output by the decoding circuit 11 are used to indicate the basic delay applied by the compensation circuit 12 to the internal write command, that is, the offset corresponding to the compensation amount corresponding to the current working mode, and this basic delay is an even multiple of the external clock cycle, for example, 2, 4, 6, ... 10, 12 external clock cycles. Among them, different enable signals correspond to different offsets. For example, the enable signal can have an enable signal corresponding to a basic delay of 2, 4, 6, ... 10, 12 external clock cycles, which are P respectively. <0> , P <2> , P <4> ,…P <8> , P <10> . After applying the basic delay, the compensation circuit 12 further superimposes an odd offset or an even offset on this basis. This depends on whether the compensation amount corresponding to the current working mode is an odd or even multiple of the external clock cycle. For example, if the compensation amount is an even number of external clock cycles, an even offset is further superimposed. If the compensation amount is an odd number of external clock cycles, an odd offset is further superimposed. For example, for the D4TYPE_PRE4 mode, the compensation amount corresponding to this mode is 6 external clock cycles. The offset (i.e., the basic delay) corresponding to the compensation amount corresponding to the D4TYPE_PRE4 mode can be set to 4 external clock cycles. Correspondingly, only P is included in the enable signal output by the decoding circuit 11. <2> In the effective state, the compensation circuit 12 applies a basic delay of 4 external clock cycles to the internal write command INT_WRCMD obtained based on the external write command, and then further superimposes a two-stage compensation method of an even offset (2 external clock cycles) to achieve the compensation amount corresponding to D4TYPE_PRE4, that is, a delay of 6 external clock cycles. For the D4TYPE_PRE2 / 3 mode, the enable signal output by the decoding circuit 11 also has only P <2> In effective state, a basic delay of 4 external clock cycles is applied, that is, the offset corresponding to the compensation amount of the D4TYPE_PRE2 / 3 mode is also 4 external clock cycles, and then the two-stage compensation method of the odd offset (1 external clock cycle) is further superimposed to achieve the compensation amount corresponding to the D4TYPE_PRE2 / 3 mode, that is, a delay of 5 external clock cycles. The two-stage compensation scheme can flexibly control the compensation amount of delay compensation according to the needs of the working mode, even if the compensation amount corresponding to different working modes is different, which may be an odd or even multiple of the external clock cycle, this scheme can also achieve accurate and flexible delay compensation.

[0045] In actual applications, the external clock CK is divided into the internal odd clock PCLK_O and the internal even clock PCLK_E after being received by the memory. The clock cycles of the internal odd clock PCLK_O and the internal even clock PCLK_E are both twice the external clock cycle tCK, and the phase difference between the internal even clock PCLK_E and the internal odd clock PCLK_O is one external clock cycle tCK.

[0046] As an example, Figure 5 FIG. 1 is a structural diagram of an exemplary write compensation circuit, as shown in FIG. Figure 5 As shown, based on any example, the compensation circuit 12 may specifically include: two processing circuits, respectively denoted as a first processing circuit 21 and a second processing circuit 22, and an output circuit 23;

[0047] The first processing circuit 21 and the second processing circuit 22 are respectively used for, when the automatic precharge enable signal AP_EN is valid, offsetting the corresponding write command RMW_E / O according to the offset corresponding to the valid enable signal according to the multiple enable signals P<…>, to obtain the corresponding offset signal CMD2_E / O; wherein the write command RMW_E / O corresponding to the first processing circuit 21 and the second processing circuit 22 is obtained by sampling the internal write command INT_WRCMD based on the internal even clock PCLK_E and the internal odd clock PCLK_O respectively; wherein the offset corresponding to the enable signal P<…> is an even number of external clock cycles, the clock cycles of the internal even clock PCLK_E and the internal odd clock PCLK_O are twice the external clock cycle tCK, and the phase difference between the internal even clock PCLK_E and the internal odd clock PCLK_O is one external clock cycle tCK;

[0048] The output circuit 23 is connected to the decoding circuit 11, the first processing circuit 21 and the second processing circuit 22, and is used to offset the offset signal CMD2_E / O corresponding to the first processing circuit 21 and the second processing circuit 22 according to the odd offset or the even offset according to the parity indication signal SW and perform an OR logic operation on the offset signal to obtain a compensated internal write command.

[0049] The functions of the first processing circuit 21 and the second processing circuit 22 are similar, that is, a basic delay offset is performed on the input signal, and then the output circuit further superimposes an odd offset or an even offset on the basis of the basic offset, wherein the basic offsets applied by the first processing circuit 21 and the second processing circuit 22 to their respective delay objects are also the same, both of which are offsets corresponding to the currently valid enable signal, but the difference between the two is that the objects of delay are different, specifically, the signals for sampling the internal write command INT_WRCMD based on the internal even clock PCLK_E and the internal odd clock PCLK_O. It can be understood that since the phases of the internal even clock PCLK_E and the internal odd clock PCLK_O differ by one external clock cycle, the phases of the write commands corresponding to the first processing circuit 21 and the second processing circuit 22 also differ by one external clock cycle. Furthermore, the write commands corresponding to the first processing circuit 21 and the second processing circuit 22 are respectively obtained by applying the same delay to the first processing circuit 21 and the second processing circuit 22, and the offset signals corresponding to the first processing circuit 21 and the second processing circuit 22, that is, CMD2_E and CMD2_O also have a phase difference of one external clock cycle. In order to distinguish, Figure 5 In the example, it is assumed that the write command corresponding to the first processing circuit is RMW_E, and the write command corresponding to the second processing circuit is RMW_O. Accordingly, the offset signal corresponding to the first processing circuit 21 is CMD2_E, and the offset signal corresponding to the second processing circuit 22 is CMD2_O.

[0050] Specifically, the output circuit 23 is used to delay the offset signals CMD2_E / O corresponding to the first processing circuit and the second processing circuit according to an even offset (for example, two external clock cycles) when the current parity indication signal SW represents that the compensation amount corresponding to the current working mode is an even multiple of the external clock cycle, and perform an OR logic operation on the two delayed signals, thereby obtaining a write signal delayed by an even multiple of the external clock cycle compared to the internal write signal. In addition, when the current parity indication signal SW represents that the compensation amount corresponding to the current working mode is an odd multiple of the external clock cycle, the output circuit 23 delays the offset signals CMD2_E / O corresponding to the first processing circuit and the second processing circuit according to an odd offset (for example, one external clock cycle), and performs an OR logic operation on the two delayed signals, thereby obtaining a write signal delayed by an odd multiple of the external clock cycle compared to the internal write signal.

[0051] In this example, the internal odd clock and the internal even clock are used to sample the internal write command signal, and the first processing circuit and the second processing circuit are used to perform basic delay on the two sampled signals to obtain the offset signals corresponding to the two processing circuits. The subsequent output circuit is based on the two offset signals, by applying an odd offset or an even offset and performing an OR logic operation to obtain a compensated write signal. The advantage of this is that the output circuit can subsequently use the internal even clock and the internal odd clock for sampling, and superimpose the delayed odd offset or even offset based on the OR logic operation, so that there is no need to generate a special clock signal for delay, and only the internal clock signal of the memory itself is needed to achieve delay compensation for the internal write command.

[0052] In one example, Figure 6 FIG. 1 is a structural example diagram of an exemplary processing circuit, such as Figure 6 As shown, each processing circuit 21 / 22 may include: a plurality of cascaded offset sub-circuits 31 corresponding one-to-one to a plurality of enable signals P<…>;

[0053] The first-stage shift subcircuit 31 receives a write command RMW_E / O corresponding to the processing circuit and an enable signal P<…> corresponding to the shift subcircuit; each shift subcircuit 31 except the first-stage receives a write command RMW_E / O corresponding to the processing circuit and an enable signal P<…> corresponding to the shift subcircuit, and is connected to the output end of the previous-stage shift subcircuit;

[0054] Each level of offset sub-circuit 31 is used to delay and output the received write command RMW_E / O when the enable signal P<…> corresponding to the offset sub-circuit is valid; and to delay and output the signal output by the previous level of offset sub-circuit when its own enable signal P<…> is invalid; the last level of offset sub-circuit 31 is used to output the offset signal CMD2_E / O corresponding to the processing circuit where it is located; wherein the total delay amount of the offset sub-circuit corresponding to the valid enable signal and all subsequent offset sub-circuits is the offset amount corresponding to the valid enable signal.

[0055] It should be noted that Figure 6 Only the specific structure of a single processing circuit is shown. The circuit shown in the figure can be regarded as the circuit structure of the first processing circuit 21 or the second processing circuit 22. Corresponding to the input signal in the figure, RMW_E / O represents the write command corresponding to the first processing circuit / the second processing circuit, and CMD2_E / O represents the corresponding offset signal output by the first processing circuit / the second processing circuit. In actual applications, the structures of the two processing circuits can be the same, so only a single circuit schematic diagram is shown here.

[0056] Reference Figure 6As shown, each level of offset subcircuit 31 is used to delay the signal input to the offset subcircuit for a certain period of time. Optionally, this period of time can be preset. The delay period of each level of offset subcircuit can be the same or different. In one example, in order to facilitate circuit design and layout, the delay period of each level of offset subcircuit is the same. For example, the delay period of each level of offset subcircuit can be two external clock signals. As an example, Figure 6 The six-stage offset subcircuit is shown in FIG. 1 , and the enable signal corresponding to the first-stage offset subcircuit is shown as P <10> The enable signal corresponding to the second-stage offset subcircuit is shown as P <8> , and so on, the enable signal corresponding to the last stage offset sub-circuit is shown as P <0> Specifically, in the processing circuit, the enable signal P<…> is used to control which level of offset sub-circuit the write command RMW_E / O corresponding to the processing circuit is input from, that is, to determine how many levels of offset sub-circuit the write command will pass through for delay, which affects the basic offset amount applied to the write command, that is, the offset amount corresponding to the compensation amount corresponding to the current working cycle.

[0057] Combined with the above example, for the D4TYPE_PRE4 mode, the internal write command is sampled based on the internal even clock and the internal odd clock to obtain the write command corresponding to the first processing circuit 21 and the second processing circuit 22. The first processing circuit 21 and the second processing circuit 22 respectively apply a basic delay of 4 external clock cycles to the corresponding write command and output CMD2_E / O. Then, the output circuit 23 applies an even offset (for example, 2 external clock cycles) to CMD2_E / O, thereby achieving the compensation amount (6 external clock cycles) corresponding to the D4TYPE_PRE4 mode. Figure 6 In the circuit shown in FIG. 1 , among the enable signals P<…> output by the decoding circuit 11, only P <2> In a valid state (e.g., high level), other enable signals are in an invalid state (e.g., low level). Therefore, the first four shift subcircuits and the sixth stage will not receive RMW_E / O, but receive the output signal of the previous shift subcircuit. For the first four shift subcircuits, since the previous shift subcircuit does not output a valid output signal, it cannot output a valid output signal either, until the fifth shift subcircuit receives RMW_E / O and outputs RMW_E / O delayed by 2 external clock cycles to the next shift subcircuit. Correspondingly, the sixth shift subcircuit receives the output signal of the fifth shift subcircuit, further superimposes the delay of 2 external clock cycles, and outputs the final CMD2_E / O. At this time, CMD2_E / O is delayed by 4 external clock cycles compared to RMW_E / O, realizing the basic delay of the internal write command in D4TYPE_PRE4 mode.

[0058] The circuit structure of the offset subcircuit is not limited. As an example, Figure 7FIG. 1 is a structural example diagram of an exemplary processing circuit, such as Figure 7 As shown, the first stage offset sub-circuit 31 comprises: a first NAND gate 311, a seventh NAND gate 312 and a first trigger 313; the first input end of the first NAND gate 311 receives an enable signal (in the figure, P <10> ), the second input end of the first NAND gate 311 receives the write command RMW_E / O corresponding to the processing circuit 21 / 22; the input end of the seventh NAND gate 312 is connected to the output end of the first NAND gate 311, the output end of the seventh NAND gate 312 is connected to the input end of the first trigger 313, and the clock end of the first trigger 313 receives the first clock signal PCLK_E1 / O1 corresponding to the processing circuit 21 / 22;

[0059] Each level of the offset subcircuit 31 except the first level includes: a second NAND gate 314, a third NAND gate 315, a fourth NAND gate 316 and a second flip-flop 317; the first input end of the second NAND gate 314 receives the enable signal of the offset subcircuit, and the second input end of the second NAND gate 314 receives the write command corresponding to the processing circuit 21 / 22; the first input end of the third NAND gate 315 receives the inverted signal P<…>B of the enable signal of the offset subcircuit, and the second input end of the third NAND gate 315 is connected to the output end of the offset subcircuit of the previous level; the first input end of the fourth NAND gate 316 is connected to the output end of the second NAND gate 314, the second input end of the fourth NAND gate 316 is connected to the output end of the third NAND gate 315, and the output end of the fourth NAND gate 316 is connected to the input end of the second flip-flop 317; the clock end of the second flip-flop 317 receives the first clock signal PCLK_E1 / O1 corresponding to the processing circuit 21 / 22;

[0060] The period of the first clock signal PCLK_E1 / O1 is the sub-offset, and the phase difference between the first clock signal PCLK_E1 corresponding to the first processing circuit 21 and the first clock signal PCLK_O1 corresponding to the second processing circuit 22 is the phase difference between the internal even clock PCLK_E and the internal odd clock PCLK_O.

[0061] Specifically, the sub-offset refers to the delay offset applied by each level of the offset sub-circuit. As an example, the write command corresponding to the first processing circuit 21 is RMW_E, the first clock signal corresponding to the first processing circuit 21 is PCLK_E1, the write command corresponding to the second processing circuit 22 is RMW_O, and the first clock signal corresponding to the second processing circuit 22 is PCLK_O1. For example, the clock cycles of PCLK_E1 and PCLK_O1 are both sub-offsets. For example, the sub-offset can be 2 external clock cycles, and correspondingly, the clock cycles of PCLK_E1 and PCLK_O1 are 2 external clock cycles. At the same time, in order to achieve that the two processing circuits apply the same basic delay to their respective corresponding write commands, the phase difference between PCLK_E1 and PCLK_O1 is consistent with the phase difference between PCLK_E and PCLK_O, for example, it can be one external clock cycle. It can be understood that the trigger in each level of the offset subcircuit responds to the valid edge (for example, the rising edge) of the first clock signal PCLK_E1 / O1 received by the clock end, and outputs the currently received input signal. The input signal of the trigger may be the write command RMW_E / O corresponding to the processing circuit, or it may be the output signal of the previous level trigger, which depends on whether the enable signal P<…> received by the first NAND gate 311 / the second NAND gate 314 of the offset subcircuit of this level is in a valid state. For example, the enable signal being valid can refer to the enable signal being in a high level state, and the enable signal being in a low level state indicates that the enable signal is invalid. As an example, when the enable signal is in a high level state, the write command RMW_E / O can pass through the first NAND gate 311 / the second NAND gate 314 normally, at this time, the inverted signal of the enable signal is in a low level state, the output signal of the previous level trigger is blocked, and the third NAND gate 315 keeps outputting a high level signal, so the signal received by the first input end of the fourth NAND gate 316, that is, RMW_E / O is transmitted to the input end of the trigger of this level. On the contrary, when the enable signal is in a low level state, the write command RMW_E / O is blocked by the first NAND gate 311 / the second NAND gate 314, and the first NAND gate 311 / the second NAND gate 314 keeps outputting a high level signal. At this time, the inverted signal of the enable signal is in a high level state, and the output signal of the previous level trigger can pass through the third NAND gate 315 normally. Therefore, the signal received by the second input terminal of the fourth NAND gate 316, that is, the output signal of the previous level trigger is transmitted to the input terminal of the current level trigger.

[0062] Through the processing circuit of the above example, it is possible to implement basic delay compensation for the write command corresponding to the processing circuit according to the offset corresponding to the currently valid enable signal, and ensure that the basic delay compensation amounts of the two processing circuits are consistent, so as to obtain two offset signals with a phase difference consistent with the phase difference of the internal odd and even clocks, so that the subsequent output circuit can implement the superimposed odd offset or even offset delay based on the two offset signals, thereby realizing write compensation. In addition, this example is implemented based on conventional devices, which is conducive to simplifying the process and reducing costs.

[0063] Subsequently, based on the offset signals output by the first processing circuit 21 and the second processing circuit 22, the output circuit 23 further adds odd offset or even offset delay to achieve write compensation in the current working mode. Figure 8 FIG. 1 is a structural example diagram of an output circuit of an example, such as Figure 8 As shown, the output circuit 23 includes: a first output sub-circuit 41, a second output sub-circuit 42 and an integration circuit 43;

[0064] The first output subcircuit 41 is connected to the first processing circuit 21 and the second processing circuit 22, and is used for sampling and outputting the offset signal CMD2_O corresponding to the second processing circuit based on the second clock signal PCLK_E2 corresponding to the first processing circuit in response to the parity indication signal SW in the first state; and sampling and outputting the offset signal CMD2_E corresponding to the first processing circuit based on the second clock signal PCLK_E2 corresponding to the first processing circuit in response to the parity indication signal SW in the second state;

[0065] The second output sub-circuit 42 is connected to the first processing circuit 21 and the second processing circuit 22, and is used for sampling and outputting the offset signal CMD2_E corresponding to the first processing circuit based on the second clock signal PCLK_O2 corresponding to the second processing circuit in response to the parity indication signal SW in the first state; and sampling and outputting the offset signal CMD2_O corresponding to the second processing circuit based on the second clock signal PCLK_O2 corresponding to the second processing circuit in response to the parity indication signal in the second state;

[0066] The integration circuit 43 is connected to the first output sub-circuit 41 and the second output sub-circuit 42, and is used to perform an OR logic operation on the output signals of the first output sub-circuit 41 and the second output sub-circuit 42, and output a compensated internal write command; wherein the second clock signal PCLK_E2 corresponding to the first processing circuit and the second clock signal PCLK_O2 corresponding to the second processing circuit have the same period, and the phase difference between the two is the phase difference between the internal even clock PCLK_E and the internal odd clock PCLK_O.

[0067] Specifically, the above example takes the write command corresponding to the first processing circuit as RMW_E, and the write command corresponding to the second processing circuit as RMW_O as an example. Among them, the clock cycles of the second clock signals corresponding to the two processing circuits are the same, and the phase difference is consistent with the phase difference between the first clock signals corresponding to the two processing circuits, that is, it is also the phase difference between the internal even clock PCLK_E and the internal odd clock PCLK_O. For example, the phase difference between the second clock signals corresponding to the two processing circuits can be 1 external clock cycle. Specifically, a certain phase delay can be set between the first clock signal and the second clock signal corresponding to each processing circuit. This is to ensure timing matching, so that the output circuit can accurately capture the valid command window in the offset signal output by the processing circuit based on the first clock signal corresponding to each processing circuit based on the second clock signal corresponding to each processing circuit, and obtain the compensated internal write command through an OR logic operation.

[0068] In one example, the write compensation circuit further includes a clock generation circuit for generating respective clock signals, as an example, Fig. 9 FIG. 1 is a structural example diagram of an exemplary clock generation circuit, such as Fig. 9 As shown, the clock generation circuit may include: a first generation circuit 51 and a second generation circuit 52. As an example, the first generation circuit 51 is used to output the first clock signal and the second clock signal corresponding to the first processing circuit, and the second generation circuit 52 is used to output the first clock signal and the second clock signal corresponding to the second processing circuit. The specific structures of the first generation circuit 51 and the second generation circuit 52 are not limited, and the specific circuits of the two may be the same or different. In an example, the first generation circuit 51 and the second generation circuit 52 adopt similar circuit structures to facilitate circuit design and manufacturing.

[0069] like Fig. 9As shown, the first generation circuit package 51 includes: a first AND operation unit 511, a second AND operation unit 512, a first OR operation unit 513, a first delay 514 and a second delay 515, the first input end of the first AND operation unit 511 receives the first cycle mode instruction EN_1N, and the second input end receives the internal even clock PCLK_E; the first input end of the second AND operation unit 512 receives the second cycle mode instruction EN_2N, and the second input end receives the internal odd clock PCLK_O; the first OR operation unit 514 receives the first cycle mode instruction EN_1N, and the second input end receives the internal odd clock PCLK_O; The first input end is connected to the output end of the first AND operation unit 511, and the second input end is connected to the output end of the second AND operation unit 512; the input end of the first delay 514 is connected to the output end of the first OR operation unit 513, and the output end of the first delay 514 is used to output the first clock signal PCLK_E1 corresponding to the first processing circuit 21; the input end of the second delay 515 is connected to the output end of the first delay 514, and the output end of the second delay 515 is used to output the second clock signal PCLK_O corresponding to the first processing circuit 21 1; the second generation circuit package 52 includes: a third AND operation unit 521, a fourth AND operation unit 522, a second OR operation unit 523, a third delay 524 and a fourth delay 525, the first input end of the third AND operation unit 521 receives the first cycle mode instruction EN_1N, and the second input end receives the internal odd clock PCLK_O; the first input end of the fourth AND operation unit 522 receives the second cycle mode instruction EN_2N, and the second input end receives the internal even clock PCLK_E; the first input end of the second OR operation unit 523 ... first cycle mode instruction EN_1N, and the second input end receives the internal odd clock PCLK_O; the first input end of the fourth AND operation unit 522 receives the second cycle mode instruction EN_2N, and the second input end receives the internal even clock PCLK_E; the first input end of the second The input end is connected to the output end of the third AND operation unit 521, and the second input end is connected to the output end of the fourth AND operation unit 522; the input end of the third delay 524 is connected to the output end of the second OR operation unit 523, and the output end of the third delay 524 is used to output the first clock signal PCLK_O1 corresponding to the second processing circuit 22; the input end of the fourth delay 525 is connected to the output end of the third delay 524, and the output end of the fourth delay 525 is used to output the second clock signal PCLK_O2 corresponding to the second processing circuit 22. Through the example clock generation circuit, it is possible to provide the working clock of each circuit module, match the signal sampling timing requirements, and thus achieve write compensation, and the clock generation scheme of this example also considers different operation modes of the memory. In practical applications, the operation modes of the memory include 1N mode and 2N mode, and the memory processes instructions at different speeds in different operation modes.

[0070] Under the coordination of each clock signal, the output circuit 23 shifts the offset signal corresponding to the first processing circuit 21 and the second processing circuit 22 according to the odd offset or the even offset according to the odd-even indication signal SW, and performs an OR logic operation on the shifted signal to obtain a compensated internal write command. It can be understood that the offset signal CMD2_E corresponding to the first processing circuit and the offset signal CMD2_O corresponding to the second processing circuit differ by one external clock cycle, the second clock signal PCLK_E2 corresponding to the first processing circuit and the second clock signal PCLK_O2 corresponding to the second processing circuit differ by one external clock cycle, and the periods of the first clock signal and the second clock signal are both two external clock cycles.

[0071] Based on the above-mentioned signal timing relationship, when the required write compensation amount is an even multiple of the external clock cycle, the first output sub-circuit 41 uses the second clock signal PCLK_E2 corresponding to the first processing circuit to sample the offset signal CMD2_E corresponding to the first processing circuit, that is, delays the offset signal CMD2_E by two tCKs. Similarly, the second output sub-circuit 42 uses the second clock signal PCLK_O2 corresponding to the second processing circuit to sample the offset signal CMD2_O corresponding to the second processing circuit, that is, delays the offset signal CMD2_O by two tCKs. Finally, the integration circuit sums the output signals of the first output sub-circuit and the second output sub-circuit. The final signal is equivalent to further delaying two tCKs on the basis of the first-level delay (even multiple delay), thereby achieving a compensation amount equivalent to an even multiple of the external clock cycle.

[0072] When the required write compensation amount is an odd multiple of the external clock cycle, the first output subcircuit 41 uses the second clock signal PCLK_E2 corresponding to the first processing circuit to sample the offset signal CMD2_O corresponding to the second processing circuit, that is, the offset signal CMD2_O is delayed by only one tCK. Similarly, the second output subcircuit 42 uses the second clock signal PCLK_O2 corresponding to the second processing circuit to sample the offset signal CMD2_E corresponding to the first processing circuit, that is, the offset signal CMD2_E is delayed by one tCK. Finally, the integration circuit sums the output signals of the first output subcircuit and the second output subcircuit. The final signal is equivalent to further delaying only one tCK on the basis of the first-level delay (even multiple delay), thereby achieving a compensation amount equivalent to an odd multiple of the external clock cycle. In practical applications, the level state of the parity indication signal can be used to characterize whether the compensation amount is an odd or even multiple of the external clock cycle. For example, when the parity indication signal is at a high level, it indicates that the compensation amount is an odd multiple of the external clock cycle, and a low level indicates an even multiple.

[0073] The specific structures of the first output sub-circuit, the second output sub-circuit and the integrated circuit are not limited. As an example, Fig.10FIG. 1 is a structural example diagram of an output circuit of an example, such as Fig.10 As shown, the first output sub-circuit 41 includes: a first AND gate 411, a second AND gate 412, a first NOR gate 413 and a third trigger 414; the first input end of the first AND gate 411 receives the offset signal CMD2_E corresponding to the first processing circuit 21, and the second input end receives the inverted signal SWB of the indication signal SW; the first input end of the second AND gate 412 receives the offset signal CMD2_O corresponding to the second processing circuit, and the second input end receives the indication signal SW; the input end of the first NOR gate 413 is connected to the output ends of the first AND gate 411 and the second AND gate 412 respectively, the output end of the first NOR gate 413 is connected to the input end of the third trigger 414, and the clock end of the third trigger 414 receives the second clock signal PCLK_E2 corresponding to the first processing circuit; the output end of the third trigger 414 is connected to the first input end of the integration circuit 43 The second output sub-circuit 42 comprises: a third AND gate 421, a fourth AND gate 422, a second NOR gate 423 and a fourth trigger 424; the first input end of the third AND gate 421 receives the offset signal CMD2_O corresponding to the second processing circuit, and the second input end receives the inverted signal SWB of the indication signal SW; the first input end of the fourth AND gate 422 receives the offset signal CMD2_E corresponding to the first processing circuit, and the second input end receives the indication signal SW; the input end of the second NOR gate 423 is respectively connected to the output ends of the third AND gate 421 and the fourth AND gate 422, the output end of the second NOR gate 423 is connected to the input end of the fourth trigger 424, and the clock end of the fourth trigger 424 receives the second clock signal PCLK_O2 corresponding to the second processing circuit; the output end of the fourth trigger 424 is connected to the second input end of the integration circuit 43. The integration circuit 43 includes a third NOR gate 431 and a first NOR gate 432, wherein the first input terminal of the third NOR gate 431 is connected to the output terminal of the first output sub-circuit 41, the second input terminal of the third NOR gate 431 is connected to the output terminal of the second output sub-circuit 42, the output terminal of the third NOR gate 431 is connected to the input terminal of the first NOR gate 432, and the output terminal of the first NOR gate 432 is used to output the internal write command after write compensation.

[0074] Based on the above example, the processing circuit 21 / 22 is composed of a plurality of offset sub-circuits 31, each of which receives a corresponding enable signal P<…> provided by the decoding circuit 21 based on the mode selection signal D4_P<…> and the mode register instruction MR3<…>, so as to perform basic delay compensation on the corresponding write command according to the enable signal. In combination with the above example, the mode selection signal D4_P<…> may include a first selection signal D4_P <0> and the second selection signal D4_P <1> ; First selection signal D4_P <0> The second selection signal D4_P is used to indicate whether the current working mode is the third mode D5TYPE. <1> It is used to indicate that the current working mode is the first mode D4TYPE_PRE4 or the second mode D4TYPE_PRE2 / 3. The mode register instruction MR3<…> may include the indication bit MDF_MR3 <0> and encoding bit MR3<n:1> Specifically, the encoding bit is MR3<n:1> Write the leveling encoding result MR3<n:1> The data segment except the last bit. Among them, MR3<n:1> It is the binary representation of the absolute value of the offset actually required for internal write leveling MDF_MR3<3:0> plus the indicator bit MDF_MR3 <0> The purpose is to realize the parity merging of the internal write leveling offset MR, so as to flexibly realize the write leveling offset of even or odd multiples of the external clock cycle. Combined with the example of Table 3, Table 3 is an example of the mode register instruction.

[0075] Table 3

[0076]

[0077] In Table 3, the coding bit MR3<n:1> The data length of 4 bits is used as an example, that is, n=3. In practical applications, the data length of the coded bits can be determined according to the requirements of write leveling. As an example, the indicator bit MDF_MR3 <0> It can be the lowest bit of the offset MDF_MR3<3:0>. Through this encoding method, the data structure of the mode register instruction can be simplified, and the internal write-leveled offset MR can be merged into an even-odd bit. It can be understood that based on the above encoding method, the indicator bit MDF_MR3 <0> A value of 0 indicates that the write leveling offset is an even multiple of the external clock cycle, and a value of 1 indicates that the write leveling offset is an odd multiple of the external clock cycle. Based on the mode selection signal D4_P<…> and the mode register instruction MR3<…>, the decoding circuit 11 outputs a parity indication signal SW and a plurality of enable signals P<…>. As an example, Fig.11 FIG. 1 is a schematic diagram of a decoding circuit as an example. Fig.11 As shown, the decoding circuit 11 includes: a parity decoding circuit 61 and a compensation decoding circuit 62;

[0078] Parity decoding circuit 61 receives the second selection signal D4_P <1> and the mode register instruction indication bit MDF_MR3 <0> , for selecting the second selection signal D4_P <1> and the mode register instruction indication bit MDF_MR3 <0> , determining whether the compensation amount is an odd or even multiple of the number of external clock cycles, when the compensation amount is an odd multiple of the number of external clock cycles, outputting the parity indication signal SW in a first state; and when the compensation amount is an even multiple of the number of external clock cycles, outputting the parity indication signal SW in a second state;

[0079] The compensation decoding circuit 62 receives the mode selection signal D4_P<…> and the encoding bit MR3 of the mode register instruction.<n:1> , used for the encoding bit MR3 of the mode selection signal D4_P<…> and the mode register instruction<n:1> Analyze and output multiple enable signals P<…>.

[0080] The fact that the odd / even indication signal is in different states indicates that the compensation amount is an odd or even multiple of the external clock cycle. <0> Different states indicate whether the current working mode is D5TYPE mode, for example, the first selection signal D4_P <0> 0 means D5TYPE mode, D4_P <0> 1 indicates that it is not D5TYPE mode. Further, the second selection signal D4_P <1> In different states, the current working mode is D4TYPE_PRE2 / 3 mode or D4TYPE_PRE4 mode. In one example, when the first selection signal D4_P <0> When it is 0, the second selection signal D4_P is designed by default <1> is 0.

[0081] For example, in combination with the above, it can be known that the compensation amount in the D4TYPE_PRE2 / 3 mode is 5 external clock cycles, that is, an odd multiple of the external clock cycle. <1> =1, the parity decoding circuit 61 should output the parity indication signal SW in the first state, for example, the first state is a high level state. For another example, the first selection signal D4_P <0> When it is 0, it indicates that the working mode is D5TYPE mode, and the parity of the compensation amount depends on whether the write leveling offset is an odd or even multiple of the external clock cycle. <0> Different states can indicate the parity of the write leveling offset. For example, when the indicator bit MDF_MR3 <0> When MDF_MR3 is 1, it indicates that the write leveling offset is an odd multiple of the external clock cycle, and the parity decoding circuit 61 outputs the parity indication signal SW in the first state, for example, a high level signal. <0> When the second selection signal D4_P is 0, the parity decoding circuit 61 outputs the parity indication signal SW in the second state, for example, a low level signal. <1> and the mode register instruction indication bit MDF_MR3 <0> When any of is 1, the parity indication signal SW at a high level is output, otherwise the parity indication signal SW at a low level is output. For example, Fig.12 FIG. 1 is a schematic diagram of a decoding circuit as an example. Fig.12 As shown, the parity decoding circuit 61 may include a fourth NOR gate 611 and a second NOR gate 612; the first input terminal of the fourth NOR gate 611 receives the second selection signal D4_P <1> The second input terminal receives the indication bit MDF_MR3 <0> The output end of the fourth NOR gate 611 is connected to the input end of the second NOR gate 612, and the output end of the second NOR gate 612 is used to output the parity indication signal SW. It should be noted that the figure is only an example, and the parity decoding circuit 61 can also be implemented by an OR gate structure, and its specific method is not limited here.

[0082] In combination with the above example, two-stage compensation is adopted, that is, the basic compensation is superimposed on the odd / even offset to achieve the complete compensation amount. Specifically, the compensation decoding circuit 62 outputs multiple enable signals based on the mode selection signal and the coding bit, wherein the enable signal corresponding to the currently required basic compensation amount is in a valid state, and the other enable signals are in an invalid state, so that each processing circuit 21 / 22 applies the delay of the basic compensation amount to the respective input signal according to the enable signal. As an example, Fig.12 As shown, the compensation decoding circuit 62 includes: a plurality of decoding sub-circuits 621 corresponding one-to-one to the plurality of offset sub-circuits 31;

[0083] Each decoding subcircuit 621 receives the encoding bit of the mode register instruction, and is used to detect whether the current value of the encoding bit of the mode register instruction is consistent with the valid value corresponding to the decoding subcircuit 621, and outputs a valid enable signal P<…> if they are consistent, otherwise outputs an invalid enable signal P<…>;

[0084] The decoding subcircuit 621 corresponding to the last-stage offset subcircuit 31 further receives the mode selection signal D4_P<…>, and is used to output an invalid enable signal P<…> when the current working mode is the first mode or the second mode according to the mode selection signal D4_P<…>; and, when the current working mode is the third mode, detect whether the current value of the encoding bit of the mode register instruction is consistent with the valid value corresponding to the decoding subcircuit 621, and output a valid enable signal P<…> if they are consistent, otherwise output an invalid enable signal P<…>;

[0085] The decoding subcircuit 621 corresponding to the last-stage previous-stage offset subcircuit 31 also receives a mode selection signal D4_P<…>, and is used to output a valid enable signal P<…> when the current working mode is the first mode or the second mode according to the mode selection signal D4_P<…>; and, when the mode selection signal D4_P<…> indicates that the current mode is in the third mode, detect whether the current value of the encoding bit of the mode register instruction is consistent with the valid value corresponding to the decoding subcircuit 621, and if they are consistent, output a valid enable signal P<…>, otherwise output an invalid enable signal P<…>.

[0086] Specifically, this example uses the decoding principle to output multiple enable signals according to the coding bits of the mode register instruction. Different valid enable signals correspond to different basic delays. In combination with the above examples, for the first mode and the second mode, the basic delay is determined. For example, in one example, when the burst length is 16, the basic delays corresponding to the D4TYPE_PRE4 mode and the D4TYPE_PRE2 / 3 mode are both 4 external clock cycles. Then, for the D4TYPE_PRE4 mode, an even offset is superimposed to achieve a compensation amount of 6 external clock cycles, and for the D4TYPE_PRE2 / 3 mode, an odd offset is superimposed to achieve a compensation amount of 5 external clock cycles. In view of the fact that these two working modes have a certain basic delay, this example is for the decoding subcircuit corresponding to the last-stage offset subcircuit and the penultimate-stage offset subcircuit. On the basis of designing that it can realize basic delay decoding in the third mode according to the coding bit, it further designs its decoding function in the first mode and the second mode. Taking the basic delays corresponding to the first mode and the second mode as 4 external clock cycles, assuming that each level of the offset subcircuit applies a delay of 2 external clock cycles, the decoding subcircuit corresponding to the second-to-last level offset subcircuit outputs a valid enable signal to the second-to-last level offset subcircuit of each processing circuit when detecting that the current mode is the first / second mode. Accordingly, the second-to-last level offset subcircuit in each processing circuit delays the received write command by 2 external clock cycles and then outputs it to the last level offset subcircuit when its own enable signal is valid. Specifically, the decoding subcircuit corresponding to the last level offset subcircuit detects that the current mode is the first / second mode, and then outputs an invalid enable signal to the last level offset subcircuit of each processing circuit. Accordingly, the last level offset subcircuit in each processing circuit delays the signal output by the previous level offset subcircuit, that is, the second-to-last level offset subcircuit, by 2 external clock cycles and then outputs it as the offset signal corresponding to the processing circuit, completing the application of the basic delay of 4 external clock cycles. That is to say, when the first / second mode is currently in effect, the enable signals output by the latter two levels of encoding sub-circuits are fixed and have nothing to do with the values ​​of the encoding bits of the mode register instructions, thereby achieving a determined basic delay for the write command in the first / second mode, which is independent of the encoding bits of the mode register instructions.

[0087] In combination with the example in which the processing circuit 21 / 22 includes a six-stage offset subcircuit 31, for example, Fig.12As shown, the decoding sub-circuit 621 corresponding to the last-stage offset sub-circuit includes: a first multi-input NOR gate 71, a third NOR gate 72, a second multi-input NOR gate 73 and a fourth NOR gate 74; the input end of the first multi-input NOR gate 71 receives the encoding bit MR3<3:1> of the mode register instruction, and the output end of the first multi-input NOR gate 71 is connected to the input end of the third NOR gate 72; the first input end of the second multi-input NOR gate 73 is connected to the output end of the third NOR gate 72, and the second input end of the second multi-input NOR gate 73 receives the mode signal D4_P <0> and D4_P <1> The output terminal of the second multi-input NOR gate 73 is used to output the enable signal P of the last stage offset sub-circuit. <0> The input end of the fourth NOT gate 74 is connected to the output end of the second multi-input NOR gate 73, and the output end of the fourth NOT gate 74 is used to output the enable signal P of the last stage offset sub-circuit <0> The inverted signal P <0> B;

[0088] The decoding subcircuit 621 corresponding to the last stage of the previous stage offset subcircuit includes: a first multi-input NAND gate 75, a second multi-input NAND gate 76 and a fifth NAND gate 77; the input end of the first multi-input NAND gate 75 receives the corresponding multiple input signals (shown as MR3 <1> 、MR3 <2> B and MR3 <3> B), the output end of the first multi-input NAND gate 75 is connected to the first input end of the second multi-input NAND gate 76, and the second input end of the second multi-input NAND gate 76 receives the inverted signal D4_P of the mode signal <0> B and D4_P <1> B, the output end of the second multi-input NAND gate 76 is used to output the enable signal P of the last stage of the previous stage offset sub-circuit <2> The input end of the fifth NOT gate 77 is connected to the output end of the second multi-input NAND gate 76, and the output end of the fifth NOT gate 77 is used to output the inverted signal P of the enable signal of the last stage of the previous stage offset sub-circuit <2> B;

[0089] The decoding subcircuit 621 corresponding to each offset subcircuit except the last two stages includes: a third multi-input AND gate 78 and a sixth NOT gate 79; the third multi-input AND gate 78 receives the corresponding multiple input signals, and the output end of the third multi-input AND gate 78 is connected to the input end of the sixth NOT gate 79; the output end of the sixth NOT gate 79 is used to output the enable signal corresponding to the offset subcircuit;

[0090] Among them, the multiple input signals corresponding to the decoding subcircuit include the 1st input signal, the 2nd input signal, ..., the ith input signal, ..., the nth input signal; if the ith bit in the effective value corresponding to the decoding subcircuit is a high level, the ith input signal is the ith bit of the coding bit of the mode register instruction; if the ith bit in the effective value corresponding to the decoding subcircuit is a low level, the ith input signal is the inverted signal of the ith bit of the coding bit of the mode register instruction, wherein 1≤i≤n, i is an integer. It should be noted that the above is only an example. As long as the enable signal for controlling the basic delay required for the execution of the processing circuit can be output in the first mode, the second mode and the third mode, the specific implementation method of the decoding circuit is not limited here. Still taking the example of the processing circuit 21 / 22 including a six-stage offset subcircuit 31, the enable signal corresponding to each offset subcircuit includes P <0> , P <2> …P <8> , P <10> As an example, P <4> The corresponding input signal of the decoding sub-circuit 621 includes MR3 <1> B. MR3 <2> and MR3 <3> B; P <6> The corresponding input signal of the decoding sub-circuit 621 includes MR3 <1> 、MR3 <2> and MR3 <3> B; P <8> The corresponding input signal of the decoding sub-circuit 621 includes MR3 <1> B. MR3 <2> B and MR3 <3> ;P <10> The corresponding input signal of the decoding subcircuit 621 includes P <8> B. and MR3 <3> Here, by using other enable signals as input signals corresponding to a decoding sub-circuit corresponding to a certain enable signal, the number of input signals can be effectively reduced, and the circuit structure can be further simplified.

[0091] In practical applications, considering the timing matching, a timing matching circuit can be set to perform timing matching processing on the internal write command, and then the compensation circuit performs compensation. For example, Fig.13 As shown, Fig.13 2 is a structural example diagram of an exemplary timing matching circuit, wherein the write compensation circuit further includes: a timing matching circuit 24; the timing matching circuit 24 includes: an even number of first inverters 241 (two are used as an example in the figure), an even number of second inverters 244 (two are used as an example in the figure), a delay unit 242, and a fifth NOR gate 243;

[0092] An even number of first inverters 241 are connected in series, and the first first inverter receives the inverted signal of the internal write command; the even number of first inverters 241 are connected in series and connected to the input end of the delay unit 242, the output end of the delay unit 242 is connected to the first input end of the fifth NOR gate 243, the second input end of the fifth NOR gate 243 receives the automatic precharge enable signal AP_EN, and the output end of the fifth NOR gate 243 is connected in series with an even number of second inverters 244 connected in series; the timing matching circuit 24 is used to output the internal write command after the timing matching processing.

[0093] In combination with the above example, two timing matching circuits may be provided, which are used to respectively perform timing matching processing on the inverted signals of INT_WRCMD_E and INT_WRCMD_O, namely INT_WRCMD_EB and INT_WRCMD_OB, and then use them as the write commands RMW_E and RMW_O corresponding to the first processing circuit 21 and the second processing circuit 22, respectively, and input them to the first processing circuit 21 and the second processing circuit 22 for basic shifting. Correspondingly, as Figure 7 As shown, a third inverter 318 is required to be provided at the output end of the last stage offset subcircuit 31 in the first processing circuit 21 and the second processing circuit 22, for outputting the offset signals CMD2_E and CMD2_O. Specifically, in this example, the inverted signal of the write command is subjected to a basic offset and then inverted again, and then respectively input to the first output word circuit 41 and the second output subcircuit 42 of the output circuit 23, and finally the internal write command after write compensation output by the output circuit 23 is obtained.

[0094] The write compensation circuit provided in this embodiment includes a decoding circuit and a compensation circuit. The decoding circuit determines the compensation amount of this time according to the mode selection signal and the mode register instruction, and outputs a parity indication signal used to characterize that the compensation amount of this time is an odd or even multiple of the external clock cycle and an enable signal corresponding to each offset, wherein only the enable signal corresponding to the offset corresponding to the current working mode is valid, and the compensation circuit performs delay compensation for the internal write command according to the parity indication signal and the enable signal according to the compensation amount of this time when the automatic precharge enable signal is valid. The specific compensation is to apply the delay of the offset corresponding to the current working mode to the internal write command, and further superimpose the delay of applying the odd offset or even offset. This scheme is for different working modes. By applying an odd offset or even offset on the basis of the corresponding offset, the internal write command is delayed and compensated, thereby satisfying the signal timing relationship required when the chip is in a write command operation including automatic precharge, and realizing a flexible write compensation scheme.

[0095] Fig.14 A structural example diagram of a memory is shown as follows: Fig.14 As shown, the memory includes: a storage array 1, and a write compensation circuit 2 as any of the aforementioned examples.

[0096] In combination with the above solution, for example, the external clock CK_t / CK_c is divided into the internal odd clock PCLK_O and the internal even clock PCLK_E for sampling after passing through the receiver of the memory. That is, each stage of DFF will shift the input signal by 2T CK and output it accordingly. Fig.15 A timing diagram of an example is shown in FIG. Fig.15As shown, assuming that the current D4_P <0> and D4_P <1> The signal is 0, which means the current working mode is D5TYPE mode. Assuming the burst length is 16 bits, MR3<n:1> =011, and MDF_MR3 <0> =1, it means that the original write leveling encoding result MR3<3:0> is -5tCK, but it is encoded as -6tCK after parity merging. In this example, the shift added to the internal write signal is CWL+4-MR3, which needs to be compensated to CWL+8. Therefore, the amount to be compensated is CWL+8-(CWL+4-MR3)=4+5=9, that is, 9 external clock cycles tCK.

[0097] After being processed by the decoding circuit 11, it is assumed that among the multiple enable signals output by the decoding circuit 11, P <6> If the signal is valid, the Figure 7 In the exemplary circuit, taking the write signal RMW_E corresponding to the first processing circuit 21 as an example, the RMW_E signal is substantially composed of P <6> The corresponding offset sub-circuit 31 input, assuming that each stage of the offset sub-circuit delays 2 tCK, then after P <6> The corresponding offset sub-circuit 31, P <4> The corresponding offset sub-circuit 31, P <2> The corresponding offset subcircuit 31 and P <0> The corresponding offset subcircuit 31 outputs the offset signal CMD2_E corresponding to the first processing circuit 21, which is compensated by 8 tCKs compared to the RMW_E signal. In addition, since the amount to be compensated this time is an odd multiple of the external clock cycle, the SW signal is valid, for example, at a high level, which means that only 1 tCK of compensation needs to be added through the output circuit 23. Fig.10 In the output circuit shown in FIG. 1 , if the SW signal is not activated, for example, at a low level, the CMD2_E should continue to be sampled by the first output sub-circuit 41 based on the second clock signal PCLK_E2 corresponding to the first processing circuit, that is, the superposition compensation of 2tCK is realized and then output to the integration circuit. However, now the SW signal is at a high level and the SWB signal is at a low level. Fig.10As shown, the CMD2_E signal will be sampled by the second output sub-circuit 42 based on the second clock signal PCLK_O2 corresponding to the second processing circuit. Since the PCLK_E2 and PCLK_O2 signals differ by 1tCK, the second output sub-circuit 42 samples CMD2_E at this time, and the output signal is only shifted by 1tCK compared to CMD2_E. Finally, after integration processing by the integration circuit 43, the output compensated INT_WRCMD signal is compensated by 8+1=9TCK compared to the original INT_WRCMD to achieve odd-numbered compensation. It can be understood that the above is only an example. For example, if the amount to be compensated is an even multiple of the external clock, SW is at a low level, so the offset signal output by the first processing circuit and the second processing circuit continues to be sampled by the first output sub-circuit and the second output sub-circuit based on their respective second clock signals, that is, 2tCK is superimposed, and finally passes through the integration circuit to obtain a write signal compensated by an even multiple of tCK.

[0098] In the memory provided by the present embodiment, the write compensation circuit includes a decoding circuit and a compensation circuit. The decoding circuit determines the compensation amount of this time according to the mode selection signal and the mode register instruction, and outputs a parity indication signal used to characterize that the compensation amount of this time is an odd or even multiple of the external clock cycle and an enable signal corresponding to each offset, wherein only the enable signal corresponding to the offset corresponding to the current working mode is valid, and the compensation circuit performs delay compensation for the internal write command according to the parity indication signal and the enable signal according to the compensation amount of this time when the automatic precharge enable signal is valid. The specific compensation is to apply the delay of the offset corresponding to the current working mode to the internal write command, and further superimpose the delay of applying the odd offset or the even offset. This scheme is for different working modes. By applying the odd offset or the even offset on the basis of the corresponding offset, the internal write command is delayed and compensated, thereby satisfying the signal timing relationship required when the chip is in a write command operation including automatic precharge, and realizing a flexible write compensation scheme.

[0099] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are intended to be exemplary only.

[0100] It should be understood that the present disclosure is not limited to the exact construction that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof.

Claims

1. A write compensation circuit, It is characterized in that include: Decoding circuit and compensation circuit; The decoding circuit receives a mode selection signal and a mode register instruction, and is used to determine the compensation amount corresponding to the current working mode and output a parity indication signal and a plurality of enable signals according to the mode selection signal and the mode register instruction, wherein different enable signals correspond to different offsets; wherein, among the enable signals, only the enable signal corresponding to the offset corresponding to the compensation amount corresponding to the current working mode is valid, and the parity indication signal indicates whether the compensation amount corresponding to the current working mode is an odd or even multiple of an external clock cycle; The compensation circuit is coupled to the decoding circuit, and is used to compensate the internal write command obtained based on the external write command according to the parity indication signal and the multiple enable signals according to the corresponding compensation amount when the automatic pre-charge enable signal is valid, so that the external write command completes the preset delay amount in different modes, and the compensation amount is obtained by superimposing the odd offset or the even offset on the offset corresponding to the compensation amount.

2. The write compensation circuit according to claim 1, It is characterized in that The working modes include a first mode, a second mode and a third mode; The transmission rate corresponding to the first mode is not greater than the preset value and the preamble code of the data selection signal is 4 external clock cycles, the transmission rate corresponding to the second mode is not greater than the preset value and the preamble code of the data selection signal is 2 or 3 external clock cycles; the transmission frequency corresponding to the third mode is greater than the preset value.

3. The write compensation circuit according to claim 2, It is characterized in that The preset delay amount is the sum of the number of external clock cycles corresponding to the column address strobe pulse write delay and half of the burst length; The compensation amount corresponding to the first mode is six external clock cycles; the compensation amount corresponding to the second mode is five external clock cycles; the compensation amount corresponding to the third mode is the sum of four external clock cycles and the absolute value of the offset represented by the mode register instruction.

4. The write compensation circuit according to claim 2 or 3, It is characterized in that The compensation circuit includes: two processing circuits, respectively denoted as a first processing circuit and a second processing circuit, and an output circuit; The first processing circuit and the second processing circuit are respectively used for, when the automatic precharge enable signal is valid, offsetting the corresponding write command according to the offset corresponding to the valid enable signal according to the multiple enable signals to obtain the corresponding offset signal; wherein the write commands corresponding to the first processing circuit and the second processing circuit are obtained by sampling the internal write command based on the internal even clock and the internal odd clock respectively; wherein the offset corresponding to the enable signal is an even number of external clock cycles, the clock cycles of the internal even clock and the internal odd clock are twice the external clock cycle, and the phase difference between the internal even clock and the internal odd clock is one external clock cycle; The output circuit is connected to the decoding circuit, the first processing circuit and the second processing circuit, and is used to offset the offset signals corresponding to the first processing circuit and the second processing circuit according to an odd offset or an even offset according to the parity indication signal and perform an OR logic operation on the offset signals to obtain a compensated internal write command.

5. The write compensation circuit according to claim 4, It is characterized in that Each processing circuit includes: a plurality of cascaded offset subcircuits corresponding one-to-one to the plurality of enable signals; The first-stage offset subcircuit receives a write command corresponding to the processing circuit and an enable signal corresponding to the offset subcircuit; each offset subcircuit except the first-stage receives a write command corresponding to the processing circuit and an enable signal corresponding to the offset subcircuit, and is connected to the output end of the offset subcircuit of the previous stage; Each level of offset subcircuit is used to delay and output the received write command when the enable signal corresponding to the offset subcircuit is valid; and to delay and output the signal output by the previous level of offset subcircuit when its own enable signal is invalid; the last level of offset subcircuit is used to output the offset signal corresponding to the processing circuit where it is located; wherein the total delay amount of the offset subcircuit corresponding to the valid enable signal and all subsequent offset subcircuits is the offset amount corresponding to the valid enable signal.

6. The write compensation circuit according to claim 5, It is characterized in that The mode selection signal includes a first selection signal and a second selection signal; the first selection signal is used to indicate whether the current working mode is the third mode, and the second selection signal is used to indicate whether the current working mode is the first mode or the second mode; the mode register instruction includes an indication bit and a coding bit; The decoding circuit comprises: an odd-even decoding circuit and a compensation decoding circuit; The parity decoding circuit receives the second selection signal and the indication bit of the mode register instruction, and is used to determine whether the compensation amount is an odd multiple or an even multiple of the number of external clock cycles according to the second selection signal and the indication bit of the mode register instruction, and outputs the parity indication signal in a first state when the compensation amount is an odd multiple of the number of external clock cycles; and outputs the parity indication signal in a second state when the compensation amount is an even multiple of the number of external clock cycles; The compensation decoding circuit receives the mode selection signal and the coding bits of the mode register instruction, and is used to parse the mode selection signal and the coding bits of the mode register instruction and output the multiple enable signals.

7. The write compensation circuit according to claim 6, It is characterized in that The compensation decoding circuit includes: a plurality of decoding sub-circuits corresponding one-to-one to the plurality of offset sub-circuits; Each decoding subcircuit receives the encoding bit of the mode register instruction, and is used to detect whether the current value of the encoding bit of the mode register instruction is consistent with the valid value corresponding to the decoding subcircuit, and outputs a valid enable signal if they are consistent, otherwise outputs an invalid enable signal; The decoding subcircuit corresponding to the last-stage offset subcircuit further receives the mode selection signal, and is used to output an invalid enable signal according to the mode selection signal when the current working mode is the first mode or the second mode; and, when the current working mode is the third mode, detect whether the current value of the encoding bit of the mode register instruction is consistent with the valid value corresponding to the decoding subcircuit, and output a valid enable signal if they are consistent, otherwise output an invalid enable signal; The decoding subcircuit corresponding to the last-stage previous-stage offset subcircuit also receives the mode selection signal, and is used to output a valid enable signal according to the mode selection signal when the current operating mode is the first mode or the second mode; and when the mode selection signal indicates that the current mode is in the third mode, detect whether the current value of the encoding bit of the mode register instruction is consistent with the valid value corresponding to the decoding subcircuit, and if they are consistent, output a valid enable signal, otherwise output an invalid enable signal.

8. The write compensation circuit according to claim 7, It is characterized in that The decoding subcircuit corresponding to the last-stage offset subcircuit includes: a first multi-input NOR gate, a third NOR gate, a second multi-input NOR gate and a fourth NOR gate; the input end of the first multi-input NOR gate receives the encoding bit of the mode register instruction, and the output end of the first multi-input NOR gate is connected to the input end of the third NOR gate; the first input end of the second multi-input NOR gate is connected to the output end of the third NOR gate, the second input end of the second multi-input NOR gate receives the mode signal, and the output end of the second multi-input NOR gate is used to output the enable signal of the last-stage offset subcircuit; the input end of the fourth NOR gate is connected to the output end of the second multi-input NOR gate, and the output end of the fourth NOR gate is used to output the inverted signal of the enable signal of the last-stage offset subcircuit; The decoding subcircuit corresponding to the last-stage previous-stage offset subcircuit comprises: a first multi-input AND gate, a second multi-input AND gate and a fifth NOT gate; the input end of the first multi-input AND gate receives the corresponding multiple input signals, the output end of the first multi-input AND gate is connected to the first input end of the second multi-input AND gate, the second input end of the second multi-input AND gate receives the inverted signal of the mode signal, and the output end of the second multi-input AND gate is used to output the enable signal of the last-stage previous-stage offset subcircuit; the input end of the fifth NOT gate is connected to the output end of the second multi-input AND gate, and the output end of the fifth NOT gate is used to output the inverted signal of the enable signal of the last-stage previous-stage offset subcircuit; The decoding subcircuit corresponding to each level of the offset subcircuit except the last two levels includes: a third multi-input AND gate and a sixth NOT gate; the third multi-input AND gate receives the corresponding multiple input signals, the output end of the third multi-input AND gate is connected to the input end of the sixth NOT gate; the output end of the sixth NOT gate is used to output the enable signal corresponding to the offset subcircuit; Among them, the multiple input signals corresponding to the decoding subcircuit include the first input signal, the second input signal, ..., the i-th input signal, ..., the n-th input signal; if the i-th bit in the effective value corresponding to the decoding subcircuit is a high level, the i-th input signal is the i-th bit of the encoding bit of the mode register instruction; if the i-th bit in the effective value corresponding to the decoding subcircuit is a low level, the i-th input signal is the inverted signal of the i-th bit of the encoding bit of the mode register instruction, wherein 1≤i≤n, i is an integer.

9. The write compensation circuit according to claim 5, It is characterized in that A first-stage offset subcircuit comprises: a first NAND gate, a seventh NAND gate and a first trigger; a first input end of the first NAND gate receives an enable signal of the first-stage offset subcircuit, and a second input end of the first NAND gate receives a write command corresponding to a processing circuit; an input end of the seventh NAND gate is connected to an output end of the first NAND gate, an output end of the seventh NAND gate is connected to an input end of the first trigger, and a clock end of the first trigger receives a first clock signal corresponding to the processing circuit; Each level of offset subcircuit except the first level includes: a second NAND gate, a third NAND gate, a fourth NAND gate and a second trigger; the first input end of the second NAND gate receives an enable signal of the offset subcircuit, and the second input end of the second NAND gate receives a write command corresponding to the processing circuit; the first input end of the third NAND gate receives an inverted signal of the enable signal of the offset subcircuit, and the second input end of the third NAND gate is connected to the output end of the previous level of offset subcircuit; the first input end of the fourth NAND gate is connected to the output end of the second NAND gate, the second input end of the fourth NAND gate is connected to the output end of the third NAND gate, and the output end of the fourth NAND gate is connected to the input end of the second trigger; the clock end of the second trigger receives a first clock signal corresponding to the processing circuit; The period of the first clock signal is a sub-offset, and the phase difference between the first clock signal corresponding to the first processing circuit and the first clock signal corresponding to the second processing circuit is the phase difference between the internal even clock and the internal odd clock.

10. The write compensation circuit according to claim 6, It is characterized in that The output circuit comprises: a first output sub-circuit, a second output sub-circuit and an integration circuit; The first output subcircuit is connected to the parity decoding circuit, the first processing circuit and the second processing circuit, and is used for sampling and outputting the offset signal corresponding to the second processing circuit based on the second clock signal corresponding to the first processing circuit in response to the parity indication signal in the first state; and sampling and outputting the offset signal corresponding to the first processing circuit based on the second clock signal corresponding to the first processing circuit in response to the parity indication signal in the second state; The second output subcircuit is connected to the parity decoding circuit, the first processing circuit and the second processing circuit, and is used to sample and output the offset signal corresponding to the first processing circuit based on the second clock signal corresponding to the second processing circuit in response to the parity indication signal in the first state; and sample and output the offset signal corresponding to the second processing circuit based on the second clock signal corresponding to the second processing circuit in response to the parity indication signal in the second state; The integration circuit is connected to the first output sub-circuit and the second output sub-circuit, and is used to perform an OR logic operation on the output signals of the first output sub-circuit and the second output sub-circuit, and output the compensated internal write command; wherein the second clock signal corresponding to the first processing circuit and the second clock signal corresponding to the second processing circuit have the same period, and the phase difference between the two is the phase difference between the internal even clock and the internal odd clock.

11. A memory, It is characterized in that include: A storage array and a write compensation circuit as claimed in any one of claims 1 to 10.

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