Voltage determination circuit and memory

Abstract

The invention discloses a voltage determination circuit and a memory, the voltage determination circuit comprises a first determination module, a second determination module and a third determination module, and the second determination module determines a second read potential value of a word line based on a target error number and a first read potential value provided by the first determination module; and a third determination module determines a third read potential value of the second bit line based on the first read potential value or the second read potential value, so that a relatively accurate read voltage can be applied to the storage unit according to the first read potential value, the second read potential value and the third read potential value, and the accuracy of the read voltage is further improved.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a voltage determination circuit and a memory. Background Art

[0002] In three-dimensional phase-change memory, the read voltage applied to the memory cell is closely related to the data extraction, device power consumption and service life of the final product.

[0003] Therefore, how to accurately determine the read voltage becomes an urgent problem to be solved. Summary of the invention

[0004] The present application provides a voltage determination circuit and a memory to alleviate the technical problem of low accuracy in reading voltage.

[0005] In a first aspect, the present application provides a voltage determination circuit, which is applied to a memory, wherein the memory includes a first bit line, a second bit line, a word line, a first storage unit and a second storage unit, the first storage unit is connected to the first bit line and the word line, and the second storage unit is connected to the second bit line and the word line, the voltage determination circuit includes a first determination module, a second determination module and a third determination module, the first determination module is configured to determine a first read potential value of the first bit line; the second determination module is connected to the first determination module, the second determination module is configured to determine a second read potential value of the word line based on a target error number and the first read potential value; the third determination module is connected to at least one of the first determination module and the second determination module, the third determination module is configured to determine a third read potential value of the second bit line based on the first read potential value or the second read potential value.

[0006] In a second aspect, the present application provides a memory, which includes a first bit line, a second bit line, a word line, a first storage unit, a second storage unit and the above-mentioned voltage determination circuit, the first storage unit is connected to the first bit line and the word line, and the second storage unit is connected to the second bit line and the word line.

[0007] The voltage determination circuit and memory provided in the present application determine the second read potential value of the word line based on the target error number and the first read potential value provided by the first determination module through the second determination module, and determine the third read potential value of the second bit line based on the first read potential value or the second read potential value through the third determination module, so that a more accurate read voltage can be applied to the storage unit according to the first read potential value, the second read potential value and the third read potential value, thereby improving the accuracy of the read voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0009] Figure 1 It is a structural schematic diagram of a storage array in the related art.

[0010] Figure 2 is a schematic diagram of a normal distribution of the threshold voltage of a memory cell.

[0011] Figure 3 This is a first principle block diagram of a voltage determination circuit provided in an embodiment of the present application.

[0012] Figure 4 This is a first principle block diagram of the second determination module.

[0013] Figure 5 A schematic diagram of the relationship between the cumulative number of errors and the read voltage provided in an embodiment of the present application.

[0014] Figure 6 This is a principle block diagram of the first acquisition unit provided in an embodiment of the present application.

[0015] Figure 7 A first principle block diagram of the third determination module provided in an embodiment of the present application.

[0016] Figure 8 This is a second principle block diagram of the second determination module.

[0017] Fig. 9 This is a principle block diagram of the second acquisition unit provided in an embodiment of the present application.

[0018] Fig.10 A second principle block diagram of the third determination module provided in an embodiment of the present application.

[0019] Fig.11 A schematic diagram of the relationship between a read voltage and a bit line voltage provided in an embodiment of the present application.

[0020] Fig.12 A second principle block diagram of the voltage determination circuit provided in an embodiment of the present application.

[0021] Fig.13 A functional block diagram of a memory provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0023] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of technical features indicated. Therefore, the features specified as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0024] Figure 1 The figure shows a schematic diagram of the structure of a storage array in a three-dimensional phase change memory. The storage array includes a first bit line BL1, a second bit line BL2, a word line WL, a first storage cell PCM1 and a second storage cell PCM2. The first storage cell PCM1 is connected to the first bit line BL1 and the word line WL, and the second storage cell PCM2 is connected to the second bit line BL2 and the word line WL. The first storage cell PCM1 and the second storage cell PCM2 located in the same column share the same word line WL, which reduces the number of word lines WL used, and is also conducive to reducing the number of power supplies used to provide corresponding voltages for the word lines WL.

[0025] Figure 2 Schematic diagram of the normal distribution of the threshold voltage of the memory cell. The Count shown on the vertical axis represents the number of memory cells, and the Vt shown on the horizontal axis represents the threshold voltage of the memory cell. The first curve W1 represents the normal distribution of the threshold voltage in the set (SET) state, and the second curve W2 represents the normal distribution of the threshold voltage in the reset (RESET) state. It can be seen that the minimum threshold voltage shown in the second curve W2 is greater than the maximum threshold voltage shown in the first curve W1.

[0026] As the memory usage time increases, the first curve W1 and the second curve W2 will move to the right. In order to ensure that the correct data "1" can be read from the storage unit shown in the first curve W1 and the correct data "0" can be read from the storage unit shown in the second curve W2, the read voltage Vread can be selected to be between the maximum threshold voltage shown in the first curve W1 and the minimum threshold voltage shown in the second curve W2, for example, Vt in the RESET state -3.5σ This ensures that the correct data “0” is read from the storage unit shown in the second curve W2, and at the same time, a sufficient time drift window can be reserved for the first curve W1.

[0027] By gradually increasing the read voltage Vread applied to the memory cell in the RESET state, erroneous data “1” will be read from the memory cell shown in the second curve W2 , and the number of erroneous data “1” read is the cumulative error number.

[0028] This embodiment provides a voltage determination circuit 100. Figures 3 to 11 ,like Figure 3 As shown, the voltage determination circuit 100 includes a first determination module 10, a second determination module 20 and a third determination module 30. The first determination module 10 is configured to determine a first read potential value Vb1 of the first bit line BL1; the second determination module 20 is connected to the first determination module 10, and the second determination module 20 is configured to determine a second read potential value Vb2 of the word line WL based on a target error number and the first read potential value Vb1; the third determination module 30 is connected to at least one of the first determination module 10 and the second determination module 20, and the third determination module 30 is configured to determine a third read potential value Vb3 of the second bit line BL2 based on the first read potential value Vb1 or the second read potential value Vb2.

[0029] It can be understood that the voltage determination circuit 100 provided in this embodiment determines the second read potential value Vb2 of the word line WL based on the target error number and the first read potential value Vb1 provided by the first determination module 10 through the second determination module 20, and the third determination module 30 determines the third read potential value Vb3 of the second bit line BL2 based on the first read potential value Vb1 or the second read potential value Vb2, so that a more accurate read voltage Vread can be applied to the storage cell according to the first read potential value Vb1, the second read potential value Vb2 and the third read potential value Vb3, thereby improving the accuracy of the read voltage Vread.

[0030] It should be noted that the first read potential value Vb1 may be preset or fixed. The target error number corresponds to the cumulative error number, both representing the number of erroneous data "1" read from the storage unit shown in the second curve W2, wherein the target error number is a preset integer value.

[0031] In some embodiments, such as Figure 4As shown, the second determination module 20 includes a first acquisition unit 21, a first determination unit 22 and a first adding unit 23. The first acquisition unit 21 is configured to acquire a first parameter curve of the first storage cell PCM1 and a second parameter curve of the second storage cell PCM2. The first parameter curve is a relationship curve between the cumulative number of errors of the first storage cell PCM1 and the read voltage Vread, and the second parameter curve is a relationship curve between the cumulative number of errors of the second storage cell PCM2 and the read voltage Vread; the first determination unit 22 is connected to the first acquisition unit 21, and the first determination unit 22 is configured to determine a first target read voltage value of the first storage cell PCM1 according to the target number of errors and the first parameter curve, and to determine a second target read voltage value of the second storage cell PCM2 according to the target number of errors and the second parameter curve; the first adding unit 23 is connected to the first determination module 10 and the first determination unit 22, and the first adding unit 23 is configured to calculate the sum of the first read potential value Vb1 and the first target read voltage value as the second read potential value Vb2.

[0032] It should be noted that the accumulated error number of the first storage unit PCM1 may be equal to the accumulated error number of the second storage unit PCM2, and the accumulated error number of the first storage unit PCM1 may also be greater than or less than the accumulated error number of the second storage unit PCM2.

[0033] Figure 5 A schematic diagram of the relationship between the cumulative number of errors and the read voltage Vread provided in an embodiment of the present application.

[0034] The vertical axis EN1 represents the cumulative number of errors, and the horizontal axis Vread represents the read voltage Vread. S1 represents the first parameter curve, S2 represents the second parameter curve, and SD1 represents the ideal relationship curve between the cumulative number of errors and the read voltage Vread. Vread1 represents the first target read voltage value, and Vread2 represents the second target read voltage value. MEN1 represents the target number of errors.

[0035] In some embodiments, such as Figure 6 As shown, the first acquisition unit 21 includes a first scanning subunit 211 and a first statistical subunit 212. The first scanning subunit 211 is configured to gradually raise the second read potential value Vb2 of the first storage cell PCM1 and the second storage cell PCM2 respectively; the first statistical subunit 212 is connected to the first scanning subunit 211 and the first determination unit 22, and the first statistical subunit 212 is configured to count the cumulative number of errors and the read voltage Vread of the first storage cell PCM1 and the cumulative number of errors and the read voltage Vread of the second storage cell PCM2 based on the second read potential value Vb2, and obtain a first parameter curve and a second parameter curve.

[0036] It should be noted that the method for obtaining the first parameter curve and the second parameter curve provided in this embodiment is only for illustration and is not limited thereto. Other methods for obtaining the first parameter curve and the second parameter curve may also be used.

[0037] In some embodiments, such as Figure 7 As shown, the third determination module 30 includes a first subtraction unit 31 and a second subtraction unit 32, the first subtraction unit 31 is connected to the first determination unit 22, and the first subtraction unit 31 is configured to calculate a first difference between the first target read voltage value and the second target read voltage value; the second subtraction unit 32 is connected to the first determination module 10 and the first subtraction unit 31, and the second subtraction unit 32 is configured to calculate a second difference between the first read potential value Vb1 and the first difference as the third read potential value Vb3.

[0038] It should be noted that the determination of the second read potential value Vb2 and the third read potential value Vb3 are both achieved through corresponding calculations, and compensation for the second read potential value Vb2 and the third read potential value Vb3 is also achieved during the calculation process, thereby improving the accuracy of the second read potential value Vb2 and the third read potential value Vb3, and the read voltage Vread of the first storage unit PCM1 is obtained by subtracting the first read potential value Vb1 from the second read potential value Vb2, and the read voltage Vread of the second storage unit PCM2 is obtained by subtracting the third read potential value Vb3 from the second read potential value Vb2, so that the read voltage Vread of the first storage unit PCM1 and the read voltage Vread of the second storage unit PCM2 are also compensated, thereby improving the accuracy of the read voltage Vread of the first storage unit PCM1 and the read voltage Vread of the second storage unit PCM2.

[0039] In some embodiments, such as Figure 8 As shown, the second determination module 20 includes a second acquisition unit 24, a second determination unit 25 and a second adding unit 26, the second acquisition unit 24 is configured to acquire a first parameter curve of the first storage cell PCM1, and the first parameter curve is a relationship curve between the cumulative number of errors of the first storage cell PCM1 and the read voltage Vread; the second determination unit 25 is connected to the second acquisition unit 24, and the second determination unit 25 is configured to determine a first target read voltage value of the first storage cell PCM1 according to the target number of errors and the first parameter curve; the second adding unit 26 is connected to the first determination module 10 and the second determination unit 25, and the second adding unit 26 is configured to calculate the sum of the first read potential value Vb1 and the first target read voltage value as the second read potential value Vb2.

[0040] It should be noted that the second determination module 20 in this embodiment reduces the process of obtaining the second parameter curve, which is beneficial to improving the efficiency of voltage determination.

[0041] In some embodiments, such as Fig. 9 As shown, the second acquisition unit 24 includes a second scanning subunit 241 and a second statistical subunit 242. The second scanning subunit 241 is configured to gradually raise the second read potential value Vb2 of the first storage cell PCM1; the second statistical subunit 242 is connected to the second determination unit 25, and the second statistical subunit 242 is configured to count the cumulative number of errors and the read voltage Vread of the first storage cell PCM1 according to the first read potential value Vb1 and the second read potential value Vb2, and obtain a first parameter curve.

[0042] It should be noted that the second acquisition unit 24 in this embodiment scans the second read potential value Vb2 of the second storage unit PCM2 and reduces the statistics of the second parameter curve, which is beneficial to improving the acquisition efficiency.

[0043] In some embodiments, such as Fig.10 As shown, the third determination module 30 includes a third acquisition unit 33, a third determination unit 34 and a third subtraction unit 35. The third acquisition unit 33 is configured to acquire a second parameter curve of the second storage unit PCM2, and the second parameter curve is a relationship curve between the cumulative number of errors of the second storage unit PCM2 and the read voltage Vread; the third determination unit 34 is connected to the third acquisition unit 33, and the third determination unit 34 is configured to determine the second target read voltage value of the second storage unit PCM2 according to the target number of errors and the second parameter curve; the third subtraction unit 35 is connected to the second addition unit 26 and the third determination unit 34, and the third subtraction unit 35 is configured to calculate a third difference between the second read potential value Vb2 and the second target read voltage value as the third read potential value Vb3.

[0044] It should be noted that this embodiment obtains the third read potential value Vb3 by scanning the voltage of the second bit line BL2 of the second storage unit PCM2, so as to accurately find the critical value of the read voltage Vread, effectively avoid over-compensation and under-compensation, and increase the read window of time drift.

[0045] Fig.11A schematic diagram of the relationship between the read voltage Vread and the bit line voltage provided in an embodiment of the present application. Among them, Vbl shown on the horizontal axis is the potential of the first bit line BL1 or the potential of the second bit line BL2, and Vread shown on the vertical axis represents the read voltage Vread. The line shown by Q1 represents the ideal offset curve of the read voltage Vread when the voltage of the bottom bit line is -2.4V. When the voltage of the bottom bit line changes by 100mV, the corresponding read voltage Vread also changes by 100mV. The line shown by Q2 represents the measured change trend of the read voltage Vread of the top storage unit. Delta-Vr represents the difference between Q1 and Q2 when Vbl is 2.4V.

[0046] Since the read voltage Vread of the memory cell may change with the bit line voltage, directly compensating the bit line voltage by the difference may result in under-compensation or over-compensation. As shown in the figure, when directly compensating the bit line voltage, it will be compensated to the intersection of the dotted line and Q1, i.e. F2. However, under this bit line voltage, the actual read voltage Vread is the intersection of Q2 and the dotted line, i.e. F1, which will result in over-compensation. Fig.10 The working method of the third determination module 30 shown in FIG. 1 can scan out similar Figure 5 The relationship curve between the cumulative number of errors and the read voltage Vread shown in SD1 in FIG. 1 can find a more suitable read voltage Vread, thereby improving or avoiding the phenomenon of over-compensation or under-compensation.

[0047] In some embodiments, such as Fig.12 As shown, the voltage determination circuit 100 also includes a storage module 40, which is connected to the first determination module 10, the second determination module 20 and the third determination module 30, and the storage module 40 is configured to store the first read potential value Vb1, the second read potential value Vb2 and the third read potential value Vb3.

[0048] It should be noted that, in this embodiment, each read potential value can be archived through the storage module 40 so as to facilitate subsequent research and use of these read potential values.

[0049] In some of these embodiments, please continue to see Figure 1 The first storage unit PCM1 is one of the top storage unit and the bottom storage unit in the same column, and the second storage unit PCM2 is the other of the top storage unit and the bottom storage unit in the same column.

[0050] It should be noted that, when the first storage cell PCM1 is the top storage cell in the same column, the first bit line BL1 is the top bit line; the second storage cell PCM2 is the bottom storage cell in the same column, and the second bit line BL2 is the bottom bit line. Alternatively, when the first storage cell PCM1 is the bottom storage cell in the same column, the first bit line BL1 is the bottom bit line; the second storage cell PCM2 is the top storage cell in the same column, and the second bit line BL2 is the top bit line. The word line WL is located between the top bit line and the bottom bit line.

[0051] In some of these embodiments, please continue to see Figure 1 and Figure 3 This embodiment provides a memory, which includes a first bit line BL1, a second bit line BL2, a word line WL, a first storage unit PCM1, a second storage unit PCM2 and the above-mentioned voltage determination circuit 100, the first storage unit PCM1 is connected to the first bit line BL1 and the word line WL, and the second storage unit PCM2 is connected to the second bit line BL2 and the word line WL.

[0052] It can be understood that since the memory provided in this embodiment includes the above-mentioned voltage determination circuit 100, the second determination module 20 can also determine the second read potential value Vb2 of the word line WL based on the target error number and the first read potential value Vb1 provided by the first determination module 10, and the third determination module 30 can determine the third read potential value Vb3 of the second bit line BL2 based on the first read potential value Vb1 or the second read potential value Vb2, so that a more accurate read voltage Vread can be applied to the storage unit according to the first read potential value Vb1, the second read potential value Vb2 and the third read potential value Vb3, thereby improving the accuracy of the read voltage Vread.

[0053] It should be noted that the memory in this embodiment may be, but is not limited to, a three-dimensional phase change memory, and may specifically be a two-layer or more-layer three-dimensional phase change memory, or may be other applicable three-dimensional memory.

[0054] In some embodiments, such as Fig.13 As shown, the memory also includes a first power supply 70, a second power supply 80 and a third power supply 90. The first power supply 70 is connected to the first bit line BL1 and the storage module 40, and is configured to provide a voltage to the first bit line BL1 according to the first read potential value Vb1 in a read operation; the second power supply 80 is connected to the word line WL and the storage module 40, and is configured to provide a voltage to the word line WL according to the second read potential value Vb2 in a read operation; the third power supply 90 is connected to the second bit line BL2 and the storage module 40, and is configured to provide a voltage to the second bit line BL2 according to the third read potential value Vb3 in a read operation.

[0055] It should be noted that in this embodiment, three power supplies can be used to apply a suitable and accurate read voltage Vread to each memory cell. Compared with the solution of using two power supplies for the same word line WL, one power supply is used to provide the corresponding voltage for the word line WL, thereby reducing the number of power supplies used.

[0056] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0057] The voltage determination circuit and memory provided in the embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A voltage determination circuit, characterized in that: The voltage determination circuit is applied to a memory, the memory comprising a first bit line, a second bit line, a word line, a first storage unit and a second storage unit, the first storage unit is connected to the first bit line and the word line, the second storage unit is connected to the second bit line and the word line, the voltage determination circuit comprises: a first determining module, the first determining module being configured to determine a first read potential value of the first bit line; a second determination module, the second determination module being connected to the first determination module, the second determination module being configured to determine a second read potential value of the word line based on a target error number and the first read potential value; A third determination module, the third determination module is connected to at least one of the first determination module and the second determination module, and the third determination module is configured to determine a third read potential value of the second bit line based on the first read potential value or the second read potential value.

2. The voltage determination circuit according to claim 1, characterized in that: The second determining module comprises: a first acquisition unit, wherein the first acquisition unit is configured to acquire a first parameter curve of the first storage unit and a second parameter curve of the second storage unit, the first parameter curve being a relationship curve between the cumulative number of errors and a read voltage of the first storage unit, and the second parameter curve being a relationship curve between the cumulative number of errors and the read voltage of the second storage unit; a first determining unit, the first determining unit being connected to the first acquiring unit, the first determining unit being configured to determine a first target read voltage value of the first storage unit according to the target error number and the first parameter curve, and to determine a second target read voltage value of the second storage unit according to the target error number and the second parameter curve; A first adding unit, wherein the first adding unit is connected to the first determining module and the first determining unit, and the first adding unit is configured to calculate a sum of the first read potential value and the first target read voltage value as the second read potential value.

3. The voltage determination circuit according to claim 2, characterized in that: The first acquiring unit includes: a first scanning subunit, wherein the first scanning subunit is configured to gradually raise the second read potential value of the first storage unit and the second storage unit respectively; A first statistical subunit, the first statistical subunit is connected to the first scanning subunit and the first determining unit, and the first statistical subunit is configured to count the cumulative number of errors and the read voltage of the first storage unit and the cumulative number of errors and the read voltage of the second storage unit based on the second read potential value, and obtain the first parameter curve and the second parameter curve.

4. The voltage determination circuit according to claim 2, characterized in that: The third determination module comprises: a first subtraction unit, the first subtraction unit being connected to the first determination unit, the first subtraction unit being configured to calculate a first difference between the first target read voltage value and the second target read voltage value; A second subtraction unit, the second subtraction unit is connected to the first determination module and the first subtraction unit, and the second subtraction unit is configured to calculate a second difference between the first read potential value and the first difference value as the third read potential value.

5. The voltage determination circuit according to claim 1, characterized in that: The second determining module comprises: a second acquisition unit, the second acquisition unit being configured to acquire a first parameter curve of the first storage unit, the first parameter curve being a relationship curve between the cumulative number of errors of the first storage unit and a read voltage; a second determining unit, the second determining unit being connected to the second acquiring unit, the second determining unit being configured to determine a first target read voltage value of the first storage unit according to the target number of errors and the first parameter curve; A second adding unit, the second adding unit is connected to the first determining module and the second determining unit, and the second adding unit is configured to calculate the sum of the first read potential value and the first target read voltage value as the second read potential value.

6. The voltage determination circuit according to claim 5, characterized in that: The second acquiring unit includes: a second scanning subunit, wherein the second scanning subunit is configured to gradually raise the second read potential value of the first storage unit; A second statistical subunit, the second statistical subunit is connected to the second determining unit, and the second statistical subunit is configured to count the cumulative number of errors and the read voltage of the first storage unit according to the first read potential value and the second read potential value, and obtain the first parameter curve.

7. The voltage determination circuit according to claim 5, characterized in that: The third determination module comprises: a third acquisition unit, the third acquisition unit being configured to acquire a second parameter curve of the second storage unit, where the second parameter curve is a relationship curve between the accumulated number of errors of the second storage unit and a read voltage; a third determining unit, the third determining unit being connected to the third acquiring unit, and the third determining unit being configured to determine a second target read voltage value of the second storage unit according to the target number of errors and the second parameter curve; A third subtracting unit is connected to the second adding unit and the third determining unit, and is configured to calculate a third difference between the second read potential value and the second target read voltage value as the third read potential value.

8. The voltage determination circuit according to any one of claims 1 to 7, characterized in that: The voltage determination circuit further includes a storage module, which is connected to the first determination module, the second determination module and the third determination module, and is configured to store the first read potential value, the second read potential value and the third read potential value.

9. A memory, characterized in that: The memory comprises: A first bit line, a second bit line, a word line, a first storage unit and a second storage unit, wherein the first storage unit is connected to the first bit line and the word line, and the second storage unit is connected to the second bit line and the word line; A voltage determination circuit as claimed in any one of claims 1 to 8.

10. The memory according to claim 9, characterized in that: The memory also includes: a first power supply, the first power supply being connected to the first bit line and the storage module and being configured to provide a voltage to the first bit line according to the first read potential value in a read operation; a second power supply, the second power supply being connected to the word line and the storage module and being configured to provide a voltage to the word line according to the second read potential value in a read operation; A third power supply is connected to the second bit line and the storage module and is configured to provide a voltage to the second bit line according to the third read potential value in a read operation.

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