Data writing method and device
By applying a data writing method of a specific pulse sequence in the control circuit of the phase change memory, the problem of high delay in the phase change memory is solved, and faster data writing and lower read error rate are achieved.
Patent Information
- Application Number
- CN202311675676.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-06
- Publication Date
- 2025-06-06
AI Technical Summary
How to reduce the delay of phase change memory, especially when writing data.
By introducing a data writing method in the control circuit of the phase change memory, the method includes applying the first pulse after applying the second pulse when performing the reset operation, and the waveform amplitude of the second pulse is smaller than the waveform amplitude of the first pulse, and the relationship between the total pulse width of the pulse applied by the reset operation and the total pulse width of the pulse applied by the set operation is: |tRtotal-tStotal|/tStotal<0.5.
This method can accelerate the process of converting phase change material from amorphous to crystalline state, reduce the delay of PCM in set operation, and make the delays of set operation and reset operation close, improve the execution speed of write operation, and reduce the read error rate.
Smart Images
Figure CN120108463A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of data storage, and more specifically, to a data writing method and device. Background Art
[0002] With the widespread application of technologies such as mobile Internet, cloud computing, big data, deep learning, and the Internet of Things, the market demand for low-latency, high-density, and large-capacity data storage is growing rapidly. Phase change memory (PCM), as one of the non-volatile storage technologies with broad application prospects, has been commercialized in various storage structure directions.
[0003] How to reduce the delay of PCM is an urgent problem to be solved. Summary of the invention
[0004] The present application provides a data writing method and device, which can reduce the delay of a phase change memory.
[0005] In a first aspect, a data writing method is provided, the method being used to write data in a phase change memory, the phase change memory comprising a control circuit and a storage array, the storage array comprising a plurality of storage cells; the method comprising: the control circuit acquiring data to be written into the storage array, the data comprising a plurality of bits, each bit corresponding to a storage cell; the control circuit performing a set operation or a reset operation on the storage cell corresponding to each bit according to the written data, the set operation being used to convert the storage cell from an amorphous state to a crystalline state, the reset operation being used to convert the storage cell from an amorphous state to a crystalline state; when performing the reset operation, the control circuit applies a second pulse to the storage cell after applying a first pulse, wherein the amplitude of the waveform of the second pulse is smaller than the amplitude of the waveform of the first pulse, and the total pulse width t of the third pulse applied when performing the reset operation is less than t Rtotal The total pulse width t of the pulse applied to perform the set operation Stotal The relationship is: |t Rtotal -t Stotal | / t Stotal <0.5.
[0006] For example, the resistance value of the PCM may have two types, wherein a higher resistance value (also referred to as a high resistance state or a reset state) is used to indicate a value of 0, and a lower resistance value (also referred to as a low resistance state or a set state) is used to indicate a value of 1.
[0007] The operation of changing PCM from a high-resistance state to a low-resistance state can be called a set operation; accordingly, the set operation changes the phase change material from a predominantly amorphous state to a predominantly crystalline state, and this phase change process can also be called a set process. Therefore, the set operation can also be understood as a "set 1" operation, and the set operation can change the value 0 to the value 1.
[0008] The operation of changing PCM from a low-resistance state to a high-resistance state can be called a reset operation; accordingly, the reset operation changes the phase change material from a mainly crystalline state to a mainly amorphous state, and this phase change process can also be called a reset process. Therefore, the reset operation can also be understood as a "set to 0" operation, and the reset operation can change the value 1 to the value 0.
[0009] In the embodiment of the present application, under the stimulation of the second pulse, a certain amount of crystal nuclei will be hatched inside the phase change material, and these crystal nuclei can serve as nucleation centers in the subsequent grain growth process, shortening the time required to produce a sufficient number of crystal nuclei, thereby facilitating the process of converting the phase change material from an amorphous state to a crystalline state, thereby reducing the delay of the PCM for set operations. It can be understood that write instructions are often executed on multiple storage cells at the same time, some of which perform set operations and some perform reset operations, and the write operation with the highest delay affects the total delay of these write instructions. The above scheme makes the delay of the set operation and the reset operation close, avoiding the situation where the set delay is large and the reset delay is small, thereby improving the execution speed of the write operation. In addition, the second pulse can accelerate the relaxation of the threshold voltage of the storage cell where the PCM is located, so that the threshold voltage of the reset state can return to a stable state faster, avoiding the read voltage from mistakenly identifying the set state as the reset state, and reducing the read error rate. Moreover, the application of the second pulse can expand the read voltage window. When the threshold voltage has not returned to a stable state, the original read voltage can still be used to successfully distinguish between the memory cells in the set state and the memory cells in the reset state, thereby reducing the read error rate.
[0010] In combination with the first aspect, in some implementations of the first aspect, there is a time interval between the second pulse and the first pulse.
[0011] When the phase change material just passes the falling edge of the first pulse, the temperature may be high and the reset state is not stable. Directly applying the second pulse at this time may cause the reset operation to fail. Therefore, setting a time interval between the second pulse and the first pulse can increase the success rate of the reset operation, thereby improving the accuracy of data written by the storage system.
[0012] In combination with the first aspect, in some implementations of the first aspect, the time interval is 100-1000 nanoseconds (ns).
[0013] In combination with the first aspect, in certain implementations of the first aspect, the maximum amplitude of the waveform of the second pulse is 10-50 microamperes (μA) and / or 0.5-4.5 volts (V).
[0014] Since the phase change material is stimulated by a larger current / voltage, the amount of crystal nuclei generated in the phase change material will be larger. Therefore, increasing the maximum amplitude of the waveform of the second pulse can further shorten the time required to generate a sufficient number of crystal nuclei, thereby facilitating the process of converting the phase change material from an amorphous state to a crystalline state, thereby reducing the delay of the PCM writing the first value. Moreover, under the stimulation of a larger current / voltage, the relaxation of the threshold voltage of the storage cell where the PCM is located is further accelerated, further reducing the read error rate. Moreover, the read voltage window is further expanded, thereby further reducing the read error rate.
[0015] In combination with the first aspect, in some implementations of the first aspect, a pulse width of the second pulse is 10-500ns.
[0016] Since the phase change material is stimulated by the current / voltage for a long time, the amount of crystal nuclei generated in the phase change material will be greater. Therefore, applying the second pulse for a longer time can further shorten the time required to generate a sufficient number of crystal nuclei, which is conducive to accelerating the process of converting the phase change material from an amorphous state to a crystalline state (i.e., writing the first value), thereby reducing the delay of PCM writing the first value.
[0017] In combination with the first aspect, in certain implementations of the first aspect, the waveform of the second pulse includes at least one of a square wave, a triangle wave, or a step wave.
[0018] In combination with the first aspect, in certain implementations of the first aspect, the maximum amplitude of the waveform of the third pulse is 5.5-7.5V.
[0019] Since the second pulse is applied after the first pulse, the threshold voltage of the reset state of the storage cell where the PCM is located is increased. Therefore, for the set operation, the maximum amplitude of the spike is required to be higher so that the third pulse reaches the threshold voltage of the reset state first. In this way, the set operation can be achieved by applying the latter part of the third pulse. However, the dynamic resistance of the storage cell where the PCM is located does not increase with the application of the second pulse. Therefore, when the latter part of the third pulse is applied to the PCM, a higher current can be provided, thereby accelerating the set operation of the PCM.
[0020] In combination with the first aspect, in certain implementations of the first aspect, a pulse width of the third pulse is 10-500ns.
[0021] In the embodiment of the present application, under the stimulation of the second pulse, a certain amount of crystal nuclei will be hatched inside the phase change material. These crystal nuclei can serve as nucleation centers in the subsequent grain growth process, shortening the time required to produce a sufficient number of crystal nuclei, thereby facilitating the process of converting the phase change material from an amorphous state to a crystalline state (i.e., writing the first value), thereby reducing the delay of the PCM writing the first value, i.e., performing a set operation.
[0022] In combination with the first aspect, in certain implementations of the first aspect, the waveform of the third pulse has at least two amplitude platforms greater than zero.
[0023] Different memory cells in the memory array have different physical distances from the driving circuit. Therefore, the interconnection resistance and interconnection capacitance through which the current signal of the third pulse passes from the driving circuit to these memory cells are also different, which results in different amplitude platforms of the pulses for the set operation that the driving circuit needs to send to different memory cells. In addition, different memory cells have certain differences in material composition, structural size, morphological damage, etc. during the process preparation, which will also result in different amplitude platforms of the waveform of the pulses for the set operation that the driving circuit needs to send to different memory cells. Therefore, using a third pulse with a waveform having at least two amplitude platforms helps to cover the amplitude platforms required for different memory cells in the memory array to perform better crystallization operations, thereby improving the success rate of the set operation.
[0024] In a second aspect, a phase change memory is provided, the phase change memory comprising a control circuit and a storage array, the control circuit being used to: obtain data to be written into the storage array, the data comprising a plurality of bits, each bit corresponding to a storage cell; perform a set operation or a reset operation on the storage cell corresponding to each bit according to the written data, the set operation being used to convert the storage cell from an amorphous state to a crystalline state, and the reset operation being used to convert the storage cell from an amorphous state to a crystalline state; when performing the reset operation, the control circuit applies a second pulse to the storage cell after applying a first pulse, wherein the amplitude of the waveform of the second pulse is smaller than the amplitude of the waveform of the first pulse, and the total pulse width t of the pulse applied when performing the reset operation is less than t Rtotal The total pulse width t of the third pulse applied to perform the set operation Stotal The relationship is: |t Rtotal -t Stotal | / t Stotal <0.5.
[0025] In a third aspect, a computing device is provided, comprising a processor and a phase change memory, wherein the processor is used to input data to be written into the phase change memory, and the phase change memory is used to execute the first aspect and any possible method of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 is a schematic block diagram of a storage unit.
[0027] Figure 2 A schematic block diagram of a storage system.
[0028] Figure 3 It is a schematic diagram of the waveform of the pulse applied in the write operation and the read voltage.
[0029] Figure 4 A schematic diagram of a three-dimensional storage array.
[0030] Figure 5 It is a schematic flow chart of a data writing method provided in an embodiment of the present application.
[0031] Figure 6 It is a schematic block diagram of a computing device provided in an embodiment of the present application.
[0032] Figure 7 It is a schematic diagram of the first pulse and the second pulse provided in an embodiment of the present application.
[0033] Figure 8 It is a schematic diagram of the third pulse provided in the embodiment of the present application.
[0034] Fig. 9 It is a schematic block diagram of a phase change memory provided in an embodiment of the present application.
[0035] Fig.10 It is a schematic block diagram of another computing device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0036] The technical solution in this application will be described below in conjunction with the accompanying drawings.
[0037] Figure 1 is a schematic block diagram of a memory cell 100 .
[0038] See also Figure 1 , the memory cell 100 may include a PCM 110 and an ovonic threshold switch (OTS) 120 .
[0039] The PCM 110 is a non-volatile memory (NVM) that can keep its resistance unchanged when the power is off.
[0040] The resistance value of the PCM 110 may be two kinds, wherein a higher resistance value (also referred to as a high resistance state or a reset state) is used to indicate a value of 0, and a lower resistance value (also referred to as a low resistance state or a set state) is used to indicate a value of 1. The time for which the PCM 110 maintains the resistance value may range from 1 second to 10 years, or may be maintained for a longer time exceeding 10 years.
[0041] PCM 110 may be based on phase change materials, for example, the phase change material may be a sulfur phase change material. PCM 110 may switch between different resistance values under heat, and the difference between the reset state and the set state may be 10 to 10,000 times, enabling accurate storage of values 0 and 1.
[0042] The operation of changing the PCM 110 from a high resistance state to a low resistance state can be called a set operation; accordingly, the set operation causes the phase change material to change from a predominantly amorphous state to a predominantly crystalline state, and this phase change process can also be called a set process. Therefore, the set operation can also be understood as a "set 1" operation, and the set operation can change the value 0 to the value 1.
[0043] The operation of changing the PCM 110 from a low resistance state to a high resistance state can be called a reset operation; accordingly, the reset operation causes the phase change material to change from a mainly crystalline state to a mainly amorphous state, and this phase change process can also be called a reset process. Therefore, the reset operation can also be understood as a "set to 0" operation, and the reset operation can change the value 1 to the value 0.
[0044] OTS120 is a volatile device. For example, OTS120 can be made of chalcogenide materials. OTS120 can be used as a gate tube in series with PCM 110. In this way, the combination of OTS120 and PCM 110 can be used as a unit of the storage array, that is, storage cell 100. OTS120 presents a high resistance state at a relatively low voltage, which can suppress leakage current and prevent the resistance state of PCM 110 from changing, resulting in data storage errors; it presents a low resistance state at a relatively high programming voltage, which can provide a sufficiently large current to implement read and write operations. In this way, when a storage cell 100 is selected, OTS120 can open a current path so that the PCM 110 in the storage cell 100 can perform a read operation or a write operation; when a storage cell 100 is not selected, OTS120 remains in a closed state, avoiding a current path in the storage cell 100 and avoiding interference with the read or write operations of other selected storage cells 100.
[0045] The storage unit 100 may be 1 selector and 1 resistor (1S1R), 1S1R may also be understood as 1 selector and 1 variable resistor memory, 1S1R may also be understood as 1 storage unit (cell). In other words, 1S1R may refer to 1 storage unit consisting of 1 selector and 1 variable resistor memory. However, the present application is not limited to this, and the storage unit 100 may also include multiple selectors and multiple memories.
[0046] A plurality of memory cells 100 are connected via word lines (WL) and bit lines (BL) to form an array of memory cells 100 .
[0047] Figure 2 is a schematic block diagram of a storage system 200 .
[0048] The memory system 200 includes a plurality of memory cells 100 (eg, a plurality of 1S1R), a row decoder 210 and a column decoder 220 .
[0049] See also Figure 2 From the perspective of the storage unit 100, each of the n WLs is connected to a "row" of storage units 100, and the row decoder is connected to the n WLs; each of the m BLs is connected to a "column" of storage units 100, and the column decoder is connected to the m BLs. From the perspective of the storage system 200 as a whole, the above solution can also be understood as that there is a storage unit 100 at the intersection of each WL and each BL. Multiple storage units 100 are connected by n WLs and m BLs to form an n*m storage array.
[0050] The storage system 200 may also include devices such as a sense amplifier, a driver circuit, a digital controller, a data buffer, or an input / output interface (not shown in the figure). The storage system 200 can read and write data through a sense amplifier and a driver circuit, and the driver circuit may include a read driver circuit and a write driver circuit. The data to be written can be stored in the data buffer before writing, and the read data can also be stored in the data buffer. In addition, the digital controller can control the above operations, and can exchange data and commands with other external systems through the input / output interface.
[0051] The storage system 200 can select a certain WL from among multiple WLs, so that a different level value from other WLs is applied to the selected WL, thereby performing a read operation or a write operation on the storage unit on the selected WL (e.g., 1S1R of a row). For example, a write operation can transmit an electrical signal to the selected WL to implement data writing; a read operation can transmit an electrical signal to the selected WL, and then transmit an electrical signal of the read operation feedback to the row decoder along the selected WL. The storage system can select a certain BL from among multiple BLs, so that a different level value from other BLs is applied to the selected BL, thereby performing a read operation or a write operation on the storage unit on the selected BL (e.g., 1S1R of a column). For example, a write operation can transmit an electrical signal to the selected BL to implement data writing; a read operation can transmit an electrical signal to the selected BL, and then transmit an electrical signal of the read operation feedback to the column decoder along the selected BL.
[0052] In this way, the storage system 200 can choose to turn on or off the OTS120 in any storage cell 100 by selecting a WL and a BL, thereby realizing a read operation or a write operation on any storage cell 100 of the entire storage array, and avoiding the situation where, when one storage cell 100 is selected, there is a current conduction path in other storage cells 100, thereby causing a current sneak path and ultimately resulting in a high read and write error rate.
[0053] It should be noted that the present application does not limit the storage system 200 to only being able to select one WL and one BL at the same time. The storage system 200 may also simultaneously select multiple WLs and multiple BLs, thereby enabling or disabling the OTS 120 of multiple storage units 100 at the same time.
[0054] See also Figure 2 , taking writing to a certain storage unit 100 (hereinafter referred to as the target storage unit) as an example, the write drive circuit ( Figure 2 (not shown) can modulate the voltage of WLx (x is a value from 1 to n) connected to the target storage unit to a certain voltage pulse, the amplitude of which is V 1 , so this pulse can also be called V 1 In addition, the write driver circuit can apply a certain pulse to BLy (y is a value from 1 to m) connected to the target storage unit, and the amplitude of the pulse is V 2 , so this pulse can also be called V 2 The above process can also be understood as the process of selecting WLx and BLy.
[0055] The above V 1 Pulse and V 2 The pulses can have opposite polarity, for example V1 Take 4V, V 2 It can be -4 V. Since the two pulses are applied to both ends of the target memory cell (ie, applied to WL and BL respectively), the effective total pulse applied to the target memory cell is the difference between the two. For example, the maximum peak voltage of the total pulse of 4 V and -4 V is 8 V.
[0056] The write driver circuit can modulate the voltage of the WL not connected to the target memory cell (i.e., the WL other than WLx) to V 3 (For example, it can be 0V), and the voltage of the BL not connected to the target storage cell (i.e., the BL other than BLy) is modulated to V 4 (For example, it may be 0V.) The above process may also be understood as a process in which WLs other than WLx and BLs other than BLy are not selected.
[0057] In this way, only the target memory cells corresponding to the selected WLx and BLy have a sufficiently large voltage difference, for example |V 1 -V 2 |The maximum peak voltage of the total pulse is 8V. This voltage difference is greater than the threshold voltage of the target memory cell, and can turn on and complete the corresponding write operation. Specifically, for the reset operation, the target memory cell is in the set state, so the voltage difference needs to be greater than the threshold voltage of the set state; for the set operation, the target memory cell is in the reset state, so the voltage difference needs to be greater than the threshold voltage of the reset state.
[0058] The voltage differences of the memory cells corresponding to the unselected WL and BL, that is, the memory cells other than the target memory cells, are all lower than the threshold voltage for turning on these memory cells, so that these memory cells are in a closed state and the PCM 110 will not be written. 1 -V 4 The maximum peak voltage of the total pulse is 4V, |V 3 -V 2 The maximum peak voltage of the total pulse is 4V, |V 3 -V 4 |The maximum peak voltage of the total pulse is 0V, 4V and 0V which are less than the threshold voltage to turn on these memory cells.
[0059] See also Figure 2 Taking the reading of a certain storage unit 100 (hereinafter referred to as the target storage unit) as an example, the read drive circuit can modulate the voltage of a certain WL connected to the target storage unit to a certain voltage pulse, the amplitude of which is V 5 , so this pulse can also be called V 5In addition, the read drive circuit can apply a certain pulse to a BL connected to the target storage unit, and the amplitude of the pulse is V 6 , so this pulse can also be called V 6 The above process can also be understood as the process of selecting WL and BL. 5 Pulse and V 6 The pulses have opposite polarity.
[0060] Similar to the write operation, the read driver circuit can modulate the voltage of WL that is not connected to the target memory cell to V 7 (For example, it can be 0V), and the voltage of BL not connected to the target storage unit is modulated to V 8 (For example, it can be 0V).
[0061] In this way, only the target memory cells corresponding to the selected WL and the selected BL have a sufficiently large voltage difference (eg |V 5 -V 6 |The maximum peak voltage of the total pulse of |, the voltage difference is greater than the threshold voltage of the set state of the target memory cell, and less than the threshold voltage of the reset state. Therefore, when the target memory cell is in the set state, the voltage of the read operation (hereinafter referred to as the read voltage) can turn on the target memory cell, so that a large current can be read; when the target memory cell is in the reset state, the read voltage cannot turn on the target memory cell, so that only a small current can be read. By distinguishing between large current and small current, the storage system 200 can determine whether the target memory cell is in the reset state or the set state, that is, determine whether the target memory cell stores a value of 0 or a value of 1.
[0062] The voltage difference between the memory cells corresponding to the unselected WL and BL (e.g. |V 5 -V 8 |、|V 7 -V 6 |、|V 7 -V 8 |The maximum peak voltage of the total pulses respectively has is less than the threshold voltage of opening these memory cells, so that these memory cells are in a closed state and the PCM 110 will not be read.
[0063] Figure 3 This is a schematic diagram of the waveform of the pulse applied during the write operation and the read voltage. Figure 3 Describes read and write operations.
[0064] Figure 3 (a) and (b) in FIG. 1 show the waveforms of the pulses applied during the write operation. Figure 3 (a) in FIG. 1 shows the waveform of the pulse applied by the reset operation. Figure 3 (b) in FIG. 1 shows the waveform of the pulse applied by the set operation.
[0065] See also Figure 3 In (a), the pulse applied by the reset operation has a short pulse width and a high amplitude, such as a pulse width of 10-50 ns (nanoseconds), an amplitude of 50-200 μA (microamperes), and / or 7.5-10 volts (V). After the threshold voltage of the set state is turned on, PCM110 first quickly reaches the melting temperature of the phase change material, and then the pulse is quickly removed with a short falling edge, so that the phase change material in PCM 110 is quickly quenched and enters the amorphous state from the molten state.
[0066] If the pulse width of the pulse applied in the reset operation is too long, the total power consumption of the reset operation will be too high. If the falling edge of the waveform of the pulse applied in the reset operation is too long, the phase change material will enter the temperature range of the set operation, and nucleation and grain growth will occur, and the phase change material will become crystalline, resulting in an unsuccessful reset operation, that is, a false set operation.
[0067] See also Figure 3 In (b), the pulse applied by the set operation has a longer pulse width and a lower amplitude, such as a pulse width of 500-1000ns, an amplitude of 10-100μA, and / or 4.5-5.5V. After the threshold voltage of the reset state is turned on, the temperature of PCM 110 is controlled to be higher than the glass transition temperature of the phase change material and lower than the melting temperature, so as to facilitate the nucleation and grain growth process of the phase change material in PCM 110. Finally, after a longer time than the reset operation, the phase change material in PCM 110 changes from an amorphous state to a crystalline state. In particular, the pulse applied by the set operation has a spike pulse that turns on OTS120 in the very beginning, and the amplitude of the spike pulse can be 100-150μA. After turning on OTS 120, the amplitude of the waveform of the pulse applied by the set operation may further decrease, and gradually decrease to 0 after stable operation.
[0068] See also Figure 3 In (c), read voltage V R0 It can be between the threshold voltage of the set state and the threshold voltage of the reset state. During the read operation, the sensitive amplifier circuit can distinguish the target memory cells in the set state and the reset state when applying the read voltage. For the target memory cell in the set state, the applied read voltage V R0 If the voltage V is greater than the threshold voltage of the target memory cell, the target memory cell can be turned on to read out a high current. For the target memory cell in the reset state, the applied read voltage V R0If the voltage is lower than the threshold voltage of the target memory cell, the target memory cell cannot be turned on, thereby reading a low current.
[0069] Due to the introduction of OTS120, the threshold voltage of the memory cell 100 may drift. Figure 3 As shown in (c) in FIG. 1 , before the threshold voltage drifts, the read voltage can correctly distinguish the memory cell 100 in the set state and the reset state. Figure 3 As shown in (d) in the figure, after the threshold voltage drifts, the threshold voltages of the set state and the reset state increase with the drift. If the original read voltage V R0 , it will cause a portion of the set state storage cells 100 to be recognized as reset state, thereby increasing the read error rate at the chip level.
[0070] like Figure 3 As shown in (e) in FIG. 1 , the physical mechanism of threshold voltage drift caused by OTS120 can be understood through defect states. OTS120 is in a low leakage state in the initial state, and there are few defect states in the center of the band gap of the OTS material. When performing the initial opening (first fire) operation, OTS 120 is stimulated by voltage (V FF ) will generate a metastable defect state. The energy of the metastable defect state is located in the center of the band gap of the OTS material, which can support a large turn-on current. After the initial opening, when OTS120 is turned on again, since the defect state has been generated, a part of the defect state will remain in the center of the band gap. OTS120 and PCM 110 are connected in series to form a memory cell 100, and the turn-on voltage of OTS120 will affect the threshold voltage of the entire memory cell 100. Therefore, when it is not initially turned on, it may not be necessary to provide a voltage V of the same magnitude as that of the initial turn-on. FF , so that the threshold voltage (V th@t0 ) is higher than V FF In other words, the OTS120 does not need to reach the voltage V FF , enough defect states can be generated to support the flow of turn-on current. It is worth noting that OTS120 has 0 After the moment is closed, the defect states in the metastable state will relax over time, and the number of defect states will gradually decrease. 0 Time to t 1 Time, t 2 At this moment, the threshold voltage of the memory cell 100 gradually returns to the threshold voltage V when the OTS material is initially turned on. FF .
[0071] To solve this problem, a read retry mechanism can be introduced at the controller level. Specifically, error correction calculations of error-correcting code (ECC) can be performed on the read data. If a correctable erroneous data bit is identified, the data bit is read again, using a different read voltage than the first read operation. For example, see Figure 3 In (f), a voltage higher than the first read voltage V R0 Higher read voltage V R1 , so that the storage unit 100 can be successfully distinguished as being in the set state and the reset state, thereby realizing successful data reading. However, this solution will introduce additional ECC error correction and repeated reading delay overhead, reducing the reading performance of the storage system 200.
[0072] The following are some solutions for three-dimensional storage arrays.
[0073] All storage arrays of a two-dimensional non-volatile memory are located on the same plane, and all storage arrays of a three-dimensional non-volatile memory (3D NVM) are located in a three-dimensional space, and can be located on multiple parallel or intersecting planes. The storage system 200 can be two-dimensional or three-dimensional. In the case where the storage system 200 is three-dimensional, Figure 2 What is shown can be understood as a cross section of the storage system 200 , or as a deck of the storage system 200 , or as a plane of the storage system 200 .
[0074] Figure 4 A schematic diagram of a three-dimensional storage array, wherein NVM1 and NVM2 may be PCM.
[0075] See also Figure 4 The left part of the upper storage unit includes NVM1, gate tube 1 and electrode 2. Figure 4 The metal extending in the plane formed by the x-direction and the y-direction connects the different memory cells with other memory cells. Among them, the metal 1 and NVM1 are connected by the electrode 1, and the metal 2 and the gate tube 1 are connected by the electrode 3.
[0076] The extension directions of the metals above and below the memory cell are not in the same direction. These metals can be used as WL and BL respectively. For example, metal 1 extends in the y direction and metal 2 extends in the x direction. If metal 1 is used as WL (or BL), metal 2 can be used as BL (or WL). The memory cells connected by metal 1 and metal 2 form a two-dimensional memory array, which is arranged on a layer. Figure 4 Further stacking in the z direction (in the center) forms a cross-stacked three-dimensional storage array. The outside of the three-dimensional storage array can be encapsulated with an insulating layer, such as Figure 4 As shown in the right part of the figure, by patterning the vertical columnar structure, the three-dimensional memory array can be scaled to the limit of lithography, so the cell density of a single layer is high.
[0077] In the manufacturing process, a storage unit in a three-dimensional storage array can be formed by etching twice. Figure 4 Taking the lower layer storage unit in as an example, the upper layer storage unit includes metal 3, electrode 4, NVM2, electrode 5, gate tube 2, electrode 6, and metal 4.
[0078] The first etching can determine the direction and shape of the metal 4 below the gate tube 2, for example, the electrode 4, NVM2, electrode 5, gate tube 2, electrode 6, and metal 4 can be etched in the y direction. The second etching can determine the direction and shape of the metal 3 above the NVM2, for example, the metal 3, electrode 4, NVM2, electrode 5, gate tube 2, and electrode 6 can be etched in the x direction. Among them, NVM2, gate tube 2, and electrodes 4, 5, and 6 are etched in both etchings, and the remaining parts are columnar. Metal 4 is only etched for the first time and extends in the y direction; metal 3 is only etched for the second time and extends in the x direction.
[0079] After etching the lower memory cells, the upper memory cells may be etched in the same manner, that is, metal 1, electrode 1, NVM 1, electrode 2, gate tube 1, electrode 3, and metal 2 are etched.
[0080] For densely stacked three-dimensional storage arrays, due to their small size and high heating efficiency, the amorphization operation during the reset process is more complete, resulting in a reduction in nucleation centers in the NVM material, making the crystallization operation during the set process more difficult, increasing the delay of the set operation and affecting the delay performance of the PCM.
[0081] Figure 51 is a schematic flow chart of a data writing method 500 provided in an embodiment of the present application. The method 500 can reduce the delay of PCM. The method 500 is used to write data in a phase change memory, the phase change memory includes a control circuit and a storage array, the storage array includes a plurality of storage units. Figure 5 and other figures describe method 500 .
[0082] S510, the control circuit obtains data to be written into the storage array, the data includes a plurality of bits, and each bit corresponds to a storage unit.
[0083] The control circuit can be a controller chip, or any device with a control function.
[0084] Exemplarily, the data to be written into the storage array may be "1100", so the data includes 4 bits, each bit corresponding to a storage unit. Specifically, the first bit "1" may correspond to storage unit #1, the second bit "1" may correspond to storage unit #2, the third bit "0" may correspond to storage unit #3, and the fourth bit "0" may correspond to storage unit #4. The storage array includes the above storage units #1 to #4.
[0085] Figure 6 is a schematic block diagram of a computing device 600 provided in an embodiment of the present application. Figure 6 , the computing device 600 includes a processor 610 , a controller chip 620 and a memory chip 630 . The phase change memory may include the controller chip 620 and the memory chip 630 .
[0086] The processor 610 can also be understood as the central processing unit (CPU) of the host. The controller chip 620 is located between the processor 610 and the memory chip 630. The memory chip 630 can also be understood as the aforementioned storage system 200. The memory chip 630 includes the aforementioned storage array. The controller chip 620 can convert the write data request of the processor 610 and the data to be written into a write data command and a write data format recognizable by the memory chip 630. The controller chip 620 can also convert the read data request of the processor 610 into a read data command recognizable by the memory chip 630, and convert the read data read from the memory chip 630 into a read data format recognizable by the processor 610. In addition, the controller chip 620 can also include functions for managing various types of failures of the memory, such as bad block management, wear leveling, repeated reading, ECC error correction calculation and other functions.
[0087] The data in the above S510 may come from the processor 610. It should be noted that: Figure 6The scenario shown is only for ease of understanding and does not constitute a limitation on the present application, nor does it mean that the present application embodiment is only applicable to the scenario. The data in the above S510 may also come from other devices, such as the controller chip 620.
[0088] S520, the control circuit performs a set operation or a reset operation on the storage cell corresponding to each bit according to the written data, the set operation is used to convert the storage cell from an amorphous state to a crystalline state, and the reset operation is used to convert the storage cell from an amorphous state to a crystalline state.
[0089] The storage unit may include a phase change material, and the phase change material has a crystalline state or an amorphous state, wherein the crystalline state may correspond to a first value, and the amorphous state may correspond to a second value, and the first value and the second value may be different. For example, the first value may be a value 1, and the second value may be a value 0, that is, the crystalline state corresponds to a value 1, and the amorphous state corresponds to a value 0.
[0090] A set operation can write 1 to a memory cell that stores 0, and a reset operation can write 0 to a memory cell that stores 1.
[0091] S530, when performing the reset operation, the control circuit applies a second pulse to the storage unit after applying the first pulse, wherein the amplitude of the waveform of the second pulse is smaller than the amplitude of the waveform of the first pulse, and the total pulse width t of the third pulse applied when performing the reset operation is Rtotal The total pulse width t of the pulse applied to perform the set operation Stotal The relationship is: |t Rtotal -t Stotal | / t Stotal <0.5.
[0092] The first pulse may be referred to as a pulse applied by a reset operation. Figure 3 As shown in (a) in the figure, but the present application is not limited to this, for example, it can also be other waveforms.
[0093] The third pulse may be referred to as a pulse applied by a set operation. Figure 3 As shown in (b) of FIG. 1 , the present application does not limit this. For example, the pulse width of the third pulse may be greater than Figure 3 If the third pulse is applied to the PCM 110, the value in the PCM 110 will be rewritten from the second value to the first value. For example, the value 0 in the PCM 110 is changed to the value 1.
[0094] In some optional embodiments, the maximum amplitude of the waveform of the second pulse is less than the maximum amplitude of the waveform of the third pulse, and therefore, the application of the second pulse to the PCM 110 does not transform the phase change material from the amorphous state to the crystalline state. In other words, after the second pulse is applied (i.e., S530 is executed), the phase change material in the PCM 110 is still in the amorphous state, that is, the value in the PCM 110 is still the second value, such as 0. The second pulse can be regarded as a post-processing pulse of the reset operation.
[0095] On the one hand, the third pulse realizes the storage of the first value in PCM 110 by converting the phase change material from an amorphous state to a crystalline state (this process may also be referred to as a crystallization process). As mentioned above, the crystallization process is divided into two processes: nucleation and grain growth. Under the stimulation of the second pulse, a certain amount of nuclei will be hatched inside the phase change material, and these nuclei can serve as nucleation centers in the subsequent grain growth process. It is understandable that if there are no existing nuclei, the phase change material needs to generate enough nuclei under the action of the third pulse before grain growth. In the presence of these nuclei, the phase change material itself has enough nuclei and can directly carry out the grain growth process; or, the phase change material can generate enough nuclei in a shorter time. Therefore, the second pulse can shorten the time required to generate a sufficient number of nuclei, which is conducive to accelerating the process of converting the phase change material from an amorphous state to a crystalline state (i.e., writing the first value), thereby reducing the delay of PCM 110 writing the first value. That is, the above scheme can reduce the delay of the set operation. It is understandable that write instructions are often executed on multiple storage units at the same time, some of which perform set operations and some perform reset operations. The write operation with the highest delay affects the total delay of these write instructions. The above scheme makes the delay of the set operation and the reset operation close, avoiding the situation where the set delay is large and the reset delay is small, thereby improving the execution speed of the write operation.
[0096] On the other hand, the maximum amplitude of the second pulse is smaller than the maximum amplitude of the first pulse, that is, smaller than the maximum amplitude of the waveform of the pulse applied by the reset operation, so that the temperature of the phase change material after the second pulse is applied is lower than the temperature range where the melting operation occurs, thereby avoiding an erroneous reset operation. Therefore, the maximum amplitude of the second pulse is smaller than the maximum amplitude of the first pulse, which can avoid an erroneous reset operation, thereby ensuring the accuracy of the written data.
[0097] On the other hand, when PCM 110 and OTS 120 are connected in series, the second pulse is applied to both ends of OTS 120. At this time, the defect state in the metastable state in OTS 120 will gain energy under the stimulation of the voltage of the second pulse and relax faster, thereby reducing the defect state until it returns to the threshold voltage corresponding to VFF Therefore, the second pulse can accelerate the relaxation of the threshold voltage of the storage unit, so that the threshold voltage of the reset state can return to the stable state faster, avoiding the read voltage from mistakenly identifying the set state as the reset state, and reducing the read error rate. In addition, compared with the solution of introducing ECC error correction and repeated reading, the embodiment of the present application reduces the probability of read errors and reduces the delay overhead of introducing additional ECC error correction and repeated reading.
[0098] On the other hand, when PCM 110 and OTS120 are connected in series, the second pulse is applied to both ends of OTS120. At this time, the threshold voltage of the reset state is increased, while the threshold voltage of the set state does not change. As mentioned above, the read voltage needs to be between the threshold voltage of the reset state and the threshold voltage of the set state. Therefore, the application of the second pulse can expand the range in which the read voltage can be applied, that is, the read voltage window is expanded. Therefore, even if the threshold voltage drifts, due to the expansion of the read voltage window, the original read voltage may still be within the read window. In this way, when the threshold voltage has not returned to a stable state, the original read voltage may still be used to successfully distinguish between the storage cell in the set state and the storage cell in the reset state, thereby reducing the read error rate.
[0099] In summary, in the embodiment of the present application, under the stimulation of the second pulse, a certain amount of crystal nuclei will be hatched inside the phase change material, and these crystal nuclei can serve as nucleation centers in the subsequent grain growth process, shortening the time required to produce a sufficient number of crystal nuclei, thereby facilitating the process of converting the phase change material from an amorphous state to a crystalline state, thereby reducing the delay of the PCM for set operations. It can be understood that write instructions are often executed on multiple storage units at the same time, some of which perform set operations and some perform reset operations, and the write operation with the highest delay affects the total delay of these write instructions. The above scheme makes the delay of the set operation and the reset operation close, avoiding the situation where the set delay is large and the reset delay is small, thereby improving the execution speed of the write operation. In addition, the second pulse can accelerate the relaxation of the threshold voltage of the storage unit where the PCM is located, so that the threshold voltage of the reset state can return to a stable state faster, avoiding the read voltage from mistakenly identifying the set state as the reset state, and reducing the read error rate. Moreover, the application of the second pulse can expand the read voltage window. When the threshold voltage has not returned to a stable state, the original read voltage can still be used to successfully distinguish between the memory cells in the set state and the memory cells in the reset state, thereby reducing the read error rate.
[0100] In some embodiments, there is a time interval between the second pulse and the first pulse.
[0101] Figure 7 It is a schematic diagram of the first pulse and the second pulse provided in an embodiment of the present application. Figure 7 The images are for illustration only and do not constitute a limitation to the present application.
[0102] See also Figure 7 In (a), the waveform of the first pulse has a current / voltage of I R1 / V R1 The second pulse has a current / voltage waveform of I R2 / V R2 A certain time interval is set between the first pulse and the second pulse, and the voltage in the time interval is 0. However, the present application is not limited to this, and the voltage in the time interval may also be a value close to 0, or other values.
[0103] For example, the current / voltage is I R1 / V R1 The width of the amplitude platform can be 10-50ns.
[0104] When the phase change material just passes the falling edge of the first pulse, the temperature may be high and the reset state is not stable. Directly applying the second pulse at this time may cause the reset operation to fail. Therefore, setting a time interval between the second pulse and the first pulse can increase the success rate of the reset operation, thereby improving the accuracy of data written by the storage system.
[0105] In some embodiments, the time interval is 100-1000 ns.
[0106] For example, Figure 7 The time interval shown in (a) can be taken from 100-1000ns.
[0107] It should be noted that the present application does not limit the time interval between the second pulse and the first pulse. Figure 7 In (b), there may be no time interval between the second pulse and the first pulse, and the second pulse is applied when the falling edge of the first pulse has not dropped to 0.
[0108] In some embodiments, the maximum amplitude of the waveform of the second pulse is 10-50 μA and / or 0.5-4.5V.
[0109] The maximum amplitude mentioned in this application may refer to the absolute value of the maximum amplitude. For example, Figure 7 I shown in (a), (b), (d), (e) and (f) R2 Taken from 10-50μA. For example, Figure 7 I shown in (c) R2The absolute value of is taken from 10-50 μA. In addition, the maximum amplitude mentioned in the present application is not limited to the maximum amplitude of the current, for example, it can also be the maximum amplitude of the voltage.
[0110] Since the phase change material is stimulated by a larger current / voltage, the amount of crystal nuclei generated in the phase change material will be larger. Therefore, increasing the maximum amplitude of the waveform of the second pulse can further shorten the time required to generate a sufficient number of crystal nuclei, thereby facilitating the process of converting the phase change material from an amorphous state to a crystalline state (i.e., writing the first value), thereby reducing the delay of PCM 110 writing the first value. Moreover, under the stimulation of a larger current / voltage, OTS 120 further accelerates the relaxation of the threshold voltage of the storage cell where PCM 110 is located, further reducing the read error rate. Moreover, the read voltage window is further expanded, thereby further reducing the read error rate.
[0111] In some embodiments, the second pulse has a pulse width of 10-500 ns.
[0112] For example, Figure 7 The applied current / voltage in (a), (b) and (c) is I R2 / V R2 The pulse width of the pulse with the amplitude of is 10-500ns. For another example, Figure 7 (d) The applied current / voltage is I R2 / V R2 The pulse width of the pulse with the applied current / voltage I R3 / V R3 The sum of the pulse widths of the pulses with the amplitude of is 10-500ns. For another example, Figure 7 (e) The applied current / voltage is from I R2 / V R2 The pulse width of the pulse that decays to 0 is 10-500ns. For another example, Figure 7 (f) The applied current / voltage changes from 0 to I R2 / V R2 The pulse width of the pulse that rises to 0 and then drops to 0 is 10-500ns.
[0113] Since the phase change material is stimulated by the current / voltage for a long time, the amount of crystal nuclei generated in the phase change material will be greater. Therefore, applying the second pulse for a longer time can further shorten the time required to generate a sufficient number of crystal nuclei, which is conducive to accelerating the process of converting the phase change material from an amorphous state to a crystalline state, thereby reducing the delay of writing the first value of the PCM.
[0114] In some embodiments, the waveform of the second pulse includes at least one of a square wave, a triangle wave, or a step wave.
[0115] For example, Figure 7 (a), (b) and (c) in FIG. 1 show some embodiments of square waves. For another example, Figure 7 (d) in FIG. 1 shows an embodiment of a step wave. For another example, Figure 7 (e) in FIG. 1 shows an embodiment of a triangular wave.
[0116] It should be noted that the waveform of the second pulse may also be other shapes, such as Figure 7 (f) in FIG. 1 shows an embodiment of a sine wave.
[0117] Figure 8 It is a schematic diagram of the third pulse provided in the embodiment of the present application.
[0118] In some embodiments, the waveform of the third pulse has a peak, and the maximum amplitude of the peak is 5.5-7.5V.
[0119] For example, see Figure 8 (a) in I S1 It can be taken from 5.5-7.5V. It should be noted that in the relevant technical solution, the maximum amplitude of the peak of the waveform of the pulse applied by the set operation is often less than 5.5V. The maximum amplitude of the above peak can also be 50-150μA. The maximum amplitude of the above peak can also be called the maximum amplitude of the third pulse.
[0120] Since the second pulse is applied after the first pulse, the threshold voltage of the reset state of the memory cell 100 where the PCM 110 is located is increased. Therefore, for the set operation, the maximum amplitude of the spike is required to be higher so that the third pulse reaches the threshold voltage of the reset state first. In this way, the set operation can be achieved by applying the latter part of the third pulse. However, the dynamic resistance of the memory cell 100 where the PCM 110 is located does not increase with the application of the second pulse. Therefore, when the latter part of the third pulse is applied to the PCM 110, a higher current can be provided, thereby accelerating the set operation of the PCM 110.
[0121] In some embodiments, the third pulse has a pulse width of 10-500 ns.
[0122] For example, see Figure 8 In (a) and (b), the pulse width can be taken from 10-500ns. It should be noted that in the relevant technical solutions, the pulse width of the pulse applied by the set operation is often greater than 500ns.
[0123] As mentioned above, the pulse width of the first pulse may be 10-50 ns, and the pulse width of the second pulse may be 10-500 ns, so the total pulse width of the first pulse and the second pulse may be 20-550 ns.
[0124] It can be seen that after adding the second pulse, the total duration of the first pulse and the second pulse is close to the duration of the third pulse. In other words, the total pulse width of the pulse applied by the reset operation is close to the pulse width of the pulse applied by the set operation. The total pulse width of the pulse applied by the reset operation and the pulse width of the pulse applied by the set operation can be expressed by the following formula.
[0125]
[0126] Among them, t Rtotal represents the total pulse width of the pulse applied by the reset operation (or the total duration of the first pulse and the second pulse), t Stotal Indicates the pulse width of the pulse applied by the set operation (or the duration of the third pulse).
[0127] In the embodiment of the present application, under the stimulation of the second pulse, a certain amount of crystal nuclei will be hatched inside the phase change material. These crystal nuclei can serve as nucleation centers in the subsequent grain growth process, shortening the time required to produce a sufficient number of crystal nuclei, thereby facilitating the process of converting the phase change material from an amorphous state to a crystalline state (i.e., writing the first value), thereby reducing the delay of the PCM writing the first value, i.e., performing a set operation.
[0128] In some embodiments, the waveform of the third pulse has at least two amplitude plates greater than zero.
[0129] When the current / voltage is kept at a certain value for a period of time, the current / voltage during this period is reflected in the graph with current / voltage and time as the coordinate axes, and will be in the shape of an amplitude platform. For example, see Figure 8 In (a), the current / voltage is I S2 / V S2 The part of can be called the amplitude platform. For another example, see Figure 8 In (b), the current / voltage is I S2 / V S2 The part can be called the amplitude platform, and the current / voltage is I S3 / V S3 The part can also be called the amplitude platform.
[0130] For example, Figure 8 (b) in FIG. 5 shows an embodiment in which the waveform of the third pulse has two amplitude platforms greater than 0. The waveform of the third pulse having at least two amplitude platforms greater than zero can also be called a step-shaped set waveform.
[0131] Different memory cells 100 in the memory array have different physical distances from the drive circuit. Therefore, the interconnection resistance and interconnection capacitance through which the current signal of the third pulse passes from the drive circuit to these memory cells 100 are also different, which results in different amplitude platforms of the pulse waveforms applied by the drive circuit to the set operation to be issued to different memory cells 100. S2 / V S2 The amplitude platform can achieve a better crystallization effect, while some memory cells 100 need to be crystallized at a current / voltage of I S3 / V S3 In addition, different memory cells 100 have certain differences in material composition, structural size, morphological damage, etc. during the process of manufacturing, which will also cause the amplitude platforms of the waveforms of the pulses applied by the driving circuit for the set operation to be issued to different memory cells 100 to be different. Therefore, the use of a third pulse with at least two amplitude platforms is helpful to cover the amplitude platforms required for different memory cells 100 in the memory array to perform better crystallization operations, thereby improving the success rate of the set operation.
[0132] The method embodiments of the present application are described in detail above. The device embodiments of the present application are described below. The device embodiments correspond to the method embodiments, so the parts not described in detail can refer to the previous method embodiments. The device can implement any possible implementation of the above method.
[0133] Fig. 9 is a schematic block diagram of a phase change memory 900 provided in an embodiment of the present application.
[0134] like Fig. 9 As shown, the device 900, the phase change memory 900, includes a control circuit 910 and a storage array 920, wherein the control circuit 910 is used to: obtain data to be written into the storage array 920, wherein the data includes a plurality of bits, and each bit corresponds to a storage unit; perform a set operation or a reset operation on the storage unit corresponding to each bit according to the written data, wherein the set operation is used to convert the storage unit from an amorphous state to a crystalline state, and the reset operation is used to convert the storage unit from an amorphous state to a crystalline state; when performing the reset operation, the control circuit 910 applies a second pulse to the storage unit after applying a first pulse, wherein the amplitude of the waveform of the second pulse is smaller than the amplitude of the waveform of the first pulse, and the total pulse width t of the pulse applied when performing the reset operation is Rtotal The total pulse width t of the third pulse applied to perform the set operation Stotal The relationship is: |t Rtotal -t Stotal | / t Stotal <0.5.
[0135] The present application also provides another computing device 1000. Fig.10 As shown, the computing device 1000 includes: a bus 1002, a processor 1004, a phase change memory 900 and a communication interface 1008. The processor 1004, the phase change memory 900 and the communication interface 1008 communicate through the bus 1002. The computing device 1000 can be a server or a terminal device. It should be understood that the present application does not limit the number of processors and memories in the computing device 1000.
[0136] The bus 1002 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.10 The bus 1002 may include a path for transmitting information between various components of the computing device 1000 (eg, the memory 1006, the processor 1004, and the communication interface 1008).
[0137] The processor 1004 may include any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP).
[0138] Phase change memory 900 may include volatile memory, such as random access memory (RAM). Memory 1006 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD) or solid state drive (SSD).
[0139] The processor 1004 is used to input data to be written into the phase change memory 900 , and the phase change memory 900 is used to execute the aforementioned data writing method.
[0140] The communication interface 1008 uses a transceiver module such as, but not limited to, a network interface card or a transceiver to implement communication between the computing device 1000 and other devices or a communication network.
[0141] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.
[0142] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.
[0143] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.
Claims
1. A data writing method, It is characterized in that The method is used to write data in a phase change memory, the phase change memory includes a control circuit and a storage array, the storage array includes a plurality of storage cells; The method comprises: The control circuit acquires data to be written into the storage array, the data comprising a plurality of bits, each bit corresponding to a storage unit; The control circuit performs a set operation or a reset operation on the storage cell corresponding to each bit according to the written data, wherein the set operation is used to convert the storage cell from an amorphous state to a crystalline state, and the reset operation is used to convert the storage cell from an amorphous state to a crystalline state; When performing the reset operation, the control circuit applies a second pulse to the storage unit after applying a first pulse, wherein the amplitude of the waveform of the second pulse is smaller than the amplitude of the waveform of the first pulse, and the total pulse width t of the pulses applied during the reset operation is Rtotal The total pulse width t of the third pulse applied to perform the set operation Stotal The relationship is: |t Rtotal -t Stotal | / t Stotal <0.
5.
2. The method according to claim 1, It is characterized in that There is a time interval between the first pulse and the second pulse.
3. The method according to claim 2, It is characterized in that The time interval is 100-1000 nanoseconds ns.
4. The method according to any one of claims 1 to 3, It is characterized in that The maximum amplitude of the waveform of the second pulse is 10-50 microamperes μA and / or 0.5-4.5 volts V.
5. The method according to any one of claims 1 to 4, It is characterized in that The pulse width of the second pulse is 10-500ns.
6. The method according to any one of claims 1 to 5, It is characterized in that The waveform of the second pulse includes at least one of a square wave, a triangle wave or a step wave.
7. The method according to any one of claims 1 to 6, It is characterized in that The maximum amplitude of the waveform of the third pulse is 5.5-7.5V.
8. The method according to any one of claims 1 to 7, It is characterized in that The pulse width of the third pulse is 10-500ns.
9. The method according to any one of claims 1 to 8, It is characterized in that The waveform of the third pulse has at least two amplitude platforms greater than zero.
10. A phase change memory, comprising a control circuit and a storage array, It is characterized in that The control circuit is used for: Acquire data to be written into the storage array, the data comprising a plurality of bits, each bit corresponding to a storage unit; Performing a set operation or a reset operation on the storage cell corresponding to each bit according to the written data, wherein the set operation is used to convert the storage cell from an amorphous state to a crystalline state, and the reset operation is used to convert the storage cell from an amorphous state to a crystalline state; When performing the reset operation, the control circuit applies a second pulse to the storage unit after applying a first pulse, wherein the amplitude of the waveform of the second pulse is smaller than the amplitude of the waveform of the first pulse, and the total pulse width t of the pulses applied during the reset operation is Rtotal The total pulse width t of the third pulse applied to perform the set operation Stotal The relationship is: |t Rtotal -t Stotal | / t Stotal <0.
5.
11. A computing device, It is characterized in that The method comprises a processor and a phase change memory, wherein the processor is used to input data to be written into the phase change memory, and the phase change memory is used to execute the method according to any one of claims 1 to 9.