RRAM multi-bit storage fast reading circuit and method

Abstract

The invention particularly relates to an RRAM multi-bit storage fast reading circuit and method, and the circuit comprises at least one RRAM conductivity value reading circuit, at least one RRAM and an analog-to-digital converter are arranged corresponding to each circuit, each circuit comprises a pre-charging node, a sampling switch, a switching element and a balance capacitor, and after a reading request is received, a target RRAM is determined from the at least one RRAM; after a sampling switch of a target RRAM conductivity value reading circuit corresponding to the target RRAM is controlled to be closed for a first preset duration, the sampling switch is switched off, and discharging is performed for a second preset duration through the pre-charging node; and reading the voltage value of the pre-charging node by using an analog-to-digital converter corresponding to the target RRAM conductivity value reading circuit, and obtaining a multi-bit reading result according to the current conductivity state of the target RRAM. Therefore, the problems that in a traditional reading mode, the pre-charging speed is low, and the reading period is long are solved, and multi-bit data can be read in a single period.

Description

Technical Field

[0001] The present application relates to the field of electronic storage technology, and in particular to a RRAM multi-bit storage fast reading circuit and method. Background Art

[0002] The rapid development of artificial intelligence technology in recent years has put forward higher requirements for hardware computing performance. The iterative update of algorithms and the explosive growth of parameter volume have put forward requirements for neural network accelerators such as greater computing power, larger memory, higher energy efficiency, and lower latency. In order to solve the storage wall problem faced by the traditional von Neumann computing architecture and the slowdown of CMOS technology development, researchers have proposed a new computing architecture: near-memory computing and storage-computing integration.

[0003] At present, the reading method of RRAM array is mostly for single-bit storage. Before the read operation, the word line is first charged to the read voltage, assisted by a clamping circuit to stabilize the read voltage, and then the current flowing through the RRAM is compared with the reference current through a sensitive amplifier to generate a comparison result. For multi-bit storage, the relevant technology is to poll the reference current or to access multiple cells at the same time to combine single-bit data into multi-bit data to achieve single-cycle reading.

[0004] In the related technologies, the analog storage and computing technology based on RRAM crossbar array integrates computing operations directly into the memory, reducing data transmission and memory access overhead, breaking through the memory wall bottleneck; the digital near-memory computing technology based on RRAM crossbar array shortens the distance between storage and computing and reduces memory access overhead. At the same time, as a single-bit storage, RRAM has a high resistance switching ratio, which alleviates the accuracy problem in analog memory calculation and improves computing reliability; and with the advancement of device technology and the optimization of device performance, it has become possible for RRAM cells to store multi-bit data, which will further optimize storage density, memory access bandwidth and computing power.

[0005] However, the analog storage and computing technology based on RRAM crossbar arrays still faces many problems. For example, the voltage drop caused by the resistance of large-scale array interconnects leads to a decrease in calculation accuracy, the difference in the degree of parallelism of convolutional layer and fully connected layer calculations leads to a large range change in the quantization circuit, and the non-ideality of the device and circuit noise affect the calculation accuracy. As the RRAM array continues to expand, the parasitic resistance and capacitance of the interconnects increase, resulting in a large time constant for the pre-charging process of the word line in the traditional reading method, and the pre-charging speed is slow, which slows down the reading speed. In addition, multi-bit reading methods in related technologies such as reference current polling will further deteriorate the reading cycle and need to be solved urgently. Summary of the invention

[0006] The present application provides a RRAM multi-bit storage fast reading circuit and method to solve the problems of slow pre-charging speed and long reading cycle in the traditional reading method, improve the reading speed, and then improve the bandwidth and chip computing power, so as to realize the reading of multi-bit data in a single cycle.

[0007] The first aspect of the present application provides an RRAM multi-bit storage fast reading circuit, including: at least one RRAM conductance value reading circuit, at least one RRAM and an analog-to-digital converter corresponding to each RRAM conductance value reading circuit, each RRAM conductance value reading circuit includes a precharge node, a sampling switch, a switch element and a balancing capacitor, wherein:

[0008] After receiving the read request, determining a target RRAM from the at least one RRAM;

[0009] Controlling a sampling switch of a target RRAM conductivity value reading circuit corresponding to the target RRAM to close for a first preset time, then opening the sampling switch to discharge through the precharge node for a second preset time;

[0010] The voltage value of the precharge node is read by an analog-to-digital converter corresponding to the target RRAM conductance value reading circuit, and the current conductance state of the target RRAM is determined according to the voltage value of the precharge node, so as to obtain a multi-bit read result according to the current conductance state.

[0011] Optionally, each analog-to-digital converter comprises:

[0012] at least three comparator modules, each of which is connected to a corresponding RRAM conductance value reading circuit;

[0013] A 2-bit logic module, used to obtain a 2-bit read result according to the output of two comparator modules among the at least three comparator modules

[0014] The 3-bit logic module is used to obtain a 3-bit read result based on the outputs of all comparator modules.

[0015] Optionally, the RRAM multi-bit storage fast reading circuit further includes: a bit line driving unit connected to the control end of each RRAM and a word line driving unit connected to the transmission end of each RRAM, wherein:

[0016] The bit line driving unit and the word line driving unit determine the target RRAM from the at least one RRAM based on the read request.

[0017] Optionally, one end of the balancing capacitor is connected to one end of the sampling switch through the pre-charging node, the other end of the balancing capacitor is connected to a ground node, and the other end of the sampling switch is connected to a pre-charging voltage output node;

[0018] A switch element, wherein a first end of the switch element is respectively connected to one end of the balancing capacitor and one end of the sampling switch through the precharge node, and a second end of the switch element is connected to the corresponding RRAM.

[0019] Optionally, the bit line driving unit includes one or more bit line drivers.

[0020] Optionally, the number of bit line drivers is equal to the number of RRAM conductance value reading circuits.

[0021] Optionally, the word line driving unit includes one or more word line drivers.

[0022] Optionally, the number of word line drivers is equal to the number of RRAMs corresponding to the RRAM conductance value reading circuit.

[0023] A second aspect of the present application provides a RRAM multi-bit storage fast reading method, using the above-mentioned RRAM multi-bit storage fast reading circuit, wherein the method comprises the following steps:

[0024] Determine whether a read request is received;

[0025] After receiving the read request, determining a target RRAM from the at least one RRAM, and controlling a sampling switch of a target RRAM conductivity value reading circuit corresponding to the target RRAM to close for a first preset time, and then opening the sampling switch to discharge through the precharge node for a second preset time;

[0026] The voltage value of the precharge node is read by an analog-to-digital converter corresponding to the target RRAM conductance value reading circuit, and the current conductance state of the target RRAM is determined according to the voltage value of the precharge node, so as to obtain a multi-bit read result according to the current conductance state.

[0027] Optionally, the read request includes at least one of a 2-bit read request and a 3-bit read request.

[0028] Thus, after receiving a read request, a target RRAM is determined from at least one RRAM; after controlling the sampling switch of the target RRAM conductivity value reading circuit corresponding to the target RRAM to close for a first preset time, the sampling switch is turned off, and the voltage value of the precharge node is discharged through the precharge node for a second preset time; the analog-to-digital converter corresponding to the target RRAM conductivity value reading circuit is used to read the voltage value of the precharge node, and the current conductivity state of the target RRAM is obtained according to the voltage value of the precharge node, so as to obtain a multi-bit reading result according to the current conductivity state. Thus, the problems of slow precharge speed and long reading cycle in the traditional reading method are solved, the reading speed is improved, and then the bandwidth and chip computing power are improved, and multi-bit data can be read out in a single cycle.

[0029] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0031] Figure 1 A schematic diagram of a RRAM multi-bit storage fast read circuit provided according to an embodiment of the present application;

[0032] Figure 2 A schematic diagram of the working timing of a RRAM multi-bit storage fast reading circuit provided according to an embodiment of the present application;

[0033] Figure 3 A schematic diagram of an overall circuit implementation of an RRAM multi-bit storage fast read circuit provided according to an embodiment of the present application;

[0034] Figure 4 A schematic diagram of an analog-to-digital conversion circuit of an RRAM multi-bit storage fast read circuit provided according to an embodiment of the present application;

[0035] Figure 5 A schematic diagram of the working timing of an analog-to-digital conversion circuit of an RRAM multi-bit storage fast read circuit provided according to an embodiment of the present application;

[0036] Figure 6 The present invention is a flowchart of a method for fast reading of RRAM multi-bit storage provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0037] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0038] Before introducing the RRAM multi-bit storage fast reading circuit and method of the embodiment of the present application, the principle of the RRAM multi-bit storage fast reading circuit of the embodiment of the present application is briefly introduced. Figure 1 shown.

[0039] Specifically, the conventional reading method based on the RRAM crossbar array in the related art is Figure 1 Node ① is precharged to the read voltage, and then the current flowing through the RRAM is read to obtain the corresponding conductivity value of the RRAM. Array parasitics cause the charging and discharging process of node ① to take a long time, which seriously affects the reading speed. When facing RRAM multi-bit digital near-memory applications, the continuous reading speed of RRAM is the main factor affecting the chip computing power.

[0040] Based on the above problems, this application proposes a RRAM multi-bit storage fast reading circuit and method, which improves the charging speed by adjusting the node of the pre-charging process (from ① to ②) because ② has a smaller capacitance. Figure 2 As shown, Figure 2 Schematic diagram of the working timing of the circuit of the embodiment of the present application, wherein V S is the control voltage of switch S, V S When the voltage is low, node ② is charged. When reading, switch S is turned off, node ② is discharged to the ground, and the discharge current is related to the RRAM conductance value. After discharging for a period of time, the different conductance states corresponding to the RRAM are distinguished according to the final node voltage value.

[0041] After receiving a read request, the embodiment of the present application determines a target RRAM from at least one RRAM; after controlling the sampling switch of the target RRAM conductivity value reading circuit corresponding to the target RRAM to close for a first preset time, the sampling switch is turned off, and the precharge node is discharged for a second preset time; the voltage value of the precharge node is read by the analog-to-digital converter corresponding to the target RRAM conductivity value reading circuit, and the current conductivity state of the target RRAM is obtained according to the voltage value of the precharge node, so as to obtain a multi-bit reading result according to the current conductivity state. Thus, the problems of slow precharge speed and long reading cycle in the traditional reading method are solved, the reading speed is improved, and then the bandwidth and chip computing power are improved, and multi-bit data can be read out in a single cycle.

[0042] Specifically, Figure 3A block diagram of a RRAM multi-bit storage fast read circuit provided in an embodiment of the present application.

[0043] like Figure 3 As shown, the RRAM multi-bit storage fast reading circuit 10 includes: at least one RRAM conductivity value reading circuit (such as Figure 3 In the RRAM conductivity value reading circuit 101, RRAM conductivity value reading circuit 102, RRAM conductivity value reading circuit 103, RRAM conductivity value reading circuit 104, ..., 10N-1, 10N), at least one RRAM (such as Figure 3 The first RRAM) and analog-to-digital converter (such as Figure 3 In the embodiment of the present invention, the analog-to-digital converter 301, the analog-to-digital converter 302, ..., the analog-to-digital converter 30M), each RRAM conductivity value reading circuit includes a pre-charge node, a sampling switch, a switch element and a balancing capacitor; wherein, after receiving a read request, a target RRAM is determined from at least one RRAM; after controlling the sampling switch of the target RRAM conductivity value reading circuit corresponding to the target RRAM to close for a first preset time, the sampling switch is opened, and the pre-charge node is discharged for a second preset time; the analog-to-digital converter corresponding to the target RRAM conductivity value reading circuit is used to read the voltage value of the pre-charge node, and the current conductivity state of the target RRAM is determined according to the voltage value of the pre-charge node, so as to obtain a multi-bit read result according to the current conductivity state.

[0044] Among them, the switch element can be a MOS tube, the target RRAM refers to one or more specific RRAM cells selected in the RRAM array according to the address specified by the read request, each RRAM cell can store a multi-bit value, and different data are represented by its resistance state (i.e., conductivity state); the first preset time length refers to the time length of closing the sampling switch in the target RRAM conductivity value reading circuit corresponding to the target RRAM; the second preset time length refers to the time length allowing the pre-charge node to discharge to the ground after the sampling switch is disconnected; the first preset time length and the second preset time length can be preset by the user, can be obtained through a limited number of experiments, or can be obtained through a limited number of computer simulations, and are not specifically limited here.

[0045] It can be understood that the embodiments of the present application can ensure that accurate data stored in the RRAM is read by precisely controlling the closing and opening time (first preset time length and second preset time length) of the sampling switch and the discharge process of the pre-charge node; multi-bit data is read according to the conductivity state of the RRAM, thereby improving the storage density and reading flexibility, optimizing the design and control flow of the reading circuit, shortening the reading time, and maintaining the reading accuracy; the embodiments of the present application are applicable to a storage array comprising multiple RRAM cells, and can efficiently manage and read the data in these cells.

[0046] Optionally, in some embodiments, each analog-to-digital converter includes: at least three comparator modules, each comparator module is connected to the corresponding RRAM conductivity value reading circuit; a 2-bit logic module, used to obtain a 2-bit reading result based on the outputs of two comparator modules among the at least three comparator modules; and a 3-bit logic module, used to obtain a 3-bit reading result based on the outputs of all comparator modules.

[0047] It is understood that each comparator receives the precharge node voltage from a specific RRAM cell as input and compares it with an internally set reference voltage; these comparators are used to determine the conductivity state of the RRAM cell. When the discharge process is completed, the comparator outputs a high or low level signal based on the relationship between the actual voltage and the reference voltage to indicate which conductivity state the RRAM cell is in. The 2-bit logic module implements multi-bit reading of RRAM cells with lower resolution. For example, in one configuration, two comparators may be used to distinguish four different conductivity states (00, 01, 10, 11), thereby completing 2-bit data reading. The 3-bit logic module is designed to provide higher resolution, that is, a 3-bit read result, taking into account the outputs of all comparators to more accurately distinguish the different conductivity states of the RRAM cell.

[0048] It should be noted that during the reading process, the target RRAM cell is discharged, and the comparator module in the ADC compares the actual voltage with the reference voltage. According to the comparison result, the 2-bit logic module or the 3-bit logic module will be selectively activated to produce the final 2-bit or 3-bit reading result. This design allows the ADC to be flexibly configured into different modes to meet the needs of different application scenarios. For example, the 2-bit mode can be selected when faster but lower resolution reading is required, and the 3-bit mode can be selected when high-resolution reading is required.

[0049] Specifically, in order to realize the single-cycle reading of multi-bit data, a 2bit / 3bit splittable analog-to-digital conversion circuit is constructed for the fast reading method proposed in the embodiment of the present application. Figure 4As shown. The circuit is based on Flash ADC logic, supplemented by group switches to achieve 2bit / 3bit separable functions. Under different switch combinations, a 2bit ADC can be realized through COMP0, COMP1, COMP2 and a 2bit logic module (COMP4, COMP5, COMP6 and another 2bit logic module can realize another 2bit ADC), or a 3bit ADC can be realized through all comparator modules and 3bit logic modules. Among them, the comparator is a traditional dynamic latch comparator, which starts to compare when the rising edge of the clock CLK0 / CLK1 / CLK2 arrives. At the moment after the comparison action occurs, the drain voltage of the input NMOS transistor drops rapidly (the drain voltage of the input transistor in the reset state is the power supply voltage), and is coupled to the input end through the gate-drain parasitic capacitance of the input NMOS, affecting the input voltage. This situation is called kick-back noise. In order to alleviate the impact of the above phenomenon, the embodiment of the present application adds a sampling switch and a balancing capacitor C at the positive and negative input ends of the comparator respectively. BANL , thereby achieving correct comparison results and optimizing the kick-back noise problem in the comparator module.

[0050] Further, Figure 5 For the analog-to-digital conversion circuit, the timing of one of the ADCs when two 2-bit ADCs are working, SAM0 and CLK0 are Figure 4 The input sampling switches and clock control signals of COMP0, COMP1, and COMP2 are shown in the figure. The clock cycle is 2ns. COMP2_VIP and COMP2_VIN are the positive and negative input signals of COMP2 respectively. COMP2_OUT is the output of COMP2. COMP0 and COMP1 are similar to the above. The negative input of the three comparators is the sampling signal of the reference voltage, and the positive input is Figure 1 The sampling signal of the voltage at node ① in the circuit. Under the control of the clock, the comparator outputs the thermometer code, which is converted into a 2-bit output by the decoding circuit.

[0051] Optionally, in some embodiments, Figure 3 As shown, the above-mentioned RRAM multi-bit storage fast reading circuit 10 further includes: a bit line driving unit (such as Figure 3 A bit line driving unit 401 connected to the control terminal of the first RRAM in the embodiment of the present invention and a word line driving unit (such as Figure 3 A word line driving unit 501 is connected to a transmission end of a first RRAM in the memory, wherein the bit line driving unit and the word line driving unit determine a target RRAM from at least one RRAM based on a read request.

[0052] Optionally, in some embodiments, the bit line driving unit includes one or more bit line drivers.

[0053] Optionally, in some embodiments, the number of bit line drivers is equal to the number of RRAM conductance value reading circuits.

[0054] Optionally, in some embodiments, the word line driving unit includes one or more word line drivers.

[0055] Optionally, in some embodiments, the number of word line drivers is equal to the number of corresponding RRAMs of the RRAM conductance value reading circuit.

[0056] Among them, the bit line driver unit is mainly used to control the bit lines (BL) in the RRAM array. It provides the necessary voltage or current signal to the bit line to realize the selection, programming, erasing or reading operations of the RRAM cell; the word line driver unit is responsible for controlling the word lines (WL) in the RRAM array. Its main task is to select the RRAM cell on a specific row for operation.

[0057] Specifically, the bitline driver unit is connected to the control end of each RRAM and is responsible for applying the necessary voltage or current signal to the RRAM unit during the read operation; during the read process, the bitline driver unit transmits a read request signal to the RRAM unit and receives a response signal from the RRAM unit, which contains the stored data information; by parsing the response signal, the bitline driver unit can extract the data stored in the RRAM unit and convert it into a format that can be recognized by the computer. The wordline driver unit is connected to the transmission end of each RRAM and is responsible for determining and selecting the target RRAM unit according to the read request, usually by applying a voltage or current signal to a specific wordline, thereby activating the RRAM unit connected to the wordline; once the target RRAM unit is selected, the wordline driver unit is responsible for transmitting the data stored in the unit to the external circuit or processor through the transmission end; the wordline driver unit is also responsible for coordinating and controlling with other circuit components to ensure the correctness and efficiency of the read operation.

[0058] Furthermore, the bit line driver and word line driver can quickly and accurately locate the target RRAM cell, speeding up the reading and writing speed; the simultaneous operation of multiple bit line drivers and word line drivers supports multiple RRAM cells to be accessed in the same time period, significantly increasing the system throughput and optimizing resource utilization; reducing the signal interference that may be introduced by multiplexing, ensuring the accuracy of each read and write operation, and reducing the error rate.

[0059] Optionally, in some embodiments, one end of the balancing capacitor is connected to one end of the sampling switch through a pre-charging node, the other end of the balancing capacitor is connected to a ground node, and the other end of the sampling switch is connected to a pre-charging voltage output node; a switch element, a first end of the switch element is respectively connected to one end of the balancing capacitor and one end of the sampling switch through the pre-charging node, and a second end of the switch element is connected to a corresponding RRAM.

[0060] It can be understood that in the pre-charging stage, the balancing capacitor receives the pre-charging voltage through the pre-charging node and stores electrical energy, which helps to provide a stable voltage source during the subsequent data reading or writing process; the balancing capacitor can also filter out high-frequency noise and fluctuations in the circuit, ensure that the voltage provided to the RRAM is stable and reliable, and help protect the RRAM from voltage fluctuations. During the data reading process, the sampling switch is closed according to the control signal, and the data in the RRAM is transmitted to the external circuit or processor through the pre-charging voltage output node for processing; during the non-sampling period, the sampling switch remains in an open state to isolate the RRAM from the external circuit to prevent data leakage or external interference. The switch device is used to connect the balancing capacitor, the sampling switch and the corresponding RRAM to achieve flexible configuration and selection of the circuit; in the pre-charging stage, the switch device is closed to allow the pre-charging voltage to enter the balancing capacitor and RRAM through the pre-charging node, preparing for subsequent data reading or writing operations.

[0061] Therefore, based on the fast reading method and analog-to-digital conversion circuit proposed in the embodiment of the present application, an overall circuit implementation is provided in conjunction with the RRAM array, such as Figure 3 As shown in the figure, nodes ① and ② are respectively Figure 1 The corresponding nodes in Figure 2 and Figure 5 Under the timing, the ADC can simultaneously perform 2-bit analog-to-digital conversion on two rows of BL or perform 3-bit analog-to-digital conversion on only one row of BL in one clock cycle. In the actual circuit, the ADC can be shared by multiple rows of BL, thereby saving area and reducing power consumption. Therefore, the embodiment of the present application realizes fast reading of RRAM multi-bit storage, and is expected to help further improve storage density and computing power density.

[0062] According to the RRAM multi-bit storage fast reading circuit proposed in the embodiment of the present application, after receiving a read request, a target RRAM is determined from at least one RRAM; after controlling the sampling switch of the target RRAM conductivity value reading circuit corresponding to the target RRAM to close for a first preset time, the sampling switch is disconnected, and the voltage value of the precharge node is discharged through the precharge node for a second preset time; the analog-to-digital converter corresponding to the target RRAM conductivity value reading circuit is used to read the voltage value of the precharge node, and the current conductivity state of the target RRAM is determined according to the voltage value of the precharge node, so as to obtain a multi-bit reading result according to the current conductivity state. Thus, the problems of slow precharge speed and long reading cycle in the traditional reading method are solved, the reading speed is improved, and then the bandwidth and chip computing power are improved, and multi-bit data can be read out in a single cycle.

[0063] Next, the RRAM multi-bit storage fast reading method proposed in the embodiment of the present application is described with reference to the accompanying drawings.

[0064] Figure 6 Flow chart of the RRAM multi-bit storage fast reading method according to an embodiment of the present application.

[0065] In this embodiment, the RRAM multi-bit storage fast reading method adopts Figure 3 The RRAM multi-bit storage fast reading circuit shown in the embodiment.

[0066] like Figure 6 As shown, the RRAM multi-bit storage fast reading method includes the following steps:

[0067] In step S601, it is determined whether a read request is received.

[0068] In step S602, after receiving a read request, a target RRAM is determined from at least one RRAM, and a sampling switch of a target RRAM conductivity value reading circuit corresponding to the target RRAM is controlled to close for a first preset time, and then the sampling switch is opened to discharge through a precharge node for a second preset time.

[0069] In step S603, the voltage value of the precharge node is read by an analog-to-digital converter corresponding to the target RRAM conductance value reading circuit, and the current conductance state of the target RRAM is determined according to the voltage value of the precharge node to obtain a multi-bit read result according to the current conductance state.

[0070] Optionally, in some embodiments, the read request includes at least one of a 2-bit read request and a 3-bit read request.

[0071] It should be noted that the above explanation of the RRAM multi-bit storage fast reading circuit embodiment is also applicable to the RRAM multi-bit storage fast reading method of this embodiment, and will not be repeated here.

[0072] According to the RRAM multi-bit storage fast reading circuit and method proposed in the embodiment of the present application, it is determined whether a read request is received. After receiving the read request, the target RRAM is determined from at least one RRAM, and the sampling switch of the target RRAM conductivity value reading circuit corresponding to the target RRAM is controlled to close for a first preset time, and then the sampling switch is disconnected. After the pre-charge node is discharged for a second preset time, the voltage value of the pre-charge node is read by the analog-to-digital converter corresponding to the target RRAM conductivity value reading circuit, and the current conductivity state of the target RRAM is obtained according to the voltage value of the pre-charge node, so as to obtain a multi-bit reading result according to the current conductivity state. In this way, the problems of slow pre-charging speed and long reading cycle in the traditional reading method are solved, the reading speed is improved, and then the bandwidth and chip computing power are improved, so as to realize the reading of multi-bit data in a single cycle.

[0073] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0074] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0075] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0076] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiment, the N steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0077] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

Claims

1. A RRAM multi-bit storage fast reading circuit, characterized in that: include: At least one RRAM conductance value reading circuit, at least one RRAM and an analog-to-digital converter are arranged corresponding to each RRAM conductance value reading circuit, each RRAM conductance value reading circuit includes a precharge node, a sampling switch, a switch element and a balancing capacitor, wherein: After receiving the read request, determining a target RRAM from the at least one RRAM; Controlling a sampling switch of a target RRAM conductivity value reading circuit corresponding to the target RRAM to close for a first preset time, then opening the sampling switch to discharge through the precharge node for a second preset time; The voltage value of the precharge node is read by an analog-to-digital converter corresponding to the target RRAM conductance value reading circuit, and the current conductance state of the target RRAM is determined according to the voltage value of the precharge node, so as to obtain a multi-bit read result according to the current conductance state.

2. The RRAM multi-bit storage fast read circuit according to claim 1, characterized in that: Each ADC includes: at least three comparator modules, each of which is connected to a corresponding RRAM conductance value reading circuit; A 2-bit logic module, used to obtain a 2-bit read result according to the output of two comparator modules among the at least three comparator modules The 3-bit logic module is used to obtain a 3-bit read result based on the outputs of all comparator modules.

3. The RRAM multi-bit storage fast reading circuit according to claim 1, characterized in that: Also includes: A bit line driving unit connected to the control terminal of each RRAM and a word line driving unit connected to the transmission terminal of each RRAM, wherein: The bit line driving unit and the word line driving unit determine the target RRAM from the at least one RRAM based on the read request.

4. The RRAM multi-bit storage fast reading circuit according to claim 1, characterized in that: One end of the balancing capacitor is connected to one end of the sampling switch through the pre-charging node, the other end of the balancing capacitor is connected to the ground node, and the other end of the sampling switch is connected to the pre-charging voltage output node; A switch element, wherein a first end of the switch element is respectively connected to one end of the balancing capacitor and one end of the sampling switch through the precharge node, and a second end of the switch element is connected to the corresponding RRAM.

5. The RRAM multi-bit storage fast reading circuit according to claim 1, characterized in that: The bit line driving unit includes one or more bit line drivers.

6. The RRAM multi-bit storage fast reading circuit according to claim 5, characterized in that: The number of bit line drivers is equal to the number of RRAM conductance value reading circuits.

7. The RRAM multi-bit storage fast reading circuit according to claim 1, characterized in that: The word line driving unit includes one or more word line drivers.

8. The RRAM multi-bit storage fast reading circuit according to claim 7, characterized in that: The number of word line drivers is equal to the number of RRAMs corresponding to the RRAM conductance value reading circuits.

9. A method for fast reading of RRAM multi-bit storage, characterized in that: The RRAM multi-bit storage fast reading circuit according to any one of claims 1 to 8 is used, wherein the method comprises the following steps: Determine whether a read request is received; After receiving the read request, determining a target RRAM from the at least one RRAM, and controlling a sampling switch of a target RRAM conductivity value reading circuit corresponding to the target RRAM to close for a first preset time, and then opening the sampling switch to discharge through the precharge node for a second preset time; The voltage value of the precharge node is read by an analog-to-digital converter corresponding to the target RRAM conductance value reading circuit, and the current conductance state of the target RRAM is determined according to the voltage value of the precharge node, so as to obtain a multi-bit read result according to the current conductance state.

10. The method according to claim 9, characterized in that The read request includes at least one of a 2-bit read request and a 3-bit read request.

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