Rram multi-bit storage fast read circuit and method

Abstract

The application particularly relates to a RRAM multi-bit storage fast reading circuit and method, which comprises at least one RRAM conductance value reading circuit, at least one RRAM arranged in correspondence with each circuit and an analog-to-digital converter, each circuit comprising a pre-charging node, a sampling switch, a switch piece and a balancing capacitor, wherein, after receiving a reading request, a target RRAM is determined from the at least one RRAM; after controlling the sampling switch of the target RRAM conductance value reading circuit corresponding to the target RRAM to be closed for a first preset time length, the sampling switch is opened, and the pre-charging node is discharged for a second preset time length; the voltage value of the pre-charging node is read by the analog-to-digital converter corresponding to the target RRAM conductance value reading circuit, and a multi-bit reading result is obtained according to the current conductance state of the target RRAM. Thus, the problems of slow pre-charging speed and long reading period in the traditional reading mode are solved, and multi-bit data is read out in a single period.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic storage, in particular to a RRAM multi-bit storage fast reading circuit and method. BACKGROUND

[0002] In recent years, the rapid development of artificial intelligence technology has put forward higher requirements for hardware computing performance. The iterative update of algorithms and the explosive growth of parameter quantity have put forward greater computing power, larger memory, higher energy efficiency, and lower latency requirements for neural network accelerators. To solve the problem of the storage wall faced by the traditional von Neumann computing architecture and the problem of the slow development of CMOS technology, researchers have proposed a new computing architecture: near-memory computing and memory-compute integration.

[0003] Currently, the reading mode of the RRAM array is mainly for single-bit storage. Before reading, the word line is first charged to the read voltage, assisted by a clamping circuit to stabilize the read voltage, and then the current flowing through the RRAM is compared with the reference current through a sensitive amplifier to generate a comparison result. For multi-bit storage, the related technology is to poll the reference current or to access multiple units simultaneously to combine multi-bit data into multi-bit data to realize single-cycle reading.

[0004] In the related technology, the analog memory-compute integration technology based on the RRAM cross array integrates the computing operation directly into the memory, reduces the data transmission and memory access overhead, and breaks through the memory wall bottleneck. The digital near-memory computing technology based on the RRAM cross array shortens the distance between storage and computing, and reduces the memory access overhead. At the same time, as a single-bit storage, RRAM has a high resistance switching ratio, which alleviates the precision problem in analog in-memory computing and improves the computing reliability. Moreover, with the advancement of device technology and optimization of device performance, it is possible for RRAM units to store multi-bit data, which will further optimize storage density, memory bandwidth, and computing power.

[0005] However, the analog memory-compute integration technology based on the RRAM cross array still faces many problems, such as the voltage drop caused by the large-scale array interconnection line resistance, which leads to a decrease in computing accuracy, the difference in parallelism between convolution layers and fully connected layers, which requires a large range change in the quantization circuit, and the influence of device non-idealities and circuit noise on computing accuracy. With the continuous expansion of the RRAM array, the parasitic resistance and capacitance of the interconnection line increase, which leads to a large time constant in the pre-charging process of the word line in the traditional reading mode, slow pre-charging speed, and thus slow reading speed. In addition, the multi-bit reading mode in the related technology, such as reference current polling, will further worsen the reading period, which needs to be solved urgently. SUMMARY

[0006] The application provides a RRAM multi-bit storage fast reading circuit and method to solve the problems of slow pre-charging speed, long reading period and the like in a conventional reading mode, improve reading speed, and thus improve bandwidth and chip computing power, and realize reading of multi-bit data in a single period.

[0007] The first aspect embodiment of the application provides a RRAM multi-bit storage fast reading circuit, comprising: at least one RRAM conductance value reading circuit, at least one RRAM and an analog-to-digital converter corresponding to each RRAM conductance value reading circuit, each RRAM conductance value reading circuit comprising a pre-charging node, a sampling switch, a switch piece and a balancing capacitor, wherein,

[0008] After receiving a reading request, a target RRAM is determined from the at least one RRAM;

[0009] After the sampling switch of the target RRAM conductance value reading circuit corresponding to the target RRAM is closed for a first preset time length, the sampling switch is opened, and the pre-charging node is discharged for a second preset time length;

[0010] The voltage value of the pre-charging node is read by the analog-to-digital converter corresponding to the target RRAM conductance value reading circuit, and the current conductance state of the target RRAM is determined according to the voltage value of the pre-charging node, so as to obtain a multi-bit reading result according to the current conductance state.

[0011] Optionally, each analog-to-digital converter comprises:

[0012] At least three comparator modules, each comparator module being connected to a corresponding RRAM conductance value reading circuit;

[0013] A 2bit logic module is configured to obtain a 2-bit reading result according to the outputs of two comparator modules in the at least three comparator modules.

[0014] A 3bit logic module is configured to obtain a 3-bit reading result according to the outputs of all comparator modules.

[0015] Optionally, the RRAM multi-bit storage fast reading circuit further comprises a bit line driving unit connected to the control end of each RRAM and a word line driving unit connected to the transmission end of each RRAM.

[0016] The bit line driving unit and the word line driving unit determine the target RRAM from the at least one RRAM based on the reading request.

[0017] Optionally, one end of the balancing capacitor is connected to one end of the sampling switch through the pre-charge node, and the other end of the balancing capacitor is connected to a ground node, and the other end of the sampling switch is connected to a pre-charge voltage output node.

[0018] a switch element, a first end of the switch element being connected to one end of the balancing capacitor and one end of the sampling switch through the pre-charge node respectively, and a second end of the switch element being connected to the corresponding RRAM.

[0019] Optionally, the bit line driving unit includes one or more bit line drivers.

[0020] Optionally, the number of the bit line drivers is equal to the number of the RRAM conductance value reading circuits.

[0021] Optionally, the word line driving unit includes one or more word line drivers.

[0022] Optionally, the number of the word line drivers is equal to the number of the corresponding RRAMs of the RRAM conductance value reading circuits.

[0023] The second aspect embodiment of the present application provides a fast reading method for RRAM multi-bit storage, which adopts the fast reading circuit for RRAM multi-bit storage described above, and the method includes the following steps:

[0024] determining whether a reading request is received;

[0025] after receiving the reading request, determining a target RRAM from the at least one RRAM, and controlling the sampling switch of the target RRAM conductance value reading circuit of the target RRAM to be closed for a first preset time length, then being opened, and discharging through the pre-charge node for a second preset time length;

[0026] reading the voltage value of the pre-charge node by using the analog-to-digital converter corresponding to the target RRAM conductance value reading circuit, and determining the current conductance state of the target RRAM according to the voltage value of the pre-charge node, so as to obtain a multi-bit reading result according to the current conductance state.

[0027] Optionally, the reading request includes at least one of a 2-bit reading request and a 3-bit reading request.

[0028] Thus, after receiving the read request, the target RRAM is determined from the at least one RRAM; after the sampling switch of the target RRAM corresponding target RRAM conductance value reading circuit is closed for a first preset time length, the sampling switch is opened, and the pre-charge node is discharged for a second preset time length; the voltage value of the pre-charge node is read by the analog-to-digital converter corresponding to the target RRAM conductance value reading circuit, and the current conductance state of the target RRAM is determined according to the voltage value of the pre-charge node, so that the multi-bit read result is obtained according to the current conductance state. Thus, the problems of slow pre-charge speed and long read period in the traditional read mode are solved, the read speed is improved, and the bandwidth and chip computing power are improved, and multi-bit data is read out in a single cycle.

[0029] Additional aspects and advantages of the present application will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0030] The above and / or additional aspects and advantages of the present application will become apparent and be readily appreciated from the following description, including the appended drawings.

[0031] Figure 1 A principle schematic diagram of a RRAM multi-bit storage fast read circuit according to an embodiment of the present application;

[0032] Figure 2 A working timing schematic diagram of a RRAM multi-bit storage fast read circuit according to an embodiment of the present application;

[0033] Figure 3 A whole circuit implementation schematic diagram of a RRAM multi-bit storage fast read circuit according to an embodiment of the present application;

[0034] Figure 4 An analog-digital conversion circuit schematic diagram of a RRAM multi-bit storage fast read circuit according to an embodiment of the present application;

[0035] Figure 5 A working timing schematic diagram of an analog-digital conversion circuit of a RRAM multi-bit storage fast read circuit according to an embodiment of the present application;

[0036] Figure 6 A flowchart of a RRAM multi-bit storage fast read method according to an embodiment of the present application. DETAILED DESCRIPTION

[0037] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0038] Before introducing the RRAM multi-bit storage fast read circuit and method of the embodiments of this application, let's briefly introduce the principle of the RRAM multi-bit storage fast read circuit of the embodiments of this application, such as... Figure 1 As shown.

[0039] Specifically, the traditional read method based on RRAM cross arrays in related technologies... Figure 1 Node ① is pre-charged to the read voltage, and then the conductance value of the RRAM is obtained by reading the current flowing through the RRAM. Array parasitics cause the charging and discharging process of node ① to take a long time, which seriously affects the read speed. In digital near memory applications for multi-bit RRAM storage, the continuous read speed of the RRAM is the main factor affecting the chip's computing power.

[0040] This application addresses the aforementioned problems by proposing a fast read circuit and method for RRAM multi-bit storage. By adjusting the node in the pre-charge process (from ① to ②), the charging speed is improved because ② has a smaller capacitor. For example... Figure 2 As shown, Figure 2 This is a timing diagram of the circuit operation according to an embodiment of this application, wherein V S V is the control voltage for switch S. S When the voltage level is low, node ② is charged. During reading, switch S is turned off, and node ② discharges to ground. The discharge current is related to the RRAM conductance value. After discharging for a period of time, the different conductance states of the RRAM are distinguished according to the different final node voltage values.

[0041] In this embodiment, upon receiving a read request, a target RRAM is determined from at least one RRAM. The sampling switch of the target RRAM conductance value reading circuit corresponding to the target RRAM is closed for a first preset time, then opened, and discharged through a pre-charge node for a second preset time. The voltage value of the pre-charge node is read using the analog-to-digital converter corresponding to the target RRAM conductance value reading circuit. Based on the voltage value of the pre-charge node and the current conductance state of the target RRAM, a multi-bit read result is obtained. This solves the problems of slow pre-charge speed and long read cycle in traditional read methods, improving read speed, thereby increasing bandwidth and chip computing power, and enabling the reading of multiple bits of data within a single cycle.

[0042] Specifically, Figure 3A block diagram of a RRAM multi-bit storage fast reading circuit provided by an embodiment of the present application.

[0043] As shown in Figure 3 , the RRAM multi-bit storage fast reading circuit 10 comprises at least one RRAM conductance value reading circuit (such as Figure 3 RRAM conductance value reading circuit 101, RRAM conductance value reading circuit 102, RRAM conductance value reading circuit 103, RRAM conductance value reading circuit 104, …, 10N-1, 10N), at least one RRAM (such as Figure 3 first RRAM) and an analog-to-digital converter (such as Figure 3 analog-to-digital converter 301, analog-to-digital converter 302, …, analog-to-digital converter 30M) corresponding to each RRAM conductance value reading circuit, each RRAM conductance value reading circuit comprising a pre-charge node, a sampling switch, a switch and a balancing capacitor; wherein, after receiving a reading request, a target RRAM is determined from the at least one RRAM; after the sampling switch of the target RRAM conductance value reading circuit corresponding to the target RRAM is closed for a first preset time length, the sampling switch is opened, and the pre-charge node is discharged for a second preset time length; the voltage value of the pre-charge node is read by the analog-to-digital converter corresponding to the target RRAM conductance value reading circuit, and the current conductance state of the target RRAM is determined according to the voltage value of the pre-charge node, so that a multi-bit reading result is obtained according to the current conductance state.

[0044] Wherein, the switch can be a MOS tube, the target RRAM refers to one or more specific RRAM units selected in the RRAM array according to the address specified by the reading request, each RRAM unit can store a multi-bit value, and different data are represented by the resistance state (i.e. the conductance state) thereof; the first preset time length refers to the time length of closing the sampling switch in the target RRAM conductance value reading circuit corresponding to the target RRAM; the second preset time length refers to the time length of allowing the pre-charge node to discharge to ground after the sampling switch is opened; the first preset time length and the second preset time length can be pre-set by the user, can be obtained through a limited number of experiments, or can be obtained through a limited number of computer simulations, which are not limited here.

[0045] It can be understood that the embodiments of the present application can ensure accurate data stored in the RRAM to be read by precisely controlling the closing and opening time of the sampling switch (the first preset time length and the second preset time length) and the discharging process of the pre-charge node; the data of multiple bits is read according to the conductance state of the RRAM, which improves the storage density and the flexibility of reading, optimizes the design and control process of the reading circuit, shortens the reading time, and at the same time maintains the accuracy of reading; the embodiments of the present application are suitable for a storage array containing multiple RRAM units, and can efficiently manage and read the data in these units.

[0046] Optionally, in some embodiments, each analog-to-digital converter comprises: at least three comparator modules, each comparator module being connected to a corresponding RRAM conductance value reading circuit; a 2bit logic module for obtaining a 2-bit reading result according to the outputs of two comparator modules in the at least three comparator modules; and a 3bit logic module for obtaining a 3-bit reading result according to the outputs of all comparator modules.

[0047] It can be understood that each comparator receives the pre-charge node voltage from a specific RRAM unit as input and compares it with the reference voltage set internally; these comparators are used to determine the conductance state of the RRAM unit. After the discharging process is completed, the comparator will output a high or low level signal according to the relationship between the actual voltage and the reference voltage, so as to indicate which conductance state the RRAM unit is in. The 2bit logic module realizes the multi-bit reading of the RRAM unit with lower resolution, for example, in one configuration, two comparators can be used to distinguish four different conductance states (00, 01, 10, 11), thereby completing the 2-bit data reading. The 3bit logic module aims to provide higher resolution, i.e. 3-bit reading result, and comprehensively considers the outputs of all comparators to more accurately distinguish different conductance states of the RRAM unit.

[0048] It should be noted that during the reading process, the target RRAM unit is discharged, and the comparator module in the ADC compares the actual voltage with the reference voltage, and according to the comparison result, the 2bit logic module or the 3bit logic module is selectively activated to generate the final 2-bit or 3-bit reading result; this design allows the ADC to be flexibly configured into different modes to adapt to different application scenario requirements. For example, the 2bit mode can be selected when faster but lower resolution reading is required; and the 3bit mode is selected when high resolution reading is pursued.

[0049] Specifically, to realize single-cycle reading of multi-bit data, a 2bit / 3bit detachable analog-to-digital conversion circuit is built for the fast reading method proposed in the embodiments of the present application, as shown in Figure 4The circuit is based on Flash ADC logic, supplemented by grouping switches to achieve 2bit / 3bit splittable function. Under different switch combinations, 2bit ADC can be achieved by COMP0, COMP1, COMP2 and a 2bit logic module (COMP4, COMP5, COMP6 and another 2bit logic module can achieve another 2bit ADC), or a 3bit ADC can be achieved by all comparator modules and a 3bit logic module. The comparator is a conventional dynamic latch comparator, which starts comparison when the rising edge of clock CLK0 / CLK1 / CLK2 comes, and the drain voltage of the input NMOS transistor drops rapidly (the drain voltage of the input transistor is the power supply voltage in the reset state) at the moment after the comparison action occurs, which is coupled to the input through the gate-drain parasitic capacitor of the input NMOS, affecting the input voltage, which is called kickback noise. To alleviate the impact of the above phenomenon, the positive and negative input terminals of the comparator are respectively provided with sampling switches and balance capacitors C BANL , so as to achieve correct comparison results and optimize the kickback noise problem in the comparator module.

[0050] Further, Figure 5 For the analog-digital conversion circuit, according to the timing of one of the two 2bit ADCs, SAM0 and CLK0 are Figure 4 the clock control signals of the input sampling switches of COMP0, COMP1 and COMP2, the clock period is 2ns, COMP2_VIP and COMP2_VIN are the positive and negative input signals of COMP2 respectively, and COMP2_OUT is the output of COMP2. COMP0 and COMP1 are similar to the above. The negative input of the three comparators is the sampling signal of the node ① voltage in the circuit of Figure 1 , and the positive input is the sampling signal of the node ① voltage in the circuit of

[0051] Alternatively, in some embodiments, as shown in Figure 3 , the above-mentioned RRAM multi-bit storage fast reading circuit 10 further comprises a bit line driving unit (such as the bit line driving unit 401 connected to the control end of the first RRAM in Figure 3 ) connected to the control end of each RRAM and a word line driving unit (such as the word line driving unit 501 connected to the transmission end of the first RRAM in Figure 3 ) connected to the transmission end of each RRAM, wherein the bit line driving unit and the word line driving unit determine the target RRAM from at least one RRAM based on a reading request.

[0052] Optionally, in some embodiments, the bit line driving unit comprises one or more bit line drivers.

[0053] Optionally, in some embodiments, the number of bit line drivers is equal to the number of RRAM conductance value reading circuits.

[0054] Optionally, in some embodiments, the word line driving unit comprises one or more word line drivers.

[0055] Optionally, in some embodiments, the number of word line drivers is equal to the number of corresponding RRAMs of the RRAM conductance value reading circuits.

[0056] The bit line driving unit is mainly used to control the bit lines (BL) in the RRAM array, which provides the necessary voltage or current signals to the bit lines to achieve the selection, programming, erasing or reading operations of the RRAM cells; the word line driving unit is responsible for controlling the word lines (WL) in the RRAM array, whose main task is to select the RRAM cells on a specific row for operation.

[0057] Specifically, the bit line driving unit is connected to the control end of each RRAM, responsible for applying the necessary voltage or current signals to the RRAM cell during reading operation; during the reading process, the bit line driving unit transmits the reading request signal to the RRAM cell and receives the response signal from the RRAM cell, which contains the stored data information; by analyzing the response signal, the bit line driving unit can extract the data stored in the RRAM cell and convert it into a format that can be recognized by the computer. The word line driving unit is connected to the transmission end of each RRAM, responsible for determining and selecting the target RRAM cell according to the reading request, usually by applying voltage or current signals to a specific word line to activate the RRAM cell connected to it; once the target RRAM cell is selected, the word line driving unit is responsible for transmitting the data stored in the cell to the external circuit or processor through the transmission end; the word line driving unit is also responsible for coordinating and controlling other circuit components to ensure the correctness and efficiency of the reading operation.

[0058] Further, the bit line driver and the word line driver can quickly and accurately locate the target RRAM cell, speeding up the reading and writing speed; the simultaneous work of multiple bit line drivers and word line drivers supports multiple RRAM cells to be accessed within the same time period, significantly increasing the throughput of the system and optimizing resource utilization; reducing the signal interference that may be introduced by multiplexing, ensuring the accuracy of each reading and writing operation and reducing the error rate.

[0059] Optionally, in some embodiments, one end of the balancing capacitor is connected to one end of the sampling switch through the pre-charge node, the other end of the balancing capacitor is connected to the ground node, and the other end of the sampling switch is connected to the pre-charge voltage output node; the switch element, the first end of the switch element is connected to the one end of the balancing capacitor and the one end of the sampling switch through the pre-charge node respectively, and the second end of the switch element is connected to the corresponding RRAM.

[0060] It can be understood that, in the pre-charge phase, the balancing capacitor receives the pre-charge voltage through the pre-charge node and stores the electric energy, which helps to provide a stable voltage source in the subsequent data reading or writing process; the balancing capacitor can also filter out high-frequency noise and fluctuations in the circuit, ensuring that the voltage provided to the RRAM is stable and reliable, which helps to protect the RRAM from the influence of voltage fluctuations. In the data reading process, the sampling switch is closed according to the control signal, and the data in the RRAM is transmitted to the external circuit or processor through the pre-charge voltage output node for processing; during the non-sampling period, the sampling switch remains in an open state to isolate the RRAM from the external circuit, preventing data leakage or external interference. The switch element is used to connect the balancing capacitor, the sampling switch and the corresponding RRAM, realizing flexible configuration and selection of the circuit; in the pre-charge phase, the switch element is closed to allow the pre-charge voltage to enter the balancing capacitor and the RRAM through the pre-charge node, preparing for subsequent data reading or writing operation.

[0061] Therefore, based on the fast reading method and the analog-digital conversion circuit proposed in the embodiments of the present application, the overall circuit implementation is given in cooperation with the RRAM array, as shown in Figure 3 The nodes ① and ② in the figure correspond to the corresponding nodes in Figure 1 Under the timing of Figure 2 and Figure 5 , the ADC can perform 2-bit analog-digital conversion on two rows of BL or only 3-bit analog-digital conversion on one row of BL in one clock cycle. In the actual circuit, the ADC can be shared by multiple rows of BL, thereby saving area and reducing power consumption. Therefore, the embodiments of the present application realize fast reading of RRAM multi-bit storage, and are expected to provide help for further improving storage density and computing power density.

[0062] According to the RRAM multi-bit storage fast reading circuit provided in the embodiment of the present application, after receiving a reading request, a target RRAM is determined from at least one RRAM; after a sampling switch of a target RRAM conductance value reading circuit corresponding to the target RRAM is closed for a first preset time length, the sampling switch is opened, and the pre-charge node is discharged for a second preset time length; a voltage value of the pre-charge node is read by an analog-to-digital converter corresponding to the target RRAM conductance value reading circuit, and a current conductance state of the target RRAM is determined according to the voltage value of the pre-charge node, so that a multi-bit reading result is obtained according to the current conductance state. Thus, the problems of slow pre-charge speed and long reading period in the traditional reading mode are solved, the reading speed is improved, and the bandwidth and chip computing power are improved, so that multi-bit data is read out in a single period.

[0063] Secondly, the RRAM multi-bit storage fast reading method provided in the embodiment of the present application is described with reference to the accompanying drawings.

[0064] Figure 6 The flowchart of the RRAM multi-bit storage fast reading method of the embodiment of the present application.

[0065] In this embodiment, the RRAM multi-bit storage fast reading method adopts Figure 3 the RRAM multi-bit storage fast reading circuit shown in the embodiment.

[0066] As Figure 6 shown, the RRAM multi-bit storage fast reading method includes the following steps:

[0067] In step S601, it is determined whether a reading request is received.

[0068] In step S602, after receiving the reading request, a target RRAM is determined from at least one RRAM, and after a sampling switch of a target RRAM conductance value reading circuit corresponding to the target RRAM is closed for a first preset time length, the sampling switch is opened, and the pre-charge node is discharged for a second preset time length.

[0069] In step S603, a voltage value of the pre-charge node is read by an analog-to-digital converter corresponding to the target RRAM conductance value reading circuit, and a current conductance state of the target RRAM is determined according to the voltage value of the pre-charge node, so that a multi-bit reading result is obtained according to the current conductance state.

[0070] Optionally, in some embodiments, the reading request includes at least one of a 2bit reading request and a 3bit reading request.

[0071] It should be noted that the foregoing explanation and description of the RRAM multi-bit storage fast reading circuit embodiment also apply to the RRAM multi-bit storage fast reading method of this embodiment, which will not be described here.

[0072] According to the RRAM multi-bit storage fast reading circuit and method provided by the embodiment of the present application, it is determined whether a reading request is received, after the reading request is received, a target RRAM is determined from at least one RRAM, and after a first preset time length, the sampling switch of the target RRAM corresponding target RRAM conductance value reading circuit is closed, the sampling switch is opened, after a second preset time length, the voltage value of the pre-charge node is read by using the analog-to-digital converter corresponding to the target RRAM conductance value reading circuit, and according to the voltage value of the pre-charge node and the current conductance state of the target RRAM, a multi-bit reading result is obtained according to the current conductance state. Thus, the problems of slow pre-charge speed and long reading period in the traditional reading mode are solved, the reading speed is improved, and the bandwidth and chip computing power are improved, and multi-bit data is read out in a single cycle.

[0073] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the description of the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or N embodiments or examples in a suitable manner. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the specification and the features of the different embodiments or examples without contradiction.

[0074] In addition, the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include at least one feature. In the description of the present application, the meaning of "N" is at least two, such as two, three, etc., unless otherwise specifically limited.

[0075] Any process or method described in the flowchart or otherwise described herein can be understood as representing a module, a fragment or a part of code including one or more executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of the present application includes additional implementations in which the functions can be performed in an order other than that shown or discussed, including in a substantially simultaneous manner or in reverse order according to the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application belong.

[0076] It should be understood that portions of the application can be implemented in hardware, software, firmware, or combinations thereof. In the above embodiments, the N steps or methods can be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. As such, if implemented in hardware, and in another embodiment, any of the following technologies, known in the art, or their combinations can be used: discrete logic circuitry having logic gates for implementing logic functions on data signals, application specific integrated circuits having appropriate combinational logic gates, programmable gate arrays (PGA), field programmable gate arrays (FPGA), and the like.

[0077] Those skilled in the art can understand that all or part of the steps carried out by the above-mentioned embodiment methods can be completed by programs instructing related hardware, and the programs can be stored in a computer readable storage medium. When the program is executed, it includes one of the steps of the method embodiment or a combination thereof.

Claims

1. A fast read circuit for RRAM multi-bit storage, characterized in that, include: At least one RRAM conductance value reading circuit is provided, and at least one RRAM and an analog-to-digital converter are provided corresponding to each RRAM conductance value reading circuit. Each RRAM conductance value reading circuit includes a pre-charge node, a sampling switch, a switching element, and a balancing capacitor. Upon receiving a read request, the target RRAM is determined from the at least one RRAM; After the sampling switch of the target RRAM conductance value reading circuit corresponding to the target RRAM is closed for a first preset time, the sampling switch is opened, and after the pre-charge node is discharged for a second preset time; The voltage value of the pre-charge node is read using the analog-to-digital converter corresponding to the target RRAM conductance value reading circuit, and the current conductance state of the target RRAM is determined based on the voltage value of the pre-charge node, so as to obtain a multi-bit reading result based on the current conductance state; one end of the balancing capacitor is connected to one end of the sampling switch through the pre-charge node, the other end of the balancing capacitor is connected to the ground node, and the other end of the sampling switch is connected to the pre-charge voltage output node; the first end of the switch is connected to one end of the balancing capacitor and one end of the sampling switch through the pre-charge node, and the second end of the switch is connected to the corresponding RRAM.

2. The RRAM multi-bit storage fast read circuit according to claim 1, characterized in that, Each analog-to-digital converter includes: At least three comparator modules, each of which is connected to a corresponding RRAM conductance value reading circuit; A 2-bit logic module is used to obtain a 2-bit read result based on the outputs of two of the at least three comparator modules; The 3-bit logic module is used to obtain a 3-bit read result based on the output of all comparator modules.

3. The RRAM multi-bit storage fast read circuit according to claim 1, characterized in that, Also includes: A bit line driving unit connected to the control terminal of each RRAM and a word line driving unit connected to the transmission terminal of each RRAM, wherein, The bit line driver unit and the word line driver unit determine the target RRAM from the at least one RRAM based on the read request.

4. The RRAM multi-bit storage fast read circuit according to claim 1, characterized in that, The bit line driving unit includes one or more bit line drivers.

5. The RRAM multi-bit storage fast read circuit according to claim 4, characterized in that, The number of bit line drivers is equal to the number of RRAM conductance value read circuits.

6. The RRAM multi-bit storage fast read circuit according to claim 1, characterized in that, The word line drive unit includes one or more word line drivers.

7. The RRAM multi-bit storage fast read circuit according to claim 6, characterized in that, The number of word line drivers is equal to the number of RRAMs corresponding to the RRAM conductance value read circuit.

8. A method for fast reading of RRAM multi-bit storage, characterized in that, The method employs a fast read / write circuit for RRAM multi-bit storage as described in any one of claims 1-7, wherein the method comprises the following steps: Determine if a read request has been received; After receiving the read request, a target RRAM is determined from the at least one RRAM, and the sampling switch of the target RRAM conductance value reading circuit corresponding to the target RRAM is closed for a first preset time, and then the sampling switch is opened, and the circuit is discharged through the pre-charge node for a second preset time. The voltage value of the pre-charge node is read using the analog-to-digital converter corresponding to the target RRAM conductance value reading circuit, and the current conductance state of the target RRAM is determined based on the voltage value of the pre-charge node, so as to obtain a multi-bit reading result based on the current conductance state; one end of the balancing capacitor is connected to one end of the sampling switch through the pre-charge node, the other end of the balancing capacitor is connected to the ground node, and the other end of the sampling switch is connected to the pre-charge voltage output node; the first end of the switch is connected to one end of the balancing capacitor and one end of the sampling switch through the pre-charge node, and the second end of the switch is connected to the corresponding RRAM.

9. The method according to claim 8, characterized in that, The read request includes at least one of a 2-bit read request and a 3-bit read request.

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