Storage chip testing method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention discloses a memory chip testing method and device, electronic equipment and a storage medium, and relates to the technical field of chip test.The method comprises the steps that in the current read / write period, n read / write clock signals are input into a memory chip, the memory chip is controlled to conduct read / write operation, and n is an integer larger than 1; acquiring first read / write data output / input by the memory chip under the first effective clock edge of the n read / write clock signals; acquiring second read / write data output / input by the memory chip under other effective clock edges of the n read / write clock signals, wherein the second read / write data is determined according to the first read / write data; and verifying the qualification of the storage chip according to the first read data, the second read data, the first write data and the second write data. The embodiment of the invention can be applied to a memory chip test scene so as to solve the problems of low test efficiency and poor reliability of the memory chip under the highest clock frequency in the prior art.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and in particular to a storage chip testing method, device, electronic equipment and storage medium. Background Art

[0002] Memory chips play a vital role in modern electronic devices. The speed and accuracy of data reading and writing are key indicators for measuring the performance of memory chips. Fast and accurate data reading and writing capabilities can ensure the efficient operation of electronic devices and meet users' needs for data storage and processing. In the production process of memory chips, strict testing is an indispensable link. Through testing, memory chips with substandard reading and writing speeds can be screened out in advance, ensuring product quality, reducing production costs, and improving production efficiency.

[0003] There are two main types of memory chip testing schemes. The first type of scheme is to read and write data at a lower clock frequency. Although this scheme can realize the operation of any data, it cannot accurately evaluate the performance of the memory chip at the highest clock frequency. The second type of scheme is to perform data read and write operations at the highest clock frequency. At this time, the tester will input multiple clock signals to the memory chip in one access cycle, so that the chip can input or output data multiple times during this period. However, this scheme also has some problems: On the one hand, since the test machine can only record one data interaction for verification in one access cycle, some data may be missed or cannot be clearly defined. In order to solve the problem of missing data, it is usually necessary to repeatedly read the same data to complete the entire test process, which significantly increases the time required for testing. On the other hand, due to the mismatch between the data processing speeds of the test machine and the memory chip, data may not be written. Summary of the invention

[0004] In view of this, embodiments of the present invention provide a memory chip testing method, device, electronic device and storage medium to solve the problems of low efficiency and poor reliability of memory chip testing at the highest clock frequency in the prior art.

[0005] In a first aspect, an embodiment of the present invention provides a memory chip testing method, which is applied to a testing machine and includes: In the current write cycle, n write clock signals are input to the memory chip to control the memory chip to perform a write operation, where n is an integer greater than 1; Acquire first write data input by the memory chip at a first valid clock edge of the n write clock signals; Acquire second write data input by the memory chip determined according to the first write data at other valid clock edges of the n write clock signals; In the current read cycle, n read clock signals are input to the memory chip to control the memory chip to perform a read operation; Acquire first read data output by the memory chip at the first valid clock edge of the n read clock signals; Acquire second read data output by the storage chip at other valid clock edges of the n read clock signals determined according to the first read data; The qualification of the memory chip is verified according to the first write data, the second write data, the first read data and the second read data.

[0006] Furthermore, the step of obtaining the first write data input by the storage chip at the first valid clock edge of the n write clock signals includes: Before inputting the first valid clock edge of the n write clock signals, acquiring data to be subsequently input by the storage chip under the triggering of the valid clock edge; and using the acquisition result as the first write data; The obtaining of the first read data output by the memory chip at the first valid clock edge of the n read clock signals comprises: After the first effective clock edge among the n read clock signals is input, the data output by the memory chip triggered by the effective clock edge is read through the output port of the memory chip; and the read result is used as the first read data.

[0007] Further, the acquiring of second write data input by the storage chip determined according to the first write data at other valid clock edges of the n write clock signals includes: After obtaining the first write data and before inputting other valid clock edges of the n write clock signals, obtaining data to be subsequently input by the storage chip under the triggering of the valid clock edge, wherein the data is determined according to the first write data; and using the obtained result as the second write data; The obtaining of second read data output by the storage chip determined according to the first read data at other valid clock edges of the n read clock signals comprises: After the first read data is obtained, the data output by the storage chip under other valid clock edges is determined according to the first read data; and the determination result is used as the second read data.

[0008] Furthermore, the method further comprises: Invert the first write data and use it as the second write data input to the memory chip at the odd-numbered other valid clock edges; use the first write data as the second write data input to the memory chip at the even-numbered other valid clock edges; or The first read data is inverted as the second read data output by the memory chip at the odd-numbered other valid clock edges; the first read data is used as the second read data output by the memory chip at the even-numbered other valid clock edges.

[0009] Further, verifying the eligibility of the memory chip according to the first write data, the second write data, the first read data, and the second read data includes: comparing the first read data with the first write data; comparing the second read data with the second write data; According to the data comparison result, it is determined whether the memory chip is qualified.

[0010] Furthermore, the method further comprises: Obtaining the number of access cycles required to complete an access operation of a data unit under the condition that n access clock signals are input in each access cycle; For each access cycle, trigger the input of n access clock signals to the memory chip in the current access cycle to control the memory chip to perform access operations.

[0011] Further, the obtaining of the number of access cycles required to complete the access operation of one data unit under the condition that n access clock signals are input in each access cycle includes: Obtaining access parameters supported by the memory chip: data bit width and clock edge type; According to the acquired access parameters, the number of access cycles required to complete the access operation of one data unit under the condition that n access clock signals are input in each access cycle is determined.

[0012] In a second aspect, an embodiment of the present invention provides a memory chip testing device, which is applied to a testing machine, and the device includes: A data writing unit, used to input n write clock signals to the memory chip in the current write cycle to control the memory chip to perform a write operation, wherein n is an integer greater than 1; A first write data acquisition unit, used for acquiring first write data input by the memory chip under the first valid clock edge of the n write clock signals; A second write data acquisition unit, used for acquiring second write data input by the storage chip at other valid clock edges of the n write clock signals determined according to the first write data; A data reading unit, used to input n read clock signals to the memory chip in the current read cycle, and control the memory chip to perform a read operation; A first read data acquisition unit, used for acquiring first read data output by the memory chip at the first valid clock edge of the n read clock signals; A second read data acquisition unit, used for acquiring second read data output by the storage chip at other valid clock edges of the n read clock signals determined according to the first read data; A chip verification unit is used to verify the qualification of the storage chip according to the first write data, the second write data, the first read data and the second read data.

[0013] Furthermore, the first write data acquisition unit is specifically used to: before inputting the first valid clock edge of the n write clock signals, acquire the data to be subsequently input by the storage chip under the triggering of the valid clock edge; and use the acquisition result as the first write data; The first read data acquisition unit is specifically used to: after inputting the first valid clock edge of the n read clock signals, read the data output by the storage chip under the triggering of the valid clock edge through the output port of the storage chip; and use the reading result as the first read data.

[0014] Further, the second write data acquisition unit is specifically used to: after obtaining the first write data and before inputting other valid clock edges of the n write clock signals, acquire data to be subsequently input by the storage chip under the triggering of the valid clock edge, wherein the data is determined according to the first write data; and use the acquisition result as the second write data; The second read data acquisition unit is specifically used to: after obtaining the first read data, determine the data output by the storage chip under other valid clock edges according to the first read data; and use the determination result as the second read data.

[0015] Furthermore, the device also includes a data determination unit, which is used to: Invert the first write data and use it as the second write data input to the memory chip at the odd-numbered other valid clock edges; use the first write data as the second write data input to the memory chip at the even-numbered other valid clock edges; or The first read data is inverted as the second read data output by the memory chip at the odd-numbered other valid clock edges; the first read data is used as the second read data output by the memory chip at the even-numbered other valid clock edges.

[0016] Furthermore, the chip verification unit is specifically used to: comparing the first read data with the first write data; comparing the second read data with the second write data; According to the data comparison result, it is determined whether the memory chip is qualified.

[0017] Furthermore, the device also includes a cycle number acquisition unit, which is used to: Obtaining the number of access cycles required to complete an access operation of a data unit under the condition that n access clock signals are input in each access cycle; For each access cycle, the data write unit is triggered to execute in the current write cycle, input n write clock signals to the storage chip, and control the storage chip to perform a write operation, or the data read unit is triggered to execute in the current read cycle, input n read clock signals to the storage chip, and control the storage chip to perform a read operation.

[0018] Furthermore, the cycle number acquisition unit is specifically used to: Obtaining access parameters supported by the memory chip: data bit width and clock edge type; According to the acquired access parameters, the number of access cycles required to complete the access operation of one data unit under the condition that n access clock signals are input in each access cycle is determined.

[0019] In a third aspect, an embodiment of the present invention provides an electronic device, comprising: a housing, a processor, a memory, a circuit board and a power supply circuit, wherein the circuit board is placed inside a space enclosed by the housing, and the processor and the memory are arranged on the circuit board; a power supply circuit for supplying power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to execute the memory chip testing method described in the first aspect above.

[0020] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the memory chip testing method described in the first aspect above.

[0021] The embodiment of the present invention specifically defines the format of the test data (read / write data) so that subsequent data can be determined from the previous data. In this way, after using the test machine to record the first read / write data output / input of the storage chip under the first valid clock edge of multiple read / write clock signals, the second read / write data output / input of the storage chip under other valid clock edges of multiple read / write clock signals can be automatically determined based on the data, thereby obtaining complete test data to verify the legitimacy of the storage chip. This method does not require repeated reading of the same data to complete the entire test process, greatly improving the test efficiency. At the same time, it can adapt well to the read and write rhythm of the storage chip, effectively avoiding the situation where data cannot be written due to the mismatch between the data processing speed of the test machine and the storage chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 A flowchart of a memory chip testing method provided in Embodiment 1 of the present invention; Figure 2 A flowchart of a memory chip testing method provided in Embodiment 2 of the present invention; Figure 3 A schematic diagram of the correspondence between the clock signal and each bit of the data unit in a conventional method and an improved method with a 1-bit data width and a single clock edge provided in Embodiment 3 of the present invention; Figure 4 A schematic diagram of the correspondence between the clock signal and each bit of the data unit in a conventional method and an improved method with a 1-bit data width and dual clock edges provided in Embodiment 3 of the present invention; Figure 5 A schematic diagram of the correspondence between the clock signal and each bit of the data unit in a conventional method and an improved method with a 2-bit data width and a single clock edge provided in Embodiment 3 of the present invention; Figure 6 A schematic diagram of the correspondence between the clock signal and each bit of the data unit in a conventional method and an improved method with a 2-bit data width and dual clock edges provided in Embodiment 3 of the present invention; Figure 7 A schematic diagram of the correspondence between the clock signal and each bit of the data unit in a conventional method and an improved method with a 4-bit data width and a single clock edge provided in Embodiment 3 of the present invention; Figure 8 A schematic diagram of the correspondence between the clock signal and each bit of the data unit in a conventional method and an improved method with a 4-bit data width and dual clock edges provided in Embodiment 3 of the present invention; Fig. 9 A schematic diagram of the structure of a memory chip testing device provided in Embodiment 4 of the present invention; Fig.10 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0025] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] The technical solution of the present invention is described in detail below through various embodiments.

[0027] Embodiment 1 This embodiment provides a memory chip testing method, which can be applied to a test machine and executed by a corresponding memory chip testing device on the test machine. Figure 1 The method specifically includes the following steps 101-107.

[0028] Step 101: In the current write cycle, n write clock signals are input to the memory chip to control the memory chip to perform a write operation.

[0029] Among them, the write clock signal is a periodic signal, which is a timing signal for synchronizing data write operations. n write clock signals refer to n write clock cycles (or clock pulses). The number and type of write clock signals determine how many times data write operations can be performed in one write cycle. One type of write clock signal is a single clock edge, and the rising edge is a valid clock edge when the clock pulse is a waveform from low level to high level, and the falling edge is a valid clock edge when the clock pulse is a waveform from high level to low level. When n write clock signals are input to the memory chip in one write cycle, there are n valid clock edges, and n data write operations can be performed on the memory chip. Another type of write clock signal is a dual clock edge, and the clock pulse is a waveform from high level to low level and then back to high level (or from low level to high level and then back to low level). Both the rising edge and the falling edge are valid clock edges. When n write clock signals are input to the memory chip in one write cycle, there are 2n valid clock edges, and 2n data write operations can be performed on the memory chip. When n=1, the clock frequency is the lowest, and in the embodiment of the present invention, n is an integer greater than 1.

[0030] In this embodiment, the memory chip can be accessed in a plurality of consecutive write cycles to write data to the memory chip. In each write cycle, n write clock signals are input to the memory chip, so that the memory chip enters a write state triggered by the first valid clock edge of the n write clock signals and then performs a write operation of the first write data, and enters a write state triggered by other valid clock edges of the n write clock signals and then performs a write operation of the second write data. For example, in each write cycle, two dual-clock edge type write clock signals are input to the memory chip, and the memory chip enters a write state triggered by the first valid clock edge (the rising edge of the first write clock signal) of the two write clock signals and performs a write operation on the first write data; enters a write state triggered by the second valid clock edge (the falling edge of the first write clock signal) of the two write clock signals and performs a write operation on the first second write data; enters a write state triggered by the third valid clock edge (the rising edge of the second write clock signal) of the two write clock signals and performs a write operation on the second second write data; and enters a write state triggered by the fourth valid clock edge (the falling edge of the second write clock signal) of the two write clock signals and performs a write operation on the third second write data.

[0031] Step 102: Acquire the first write data input by the memory chip at the first valid clock edge of the n write clock signals.

[0032] In this step, the first write data can be acquired in any one of two ways.

[0033] Method 1: before inputting the first valid clock edge among the n write clock signals in the current write cycle, obtaining the data to be input by the storage chip under the triggering of the valid clock edge; and using the obtained result as the first write data.

[0034] Method 2: After the first valid clock edge among the n write clock signals in the current write cycle is input and the memory chip enters the write state triggered by the valid clock edge, the data to be input by the memory chip at this time is obtained, and the obtained result is input to the memory chip as the first write data.

[0035] The operation of obtaining the data to be inputted by the memory chip may specifically be to generate the data to be inputted by the memory chip in real time, or may be to read the pre-generated data to be inputted by the memory chip. The first write data may be generated in a random manner.

[0036] Step 103 : Acquire second write data input by the storage chip determined according to the first write data at other valid clock edges of the n write clock signals.

[0037] In this step, the second write data can be acquired in any one of two ways.

[0038] Method 1: For each valid clock edge except the first valid clock edge, after obtaining the first write data and before inputting the other valid clock edges currently targeted among the n write clock signals, the data to be input by the storage chip under the trigger of the currently targeted valid clock edge can be obtained, and the obtained result can be used as the second write data.

[0039] Method 2: For each valid clock edge except the first valid clock edge, after obtaining the first write data and entering the current write cycle, input the other valid clock edges currently targeted among the n write clock signals, and after the storage chip enters the write state under the trigger of the currently targeted valid clock edge, obtain the data to be input by the storage chip at this time, and input the obtained result into the storage chip as the second write data.

[0040] The above-mentioned operation of obtaining the data to be input by the storage chip can specifically be real-time generation of the data to be input by the storage chip, or reading the pre-generated data to be input by the storage chip. In the current write cycle, there are as many second write data as there are valid clock edges other than the first valid clock edge among the n input write clock signals. Each second write data can be determined according to the first write data, for example, by performing a preset operation on the second write data to obtain each second write data. Preferably, the first write data is inverted as the second write data input by the storage chip at the other odd valid clock edges; the first write data is used as the second write data input by the storage chip at the other even valid clock edges.

[0041] The two methods in step 102 and the two methods in step 103 are different in the time node of obtaining the write data. Whether it is step 102 or step 103, method 1 is preferred for the following reasons: Prepare in advance: Get data before the input valid clock edge, allowing the system to complete data preparation before the clock signal arrives, ensuring that the data is more fully prepared; Reduced dependency: The timing of data acquisition does not depend on the triggering of the clock signal, which reduces the dependency on timing and helps improve the stability of the system; Reduced latency: By acquiring data in advance, latency can be reduced during data transmission, especially in high-frequency clock conditions, making overall read and write efficiency higher; Optimized data management: This approach allows designers to more flexibly manage the timing of data input, so that data input can be performed when conditions are more appropriate, which helps to handle complex logic or data flow situations; Better timing control: Since data acquisition is completed before the clock edge, the entire system is easier to control when facing timing requirements, reducing the risk of timing violations.

[0042] Step 104: In the current read cycle, n read clock signals are input to the memory chip to control the memory chip to perform a read operation.

[0043] Among them, the read clock signal is a periodic signal, which is a timing signal used to synchronize data reading operations. n read clock signals refer to n read clock cycles (or clock pulses). The number and type of read clock signals determine how many times data reading operations can be performed in one read cycle. One type of read clock signal is a single clock edge. When the clock pulse is a waveform from low level to high level, the rising edge is a valid clock edge. When the clock pulse is a waveform from high level to low level, the falling edge is a valid clock edge. When n read clock signals are input to the memory chip in one read cycle, there are n valid clock edges, and n data reading operations can be performed on the memory chip. Another type of read clock signal is a dual clock edge. The clock pulse is a waveform from high level to low level and then back to high level (or from low level to high level and then back to low level). Both the rising edge and the falling edge are valid clock edges. When n read clock signals are input to the memory chip in one read cycle, there are 2n valid clock edges, and 2n data reading operations can be performed on the memory chip.

[0044] In this embodiment, the memory chip can be accessed in a plurality of consecutive read cycles to read data from the memory chip. In each read cycle, n read clock signals are input to the memory chip, so that the memory chip enters a read state triggered by the first valid clock edge of the n read clock signals and then performs a read operation of the first read data, and enters a read state triggered by other valid clock edges of the n read clock signals and then performs a read operation of the second read data. For example, in each read cycle, two dual-clock edge type read clock signals are input to the memory chip, and the memory chip enters a read state triggered by the first valid clock edge (the rising edge of the first read clock signal) of the two read clock signals and performs a read operation on the first read data; enters a read state triggered by the second valid clock edge (the falling edge of the first read clock signal) of the two read clock signals and performs a read operation on the first second read data; enters a read state triggered by the third valid clock edge (the rising edge of the second read clock signal) of the two read clock signals and performs a read operation on the second second read data; and enters a read state triggered by the fourth valid clock edge (the falling edge of the second read clock signal) of the two read clock signals and performs a read operation on the third second read data.

[0045] For the convenience of testing, the read cycle is the same as the write cycle, and the read clock signal and the write clock signal waveform are the same.

[0046] Step 105 : Acquire the first read data output by the memory chip at the first valid clock edge of the n read clock signals.

[0047] In this step, after entering the current read cycle and inputting the first valid clock edge of the n read clock signals, the data output by the memory chip under the triggering of the valid clock edge can be read through the output port of the memory chip; the read result is used as the first read data. Therefore, the first read data is the data directly read from the actual physical output port of the memory chip.

[0048] Step 106 : Acquire second read data output by the storage chip determined according to the first read data at other valid clock edges of the n read clock signals.

[0049] In this step, for each valid clock edge other than the first valid clock edge: after obtaining the first read data, determine the data output by the storage chip under the other valid clock edge according to the first read data; and use the determination result as the second read data. In a specific implementation, for each valid clock edge other than the first valid clock edge, after obtaining the first read data and entering the current read cycle, input the other valid clock edge currently targeted among the n read clock signals, and after the storage chip enters the read state under the triggering of the current valid clock edge, determine the data output by the storage chip under the other valid clock edge according to the first read data; and use the determination result as the second read data.

[0050] Because the existing test machine can only obtain the first read data from the output port of the storage chip through data interaction with the storage chip in a read cycle, but cannot obtain the second read data. In this embodiment, a special read data format is specifically defined, and the second read data is associated with the first read data. On the basis of the known first read data, the second read data can be automatically determined according to the first read data and the associated relationship, and can be obtained specifically by calculating the first read data. Preferably, the first read data is inverted as the second read data output by the storage chip at the odd-numbered other valid clock edge; the first read data is used as the second read data output by the storage chip at the even-numbered other valid clock edge.

[0051] The operation mechanism of the second read / write data in the above preferred mode will cause the read / write data under adjacent valid clock edges in the same read / write cycle to be reversed, thereby requiring the memory chip to process different state data in a short time, increasing the workload and complexity of the memory chip. In this way, the performance of the memory chip under complex working conditions can be more comprehensively tested.

[0052] It should be noted that in the embodiments of the present invention, data read / write operations need to be performed under different clock edge triggers in different read / write cycles. The order in which data is read should be consistent with the order in which data is written. Specifically, when reading data, the data in the storage chip should be accessed in the order in which the data is written. This ensures the consistency and predictability of the data and avoids data confusion or errors caused by inconsistent order.

[0053] Step 107 : Verify the eligibility of the memory chip according to the first write data, the second write data, the first read data, and the second read data.

[0054] In this step, the qualification of the storage chip in terms of read and write correctness can be verified according to the acquisition results of the first write data, the second write data, the first read data, and the second read data. Specifically, the first write data and the first read data can be compared; the second write data and the second read data can be compared, and whether the storage chip is qualified can be judged according to the data comparison result. Specifically, if the first read data is equal to the first write data, it means that the first write data has been successfully stored and correctly read. The second read data is equal to the second write data, which means that the second write data has also been successfully stored and correctly read. If the first read data is equal to the first write data, and the second read data is equal to the second write data, it means that the storage chip is normal and can correctly save and read data. If any comparison is not equal, the storage chip may be defective and further testing or replacement is required. Of course, the first write data and the second write data can also be combined according to the read and write order to form merged write data; at the same time, the first read data and the second read data can be combined to form merged read data. Subsequently, by comparing the consistency of the merged write data and the merged read data, it is judged whether the storage chip is qualified in terms of read and write correctness.

[0055] Furthermore, the read / write time interval of the data can be calculated according to the time point when the first write data is written into the storage chip and the time point when the first read data is read from the storage chip, and the read / write speed eligibility of the storage chip can be verified accordingly. For example, if the time interval is within the expected read / write speed range, and the read / write time intervals of different data meet the preset relative stability condition, then the read / write speed of the storage chip can be determined to be qualified.

[0056] The technical solution provided in this embodiment has the following beneficial effects: Complete data acquisition: Although the existing test machine can only record the first read data and the first write data, the improved method of this embodiment uses a special data format to automatically derive the read / write data under other subsequent valid clock edges based on the first read / write data under a previous valid clock edge, thereby improving the data integrity and accuracy of the entire test process; Improve test efficiency: Allow multiple data interactions in the same cycle, reduce the need for repeated reading of single data, speed up testing, and improve work efficiency; Strong compatibility: This method can reuse the existing test machine to interact with the memory chip. It only needs to input multiple clock signals in the current access cycle, without replacing the test equipment, thus saving resources and costs. Comprehensive performance verification: By inputting multiple clock signals in one access cycle, the working conditions under high clock frequency are simulated; under this condition, the memory chip will be frequently read and written, so that its true performance and stability in a high-frequency environment can be fully evaluated, ensuring its reliability and effectiveness in actual applications.

[0057] Embodiment 2 This embodiment is based on the memory chip testing method provided in the above embodiment 1, and describes the memory chip testing under multiple cycles. Figure 2 , a memory chip testing method is applied to a testing machine, including the following steps 201-205.

[0058] Step 201: Obtain the number of write cycles required to complete a write operation of a data unit under the condition that n write clock signals are input in each write cycle.

[0059] In this embodiment, the memory chip can be accessed according to the access cycle, wherein the access can be reading or writing. The access parameters supported by the memory chip can be obtained in advance: data bit width W and clock edge type; according to the obtained access parameters, the number of write cycles M required to complete the write operation of a data unit under the condition of inputting n write clock signals in each write cycle is determined. Among them, n is still an integer greater than 1. The data unit can be a binary sequence, and the number of bits of the sequence should be a positive integer multiple of the data bit width W, set to k×W. Under the single clock edge type, the number of write cycles M= ; Under the dual clock edge type, the number of write cycles M= The following is an example.

[0060] Table 1 below shows the number of write cycles and write clock signals required to complete a write operation of a data unit of an 8-bit binary sequence under different access parameters in a traditional manner under the condition that one write clock signal is input in each write cycle.

[0061]

[0062] Table 2 below shows the number of write cycles and write clock signals required to complete a write operation of a data unit of an 8-bit binary sequence under different access parameters under the condition that two write clock signals are input in each write cycle in this embodiment.

[0063]

[0064] Step 202: For each write cycle, perform the following operations: In the current write cycle, n write clock signals are input to the memory chip to control the memory chip to perform a write operation; Acquire first write data input by the memory chip at the first valid clock edge of the n write clock signals; The second write data input by the memory chip determined according to the first write data at other valid clock edges of the n write clock signals is obtained.

[0065] This step is the same as steps 101-103 in the above-mentioned embodiment 1, and will not be repeated here.

[0066] Step 203: Obtain the number of read cycles required to complete a read operation of a data unit under the condition that n read clock signals are input in each read cycle.

[0067] As with the write cycle, the access parameters supported by the memory chip can be obtained in advance: data bit width and clock edge type; based on the obtained access parameters, the number of read cycles M required to complete the read operation of a data unit under the condition of inputting n read clock signals in each read cycle is determined. The calculation method of the number of read cycles is the same as that of the number of write cycles, which will not be repeated here.

[0068] For the convenience of testing, the read cycle can be the same as the write cycle, and the read clock signal can have the same waveform as the write clock signal.

[0069] Step 204: For each read cycle, perform the following operations: In the current read cycle, n read clock signals are input to the memory chip to control the memory chip to perform a read operation; Acquire the first read data output by the memory chip at the first valid clock edge of the n read clock signals; Acquire second read data output by the storage chip determined according to the first read data at other valid clock edges of the n read clock signals.

[0070] This step is the same as steps 104-106 in the above-mentioned embodiment 1, and will not be described again here.

[0071] Step 205 : Verify the eligibility of the memory chip according to the first write data, the second write data, the first read data, and the second read data.

[0072] In this embodiment, in the read data operation of a data unit, the operation is divided into M read cycles. The tester can obtain a first read data and at least one second read data in each read cycle. The first read data and all the second read data obtained in the i-th read cycle are combined together to form the complete read data in the i-th read cycle. Similarly, the complete write data in the i-th write cycle can be formed. For each read cycle and the corresponding write cycle, the qualification of the storage chip is verified according to the first write data, the second write data, the first read data and the second read data in the targeted cycle. Of course, all the read data in M ​​read cycles can also be combined to finally obtain the complete read data of a data unit. All the write data in M ​​write cycles are combined to finally obtain the complete write data of a data unit. Then, the qualification of the storage chip is verified according to the complete write data and the complete read data of a data unit.

[0073] Embodiment 3 This embodiment provides a preferred embodiment based on all the above embodiments. This embodiment provides a memory chip testing method, which includes two stages: a preparation stage and a testing stage, as described below.

[0074] 1. Preparation 1. The tester determines the number of access cycles M and the total number of clock signals N required to complete a read or write operation of a data unit under the condition of a set clock frequency.

[0075] Among them, the access parameters supported by the memory chip are obtained: data bit width W and clock edge type; according to the obtained results, the M and N are determined. Under the set clock frequency, the test machine will input n clock signals to the memory chip every cycle, and n is an integer greater than 1. In this embodiment, the read operation and the write operation use the same cycle (referred to as the access cycle), and the read cycle and the write cycle are no longer distinguished. In addition, the clock signals are also completely consistent, and the read clock signal and the write clock signal are no longer distinguished. Therefore, whether performing a read operation or a write operation, the required number of access cycles M and the total number of clock signals N are the same. For the calculation of the number of access cycles M, please refer to the relevant description in the above-mentioned embodiment 2, which will not be repeated here. The total number of clock signals N refers to the number of clock signals that need to be input to the memory chip within the M access cycles, N=M×n.

[0076] 2. The test machine obtains multiple data units required for the pre-generated test.

[0077] In this embodiment, each data unit is a binary sequence with the same number of bits, and the number of bits should be a positive integer multiple of the data width W, set to k×W. For example, when the data width is 1, 2 or 4 bits, each 8-bit binary sequence is a data unit. The data unit can be automatically generated by the test machine in the following manner: (1) Generate M bit sequences, each of which uniquely corresponds to an access cycle; wherein the generation of the i-th bit sequence includes: ① Randomly generate a first bit subsequence of a data bit width W, which is used for reading and writing under the first valid clock edge in the i-th access cycle among M access cycles; ② Based on the first bit subsequence, generate at least one second bit subsequence with a data bit width W, where: a. Single clock edge type Performing operations on the first bit sequence to generate a second bit subsequence of n-1 data bit width W; b. Dual clock edge type Performing operations on the first bit sequence to generate a second bit subsequence of 2n-1 data bit width W; In a and b above, each second bit subsequence is used for reading and writing at other valid clock edges in the i-th access cycle in M ​​access cycles; one second bit subsequence uniquely corresponds to one other valid clock edge after the first clock edge; ③ Combine the first bit subsequence and each second bit subsequence to obtain the i-th bit sequence; The first bit subsequence and each second bit subsequence can be combined in order from high to low (or from low to high) to obtain the i-th bit sequence. The first bit subsequence is obtained by negating the first bit subsequence, and the adjacent second bit subsequences are the negations of each other. For example, the first bit subsequence is 01, and there are 3 second bit subsequences, namely: 10, 01, 10, and the i-th bit sequence is: 01100110.

[0078] (2) According to the order of access cycles, each bit sequence is combined to obtain m / k or 2m / k data units. Specifically, in the case of a single clock edge type, m / k is a positive integer greater than or equal to 1, wherein when m / k is a positive integer greater than 1, m / k identical data units are obtained; in the case of a dual clock edge type, 2m / k is a positive integer greater than or equal to 1, wherein when 2m / k is a positive integer greater than 1, 2m / k identical data units are obtained. Among them, m can be a combination of n of multiple access cycles corresponding to multiple data units.

[0079] In the above, whether it is the combination order between subsequences within each bit sequence or the combination order between each bit sequence, it depends on the start bit of the read and write operation. If the read and write operation starts from the high bit first, the combination order from the high bit to the low bit is adopted. If the read and write operation starts from the low bit first, the combination order from the low bit to the high bit is adopted.

[0080] The following examples illustrate this.

[0081] See also Figure 3 , it is known that: the data unit is an 8-bit binary sequence, the data bit width supported by the memory chip is 1, and the clock edge type is a single clock edge (assuming the rising edge is valid); then: 1. In the traditional method, one clock signal is input to the memory chip in each access cycle, and eight access cycles and eight clock signals are required to complete a read or write operation of a data unit; The 8-bit binary sequence of the data unit is divided into 8 segments, in order from high to low, where: The first segment is the 8th bit (bit7), which is used for: reading and writing at the rising edge of an input clock signal in the first access cycle among 8 access cycles; The second segment is the 7th bit (bit6), which is used for: reading and writing at the rising edge of an input clock signal in the second access cycle among 8 access cycles; And so on; 2. In this embodiment, two clock signals are input to the memory chip in each access cycle, and four access cycles and eight clock signals are required to complete a read operation or a write operation of a data unit; The 8-bit binary sequence of the data unit is divided into 4 segments, in order from high to low, where: The first segment consists of a first bit subsequence and a second bit subsequence, which are: the 8th bit (bit7), which is used for reading and writing at the rising edge of the first input clock signal in the first access cycle; the 7th bit (bit6), which is used for reading and writing at the rising edge of the second input clock signal in the first access cycle, and this bit is the inversion of the 8th bit (bit7); The second segment consists of a first bit subsequence and a second bit subsequence, which are: the sixth bit (bit5), which is used for reading and writing at the rising edge of the first input clock signal in the second access cycle; the fifth bit (bit4), which is used for reading and writing at the rising edge of the second input clock signal in the second access cycle, and this bit is the inversion of the sixth bit (bit5); The third segment consists of a first bit subsequence and a second bit subsequence, which are: the fourth bit (bit3), which is used for reading and writing at the rising edge of the first input clock signal in the third access cycle; the third bit (bit2), which is used for reading and writing at the rising edge of the second input clock signal in the third access cycle, and this bit is the inversion of the fourth bit (bit3); The fourth segment consists of a first bit subsequence and a second bit subsequence, which are: the second bit (bit1), used for reading and writing at the rising edge of the first input clock signal in the fourth access cycle; the first bit (bit0), used for reading and writing at the rising edge of the second input clock signal in the fourth access cycle, and this bit is the inverse of the second bit (bit1).

[0082] See also Figure 4 , it is known that: the data unit is an 8-bit binary sequence, the data bit width supported by the memory chip is 1, and the clock edge type is a dual clock edge (both the rising edge and the falling edge are valid); then: 1. In the traditional method, one clock signal is input to the memory chip every two access cycles, and it takes eight access cycles and four clock signals to complete a read or write operation of a data unit; The 8-bit binary sequence of the data unit is divided into 8 segments, in order from high to low, where: The first segment is the 8th bit (bit7), which is used for: reading and writing at the rising edge of the input clock signal a in the first access cycle of 8 access cycles; The second segment is the 7th bit (bit6), which is used for: reading and writing at the falling edge of the input clock signal a in the second access cycle among the 8 access cycles; The third segment is the sixth bit (bit 5), which is used for: reading and writing at the rising edge of the input clock signal b in the third access cycle among the eight access cycles; The fourth segment is the fifth bit (bit4), which is used for: reading and writing at the falling edge of the input clock signal b in the fourth access cycle among the eight access cycles; And so on; 2. In this embodiment, two clock signals are input to the memory chip in each access cycle, and two access cycles and four clock signals are required to complete a read operation or a write operation of a data unit; The 8-bit binary sequence of the data unit is divided into 2 segments, in order from high to low, where: (1) The first segment consists of one first bit subsequence and three second bit subsequences, which are: The 8th bit (bit7) is used for reading and writing at the rising edge of the first input clock signal in the first access cycle; The 7th bit (bit6) is used for reading and writing at the falling edge of the first input clock signal in the first access cycle. This bit is the inversion of the 8th bit (bit7); The sixth bit (bit5) is used for reading and writing at the rising edge of the second clock signal input in the first access cycle. This bit is the inverse of the seventh bit (bit6), that is, the eighth bit (bit7); The fifth bit (bit4) is used for reading and writing at the falling edge of the second input clock signal in the first access cycle. This bit is the inversion of the sixth bit (bit5), that is, the inversion of the eighth bit (bit7); (2) The second segment consists of one first bit subsequence and three second bit subsequences, which are: The fourth bit (bit 3) is used for reading and writing at the rising edge of the first input clock signal in the second access cycle; The third bit (bit2) is used for reading and writing at the falling edge of the first input clock signal in the second access cycle. This bit is the inversion of the fourth bit (bit3); The second bit (bit1) is used for reading and writing at the rising edge of the second input clock signal in the second access cycle. This bit is the inverse of the third bit (bit2), that is, the fourth bit (bit3); The first bit (bit0) is used for reading and writing at the falling edge of the second input clock signal in the second access cycle. This bit is the inversion of the second bit (bit1), that is, the inversion of the fourth bit (bit3).

[0083] See also Figure 5 , it is known that: the data unit is an 8-bit binary sequence, the data bit width supported by the memory chip is 2, and the clock edge type is a single clock edge (assuming the rising edge is valid); then: 1. In the traditional method, one clock signal is input to the memory chip in each access cycle, and it takes four access cycles and four clock signals to complete a read or write operation of a data unit; The 8-bit binary sequence of the data unit is divided into 4 segments, in order from high to low, where: The first segment is bit 8 (bit 7) and bit 7 (bit 6), which are used for: reading and writing at the rising edge of an input clock signal in the first access cycle of four access cycles; The second segment is bit 6 (bit 5) and bit 5 (bit 4), which are used for: reading and writing at the rising edge of a clock signal input in the second access cycle of four access cycles; The third segment is the fourth bit (bit3) and the third bit (bit2), which are used for: reading and writing at the rising edge of a clock signal input in the third access cycle among four access cycles; The fourth segment is the second bit (bit1) and the first bit (bit0), which are used for: reading and writing at the rising edge of a clock signal input in the fourth access cycle among four access cycles; 2. In this embodiment, two clock signals are input to the memory chip in each access cycle, and two access cycles and four clock signals are required to complete a read operation or a write operation of a data unit; The 8-bit binary sequence of the data unit is divided into 2 segments, in order from high to low, where: (1) The first segment consists of a first bit subsequence and a second bit subsequence, which are: The first bit subsequence bit7bit6 composed of the 8th bit (bit7) and the 7th bit (bit6) is used for reading and writing at the rising edge of the first input clock signal in the first access cycle; The second bit subsequence composed of the sixth bit (bit5) and the fifth bit (bit4) is used for reading and writing at the rising edge of the second input clock signal in the first access cycle. This subsequence is the inverse of the first bit subsequence bit7bit6; (2) The second segment consists of a first bit subsequence and a second bit subsequence, which are: The first bit subsequence bit3bit2 composed of the fourth bit (bit3) and the third bit (bit2) is used for reading and writing at the rising edge of the first input clock signal in the second access cycle; The second bit subsequence composed of the second bit (bit1) and the first bit (bit0) is used for reading and writing at the rising edge of the second input clock signal in the second access cycle. This subsequence is the inverse of the first bit subsequence bit3bit2.

[0084] See also Figure 6 , it is known that: the data unit is an 8-bit binary sequence, the data bit width supported by the memory chip is 2, and the clock edge type is a dual clock edge (both the rising edge and the falling edge are valid); then: 1. In the traditional method, one clock signal is input to the memory chip every two access cycles, and it takes four access cycles and two clock signals to complete the read or write operation of one data unit; The 8-bit binary sequence of the data unit is divided into 4 segments, in order from high to low, where: The first segment is bit 8 (bit 7) and bit 7 (bit 6), which are used for: reading and writing at the rising edge of the input clock signal a in the first access cycle of four access cycles; The second segment is bit 6 (bit5) and bit 5 (bit4), which are used for: reading and writing at the falling edge of the input clock signal a in the second access cycle of the four access cycles; The third segment is the fourth bit (bit3) and the third bit (bit2), which are used for: reading and writing at the rising edge of the input clock signal b in the third access cycle among the four access cycles; The fourth segment is the second bit (bit1) and the first bit (bit0), which are used for: reading and writing at the falling edge of the input clock signal b in the fourth access cycle among the four access cycles; 2. In this embodiment, two clock signals are input to the memory chip in each access cycle, and one access cycle and two clock signals are required to complete a read operation or a write operation of a data unit; The 8-bit binary sequence of the data unit consists of only one segment, which consists of one first bit subsequence and three second bit subsequences, namely: The first bit subsequence bit7bit6 composed of the 8th bit (bit7) and the 7th bit (bit6) is used for reading and writing at the rising edge of the first input clock signal in one access cycle; The second bit subsequence bit5bit4 composed of the sixth bit (bit5) and the fifth bit (bit4) is used for reading and writing at the falling edge of the first input clock signal within one access cycle. This subsequence is the inverse of the first bit subsequence bit7bit6; The second bit subsequence bit3bit2 composed of the fourth bit (bit3) and the third bit (bit2) is used for reading and writing at the rising edge of the second input clock signal within one access cycle. This subsequence is the inverse of the second bit subsequence bit5bit4, that is, the first bit subsequence bit7bit6; The second bit subsequence bit1bit0 composed of the second bit (bit1) and the first bit (bit0) is used for reading and writing at the falling edge of the second input clock signal within one access cycle. This subsequence is the inversion of the second bit subsequence bit3bit2, that is, the inversion of the first bit subsequence bit7bit6.

[0085] See also Figure 7 , it is known that: the data unit is an 8-bit binary sequence, the data bit width supported by the memory chip is 4, and the clock edge type is a single clock edge (assuming the rising edge is valid); then: 1. In the traditional method, one clock signal is input to the memory chip in each access cycle, and two access cycles and two clock signals are required to complete a read or write operation of a data unit; The 8-bit binary sequence of the data unit is divided into 2 segments, in order from high to low, where: The first segment consists of the 8th bit (bit7), the 7th bit (bit6), the 6th bit (bit5) and the 5th bit (bit4), and is used for: reading and writing at the rising edge of an input clock signal in the first access cycle of two access cycles; The first segment consists of the 4th bit (bit3), the 3rd bit (bit2), the 2nd bit (bit1) and the 1st bit (bit0), and is used for: reading and writing at the rising edge of an input clock signal in the second access cycle of two access cycles; 2. In this embodiment, two clock signals are input to the memory chip in each access cycle, and one access cycle and two clock signals are required to complete a read operation or a write operation of a data unit; The 8-bit binary sequence of the data unit is only one segment, consisting of one first bit subsequence and one second bit subsequence, respectively: The first bit subsequence bit7bit6 bit5bit4 consisting of the 8th bit (bit7), the 7th bit (bit6), the 6th bit (bit5) and the 5th bit (bit4) is used for reading and writing at the rising edge of the first input clock signal in one access cycle; The first bit subsequence bit3bit2 bit1bit0 composed of the 4th bit (bit3), the 3rd bit (bit2), the 2nd bit (bit1) and the 1st bit (bit0) is used for reading and writing at the rising edge of the second input clock signal within one access cycle. This subsequence is the inverse of the first bit subsequence bit7bit6 bit5bit4.

[0086] See also Figure 8 , it is known that: the data unit is an 8-bit binary sequence, the data bit width supported by the memory chip is 4, and the clock edge type is a dual clock edge (both the rising edge and the falling edge are valid); then: 1. In the traditional method, a clock signal is input to the memory chip every two access cycles, and it takes two access cycles and one clock signal to complete a read or write operation of a data unit; The 8-bit binary sequence of the data unit is divided into 2 segments, in order from high to low, where: The first segment consists of the 8th bit (bit7), the 7th bit (bit6), the 6th bit (bit5) and the 5th bit (bit4), which are used for reading and writing at the rising edge of the input clock signal a in the first access cycle; The second segment consists of the 4th bit (bit3), the 3rd bit (bit2), the 2nd bit (bit1) and the 1st bit (bit0), and is used for reading and writing at the falling edge of the input clock signal a in the first access cycle; 2. In this embodiment, two clock signals are input to the memory chip in each access cycle, and one access cycle and two clock signals are required to complete a read operation or a write operation of a data unit; in this mode, the data unit will be read and written twice under two clock signals; The 8-bit binary sequence of the data unit read and written twice constitutes a 16-bit binary sequence, which is only one segment, consisting of one first bit subsequence and three second bit subsequences, respectively: The first bit subsequence bit7bit6 bit5bit4 consisting of the 8th bit (bit7), the 7th bit (bit6), the 6th bit (bit5) and the 5th bit (bit4) of the first read / write data unit is used for reading and writing at the rising edge of the first input clock signal a within one access cycle; The second bit subsequence bit3bit2 bit1bit0 composed of the 4th bit (bit3), the 3rd bit (bit2), the 2nd bit (bit1) and the 1st bit (bit0) of the first read / write data unit is used for reading and writing at the falling edge of the first input clock signal a within one access cycle. This subsequence is the inverse of the first bit subsequence bit7bit6 bit5bit4; The second bit subsequence bit7bit6 bit5bit4 composed of the 8th bit (bit7), the 7th bit (bit6), the 6th bit (bit5) and the 5th bit (bit4) of the second read / write data unit is used for reading and writing at the rising edge of the second input clock signal b within one access cycle. This subsequence is the inversion of the second bit subsequence bit3bit2 bit1bit0, that is, the first bit subsequence bit7bit6 bit5bit4; The second bit subsequence bit3bit2 bit1bit0 composed of the 4th bit (bit3), the 3rd bit (bit2), the 2nd bit (bit1) and the 1st bit (bit0) of the second read / write data unit is used for reading and writing at the falling edges of the two input clock signals b within one access cycle. This subsequence is the inversion of the second bit subsequence bit7bit6 bit5bit4.

[0087] 2. Testing Phase 1. Write data For each data unit, M access cycles are used to complete the writing of the data unit. Specifically, in each access cycle: ① Obtain a pre-generated bit sequence corresponding to the current access cycle, use the first bit subsequence therein as the first write data, and use each second bit subsequence as the second write data; ② Input n clock signals to the memory chip to control the memory chip to perform write operations, including: After the memory chip enters a write state under the triggering of the first valid clock edge among the n write clock signals, the tester writes the first write data into the memory chip; After the memory chip enters the write state under the triggering of other valid clock edges among the n write clock signals, the tester writes the second write data into the memory chip.

[0088] Among them, in the case of a single clock edge, the number of other valid clock edges is n-1, and these other valid clock edges correspond one by one to the n-1 second bit subsequences in the bit sequence corresponding to the current access cycle; as each other valid clock edge is triggered successively, one second bit subsequence in the n-1 second bit subsequences is taken in turn according to the combination order as the corresponding second write data.

[0089] Similarly, in the case of double clock edges, the number of other valid clock edges is 2n-1, and these other valid clock edges correspond one-to-one to the 2n-1 second bit subsequences in the bit sequence corresponding to the current access cycle; as each other valid clock edge is triggered successively, one second bit subsequence in the 2n-1 second bit subsequences is taken in turn according to the combination order as the corresponding second write data.

[0090] 2. Read data For each data unit, M access cycles are used to complete the reading of the data unit. Specifically, in each access cycle: Input n read clock signals to the memory chip to control the memory chip to perform a read operation, where: After the memory chip enters the read state under the triggering of the first effective clock edge among the n clock signals, the tester reads the data output by the memory chip under the effective clock edge through the output port of the memory chip, and uses the read result as the first read data; After the memory chip enters the read state triggered by other valid clock edges among the n clock signals, the tester determines the data output by the memory chip under the other valid clock edges according to the first read data; and uses the determination result as the second read data.

[0091] If the current other valid clock edge is the odd number among all other valid clock edges, the first read data is inverted to obtain the data output by the memory chip under the current other valid clock edge. If the current other valid clock edge is the even number among all other valid clock edges, the first read data is used as the data output by the memory chip under the current other valid clock edge.

[0092] 3. Data comparison After executing the above steps 1 and 2, the write data of each data unit and its corresponding read data can be obtained. The tester will compare the consistency of the write data of each data unit and its corresponding read data one by one to determine whether the memory chip is qualified in this test.

[0093] Embodiment 5 This embodiment provides a memory chip testing device, which can be applied to a tester to execute the memory chip testing method described in the embodiment of the present invention, and can be implemented by software and / or hardware. Fig. 9 , the device specifically includes the following units: The data writing unit 901 is used to input n write clock signals to the memory chip in the current write cycle to control the memory chip to perform a write operation, where n is an integer greater than 1; A first write data acquisition unit 902 is used to acquire first write data input by the memory chip under the first valid clock edge of the n write clock signals; A second write data acquisition unit 903 is used to acquire second write data input by the storage chip at other valid clock edges of the n write clock signals determined according to the first write data; The data reading unit 904 is used to input n read clock signals to the memory chip in the current read cycle to control the memory chip to perform a read operation; A first read data acquisition unit 905, configured to acquire first read data output by the memory chip at the first valid clock edge of the n read clock signals; A second read data acquisition unit 906, configured to acquire second read data output by the storage chip at other valid clock edges of the n read clock signals determined according to the first read data; The chip verification unit 907 is used to verify the qualification of the storage chip according to the first write data, the second write data, the first read data and the second read data.

[0094] The memory chip testing device in this embodiment can implement the memory chip testing method described in any of the aforementioned embodiments, and its implementation principles and corresponding technical effects are basically the same, which will not be repeated here.

[0095] Exemplarily, the first write data acquisition unit 902 is specifically configured to: Before inputting the first valid clock edge of the n write clock signals, acquiring data to be subsequently input by the storage chip under the triggering of the valid clock edge; and using the acquisition result as the first write data; The first read data acquisition unit 905 is specifically used to: after inputting the first valid clock edge of the n read clock signals, read the data output by the storage chip under the triggering of the valid clock edge through the output port of the storage chip; and use the read result as the first read data.

[0096] Exemplarily, the second write data acquiring unit 903 is specifically configured to: After obtaining the first write data and before inputting other valid clock edges of the n write clock signals, obtaining data to be subsequently input by the storage chip under the triggering of the valid clock edge, wherein the data is determined according to the first write data; and using the obtained result as the second write data; The second read data acquisition unit 906 is specifically used to: after obtaining the first read data, determine the data output by the storage chip under other valid clock edges according to the first read data; and use the determination result as the second read data.

[0097] Exemplarily, the memory chip test device in this embodiment further includes a data determination unit 908, which is used to: invert the first write data as the second write data input by the memory chip at the odd-numbered other valid clock edges; use the first write data as the second write data input by the memory chip at the even-numbered other valid clock edges; or The first read data is inverted as the second read data output by the memory chip at the odd-numbered other valid clock edges; the first read data is used as the second read data output by the memory chip at the even-numbered other valid clock edges.

[0098] Exemplarily, the chip verification unit 907 is specifically used to: compare the first read data with the first write data; compare the second read data with the second write data; and determine whether the memory chip is qualified according to the data comparison result.

[0099] Exemplarily, the device also includes a cycle number acquisition unit 900, which is used to: obtain the number of access cycles required to complete the access operation of a data unit under the condition that n access clock signals are input in each access cycle; for each access cycle, trigger the data write unit 901 to execute in the current write cycle, input n write clock signals to the storage chip, and control the storage chip to perform a write operation, or trigger the data read unit 904 to execute in the current read cycle, input n read clock signals to the storage chip, and control the storage chip to perform a read operation.

[0100] Exemplarily, the cycle number acquisition unit 900 is specifically used to: obtain the access parameters supported by the memory chip: data bit width and clock edge type; based on the obtained access parameters, determine the number of access cycles required to complete the access operation of a data unit under the condition of inputting n access clock signals in each access cycle.

[0101] Fig.10 FIG. 1 is a schematic diagram of the structure of an embodiment of an electronic device of the present invention, which can implement the process of the embodiment of the method of the present invention, such as Fig.10 As shown, the above-mentioned electronic device may include: a shell 1001, a processor 1002, a memory 1003, a circuit board 1004 and a power supply circuit 1005, wherein the circuit board 1004 is arranged inside the space enclosed by the shell 1001, and the processor 1002 and the memory 1003 are arranged on the circuit board 1004; the power supply circuit 1005 is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory 1003 is used to store executable program codes; the processor 1002 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 1003, so as to execute the storage chip testing method described in any of the above-mentioned embodiments.

[0102] The specific execution process of the above steps by the processor 1002 and the steps further executed by the processor 1002 by running the executable program code can be found in the description of the embodiment of the method of the present invention, which will not be repeated here.

[0103] This electronic device exists in many forms, including but not limited to: (1) Server: A device that provides computing services. The server consists of a processor, hard disk, memory, system bus, etc. The server has a similar architecture to general computers, but because it needs to provide highly reliable services, it has higher requirements in terms of processing power, stability, reliability, security, scalability, and manageability. (2) Other electronic equipment with data processing and communication functions.

[0104] Furthermore, an embodiment of the present invention also provides a computer-readable storage medium, which stores one or more programs. The one or more programs can be executed by one or more processors to implement the memory chip testing method described in the above embodiment.

[0105] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0106] In the embodiments of the present invention, the term "and / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0107] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0108] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0109] For the convenience of description, the above device is described by dividing the functions into various units / modules. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0110] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0111] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A memory chip testing method, characterized in that: Applied to a testing machine, the method comprises: In the current write cycle, n write clock signals are input to the memory chip to control the memory chip to perform a write operation, where n is an integer greater than 1; Acquire first write data input by the memory chip at a first valid clock edge of the n write clock signals; Acquire second write data input by the memory chip determined according to the first write data at other valid clock edges of the n write clock signals; In the current read cycle, n read clock signals are input to the memory chip to control the memory chip to perform a read operation; Acquire first read data output by the memory chip at the first valid clock edge of the n read clock signals; Acquire second read data output by the storage chip at other valid clock edges of the n read clock signals determined according to the first read data; The qualification of the memory chip is verified according to the first write data, the second write data, the first read data and the second read data.

2. The method according to claim 1, characterized in that: The obtaining of the first write data input by the memory chip at the first valid clock edge of the n write clock signals comprises: Before inputting the first valid clock edge of the n write clock signals, acquiring data to be subsequently input by the storage chip under the triggering of the valid clock edge; and using the acquisition result as the first write data; The obtaining of the first read data output by the memory chip at the first valid clock edge of the n read clock signals comprises: After the first effective clock edge among the n read clock signals is input, the data output by the memory chip triggered by the effective clock edge is read through the output port of the memory chip; and the read result is used as the first read data.

3. The method according to claim 1, characterized in that The obtaining of second write data input by the storage chip determined according to the first write data at other valid clock edges of the n write clock signals comprises: After obtaining the first write data and before inputting other valid clock edges of the n write clock signals, obtaining data to be subsequently input by the storage chip under the triggering of the valid clock edge, wherein the data is determined according to the first write data; and using the obtained result as the second write data; The obtaining of second read data output by the storage chip determined according to the first read data at other valid clock edges of the n read clock signals comprises: After the first read data is obtained, the data output by the storage chip under other valid clock edges is determined according to the first read data; and the determination result is used as the second read data.

4. The method according to claim 1, characterized in that The method further comprises: Invert the first write data and use it as the second write data input to the memory chip at the odd-numbered other valid clock edges; use the first write data as the second write data input to the memory chip at the even-numbered other valid clock edges; or The first read data is inverted as the second read data output by the memory chip at the odd-numbered other valid clock edges; the first read data is used as the second read data output by the memory chip at the even-numbered other valid clock edges.

5. The method according to claim 1, characterized in that The step of verifying the eligibility of the memory chip according to the first write data, the second write data, the first read data, and the second read data includes: comparing the first read data with the first write data; comparing the second read data with the second write data; According to the data comparison result, it is determined whether the memory chip is qualified.

6. The method according to any one of claims 1 to 5, characterized in that The method further comprises: Obtaining the number of access cycles required to complete an access operation of a data unit under the condition that n access clock signals are input in each access cycle; For each access cycle, trigger the input of n access clock signals to the memory chip in the current access cycle to control the memory chip to perform access operations.

7. The method according to claim 6, characterized in that The obtaining of the number of access cycles required to complete the access operation of a data unit under the condition that n access clock signals are input in each access cycle includes: Obtaining access parameters supported by the memory chip: data bit width and clock edge type; According to the acquired access parameters, the number of access cycles required to complete the access operation of one data unit under the condition that n access clock signals are input in each access cycle is determined.

8. A memory chip testing device, characterized in that: Applied to a testing machine, the device comprises: A data writing unit, used to input n write clock signals to the memory chip in the current write cycle to control the memory chip to perform a write operation, wherein n is an integer greater than 1; A first write data acquisition unit, used for acquiring first write data input by the memory chip under the first valid clock edge of the n write clock signals; A second write data acquisition unit, used for acquiring second write data input by the storage chip at other valid clock edges of the n write clock signals determined according to the first write data; A data reading unit, used to input n read clock signals to the memory chip in the current read cycle, and control the memory chip to perform a read operation; A first read data acquisition unit, used for acquiring first read data output by the memory chip at the first valid clock edge of the n read clock signals; A second read data acquisition unit, used for acquiring second read data output by the storage chip at other valid clock edges of the n read clock signals determined according to the first read data; A chip verification unit is used to verify the qualification of the storage chip according to the first write data, the second write data, the first read data and the second read data.

9. The device according to claim 8, characterized in that The first write data acquisition unit is specifically used to: before inputting the first valid clock edge of the n write clock signals, acquire the data to be subsequently input by the storage chip under the triggering of the valid clock edge; and use the acquisition result as the first write data; The first read data acquisition unit is specifically used to: after inputting the first valid clock edge of the n read clock signals, read the data output by the storage chip under the triggering of the valid clock edge through the output port of the storage chip; This read result is used as the first read data.

10. The device according to claim 8, characterized in that The second write data acquisition unit is specifically used to: after obtaining the first write data and before inputting other valid clock edges of the n write clock signals, acquire data to be subsequently input by the storage chip under the triggering of the valid clock edge, wherein the data is determined according to the first write data; and use the acquisition result as the second write data; The second read data acquisition unit is specifically used to: after obtaining the first read data, determine the data output by the storage chip under other valid clock edges according to the first read data; and use the determination result as the second read data.

11. The device according to claim 8, characterized in that The device also includes a data determination unit, configured to: Invert the first write data to serve as the second write data input to the memory chip at the odd-numbered other valid clock edges; and use the first write data as the second write data input to the memory chip at the even-numbered other valid clock edges; or The first read data is inverted as the second read data output by the memory chip at the odd-numbered other valid clock edges; the first read data is used as the second read data output by the memory chip at the even-numbered other valid clock edges.

12. The device according to claim 8, characterized in that The chip verification unit is specifically used for: comparing the first read data with the first write data; comparing the second read data with the second write data; According to the data comparison result, it is determined whether the memory chip is qualified.

13. The device according to any one of claims 8 to 12, characterized in that The device also includes a cycle number acquisition unit, which is used to: Obtaining the number of access cycles required to complete an access operation of a data unit under the condition that n access clock signals are input in each access cycle; For each access cycle, the data write unit is triggered to execute in the current write cycle, input n write clock signals to the storage chip, and control the storage chip to perform a write operation, or the data read unit is triggered to execute in the current read cycle, input n read clock signals to the storage chip, and control the storage chip to perform a read operation.

14. The device according to claim 13, characterized in that The cycle number acquisition unit is specifically used for: Obtaining access parameters supported by the memory chip: data bit width and clock edge type; According to the acquired access parameters, the number of access cycles required to complete the access operation of one data unit under the condition that n access clock signals are input in each access cycle is determined.

15. An electronic device, characterized in that: The electronic device comprises: a housing, a processor, a memory, a circuit board and a power supply circuit, wherein the circuit board is placed inside the space enclosed by the housing, and the processor and the memory are arranged on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program codes; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to execute the method described in any one of claims 1 to 7.

16. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the method of any one of the preceding claims 1-7.

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