A test system and test method for a storage chip

Abstract

The present invention provides a test system and a test method for a storage chip. The test system includes a chip test socket for installing the storage chip. The storage chip is configured with multiple working modes. A central processing unit is used to write first host data into the storage chip and obtain the corresponding write amplification factor when the storage chip is in each working mode. The central processing unit is used to write second host data into the storage chip when the storage chip is in each working mode, and calculate the total data volume that can be written into the storage chip according to the total data volume of the second host data and the write amplification factor corresponding to each working mode. Wherein, the total data volume of the second host data is greater than or equal to the storage space of the storage chip. The present invention can save the time and cost for obtaining the service life of the storage chip.

Description

Technical Field

[0001] The present invention relates to the technical field of static storage, and particularly to a test system and a test method for a storage chip. Background Art

[0002] With the wide application of storage chips in terminal products such as televisions, set-top boxes, tablet computers or mobile phones, the requirements for the performance and reliability of storage chips are getting higher and higher. The most important thing is to ensure the stability and reliability of the data in the storage chips. Maximizing the lifespan of storage chips is an important indicator to measure products. When the number of erasure and write cycles of the storage units in actual storage chips is fixed, the number of erasure and write cycles of the storage units needs to be used for valid data, rather than for actions such as garbage collection in firmware. In the prior art, it is impossible to quickly know the actual storage data volume of the storage chip. Therefore, there is room for improvement. Summary of the Invention

[0003] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a test system and a test method for a storage chip, which are used to solve the problem that the service life of the storage chip cannot be quickly known in the prior art.

[0004] To achieve the above object and other related objects, the present invention provides a test system for a storage chip, including:

[0005] A chip test socket for installing the storage chip; the storage chip is configured with multiple working modes;

[0006] A central processing unit for writing first host data into the storage chip and obtaining a corresponding write amplification factor when the storage chip is in each working mode;

[0007] The central processing unit is used to write second host data into the storage chip when the storage chip is in each working mode, and calculate the total data volume that can be written into the storage chip according to the total data volume of the second host data and the write amplification factor corresponding to each working mode;

[0008] Wherein, the total data volume of the second host data is greater than or equal to the storage space of the storage chip.

[0009] In an embodiment of the present invention, the central processing unit is used to obtain the data volume of the first host data requested to be written into the storage chip and the data volume actually written into the storage chip when the storage chip is in each working mode, and calculate the corresponding write amplification factor according to the actually written data volume and the data volume of the first host data requested to be written.

[0010] In one embodiment of the present invention, when the storage chip is in each working mode, the central processing unit is configured to divide the first host data into multiple sub-data with the same data volume, write the multiple sub-data into the storage chip, and count the number of times the storage chip receives the multiple sub-data.

[0011] In one embodiment of the present invention, the total data volume that can be written into the storage chip , satisfies:

[0012] ;

[0013] Wherein, represents the total data volume of the second host data, represents the number of all working modes of the storage chip, , , ……, respectively represent the reception times corresponding to different working modes, , , ……, respectively represent the write amplification factors corresponding to different working modes.

[0014] In one embodiment of the present invention, the working mode includes at least one of a cache enabled mode, a cache disabled mode, a sleep mode, an abnormal power-off mode, a background operation mode, a programming / erasing balance mode, a preprocessing hot and cold data mode, and a logical address distribution mode.

[0015] In one embodiment of the present invention, the central processing unit is configured to sort the corresponding write amplification factors in descending order in all functional modes of the storage chip, and compare the write amplification factors with a preset coefficient threshold;

[0016] Obtain the working mode corresponding to the write amplification factor greater than the coefficient threshold, and optimize the firmware to reduce the write amplification factor corresponding to this working mode.

[0017] In one embodiment of the present invention, the central processing unit is configured to read the average number of erasures of the storage chip in each working mode of the storage chip;

[0018] Calculate the data volume to be written according to the data volume of a sub-data and the reception times corresponding to each functional mode;

[0019] Calculate the erased data volume based on the average number of erasures, the number of blocks of the storage chip, and the storage space of the block, and obtain the actual written data volume based on the erased data volume and the data volume to be written.

[0020] In an embodiment of the present invention, after the central processing unit writes the second host data to the storage chip, the total amount of data erased by the storage chip is obtained;

[0021] The total amount of data actually written to the storage chip is obtained by subtracting the total amount of erased data from the total amount of the second host data;

[0022] The total writable data amount of the storage chip is compared with the actually written data amount to calculate the error between the total writable data amount and the actually written data amount of the storage chip.

[0023] In an embodiment of the present invention, the data amount of a sub-data is 4KB / 8KB / 16KB / 32KB / 64KB / 128KB / 256KB / 512KB.

[0024] The present invention also provides a test method for a storage chip, including:

[0025] When the storage chip is in each working mode, write the first host data into the storage chip and obtain the corresponding write amplification factor; the storage chip is configured with multiple working modes;

[0026] When the storage chip is in each working mode, write the second host data into the storage chip, and calculate the total writable data amount of the storage chip according to the total data amount of the second host data and the write amplification factor corresponding to each working mode;

[0027] Wherein, the total data amount of the second host data is greater than or equal to the storage space of the storage chip.

[0028] As described above, a test system and a test method for a storage chip according to the present invention can calculate the total writable data amount of the storage chip when the storage chip is in different working modes, saving the test time and test cost for obtaining the total writable data amount of the storage chip. Description of the Drawings

[0029] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the following drawings are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0030] Figure 1 It is a structural block diagram of a test system for a storage chip provided by an embodiment of the present invention.

[0031] Figure 2Schematic diagram of multiple working modes in a storage chip provided by an embodiment of the present invention.

[0032] Figure 3 Flow schematic diagram of a test method for a storage chip provided by an embodiment of the present invention. Detailed implementation manners

[0033] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0034] It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0035] In the following description, a large number of details are explored to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0036] Please refer to Figures 1 to 3 , the present invention proposes a test system and a test method for a storage chip, which can be applied to the test fields of storage devices such as Embedded Multi Media Card (EMMC), Solid State Disk (SSD), and Universal Flash Storage (UFS). According to the proportion of the storage chip in different working modes, the total amount of data that can be written into the storage chip and the write amplification factor can be theoretically calculated, which can save the time and cost of obtaining the total amount of data that can be written into the storage chip. The following is a detailed analysis through specific embodiments.

[0037] Please refer to Figure 1 , in an embodiment of the present invention, the test system of the storage chip may include a chip test socket, a central processing unit 10, a power supply module 30, a dynamic random access memory 40, and an interface module 50.

[0038] Specifically, the power supply module 30 can be used to supply power to the central processing unit 10, the dynamic random access memory 40, and the chip test socket. A memory chip 20 to be tested can be installed on the chip test socket. The memory chip 20 is configured with different working modes, including a single working mode and a combined working mode formed by combining different single working modes.

[0039] For example, the single working mode can be one of a cache-on mode (Cache ON), a cache-off mode (Cache Off), a sleep mode (Sleep), a sudden power-off recovery mode (SPOR), a background operation mode (BKOPS), a programming / erasing balance mode (Wear Leveling), a preprocessing hot and cold data mode (OP Data Ratio), and a logical address distribution mode (LBAMapping).

[0040] The combined working mode can be at least two of a cache-on mode (Cache ON), a cache-off mode (Cache Off), a sleep mode (Sleep), a sudden power-off recovery mode (SPOR), a background operation mode (BKOPS), a programming / erasing balance mode (WearLeveling), a preprocessing hot and cold data mode (OP Data Ratio), and a logical address distribution mode (LBA Mapping).

[0041] Specifically, the dynamic random access memory 40 can store and run the system software on the central processing unit 10. The interface module 50 can transmit and send data to and from the host. Host data refers to application data written by the host. The host can write host data and send instructions to the central processing unit 10, or the host can read host data and receive instructions from the central processing unit 10. The host can be a communication device such as a personal computer (PC), a tablet computer (Pad), or a mobile phone (Cell Phone).

[0042] Please refer to Figure 1 , in an embodiment of the present invention, the central processing unit 10 can write the first host data into the memory chip 20 and obtain the corresponding write amplification factor when the memory chip 20 is in each working mode.

[0043] Specifically, the write amplification factor describes the ratio between the amount of data actually written to the storage chip 20 and the amount of data that the host requests to write to the storage chip 20. When the write amplification factor is 1, it means that the amount of data that the host requests to write to the storage chip 20 is exactly equal to the amount of data actually written to the storage chip 20, which is the ideal case. When the write amplification factor is greater than 1, it means that the amount of data actually written to the storage chip 20 exceeds the amount of data that the host requests to write to the storage chip 20. This is usually due to additional writes caused by internal management operations such as garbage collection and wear leveling in the storage chip 20.

[0044] The central processing unit 10 is also used to write the second host data into the storage chip 20 when the storage chip 20 is in each working mode, and calculate the total amount of data that can be written to the storage chip 20 according to the total amount of the second host data and the write amplification factor corresponding to each working mode.

[0045] Among them, the total amount of the second host data is greater than or equal to the storage space of the storage chip 20, that is, it is required that the total amount of the second host data can fill the storage space of the storage chip 20. The total amount of the second host data can be 8GB / 32GB / 64GB / 128GB / 256GB / 512GB / 1024GB, etc.

[0046] In this embodiment, the total amount of data that can be written and the write amplification factor of the storage chip 20 in different working modes can be estimated theoretically first, without the need to use the traditional method to set different read / write orders and data amounts from the application side for evaluation, and without investing a large amount of test time and test resources.

[0047] Moreover, when writing the second host data to the storage chip 20 subsequently, the overall competitiveness of the product can be improved according to the write amplification factor, the total amount of the second host data, and the total amount of data that can be written analyzed theoretically. By finely decomposing the different working modes of the storage chip 20 and implementing the idea of breaking it into parts, the total amount of data that can be written to the storage chip 20 can be obtained quickly, avoiding the time and test resources consumed by testing the service life of the storage chip 20 in the traditional method.

[0048] Please refer to Figure 1 , in an embodiment of the present invention, in each working mode of the storage chip 20, the central processing unit 10 can obtain the amount of data of the first host data requested to be written to the storage chip 20 and the amount of data actually written to the storage chip 20, and calculate the corresponding write amplification factor according to the amount of data actually written and the amount of the first host data requested to be written.

[0049] Please refer to Figure 1, in an embodiment of the present invention, the central processing unit 10 can be used to receive the first host data, divide the first host data into multiple sub-data with the same data volume, and the data volume of each sub-data is 4KB / 8KB / 16KB / 32KB / 64KB / 128KB / 256KB / 512KB. When the storage chip 20 is in various working modes, the central processing unit 10 writes the multiple sub-data into the storage chip 20, which can be in the way of sequential writing and random writing to write the multiple sub-data into the storage chip 20.

[0050] When the storage chip 20 is in various working modes and the central processing unit 10 writes the multiple sub-data into the storage chip 20, the reception times of the storage chip 20 receiving the multiple sub-data can be counted, and the reception times are the usage frequencies (usage times) of the storage chip 20 receiving sub-data in various working modes. At the same time, the central processing unit 10 obtains the data volume of the first host data requested to be written into the storage chip 20 and the data volume actually written into the storage chip 20, and calculates the corresponding write amplification factor (WAI, Write Amplification Index) according to the data volume actually written and the data volume of the first host data requested to be written.

[0051] The central processing unit 10 calculates the total data volume that can be written into the storage chip 20 according to the total data volume of the second host data, the reception times in each working mode, and the write amplification factor.

[0052] For example, the total data volume that can be written into the storage chip 20 , satisfies:

[0053] .

[0054] Among them, represents the total data volume of the second host data, represents the total number of all working modes of the storage chip 20, , , ……, respectively represent the reception times corresponding to different working modes, , , ……, respectively represent the write amplification factors corresponding to different working modes.

[0055] For example, when the working modes of the storage chip 20 are cache-on mode, cache-off mode, sleep mode, abnormal power-off mode, background operation mode, programming / erase balance mode, preprocessing hot and cold data mode, or logical address distribution mode, , , ……, respectively represent the reception times corresponding to the above different working modes, , , ……, respectively represent the write amplification factors corresponding to the above different working modes.

[0056] Please refer to Figure 1 and Figure 2 , in an embodiment of the present invention, the central processing unit 10 is used to issue control instructions, and the storage chip 20 enters different working modes based on the control instructions and receives multiple sub-data in different working modes.

[0057] The central processing unit 10 is used to sort the corresponding write amplification factors in descending order when the storage chip 20 is in all working modes, and compare the write amplification factors with a preset coefficient threshold. Obtain the working mode corresponding to the write amplification factor greater than the coefficient threshold, and optimize the firmware to reduce the write amplification factor corresponding to this working mode.

[0058] For example, when the working mode of the storage chip 20 is cache enabled mode, cache disabled mode, sleep mode, abnormal power-off mode, background operation mode, programming / erase balance mode, preprocessing hot and cold data mode, or logical address distribution mode, considering the influence ratio of the storage chip 20 on its lifetime model in different working modes, select the maximum value Max(Y1 / Y2 / Y3 / Y4 / Y5 / Y6 / Y7 / Y8) of the write amplification factors of different working modes, and select the minimum value Min(Y1 / Y2 / Y3 / Y4 / Y5 / Y6 / Y7 / Y8) of the write amplification factors, and the write amplification factors can be sorted in descending order. The write amplification factors of the combined working mode and the write amplification factors of the single working mode can also be compared together and sorted in descending order to conduct a comprehensive analysis.

[0059] Find the differences according to the combinations of different firmware working modes of the storage chip 20 and optimize them. The firmware is optimized to different degrees according to different test combinations. For example, in the working mode corresponding to a larger write amplification factor, the firmware is optimized to a greater extent, and in the working mode corresponding to a smaller write amplification factor, the firmware is optimized to a smaller extent, so as to increase the value of the total amount of data that can be written, that is, the service life value of the storage chip 20.

[0060] Please refer to Figure 1 and Figure 2, in an embodiment of the present invention, the central processing unit 10 is used to store the average erase count (AVG-ECT, Average Erase Count) of the storage chip 20 in each working mode. The average erase count (Average Erase Count) of the storage chip 20 represents the average erase count corresponding to each storage block.

[0061] According to the data volume of a sub-data and the number of receptions corresponding to a working mode, the data volume to be written upon request is calculated. According to the average erase count, the number of blocks of the storage chip 20, and the storage space of the blocks, the erased data volume is calculated. According to the erased data volume and the data volume to be written upon request, the actual written data volume is obtained.

[0062] Specifically, as can be seen from the above, the data volume of a sub-data is 4KB / 8KB / 16KB / 32KB / 64KB / 128KB / 256KB / 512KB. By multiplying the data volume of a sub-data by the number of receptions corresponding to a working mode, the data volume to be written upon request corresponding to a working mode can be obtained.

[0063] Specifically, since there may be erase operations such as garbage collection (GC, Garbage Collection) inside the storage chip 20, multiplying the average erase count by the number of blocks of the storage chip 20 can obtain the number of erased blocks of the storage chip 20. Multiplying the number of erased blocks of the storage chip 20 by the storage space of the blocks can obtain the erased data volume. Adding the erased data volume and the data volume to be written upon request can obtain the actual data volume written into the storage chip 20. The writing of the first host data into the storage chip 20 will be described below in various working modes.

[0064] Specifically, after receiving the write instruction transmitted by the central processing unit 10, the storage chip 20 can enter the cache-on mode (Cache ON), and count the number of receptions of multiple sub-datas by the storage chip 20. The number of receptions is the usage frequency (number of usage times) of the sub-data received by the firmware of the storage chip 20 in the cache-on mode (Cache ON). And in the cache-on mode (Cache ON), it can obtain the data volume to be written into the storage chip 20 and the actual data volume written into the storage chip 20, and calculate the write amplification factor corresponding to the cache-on mode (Cache ON) according to the actual written data volume and the data volume to be written upon request.

[0065] Specifically, after receiving the write instruction transmitted by the central processing unit 10, the storage chip 20 can enter the cache off mode, and count the number of receptions of multiple sub-data by the storage chip 20. The number of receptions is the usage frequency (number of uses) of the sub-data received by the firmware of the storage chip 20 in the cache off mode. And in the cache off mode, it can obtain the amount of data requested to be written to the storage chip 20, the amount of data actually written to the storage chip 20, and calculate the corresponding write amplification factor in the cache off mode according to the amount of data actually written and the amount of data requested to be written.

[0066] Specifically, after receiving the write instruction transmitted by the central processing unit 10, the storage chip 20 can enter the sleep mode, and count the number of receptions of multiple sub-data by the storage chip 20. The number of receptions is the usage frequency (number of uses) of the sub-data received by the firmware of the storage chip 20 in the sleep mode. And in the sleep mode, it can obtain the amount of data requested to be written to the storage chip 20, the amount of data actually written to the storage chip 20, and calculate the corresponding write amplification factor in the sleep mode according to the amount of data actually written and the amount of data requested to be written.

[0067] Specifically, after receiving the write instruction transmitted by the central processing unit 10, the storage chip 20 can enter the sudden power-off recovery mode (SPOR), and count the number of receptions of multiple sub-data by the storage chip 20. The number of receptions is the usage frequency (number of uses) of the sub-data received by the firmware of the storage chip 20 in the sudden power-off recovery mode (SPOR). And in the sudden power-off recovery mode (SPOR), it can obtain the amount of data requested to be written to the storage chip 20, the amount of data actually written to the storage chip 20, and calculate the corresponding write amplification factor in the sudden power-off recovery mode (SPOR) according to the amount of data actually written and the amount of data requested to be written.

[0068] Specifically, after receiving the write instruction transmitted by the central processing unit 10, the storage chip 20 can enter the background operations mode (BKOPS), and count the number of receptions of multiple sub-data by the storage chip 20. The number of receptions is the usage frequency (number of uses) of the sub-data received by the firmware of the storage chip 20 in the background operations mode (BKOPS). And in the background operations mode (BKOPS), it can obtain the amount of data requested to be written to the storage chip 20, the amount of data actually written to the storage chip 20, and calculate the corresponding write amplification factor in the background operations mode (BKOPS) according to the amount of data actually written and the amount of data requested to be written.

[0069] Specifically, after receiving the write instruction transmitted by the central processing unit 10, the storage chip 20 can enter the programming / erasing balance mode (Wear Leveling), and count the number of times of receiving multiple sub-data by the storage chip 20. The number of receiving times is the usage frequency (number of usage times) of the sub-data received by the firmware of the storage chip 20 in the programming / erasing balance mode (Wear Leveling). And in the programming / erasing balance mode (Wear Leveling), it can obtain the amount of data requested to be written into the storage chip 20, the amount of data actually written into the storage chip 20, and calculate the corresponding write amplification factor in the programming / erasing balance mode (Wear Leveling) according to the amount of data actually written and the amount of data requested to be written.

[0070] Specifically, after receiving the write instruction transmitted by the central processing unit 10, the storage chip 20 can enter the preprocessing cold and hot data mode (OP Data Ratio), and count the number of times of receiving multiple sub-data by the storage chip 20. The number of receiving times is the usage frequency (number of usage times) of the sub-data received by the firmware of the storage chip 20 in the preprocessing cold and hot data mode (OP Data Ratio). And in the preprocessing cold and hot data mode (OP Data Ratio), it can obtain the amount of data requested to be written into the storage chip 20, the amount of data actually written into the storage chip 20, and calculate the corresponding write amplification factor in the preprocessing cold and hot data mode (OP Data Ratio) according to the amount of data actually written and the amount of data requested to be written.

[0071] Specifically, after receiving the write instruction transmitted by the central processing unit 10, the storage chip 20 can enter the logical address distribution mode (LBA Mapping), and count the number of times of receiving multiple sub-data by the storage chip 20. The number of receiving times is the usage frequency (number of usage times) of the sub-data received by the firmware of the storage chip 20 in the logical address distribution mode (LBA Mapping). And in the logical address distribution mode (LBA Mapping), it can obtain the amount of data requested to be written into the storage chip 20, the amount of data actually written into the storage chip 20, and calculate the corresponding write amplification factor in the logical address distribution mode (LBA Mapping) according to the amount of data actually written and the amount of data requested to be written.

[0072] The above is the description of writing the first host data into the storage chip 20 in a single working mode. It should be understood that when the storage chip 20 writes the first host data in a combined working mode, there is a similar description.

[0073] Please refer to Figure 1 and Figure 2, in an embodiment of the present invention, after the central processing unit 10 writes the second host data to the storage chip 20, the total amount of data erased by the storage chip 20 can be obtained. Specifically, the total amount of data actually written to the storage chip 20 is obtained by subtracting the total amount of erased data from the total amount of the second host data. The total amount of writable data is compared with the total amount of actually written data to determine the error between the total amount of writable data and the total amount of actually written data.

[0074] Specifically, from the calculation formula of the total amount of data writable by the storage chip 20 , it can be known that the write amplification factor of the storage chip 20 is greater than 1, and the total amount of data writable by the storage chip 20 is less than the total amount of host data .

[0075] Since the total amount of writable data is calculated from the total amount of host data, the number of receptions in each working mode, and the write amplification factor, the closeness between the total amount of writable data and the total amount of actually written data is unknown and needs to be verified. By comparing the total amount of actually written data with the total amount of writable data, the error between the total amount of writable data and the total amount of actually written data is determined.

[0076] Specifically, when the total amount of actually written data is close to the total amount of writable data, it indicates that the estimation of the total amount of writable data is relatively accurate.

[0077] When the total amount of actually written data is not close to the total amount of writable data, it indicates that the estimation of the total amount of writable data is not accurate enough. The possible reason is that initially, the firmware of the storage chip 20 writes the host data in the single-level cell (SLC) block. When the SLC block is used up, the host data is written into the trinary-level cell (XLC) block, resulting in a change in the write amplification factor corresponding to different working modes.

[0078] Please refer to Figure 1 、 Figure 2 , in an embodiment of the present invention, the test system further includes a display screen. The total amount of data writable by the storage chip 20 is displayed on one window of the display screen, and the write amplification factor corresponding to different working modes is displayed on another window of the display screen.

[0079] Specifically, the image file means that the dynamic random access memory 40 can store and run the system software on the central processing unit 10 and can be selected. The basic transmission unit means that the data volume of one piece of the sub-data is 4KB / 8KB / 16KB / 32KB / 64KB / 128KB / 256KB / 512KB, which can be selected based on the actual situation.

[0080] At least one of the cache enable mode, cache disable mode, sleep mode, abnormal power-off mode, background operation mode, programming / erase balance mode, preprocessing hot and cold data mode, and logical address distribution mode can be selected, and the storage chip 20 is set to operate in a single working mode or a combined working mode, so that the total amount of writable data and the write amplification factor corresponding to the storage chip 20 in different working modes can be theoretically deduced.

[0081] Specifically, the storage chip 20 can be set to operate in a single working mode, and the total amount of writable data and the write amplification factor corresponding to the storage chip 20 can be theoretically deduced. The storage chip 20 can also be set to operate in a combined working mode, and the total amount of writable data and the write amplification factor corresponding to the storage chip 20 can be theoretically deduced.

[0082] Please refer to Figure 3 , in an embodiment of the present invention, a test method for a storage chip includes the following steps.

[0083] Step S10: Write the first host data into the storage chip when the storage chip is in each working mode, and obtain the corresponding write amplification factor; the storage chip is configured with multiple working modes.

[0084] Step S20: Write the second host data into the storage chip when the storage chip is in each working mode, and calculate the total amount of writable data of the storage chip according to the total data volume of the second host data and the write amplification factor corresponding to each working mode.

[0085] By finely decomposing multiple working modes in the firmware of the storage chip 20, the idea of breaking up the whole into parts is realized, and the rapid acquisition of the service life confirmation of the storage chip 20 is achieved, avoiding the time and test resources consumed in the traditional method for testing the service life of the storage chip 20.

[0086] In summary, a test system and a test method for a storage chip disclosed in the present invention can theoretically calculate the total amount of writable data and the write amplification factor according to the usage ratio of the storage chip in different working modes, and can save the time and cost for obtaining the service life of the storage chip. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0087] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A test system for a storage chip, characterized in that, Including: A chip test socket for installing a storage chip; The storage chip is configured with multiple working modes; A central processing unit for writing first host data into the storage chip and obtaining a corresponding write amplification factor when the storage chip is in each working mode; The central processing unit is used to write second host data into the storage chip when the storage chip is in each working mode, and calculate the total data volume that can be written into the storage chip according to the total data volume of the second host data and the write amplification factor corresponding to each working mode; Wherein, the total data volume of the second host data is greater than or equal to the storage space of the storage chip.

2. The test system for a storage chip according to claim 1, characterized in that, The central processing unit is used to obtain the data volume of the first host data requested to be written into the storage chip and the data volume actually written into the storage chip when the storage chip is in each working mode, and calculate the corresponding write amplification factor according to the actually written data volume and the data volume of the first host data requested to be written.

3. The test system for a storage chip according to claim 1, wherein When the storage chip is in each working mode, the central processing unit is used to divide the first host data into multiple sub-data with the same data volume, write the multiple sub-data into the storage chip, and count the number of times the storage chip receives the multiple sub-data.

4. The test system for a storage chip according to claim 3, wherein, The total amount of data that can be written to the storage chip , satisfies: ； Among them, represents the total data volume of the second host data, represents the number of all working modes of the storage chip, , , ……, respectively represent the reception times corresponding to different working modes, , , ……, respectively represent the write amplification factors corresponding to different working modes.

5. The test system for a storage chip according to claim 1, characterized in that, The working modes include at least one of a cache-on mode, a cache-off mode, a sleep mode, an abnormal power-off mode, a background operation mode, a programming / erasing balance mode, a preprocessing hot / cold data mode, and a logical address distribution mode.

6. The test system for a storage chip according to claim 1, characterized in that, The central processing unit is used to sort the corresponding write amplification factors in descending order in all working modes of the storage chip, and compare the write amplification factors with a preset coefficient threshold; Obtain the working mode corresponding to the write amplification factor greater than the coefficient threshold, and optimize the firmware to reduce the write amplification factor corresponding to this working mode.

7. The test system for a storage chip according to claim 3, wherein The central processing unit is used to read the average number of erasures of the storage chip in each working mode of the storage chip; Calculate the data volume requested to be written according to the data volume of a sub-data and the number of receptions corresponding to each working mode; Calculate the erased data volume according to the average number of erasures, the number of blocks of the storage chip, and the storage space of the block, and obtain the actually written data volume according to the erased data volume and the data volume requested to be written.

8. The test system for a storage chip according to claim 1, wherein, After the central processing unit writes the second host data into the storage chip, obtain the total data volume erased by the storage chip; Subtract the total data volume erased from the total data volume of the second host data to obtain the total data volume actually written into the storage chip; Compare the total data volume that can be written into the storage chip with the total data volume actually written to calculate the error between the total data volume that can be written into the storage chip and the total data volume actually written.

9. The test system for a storage chip according to claim 3, wherein The data volume of a sub-data is 4KB / 8KB / 16KB / 32KB / 64KB / 128KB / 256KB / 512KB.

10. A test method for a storage chip, characterized in that, Including: When the storage chip is in each working mode, write the first host data into the storage chip and obtain the corresponding write amplification factor; The storage chip is configured with multiple working modes; When the storage chip is in each working mode, write the second host data into the storage chip, and calculate the total data volume that can be written into the storage chip according to the total data volume of the second host data and the write amplification factor corresponding to each working mode; Wherein, the total data volume of the second host data is greater than or equal to the storage space of the storage chip.

Images