Wafer processing apparatus and wafer processing method

Abstract

The present application relates to a kind of wafer processing device and wafer processing method, the device includes: shell and the reaction cavity that shell is wrapped;Reaction cavity is divided into upper cavity and lower cavity by filter device;Filter device includes first baffle and with first baffle vertically adjacent second baffle, first baffle is provided with multiple first filter hole through first baffle, second baffle is provided with multiple second filter hole through second baffle;It further includes reaction rate control system, it controls first filter hole and second filter hole vertically coincident, partial misregistration or complete misregistration.The processing method uses above-mentioned processing device.The present application is by optimizing the filtering and control mechanism of plasma, effectively solve the problem that ion damage and processing efficiency are difficult to take into account in prior art, and it has important application value.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a wafer processing apparatus and a wafer processing method. Background Technology

[0002] Plasma, also known as electroporation, is an ionized gaseous substance composed of positive and negative ions, electrons, free radicals, and central particles generated after the ionization of atoms and atomic groups. It is a macroscopically neutral ionized gas with a scale greater than the Debye length, and its motion is primarily governed by electromagnetic forces, exhibiting significant collective behavior. Plasma has important applications in the semiconductor industry, especially in wafer fabrication, involving various equipment and processes, such as semiconductor plasma resist stripping equipment, plasma etching equipment, and plasma thin film deposition equipment. However, existing equipment using plasma often suffers ion damage to the wafer substrate due to process limitations. Reducing ion damage leads to a decrease in reaction rate. Therefore, achieving a balance between low ion damage and high reaction rate has become a critical technical challenge for existing equipment. Furthermore, as semiconductor manufacturing processes advance towards higher precision and smaller dimensions, the performance requirements for plasma equipment are increasing, further complicating this problem. Summary of the Invention

[0003] Based on this, and to address the aforementioned problems, the present invention provides a wafer processing apparatus and a wafer processing method that effectively reduce ion damage while maintaining high processing efficiency by optimizing the plasma filtration and control mechanism.

[0004] This invention provides a wafer processing apparatus, comprising: a housing and a reaction chamber enclosed by the housing;

[0005] The reaction chamber is divided into an upper chamber and a lower chamber by a filtration device;

[0006] The filtration device includes a first baffle and a second baffle that is vertically adjacent to the first baffle. The first baffle is provided with a plurality of first filter holes that penetrate the first baffle, and the second baffle is provided with a plurality of second filter holes that penetrate the second baffle.

[0007] It also includes a reaction rate control system, which controls the first and second filter holes to overlap, partially misalign, or completely misalign in the vertical direction, thereby adjusting the amount of charged particles passing through the plasma and the reaction rate.

[0008] In some embodiments, by controlling the first baffle to rotate about the center of the first baffle and / or controlling the second baffle to rotate about the center of the second baffle, the first filter hole and the second filter hole are made to coincide, partially misaligned or completely misaligned in the vertical direction.

[0009] In other embodiments, by controlling the translation of the first baffle and / or the second baffle, the first filter hole and the second filter hole are made to overlap, partially misalign, or completely misalign in the vertical direction.

[0010] In some embodiments, both the first baffle and the second baffle are cylinders, and the outer walls of the first baffle and the second baffle are fitted to the inner wall of the housing.

[0011] In some embodiments, the thickness of both the first baffle and the second baffle is 5mm, and the vertical distance between the first baffle and the second baffle can be fixed or adjustable.

[0012] In some embodiments, the vertical distance between the first baffle and the second baffle is 2.5 mm.

[0013] In some embodiments, the radius of the first filter hole and the second filter hole is 2 mm.

[0014] In some embodiments, the distance between the centers of every two adjacent first filter holes is 6.35 mm; the distance between the centers of every two adjacent second filter holes is 6.35 mm.

[0015] In some embodiments, an ion density analysis system is also included for real-time monitoring of the density of charged particles, such as ions or electrons, in the plasma arriving at the lower cavity. This system can provide real-time feedback of ion density information in order to adjust the state of the baffle.

[0016] In some embodiments, the ion density analysis system is provided with a detection probe that extends into the lower cavity to detect the ion density; preferably, a Langmuir probe is used.

[0017] In some embodiments, a process gas source is also provided, which is connected to the upper cavity via a pipeline. The process gas includes, but is not limited to, CxFy, O2, Ar, N2, H2, He, etc.

[0018] In some embodiments, a plasma excitation device is also provided to excite the process gas into plasma, which enters the upper cavity and passes through a baffle to reach the lower cavity for operation.

[0019] In some embodiments, the first baffle and the second baffle are made of conductors, and the baffles include aluminum baffles or aluminum baffles with aluminum nitride or aluminum oxide coated on the surface.

[0020] In some embodiments, a wafer stage is further disposed within the lower cavity, and the wafer to be processed is disposed on the wafer stage. During wafer processing, by controlling the filtration state of the filtration device, damage to the wafer substrate by ions can be effectively reduced, while maintaining high processing efficiency.

[0021] In some embodiments, a gas extraction pipe is also provided inside the reaction chamber for discharging gas from the chamber. The gas extraction pipe is connected to a pump to ensure that the pressure and gas composition inside the chamber meet process requirements.

[0022] This application also provides a wafer processing method using the above-described wafer processing apparatus.

[0023] The processing method includes:

[0024] Confirm the operations that need to be performed on the wafer to be processed and the desired wafer product;

[0025] The vertical misalignment amplitude of the first and second filter holes at different time periods during wafer processing is designed.

[0026] The misalignment amplitude is adjusted by the reaction rate control system to process the wafer to obtain the wafer product.

[0027] In some embodiments, the method for designing the misalignment amplitude includes:

[0028] S1: Establish the relationship curves between D, R, P and the misalignment amplitude;

[0029] S2: Set the target value D for different times t. t R t P t And determine the selection range of D, R, and P at time t; for example, confirm the target value D at time t0. t0 R t0 P t0 and determine D <D t0 R>R t0 P <P t0 ;

[0030] S3: Substitute the selection range of D, R, and P at time t in S2 into the relationship curve obtained in S1, and design the required misalignment amplitude at time t;

[0031] Where D is the ion density, R is the reaction rate, P is the ion damage per unit reaction rate, P=D / R; the misalignment range is 0-100%, where overlap is 0%, 0% < partial misalignment < 100%, and complete misalignment is 100%.

[0032] In some embodiments, the processing method includes growing a thin film on a wafer or removing a thin film from a wafer.

[0033] In some embodiments, the misalignment amplitude can be fixed at different time periods, for example:

[0034] When removing the thin film on the wafer, the first baffle and / or the second baffle are first rotated so that the first filter hole and the second filter hole coincide; when approaching the termination interface, the first baffle and / or the second baffle are rotated so that the first filter hole and the second filter hole are misaligned.

[0035] When growing a thin film on a wafer, the first baffle and / or the second baffle are first rotated to misalign the first and second filter holes. As the film reaches a certain thickness, the first baffle and / or the second baffle are rotated again to align the first and second filter holes. Near the end of the growth process, the first baffle and / or the second baffle are rotated again to misalign the first and second filter holes. This ensures a high reaction rate while minimizing ion damage to the substrate. In specific processing, depending on the wafer and processing requirements, the misalignment can be complete or partial.

[0036] In other embodiments, the misalignment amplitude can be continuously adjusted, but the selection ranges of D, R, and P at different times must be met. In the aforementioned wafer processing apparatus, when low ion damage and low reaction rate are required, the two filter layers are completely misaligned; when a high reaction rate is required, the two filter layers overlap. Ion damage can be monitored in real time by an ion density analysis system, and the horizontal gap between the two filter layers can be adjusted in real time. This achieves the effect of controlling both reaction rate and ion damage. This invention, by optimizing the plasma filtration and control mechanism, effectively solves the problem of balancing ion damage and processing efficiency in existing technologies, and has significant application value. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the wafer processing apparatus of the present invention;

[0038] Figure 2 This is a schematic diagram of the structure of the first baffle and the second baffle in one embodiment of the present invention;

[0039] Figure 3 This is a schematic diagram of the structure when the filter holes in the first baffle and the second baffle are misaligned in one embodiment of the present invention;

[0040] Figure 4 This is a schematic diagram of the structure when the filter holes in the first baffle and the second baffle are completely misaligned in one embodiment of the present invention.

[0041] Reference numerals: 1-Shell; 2-Upper cavity; 3-Lower cavity; 4-First baffle; 5-Second baffle; 6-Process gas source; 7-Plasma excitation device; 8-Ion density analysis system; 9-Detection probe; 10-Wafer to be processed; 11-Wafer stage; 12-Evacuation pipe. Detailed Implementation

[0042] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that this disclosure will be thorough and complete.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0044] In the description of this invention, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the method or positional relationship shown in the drawings, and are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0045] In plasma etching and plasma resist removal processes, some processes have strict requirements for ion damage. Excessive plasma density can lead to severe ion bombardment of the substrate and excessive charge accumulation on the substrate, causing substrate breakdown damage. On the other hand, some processes require a high reaction rate, and the substrate surface film is stable and hard enough that ion bombardment will not damage the substrate. In this case, increasing the ion density can improve the reaction activity and increase the reaction rate.

[0046] This invention provides a wafer processing apparatus, such as... Figure 1 As shown, it includes a shell 1 and a reaction chamber enclosed by the shell 1;

[0047] The reaction chamber is divided into an upper chamber 2 and a lower chamber 3 by a filtration device;

[0048] The filter device includes a first baffle 4 and a second baffle 5 that is vertically adjacent to the first baffle 4, such as... Figure 2 As shown, the first baffle 4 is provided with a plurality of first filter holes penetrating the first baffle 4, and the second baffle 5 is provided with a plurality of second filter holes penetrating the second baffle 5.

[0049] It also includes a reaction rate control system, which controls the first and second filter holes to overlap, partially misalign, or completely misalign in the vertical direction, thereby adjusting the amount of charged particles passing through the plasma and the reaction rate.

[0050] In some embodiments, by controlling the first baffle 4 to rotate about the center of the first baffle 4 and / or controlling the second baffle 5 to rotate about the center of the second baffle 5, the first filter hole and the second filter hole are made to coincide, partially misaligned or completely misaligned in the vertical direction.

[0051] The number of first filter holes is not required and can be selected according to the actual processing requirements. However, at least one of the first baffle 4 and the second baffle 5 must not have filter holes near the center to prevent the filter holes of different baffles from being too close in the horizontal direction to be misaligned.

[0052] In other embodiments, by controlling the translation of the first baffle and / or the second baffle, the first filter hole and the second filter hole are made to overlap, partially misalign, or completely misalign in the vertical direction.

[0053] In some other embodiments, more baffles may be provided depending on the processing requirements.

[0054] In some embodiments, the first baffle 4 and the second baffle 5 are both cylinders, and the outer sidewalls of the first baffle 4 and the second baffle 5 are attached to the inner sidewall of the housing 1.

[0055] In some embodiments, the thickness of the first baffle 4 and the second baffle 5 is 5 mm, and the vertical distance between the first baffle 4 and the second baffle 5 is 2.5 mm.

[0056] In some embodiments, the radius of the first filter hole and the second filter hole is 2 mm.

[0057] In some embodiments, the distance between the centers of every two adjacent first filter holes is 6.35 mm; the distance between the centers of every two adjacent second filter holes is 6.35 mm.

[0058] In some embodiments, an ion density analysis system 8 is also included, which is used to monitor the density of charged particles, such as ion or electron density, in the plasma arriving at the lower cavity 3 in real time. It can provide real-time feedback of ion density information in order to adjust the state of the baffle.

[0059] In some embodiments, the ion density analysis system 8 is provided with a detection probe 9, which extends into the lower cavity 3 to detect the ion density; preferably, a Langmuir probe is used.

[0060] In some embodiments, a process gas source 6 is also provided, which is connected to the upper cavity 2 via a pipeline. The process gas includes, but is not limited to, CxFy, O2, Ar, N2, H2, He, etc.

[0061] In some embodiments, a plasma excitation device 7 is also provided, which is used to excite the process gas into plasma, which enters the upper cavity 2 and reaches the lower cavity 3 for operation after passing through a baffle.

[0062] In some embodiments, the first baffle 4 and the second baffle 5 are made of conductors, and the baffles include aluminum baffles or aluminum baffles with aluminum nitride or aluminum oxide coated on the surface.

[0063] In some embodiments, a wafer stage 11 is further provided in the lower cavity 3, and the wafer 10 to be processed is placed on the wafer stage 11. During the processing of the wafer 10, by controlling the filtration state of the filtration device, damage to the wafer substrate by ions can be effectively reduced, while maintaining high processing efficiency.

[0064] In some embodiments, a suction pipe 12 is also provided at the bottom of the lower cavity 3 for discharging gas from the cavity. The suction pipe 12 is connected to a pump to ensure that the pressure and gas composition in the cavity meet the process requirements.

[0065] This application also provides a wafer processing method using the above-described wafer processing apparatus.

[0066] The processing method includes:

[0067] Confirm the operations to be performed on wafer 10 and the desired wafer product;

[0068] The vertical misalignment amplitude of the first and second filter holes was designed at different time periods when processing wafer 10.

[0069] The misalignment amplitude is adjusted by the reaction rate control system, and the wafer to be processed 10 is processed to obtain the wafer product.

[0070] In some embodiments, the method for designing the misalignment amplitude includes:

[0071] S1: Establish the relationship curves between D, R, P and the misalignment amplitude;

[0072] S2: Set the target value D for different times t. t R t P t And determine the selection range of D, R, and P at time t; for example, confirm the target value D at time t0. t0 R t0 P t0 and determine D <D t0 R>R t0 P <P t0 ;

[0073] S3: Substitute the selection range of D, R, and P at time t in S2 into the relationship curve obtained in S1, and design the required misalignment amplitude at time t;

[0074] Where D is the ion density, R is the reaction rate, and P is the ion damage per unit reaction rate, P = D / R; the misalignment range is 0-100%, where overlap is 0%, 0% < partial misalignment < 100%, and complete misalignment is 100%. For example... Figure 3 As shown, when the filter holes are partially misaligned, the first and second filter holes are closer together in the horizontal direction. Some plasma is annihilated by hitting the baffle, but some plasma still reaches the lower cavity to perform its function. The amount of plasma reaching the lower cavity for operation can be controlled by adjusting the horizontal distance between the first and second filter holes. Figure 4 As shown, when the filter holes are completely misaligned, all plasma hits the baffle and is annihilated, resulting in a reaction rate that is minimized.

[0075] In some embodiments, the processing method includes growing a thin film on the wafer 10 to be processed or removing a thin film from the wafer 10 to be processed.

[0076] In some embodiments, the misalignment amplitude can be fixed at different time periods, for example:

[0077] When removing the thin film on the wafer 10 to be processed, first control the first baffle 4 and / or the second baffle 5 to rotate so that the first filter hole and the second filter hole coincide; when approaching the termination interface, control the first baffle 4 and / or the second baffle 5 to rotate so that the first filter hole and the second filter hole are misaligned.

[0078] When growing a thin film on the wafer 10 to be processed, the first baffle 4 and / or the second baffle 5 are first rotated to misalign the first and second filter holes. When growing a film of a certain thickness, the first baffle 4 and / or the second baffle 5 are rotated again to make the first and second filter holes coincide. Near the end of the growth process, the first baffle 4 and / or the second baffle 5 are rotated again to misalign the first and second filter holes. This ensures a high reaction rate while reducing ion damage to the substrate. In specific processing, depending on the wafer and processing requirements, the misalignment can be complete or partial.

[0079] In other embodiments, the misalignment amplitude can be continuously adjusted, but the selection ranges of D, R, and P at different times must be met.

[0080] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0081] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A wafer processing apparatus, characterized in that, Includes: a shell and a reaction chamber enclosed by the shell; The reaction chamber is divided into an upper chamber and a lower chamber by a filtration device; The filtering device includes a first baffle and a second baffle that is vertically adjacent to the first baffle. The first baffle is provided with a plurality of first filter holes that penetrate the first baffle, and the second baffle is provided with a plurality of second filter holes that penetrate the second baffle. It also includes an ion density analysis system, which is used to monitor the density of charged particles in the plasma reaching the lower cavity in real time. The ion density analysis system can provide real-time feedback of ion density information to monitor ion damage in real time so as to adjust the state of the baffle. It also includes a reaction rate control system, which adjusts the misalignment amplitude to control the first filter hole and the second filter hole to overlap, partially misalign, or completely misalign in the vertical direction, thereby adjusting the reaction rate; wherein, the misalignment amplitude is defined as 0-100%, overlap is 0%, 0% < partial misalignment < 100%, and complete misalignment is 100%, and there are pre-established relationship curves between D, R, P and the misalignment amplitude, where D is the ion density, R is the reaction rate, P is the ion damage per unit reaction rate, and P = D / R.

2. The wafer processing apparatus according to claim 1, characterized in that, By controlling the first baffle to rotate about its central axis and / or controlling the second baffle to rotate about its central axis, the first filter hole and the second filter hole can be made to overlap, partially misalign, or completely misalign in the vertical direction.

3. The wafer processing apparatus according to claim 1, characterized in that, By controlling the translation of the first baffle and / or the second baffle, the first filter hole and the second filter hole can be made to coincide, partially misalign, or completely misalign in the vertical direction.

4. The wafer processing apparatus according to claim 1, characterized in that, The ion density analysis system is equipped with a detection probe that extends into the lower cavity to detect the ion density.

5. The wafer processing apparatus according to claim 4, characterized in that, It also includes a process gas source and a plasma excitation device, wherein the process gas source and the upper cavity are connected by a pipeline; The plasma excitation device is used to excite the process gas into plasma and enter the upper cavity.

6. The wafer processing apparatus according to claim 5, characterized in that, The lower cavity is also equipped with a wafer stage, on which the wafer to be processed is placed.

7. The wafer processing apparatus according to claim 6, characterized in that, The reaction chamber is also equipped with an exhaust pipe for venting gas from the chamber.

8. A wafer processing method, using the wafer processing apparatus according to any one of claims 1-7.

9. The processing method according to claim 8, characterized in that, The processing method includes: Confirm the operations that need to be performed on the wafer to be processed and the desired wafer product; The vertical misalignment amplitude of the first and second filter holes is designed for different time periods during wafer processing; The misalignment amplitude is adjusted by a reaction rate control system to process the wafer to be processed and obtain the wafer product.

10. The processing method according to claim 9, characterized in that, The design method for the misalignment amplitude includes: S1: Establish the relationship curves between D, R, P and the misalignment amplitude; S2: Set the target value D for different times t. t R t P t And determine the selection range of D, R, and P at time t; S3: Substitute the selection range of D, R, and P at time t in S2 into the relationship curve obtained in S1, and design the required misalignment amplitude at time t; Where D is the ion density, R is the reaction rate, P is the ion damage per unit reaction rate, and P = D / R; the misalignment range is 0-100%, where overlap is 0%, 0% < partial misalignment < 100%, and complete misalignment is 100%.

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