Method for manufacturing interlayer of semiconductor device and semiconductor device

Abstract

The invention relates to a manufacturing method of an interlayer of a semiconductor device and the semiconductor device, and the manufacturing method comprises the steps: providing a semiconductor substrate, and forming a gate structure on the front surface of the semiconductor substrate; forming a first interlayer dielectric layer on the front surface of the semiconductor substrate, wherein the first interlayer dielectric layer covers the semiconductor substrate and the gate structure; a second interlayer dielectric layer is formed on the front face of the first interlayer dielectric layer, the second interlayer dielectric layer covers the first interlayer dielectric layer, and the first interlayer dielectric layer and the second interlayer dielectric layer jointly form an interlayer dielectric layer. According to the manufacturing method, by covering the first interlayer dielectric layer and the second interlayer dielectric layer, the flatness and the thickness uniformity of the first interlayer dielectric layer and the second interlayer dielectric layer can be controlled independently, so that the flatness and the thickness uniformity of the whole formed interlayer dielectric layer are improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor device manufacturing, and in particular, to a method for manufacturing an interlayer of a semiconductor device and a semiconductor device. Background Art

[0002] The interlayer is a circuit structure that isolates and protects semiconductor devices. It is mainly used to achieve electrical isolation between different circuits, prevent current leakage and interference, and improve the reliability and stability of semiconductor devices.

[0003] In the related art, when the interlayer of the semiconductor device is manufactured, only a single process is used to form a single-layer structure, which is prone to contain a large amount of moisture and impurities. As a result, after the interlayer is ground, the flatness of the interlayer is poor and the thickness is uneven. Summary of the invention

[0004] The purpose of the present disclosure is to provide a method for manufacturing an interlayer of a semiconductor device and a semiconductor device to solve the problems in the above-mentioned related art.

[0005] In order to achieve the above object, one aspect of the present disclosure provides a method for manufacturing an interlayer of a semiconductor device, the manufacturing method comprising:

[0006] S101, providing a semiconductor substrate, wherein a gate structure is formed on a front surface of the semiconductor substrate;

[0007] S102, forming a first interlayer dielectric layer on the front surface of the semiconductor substrate, wherein the first interlayer dielectric layer covers the semiconductor substrate and the gate structure;

[0008] S103 , forming a second interlayer dielectric layer on the front surface of the first interlayer dielectric layer, wherein the second interlayer dielectric layer covers the first interlayer dielectric layer, and the first interlayer dielectric layer and the second interlayer dielectric layer together constitute an interlayer dielectric layer.

[0009] In step S102, forming a first interlayer dielectric layer on the front surface of the semiconductor substrate includes:

[0010] S1021, depositing a first insulating material on the front surface of the semiconductor substrate by chemical vapor deposition, wherein the first insulating material covers the semiconductor substrate and the gate structure;

[0011] S1022 , heating and curing the first insulating material to form the first interlayer dielectric layer.

[0012] Optionally, in step S1022, the temperature of the heating and curing is 225°C-235°C, and the time of the heating and curing is 5min-7min.

[0013] Optionally, in step S103, forming a second interlayer dielectric layer on the front surface of the first interlayer dielectric layer includes:

[0014] S1031, depositing a second insulating material on the front surface of the first interlayer dielectric layer by using a chemical vapor method, wherein the second insulating material covers the first interlayer dielectric layer;

[0015] S1032, heating and curing the second insulating material to form the second interlayer dielectric layer.

[0016] Optionally, in step S1032, the temperature of the heating and curing is 225°C-235°C, and the time of the heating and curing is 5min-7min.

[0017] Optionally, the semiconductor substrate includes a silicon substrate.

[0018] Optionally, the thickness of the first interlayer dielectric layer is 1900A-2100A, and the thickness of the second interlayer dielectric layer is 1900A-2100A;

[0019] The first interlayer dielectric layer and the second interlayer dielectric layer are both silicon oxide or silicon nitride.

[0020] Optionally, the gate structure has a high dielectric constant layer and a metal gate, so that the gate structure is formed as a 28 nm HKMG structure.

[0021] Optionally, the manufacturing method further comprises:

[0022] S104 , spraying a polishing liquid on the second interlayer dielectric layer to grind the second interlayer dielectric layer.

[0023] A second aspect of the present disclosure also provides a semiconductor device manufactured using the method for manufacturing an interlayer of a semiconductor device.

[0024] The above technical solution, by covering the interlayer dielectric layer twice, that is, covering the first interlayer dielectric layer and the second interlayer dielectric layer, can facilitate the control of the flatness and thickness uniformity of the first interlayer dielectric layer and the second interlayer dielectric layer separately, thereby improving the flatness and thickness uniformity of the entire interlayer dielectric layer. In other words, the manufacturing method of the interlayer divides the original one-time manufacturing process of the interlayer dielectric layer into two times, so that the thickness of the first interlayer dielectric layer and the second interlayer dielectric layer covered in a single time is reduced, and the flatness and thickness uniformity can be conveniently controlled.

[0025] Other features and advantages of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0027] Figure 1 is a schematic flow chart of a manufacturing method according to an embodiment of the present disclosure;

[0028] Figure 2 is a schematic structural diagram of a semiconductor device in step S1021 of a manufacturing method according to an embodiment of the present disclosure;

[0029] Figure 3 is a schematic structural diagram of a semiconductor device in step S1022 of a manufacturing method according to an embodiment of the present disclosure;

[0030] Figure 4 is a schematic structural diagram of a semiconductor device in step S1031 of a manufacturing method according to an embodiment of the present disclosure;

[0031] Figure 5 It is a schematic structural diagram of a semiconductor device in step S1032 of a manufacturing method according to an embodiment of the present disclosure.

[0032] Description of Reference Numerals

[0033] 1. semiconductor substrate, 2. gate structure, 3. first interlayer dielectric layer, 4. second interlayer dielectric layer, 5. first insulating material, 6. second insulating material. DETAILED DESCRIPTION

[0034] The specific implementation of the present disclosure is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the present disclosure, and is not used to limit the present disclosure.

[0035] In the present disclosure, unless otherwise stated, directional words such as "upper, lower, left, right" are usually defined by the direction of the drawing, and "inner" and "outer" refer to the inside and outside of the relevant parts. In addition, the terms "first", "second", etc. are only used to distinguish descriptions and cannot be understood as indicating or implying relative importance.

[0036] In the description of the present disclosure, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection, it can be a direct connection, it can be indirectly connected through an intermediate medium, and it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0037] One aspect of the present disclosure provides a method for manufacturing an interlayer of a semiconductor device, the manufacturing method comprising:

[0038] S101, providing a semiconductor substrate 1, and forming a gate structure 2 on the front surface of the semiconductor substrate 1;

[0039] S102, forming a first interlayer dielectric layer 3 on the front surface of the semiconductor substrate 1, wherein the first interlayer dielectric layer 3 covers the semiconductor substrate 1 and the gate structure 2;

[0040] S103 , forming a second interlayer dielectric layer 4 on the front surface of the first interlayer dielectric layer 3 , wherein the second interlayer dielectric layer 4 covers the first interlayer dielectric layer 3 , and the first interlayer dielectric layer 3 and the second interlayer dielectric layer 4 together constitute an interlayer dielectric layer.

[0041] The semiconductor substrate 1 is used to support the gate structure 2. A plurality of gate structures 2 may be arranged on the front surface of the semiconductor substrate 1. The semiconductor substrate 1 may have a PMOS region and an NMOS region, and the PMOS region and the NMOS region respectively have a gate structure 2. The gate structure 2 may include multiple layers of material.

[0042] The first interlayer dielectric layer 3 and the second interlayer dielectric layer 4 are stacked and arranged, and the first interlayer dielectric layer 3 and the second interlayer dielectric layer 4 can be connected together to form an interlayer dielectric layer.

[0043] In the above technical solution, by covering the interlayer dielectric layer twice, that is, covering the first interlayer dielectric layer 3 and the second interlayer dielectric layer 4, it is possible to control the flatness and thickness uniformity of the first interlayer dielectric layer 3 and the second interlayer dielectric layer 4 separately, thereby improving the flatness and thickness uniformity of the entire interlayer dielectric layer. In other words, the manufacturing method of the interlayer divides the original one-time manufacturing process of the interlayer dielectric layer into two times, so that the thickness of the first interlayer dielectric layer 3 and the second interlayer dielectric layer 4 covered in a single time is reduced, and the flatness and thickness uniformity can be conveniently controlled.

[0044] Optionally, in an embodiment of the present disclosure, in step S102, forming a first interlayer dielectric layer 3 on the front surface of the semiconductor substrate 1 includes:

[0045] S1021, depositing a first insulating material 5 on the front surface of the semiconductor substrate 1 by chemical vapor deposition, the first insulating material 5 covering the semiconductor substrate 1 and the gate structure 2. The first insulating material 5 is deposited on the front surface of the semiconductor substrate 1, thereby covering the semiconductor substrate 1 and the gate structure 2.

[0046] S1022, heat and cure the first insulating material 5 to form the first interlayer dielectric layer 3. By heating and curing the first insulating material 5, moisture in the first insulating material 5 can be discharged, and impurities can be precipitated, thereby reducing moisture and impurities in the first interlayer dielectric layer 3, thereby improving the thickness uniformity and flatness of the first interlayer dielectric layer 3.

[0047] Optionally, in one embodiment of the present disclosure, in step S1022, the temperature of heating and curing is 225°C-235°C, and the time of heating and curing is 5min-7min. Such a setting can facilitate the curing of the first insulating material 5, and discharge the moisture and impurities in the first insulating material 5 to form the first interlayer dielectric layer 3. In some examples, the temperature of heating and curing is 230°C, and the time of heating and curing is 5min.

[0048] Optionally, in an embodiment of the present disclosure, in step S103, forming the second interlayer dielectric layer 4 on the front surface of the first interlayer dielectric layer 3 includes:

[0049] S1031, depositing a second insulating material 6 on the front surface of the first interlayer dielectric layer 3 by chemical vapor deposition, and the second insulating material 6 covers the first interlayer dielectric layer 3. The second insulating material 6 is deposited on the front surface of the first interlayer dielectric layer 3, so that the second insulating material 6 completely covers the first interlayer dielectric layer 3.

[0050] S1032, heat and cure the second insulating material 6 to form a second interlayer dielectric layer 4. By heating and curing the second insulating material 6, moisture in the second insulating material 6 can be discharged, and impurities can be precipitated, thereby reducing moisture and impurities in the second interlayer dielectric layer 4, thereby improving the thickness uniformity and flatness of the second interlayer dielectric layer 4.

[0051] That is to say, after the first insulating material 5 is deposited and heated and cured to form the first interlayer dielectric layer 3, the second insulating material 6 is deposited. The process of heating and curing to expel moisture and precipitate impurities is also divided into two steps. The first insulating material 5 and the second insulating material 6 can be heated and cured separately, so that after the moisture and impurities in the first insulating material 5 are discharged, the second insulating material 6 is covered to avoid the situation that the moisture and impurities in the first insulating material 5 cannot be discharged after being covered by the second insulating material 6, thereby improving the uneven thickness and flatness of the interlayer dielectric layer.

[0052] Optionally, in one embodiment of the present disclosure, in step S1032, the temperature of heating and curing is 225°C-235°C, and the time of heating and curing is 5min-7min. Such a setting can facilitate the curing of the second insulating material 6, and discharge the moisture and impurities in the second insulating material 6 to form the second interlayer dielectric layer 4. In some examples, the temperature of heating and curing is 230°C, and the time of heating and curing is 5min.

[0053] Optionally, in one embodiment of the present disclosure, the semiconductor substrate 1 includes a silicon substrate. Of course, the semiconductor substrate 1 may also be a substrate of other materials, which is not limited here.

[0054] Optionally, in one embodiment of the present disclosure, the thickness of the first interlayer dielectric layer 3 is 1900A-2100A, and the thickness of the second interlayer dielectric layer 4 is 1900A-2100A;

[0055] The first interlayer dielectric layer 3 and the second interlayer dielectric layer 4 are both silicon oxide or silicon nitride. By setting in this way, the thickness of the interlayer dielectric layer can be guaranteed, and the insulating isolation function of the interlayer dielectric layer can be guaranteed. In some examples, the thickness of the first interlayer dielectric layer 3 is 2000A, and the thickness of the second interlayer dielectric layer 4 is 2000A.

[0056] Optionally, in one embodiment of the present disclosure, the gate structure 2 has a high dielectric constant layer and a metal gate, so that the gate structure 2 is formed into a 28nm HKMG structure, wherein HK refers to a high dielectric constant layer, and MG refers to a metal gate. In addition, sidewalls may be formed on both sides of the gate structure 2. Grooves are respectively provided on both sides of a gate structure 2, and multiple gate structures 2 may be provided on the front side of the semiconductor substrate 1, so that the number of grooves may also be multiple, and adjacent gate structures 2 are separated by the grooves, and source / drain regions are respectively formed on both sides of the gate structure 2.

[0057] Optionally, in one embodiment of the present disclosure, the manufacturing method further comprises:

[0058] S104, spraying a polishing liquid on the second interlayer dielectric layer 4 to grind the second interlayer dielectric layer 4. After spraying the polishing liquid, mechanical grinding is used to grind the front surface of the second interlayer dielectric layer 4 flat and eliminate surface defects, so as to achieve planarization of the front surface of the entire interlayer dielectric layer.

[0059] A second aspect of the present disclosure also provides a semiconductor device manufactured using the method for manufacturing an interlayer of a semiconductor device.

[0060] The preferred embodiments of the present disclosure are described in detail above in conjunction with the accompanying drawings; however, the present disclosure is not limited to the specific details in the above embodiments. Within the technical concept of the present disclosure, a variety of simple modifications can be made to the technical solution of the present disclosure, and these simple modifications all fall within the protection scope of the present disclosure.

[0061] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present disclosure will not further describe various possible combinations.

[0062] In addition, various embodiments of the present disclosure may be arbitrarily combined, and as long as they do not violate the concept of the present disclosure, they should also be regarded as the contents disclosed by the present disclosure.

Claims

1. A method for manufacturing an interlayer of a semiconductor device, It is characterized in that The manufacturing method comprises: S101, providing a semiconductor substrate, wherein a gate structure is formed on a front surface of the semiconductor substrate; S102, forming a first interlayer dielectric layer on the front surface of the semiconductor substrate, wherein the first interlayer dielectric layer covers the semiconductor substrate and the gate structure; S103 , forming a second interlayer dielectric layer on the front surface of the first interlayer dielectric layer, wherein the second interlayer dielectric layer covers the first interlayer dielectric layer, and the first interlayer dielectric layer and the second interlayer dielectric layer together constitute an interlayer dielectric layer.

2. The method for manufacturing an interlayer of a semiconductor device according to claim 1, It is characterized in that In step S102, forming a first interlayer dielectric layer on the front surface of the semiconductor substrate includes: S1021, depositing a first insulating material on the front surface of the semiconductor substrate by chemical vapor deposition, wherein the first insulating material covers the semiconductor substrate and the gate structure; S1022 , heating and curing the first insulating material to form the first interlayer dielectric layer.

3. The method for manufacturing an interlayer of a semiconductor device according to claim 2, It is characterized in that In step S1022, the temperature of the heating and curing is 225°C-235°C, and the time of the heating and curing is 5min-7min.

4. The method for manufacturing an interlayer of a semiconductor device according to claim 1, It is characterized in that In step S103, forming a second interlayer dielectric layer on the front surface of the first interlayer dielectric layer includes: S1031, depositing a second insulating material on the front surface of the first interlayer dielectric layer by using a chemical vapor method, wherein the second insulating material covers the first interlayer dielectric layer; S1032, heating and curing the second insulating material to form the second interlayer dielectric layer.

5. The method for manufacturing an interlayer of a semiconductor device according to claim 4, It is characterized in that In step S1032, the temperature of the heating and curing is 225°C-235°C, and the time of the heating and curing is 5min-7min.

6. The method for manufacturing an interlayer of a semiconductor device according to claim 1, It is characterized in that The semiconductor substrate includes a silicon substrate.

7. The method for manufacturing an interlayer of a semiconductor device according to claim 1, It is characterized in that The thickness of the first interlayer dielectric layer is 1900A-2100A, and the thickness of the second interlayer dielectric layer is 1900A-2100A; The first interlayer dielectric layer and the second interlayer dielectric layer are both silicon oxide or silicon nitride.

8. The method for manufacturing an interlayer of a semiconductor device according to claim 1, It is characterized in that The gate structure has a high dielectric constant layer and a metal gate, so that the gate structure is formed as a 28 nm HKMG structure.

9. The method for manufacturing an interlayer of a semiconductor device according to claim 1, It is characterized in that The manufacturing method further comprises: S104 , spraying a polishing liquid on the second interlayer dielectric layer to grind the second interlayer dielectric layer.

10. A semiconductor device manufactured using the method for manufacturing an interlayer of a semiconductor device according to any one of claims 1 to 9.

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