Terminal structure of semiconductor device

Abstract

The invention discloses a terminal structure of a semiconductor device. The terminal structure comprises a semiconductor layer, a polycrystalline silicon layer, a first insulating layer, a metal layer and a passivation layer. The polycrystalline silicon layer partially covers the first surface of the semiconductor layer. The first insulating layer covers the polysilicon layer. The metal layer covers the first insulating layer and the polysilicon layer. The edge of the metal layer forms at least two steps on the first surface of the semiconductor layer. The at least two steps comprise the highest step and the lowest step. The passivation layer covers the first surface of the semiconductor layer which is not covered by the metal layer and extends to cover a partial region of the lowest step of the metal layer. According to the terminal structure of the semiconductor device, by adjusting the structure of each layer below the metal layer, the metal layer forms a step, and the edge of the passivation layer falls on the lowest step or the middle step of the metal layer, so that the highest height of the passivation layer is lower than the highest height of the metal layer, the shearing force of packaging on the passivation layer is weakened, and the packaging quality is improved. And the risk of generating cracks on the passivation layer is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a terminal structure of a semiconductor device. Background Art

[0002] With the advancement and development of science and technology, semiconductor materials have also undergone a generational change. The third-generation semiconductor materials have economic and environmental benefits such as small size, less pollution, and low operating loss. They can meet the requirements of modern society for high temperature, high power, high voltage, high frequency, and radiation resistance. Therefore, the third-generation semiconductor materials are gradually becoming the focus of development. The current mainstream third-generation semiconductor materials are silicon carbide and gallium nitride. Silicon carbide materials are mostly used in high-voltage occasions such as smart grids and rail transportation; gallium nitride materials have greater applications in the high-frequency field.

[0003] At present, silicon carbide power devices are mainly positioned in scenarios with power between 1kw-500kw and operating frequency between 10KHz-100MHz. In particular, they can replace some silicon-based MOSFETs and IGBTs in some applications with high requirements for energy efficiency and space size. The manufacturing process of silicon carbide power devices requires device preparation and packaging processes. At the end of the device preparation process, a passivation layer structure needs to be set above the dielectric layer and the metal layer to block the intrusion of external water vapor and improve the stability of the device. In the packaging process, the packaged device is formed by filling the plastic packaging material and the shell.

[0004] During the packaging process of silicon carbide power devices, the packaged devices need to undergo reliability tests such as TCT (Thermal Cycle Test) / TST (Thermal Shock Test). Due to the mismatch in linear expansion coefficients between the plastic packaging material / dielectric layer / metal layer, excessive stress may cause cracks in the passivation layer structure or metal deformation, which will not only affect the appearance of the device, but more importantly, reduce the device's ability to resist water vapor erosion, thereby affecting the long-term working reliability of the device. Summary of the invention

[0005] The present application provides a terminal structure of a semiconductor device, which forms steps in the metal layer by adjusting the structures of the layers below the metal layer, and makes the edge of the passivation layer fall on the lowest step or the middle step of the metal layer, so that the highest height of the passivation layer is lower than the highest height of the metal layer, thereby weakening the shear force of the package on the passivation layer and reducing the risk of cracks in the passivation layer.

[0006] According to one embodiment of the present invention, a terminal structure of a semiconductor device is provided, comprising a semiconductor layer, a polysilicon layer, a first insulating layer, a metal layer and a passivation layer. The semiconductor layer has a first surface of the semiconductor layer. The polysilicon layer partially covers the first surface of the semiconductor layer. The first insulating layer covers the polysilicon layer. The metal layer at least covers the first insulating layer and the polysilicon layer. The metal layer forms at least two steps on the first surface of the semiconductor layer, including a highest step and a lowest step. The passivation layer covers the first surface of the semiconductor layer not covered by the metal layer, and extends to cover a portion of the lowest step of the metal layer.

[0007] In one embodiment, the first insulating layer covers a portion of the polysilicon layer. The edge region of the polysilicon layer is not covered by the first insulating layer. The lowest step of the metal layer covers the first surface of the semiconductor layer. The highest step of the metal layer covers the first insulating layer and is located above the stack of the first insulating layer and the polysilicon layer. The metal layer also includes an intermediate step covering the edge region of the polysilicon layer. The highest step, the intermediate step and the lowest step of the metal layer are sequentially connected through other parts of the metal layer.

[0008] In one embodiment, the metal layer further includes an intermediate step.

[0009] In one embodiment, the passivation layer extends to cover the lowest step of the metal layer, and further extends to cover a portion of the middle step of the metal layer.

[0010] In one embodiment, the first insulating layer covers the entire area of ​​the polysilicon layer, and the edge area of ​​the first insulating layer extends to cover the first surface of the semiconductor layer, the lowest step of the metal layer covers the first surface of the semiconductor layer, the highest step of the metal layer covers the first insulating layer and is located above the stack of the first insulating layer and the polysilicon layer, the metal layer also includes an intermediate step covering the edge area of ​​the first insulating layer, and the highest step, the intermediate step and the lowest step of the metal layer are connected in sequence through other parts of the metal layer.

[0011] In one embodiment, the first insulating layer covers a portion of the polysilicon layer, and the polysilicon layer extends between the lowest step of the metal layer and the first surface of the semiconductor layer, and between the passivation layer and the first surface of the semiconductor layer. The lowest step of the metal layer covers the polysilicon layer, and the highest step of the metal layer covers the first insulating layer and is located above the stack of the first insulating layer and the polysilicon layer. The highest step and the lowest step of the metal layer are connected through other parts of the metal layer.

[0012] In one embodiment, the sum of the thickness of the first insulating layer and the polysilicon layer is greater than the thickness of the passivation layer.

[0013] In one embodiment, the thickness of the first insulating layer is greater than the thickness of the passivation layer.

[0014] In one embodiment, the thickness of the polysilicon layer is greater than the thickness of the passivation layer.

[0015] In one embodiment, a second insulating layer is further included between the passivation layer and the first surface of the semiconductor layer. The second insulating layer is completely covered by the passivation layer and does not overlap with the metal layer in a direction perpendicular to the first surface of the semiconductor layer.

[0016] In one embodiment, the semiconductor layer includes: a substrate layer, an epitaxial layer, and a third insulating layer. The epitaxial layer is located on the substrate layer. The third insulating layer is located on the epitaxial layer and forms a stacked structure with the epitaxial layer and the substrate layer. The first surface of the semiconductor layer includes the outer surface of the third insulating layer. The outer surface of the third insulating layer is parallel to and not in contact with the surface of the epitaxial layer.

[0017] In one embodiment, the semiconductor layer includes a substrate layer, an epitaxial layer and a fourth insulating layer. The epitaxial layer is located on the substrate layer. The fourth insulating layer is located on the epitaxial layer and forms a stacked structure with the epitaxial layer and the substrate layer. The first surface of the semiconductor layer includes an outer surface of the fourth insulating layer. The outer surface of the fourth insulating layer is parallel to and not in contact with the surface of the epitaxial layer.

[0018] In one embodiment, a second insulating layer is further included between the passivation layer and the first surface of the semiconductor layer. The second insulating layer is completely covered by the passivation layer and does not overlap with the metal layer in a direction perpendicular to the first surface of the semiconductor layer.

[0019] In one embodiment, a third insulating layer is further included between the second insulating layer and the epitaxial layer, and an edge of the third insulating layer is connected to an edge of the fourth insulating layer below the second insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings:

[0021] Figure 1 It is a structural schematic diagram of a terminal structure 100 of an existing semiconductor device;

[0022] Figure 2 is a schematic structural diagram of a terminal structure 200 of a semiconductor device according to an embodiment of the present application;

[0023] Figure 3 is a structural schematic diagram of a terminal structure 300 of a semiconductor device according to an embodiment of the present application;

[0024] Figure 4 is a structural schematic diagram of a terminal structure 400 of a semiconductor device according to an embodiment of the present application;

[0025] Figure 5is a structural schematic diagram of a terminal structure 500 of a semiconductor device according to an embodiment of the present application;

[0026] Figure 6 is a structural schematic diagram of a terminal structure 600 of a semiconductor device according to an embodiment of the present application;

[0027] Figure 7 is a structural schematic diagram of a terminal structure 700 of a semiconductor device according to an embodiment of the present application;

[0028] Figure 8 is a structural schematic diagram of a terminal structure 800 of a semiconductor device according to an embodiment of the present application;

[0029] Fig. 9 is a schematic structural diagram of a terminal structure 900 of a semiconductor device according to an embodiment of the present application;

[0030] Fig.10 is a structural schematic diagram of a terminal structure 1000 of a semiconductor device according to an embodiment of the present application;

[0031] Fig.11 is a structural schematic diagram of a terminal structure 1100 of a semiconductor device according to an embodiment of the present application;

[0032] Fig.12 is a schematic structural diagram of a terminal structure 1200 of a semiconductor device according to an embodiment of the present application;

[0033] Fig.13 is a structural schematic diagram of a terminal structure 1300 of a semiconductor device according to an embodiment of the present application;

[0034] Fig.14 is a structural schematic diagram of a terminal structure 1400 of a semiconductor device according to an embodiment of the present application;

[0035] Fig.15 is a schematic structural diagram of a terminal structure 1500 of a semiconductor device according to an embodiment of the present application;

[0036] Fig.16 1 is a schematic structural diagram of a terminal structure 1600 of a semiconductor device according to an embodiment of the present application. DETAILED DESCRIPTION

[0037] The specific embodiments of the present invention will be described in detail below. It should be noted that the embodiments described herein are only for illustration and are not intended to limit the present invention. In the following description, a large number of specific details are set forth in order to provide a thorough understanding of the present invention. However, it is obvious to those of ordinary skill in the art that these specific details do not have to be used to implement the present invention. In other examples, in order to avoid confusing the present invention, known circuits, materials or methods are not specifically described.

[0038] Throughout the specification, references to "one embodiment", "an embodiment", "an example" or "an example" mean that a particular feature, structure or characteristic described in conjunction with the embodiment or example is included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment", "in an embodiment", "an example" or "an example" appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. In addition, particular features, structures or characteristics may be combined in one or more embodiments or examples in any appropriate combination and / or sub-combination. In addition, it should be understood by those of ordinary skill in the art that the drawings provided herein are for illustrative purposes and that the drawings are not necessarily drawn to scale. The same reference numerals indicate the same elements. The term "and / or" used herein includes any and all combinations of one or more related listed items. The drawings are not drawn to scale and are for illustrative purposes only. For clarity, unless otherwise specified, the same elements have been designated by corresponding reference numerals in different drawings.

[0039] The terms “having,” “comprising,” “including,” “including,” and the like are open ended, and these terms indicate the presence of stated structures, elements, or features, but do not exclude additional elements or features.

[0040] When describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly on the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the device is turned over, the layer or region will be "below" or "beneath" another layer or region.

[0041] If it is intended to describe a situation where it is directly on another layer or another area, this article will use the expression “directly on…” or “on… and adjacent to…”.

[0042] Figure 1 FIG. 1 is a schematic diagram of a terminal structure 100 of an existing semiconductor device. Figure 1As shown, the terminal structure 100 of the semiconductor device includes a semiconductor layer 101, a polysilicon layer 106, an insulating layer 107, a metal layer 108 and a passivation layer 109. The semiconductor layer 101 includes a substrate layer 102, an epitaxial layer 103, an insulating layer 104 and an insulating layer 105 constituting a stacked structure. The insulating layer 104 is partially covered with a polysilicon layer 106. The polysilicon layer 106, the insulating layer 104 and the insulating layer 105 are sequentially covered with an insulating layer 107, a metal layer 108 and a passivation layer 109. The passivation layer 109 covers the entire terminal structure to play a role in electrical insulation and device protection.

[0043] from Figure 1 As can be seen in the figure, the passivation layer 109 completely covers the metal layer 108 and the insulating layer 107. When the semiconductor device is subjected to reliability testing during the packaging process, the materials of the passivation layer 109, the metal layer 108 and the insulating layer 107 are different, and the linear expansion coefficients therebetween are mismatched. Excessive stress may cause cracks in the passivation layer structure or metal deformation.

[0044] Figure 2 FIG. 2 is a schematic diagram of a terminal structure 200 of a semiconductor device according to an embodiment of the present application. Figure 2 As shown, the terminal structure 200 includes a semiconductor layer 201, a polysilicon layer 206, an insulating layer 207-1, an insulating layer 207-2, a metal layer 208 and a passivation layer 209. The semiconductor layer 201 includes a substrate layer 202, an epitaxial layer 203, an insulating layer 204 and an insulating layer 205.

[0045] The substrate layer 202 and the epitaxial layer 203 include silicon-based materials, silicon carbide-based materials, or gallium nitride materials. The substrate layer 202 and the epitaxial layer 203 have the same doping type, for example, both may be P-type materials, or both may be N-type materials. The doping concentration of the substrate layer 202 is greater than the doping concentration of the epitaxial layer 203. In some embodiments, the epitaxial layer 203 may be a multi-layer epitaxial structure, that is, a multi-layer structure including different doping concentrations. In addition, the portion of the epitaxial layer 203 away from the substrate layer may also include device structures of multiple different materials to meet the performance requirements of the terminal area.

[0046] The insulating layer 204 and the insulating layer 205 cover the epitaxial layer 203. In some embodiments, the insulating layer 204 includes a gate oxide layer, and the insulating layer 205 includes a field oxide layer. The material of the insulating layer 204 includes silicon dioxide (SiO2), silicon nitride (Si3N4) or hafnium-based oxide (HfO2). The material of the insulating layer 205 includes silicon dioxide (SiO2). The thickness of the insulating layer 205 is greater than the thickness of the insulating layer 204, and the two have a step structure at the intersection of the surface of the epitaxial layer 203.

[0047] exist Figure 2In the embodiment, the polysilicon layer 206 covers the insulating layer 204 and the insulating layer 205 in part, and covers the step structure formed at the junction of the insulating layer 204 and the insulating layer 205, so that the polysilicon layer 206 itself also forms a step structure with high and low distribution in the direction perpendicular to the surface of the epitaxial layer 203. Furthermore, the polysilicon layer 206 is also covered with an insulating layer 207-1. The insulating layer 207-1 covers the step structure of the polysilicon layer 206, and thus also has a step structure. Figure 2 In the embodiment, the insulating layer 207-1 is an interlayer dielectric layer, which is used to isolate the conductive layer, prevent electrical short circuits and interference, and can also provide mechanical support and the like. The insulating layer 207-2 is also an interlayer dielectric layer, and can be manufactured synchronously with the insulating layer 207-1 during the process. The insulating layer 207-1 and the insulating layer 207-2 can be different regions of the same dielectric layer. The materials of the insulating layer 207-1 and the insulating layer 207-2 can be low dielectric constant materials such as silicon dioxide (SiO2), fluorosilicate glass (FSG), carbon-doped oxide (CDO), or high dielectric constant materials such as hafnium-based oxide (HfO2). In an embodiment of the present application, the spacing Ld between the insulating layer 207-1 and the insulating layer 207-2 is greater than the thickness of the metal layer 208. In other embodiments below, the same rule applies.

[0048] exist Figure 2 In the embodiment, the insulating layer 207-1 does not completely cover the polysilicon layer 206. That is, the edge region 206a of the polysilicon layer 206 is not covered by the insulating layer 207-1. The metal layer 208 covers the insulating layer 205, the polysilicon layer 206 and the insulating layer 207-1. Due to the step structure of the polysilicon layer 206 and the insulating layer 207-1 on the surface of the insulating layer 205, the metal layer 208 forms a three-step structure, wherein the lowest step 208a of the metal layer 208 is located on the surface of the insulating layer 205, the middle step 208c is located on the surface of the edge region 206a of the polysilicon layer 206, and the highest step 208b is located on the surface of the insulating layer 207-1. The steps of the metal layer 208 are sequentially connected through other parts of the metal layer to form a whole.

[0049] The material of the metal layer 208 may include any one of aluminum, silver, copper and gold, or a combination of at least two thereof.

[0050] exist Figure 2 In the embodiment, a multi-level structure of metal layers is formed on the surface of the insulating layer 205 , and the surface 205 a of the insulating layer 205 is also referred to as the first surface of the semiconductor layer.

[0051] exist Figure 2In the embodiment, in a direction perpendicular to the first surface 205a of the semiconductor layer, below the lowest step 208a of the metal layer 208 is the insulating layer 205, below the middle step 208c is the stack of the polysilicon layer 206 and the insulating layer 205, and below the highest step 208b is the stack of the insulating layer 207-1, the polysilicon layer 206, and the insulating layer 205.

[0052] In one embodiment, the thickness of the metal layer 208 is greater than or equal to 0.5 μm. The thickness of the polysilicon layer 206 is greater than or equal to 0.1 μm. The thickness of the insulating layer 207-1 and the insulating layer 207-2 is greater than or equal to 0.1 μm. The height H1 of the lowest step 208a of the metal layer 208 from the first surface 205a of the semiconductor layer is the thickness of the metal layer 208. The height H2 of the middle step 208c of the metal layer 208 from the first surface 205a of the semiconductor layer is the thickness of the metal layer 208 plus the thickness of the polysilicon layer 206. The height H3 of the highest step 208b of the metal layer 208 from the first surface 205a of the semiconductor layer is the thickness of the metal layer 208 plus the thickness of the insulating layer 207-1 and the thickness of the polysilicon layer 206.

[0053] exist Figure 2 In the embodiment, the height difference between the lowest step 208a and the middle step 208c of the metal layer 208 is equal to the thickness of the polysilicon layer 206, the height difference between the middle step 208c and the highest step 208b is equal to the thickness of the insulating layer 207-1, and the height difference between the lowest step 208a and the highest step 208b is equal to the thickness of the polysilicon layer 206 plus the thickness of the insulating layer 207-1.

[0054] exist Figure 2 In an embodiment, the passivation layer 209 covers the first surface 205a of the semiconductor layer not covered by the metal layer 208, and extends to cover a partial area of ​​the lowest step 208a of the metal layer 208. An insulating layer 207-2 is also sandwiched between the first surface 205a of the semiconductor layer and a partial area of ​​the passivation layer 209. That is, the insulating layer 207-2 covers a partial area of ​​the first surface 205a of the semiconductor layer not covered by the metal layer, the passivation layer covers the insulating layer 207-2, and also covers the first surface 205a of the semiconductor layer not covered by the insulating layer 207-2 and the metal layer 208. The thickness of the passivation layer 209 is greater than or equal to 0.05 μm. The highest height H4 of the passivation layer 209 from the first surface 205a of the semiconductor layer is the thickness of the metal layer 208 plus the thickness of the passivation layer 209. Figure 2 In the embodiment, the highest height H4 of the passivation layer 209 from the first surface 205a of the semiconductor layer is smaller than the highest height of the metal layer 208, ie, smaller than the height H3 of the highest step 208b of the metal layer 208 from the first surface 205a of the semiconductor layer.

[0055] exist Figure 2 In an embodiment, the thickness of the passivation layer 209 is less than the sum of the thickness of the polysilicon layer 206 and the thickness of the insulating layer 207 - 1 .

[0056] The material of the passivation layer 209 may include silicon oxide, silicon nitride, or a stacked layer made of silicon oxide and silicon nitride.

[0057] In the embodiment of the present application, the insulating layer 207 - 1 is also referred to as the first insulating layer, the insulating layer 207 - 2 is also referred to as the second insulating layer, the insulating layer 205 is also referred to as the third insulating layer, and the insulating layer 204 is also referred to as the fourth insulating layer.

[0058] It should be understood that the edge region 206 a of the polysilicon layer 206 described in the embodiment of the present application represents the edge of the polysilicon layer 206 and a partial region connected to the edge.

[0059] Figure 3 FIG. 3 is a schematic diagram of a terminal structure 300 of a semiconductor device according to an embodiment of the present application. Figure 2 The terminal structure 200 of the embodiment is similar, except that Figure 3 In the embodiment, after the passivation layer 309 covers the lowest step 208 a of the metal layer 208 , it further extends to cover the middle step 208 c of the metal layer 208 .

[0060] exist Figure 3 In the embodiment, the maximum height H4 of the passivation layer 309 from the first surface 205a of the semiconductor layer is the thickness of the metal layer 208 plus the thickness of the polysilicon layer 206 and the thickness of the passivation layer 309. Figure 3 In the embodiment, the highest height H4 of the passivation layer 309 from the first surface 205a of the semiconductor layer is smaller than the highest height of the metal layer 208, ie, smaller than the height H3 of the highest step 208b of the metal layer 208 from the first surface 205a of the semiconductor layer.

[0061] exist Figure 3 In an embodiment, the thickness of the passivation layer 309 is less than the thickness of the insulating layer 207 - 1 .

[0062] Figure 4 FIG. 4 is a schematic diagram of a terminal structure 400 of a semiconductor device according to an embodiment of the present application. Figure 2 The terminal structure 200 of the embodiment is similar, except that Figure 4In the embodiment, the insulating layer 407-1 (first insulating layer) completely covers the polysilicon layer 406, and after covering the polysilicon layer 406, continues to extend to the first surface 205a of the semiconductor layer at the edge of the polysilicon layer 406, forming a step structure. That is, the first surface 205a of the semiconductor layer, the edge region 407-1a of the insulating layer 407-1, and the stack of the polysilicon layer 406 and the insulating layer 407-1 form a step structure, so that the metal layer 408 covered thereon also forms a corresponding step structure.

[0063] exist Figure 4 In the embodiment, in a direction perpendicular to the first surface 205a of the semiconductor layer 201, below the lowest step 408a of the metal layer 408 is the insulating layer 205, below the middle step 408c is the stack of the insulating layer 407-1 and the insulating layer 205, and below the highest step 408b is the stack of the insulating layer 407-1, the polysilicon layer 406 and the insulating layer 205.

[0064] exist Figure 4 In the embodiment, the height H1 of the lowest step 408a of the metal layer 408 from the first surface 205a of the semiconductor layer is the thickness of the metal layer 408. The height H2 of the middle step 408c of the metal layer 408 from the first surface 205a of the semiconductor layer is the thickness of the metal layer 408 plus the thickness of the insulating layer 407-1. The height H3 of the highest step 408b of the metal layer 408 from the first surface 205a of the semiconductor layer is the thickness of the metal layer 408 plus the thickness of the insulating layer 407-1 and the thickness of the polysilicon layer 406.

[0065] exist Figure 4 In the embodiment, the height difference between the lowest step 408a and the middle step 408c of the metal layer 408 is equal to the thickness of the insulating layer 207-1, the height difference between the middle step 408c and the highest step 408b is equal to the thickness of the polysilicon layer 206, and the height difference between the lowest step 408a and the highest step 408b is equal to the thickness of the polysilicon layer 406 superimposed on the thickness of the insulating layer 407-1.

[0066] exist Figure 4 In the embodiment, the passivation layer 209 covers the first surface 205a of the semiconductor layer that is not covered by the metal layer 408, and extends to cover a portion of the lowest step 408a of the metal layer 408. The highest height H4 of the passivation layer 209 from the first surface 205a of the semiconductor layer is the thickness of the metal layer 408 plus the thickness of the passivation layer 209. Figure 4 In the embodiment, the highest height H4 of the passivation layer 209 from the first surface 205a of the semiconductor layer is smaller than the highest height of the metal layer 408, ie, smaller than the height H3 of the highest step 408b of the metal layer 408 from the first surface 205a of the semiconductor layer.

[0067] exist Figure 4 In an embodiment, the thickness of the passivation layer 209 is less than the sum of the thickness of the polysilicon layer 406 and the thickness of the insulating layer 407 - 1 .

[0068] It should be understood that the edge region 407 - 1 a of the insulating layer 407 - 1 described in the embodiment of the present application represents the edge of the insulating layer 407 - 1 and a partial region connected to the edge.

[0069] Figure 5 FIG. 5 is a schematic diagram of a terminal structure 500 of a semiconductor device according to an embodiment of the present application. Figure 4 The terminal structure 400 of the embodiment is similar, except that Figure 5 In the embodiment, after the passivation layer 509 covers the lowest step 408 a of the metal layer 408 , it further extends to cover the middle step 408 c of the metal layer 408 .

[0070] exist Figure 5 In the embodiment, the highest height H4 of the passivation layer 509 from the first surface 205a of the semiconductor layer is the thickness of the metal layer 508 plus the thickness of the insulating layer 407-1 and the thickness of the passivation layer 509. Figure 5 In the embodiment, the highest height H4 of the passivation layer 509 from the first surface 205a of the semiconductor layer is smaller than the highest height of the metal layer 408, ie, smaller than the height H3 of the highest step 408b of the metal layer 408 from the first surface 205a of the semiconductor layer.

[0071] exist Figure 5 In an embodiment, the thickness of the passivation layer 509 is less than the thickness of the polysilicon layer 406 .

[0072] Figure 6 FIG. 6 is a schematic diagram of a terminal structure 600 of a semiconductor device according to an embodiment of the present application. Figure 2 The terminal structure 200 of the embodiment is similar, except that Figure 6In the embodiment, the polysilicon layer 606 extends outside the insulating layer 607-1 (first insulating layer) and the metal layer 608, and the edge region 606a of the polysilicon layer 606 passes through the metal layer 608 and is located below the passivation layer 609. Below the passivation layer 609 and at a distance from the edge of the metal layer 608, the edge region 606a of the polysilicon layer 606 is covered by the insulating layer 607-2 (second insulating layer). The insulating layer 607-2 covers a portion of the first surface 205a of the semiconductor layer and extends to cover the edge region 606a of the polysilicon layer 606. Due to the extension of the polysilicon layer 606, the lowest point of the passivation layer 609 is located on the polysilicon layer 606, and at the junction of the metal layer 608 and the passivation layer 609, the metal layer 608 forms a two-stage step. The metal layer 608 covers a portion of the polysilicon layer 606 and the insulating layer 607-1. The lowest step 608a of the metal layer 608 is located on the surface of the polysilicon layer 606, and the highest step 608b is located on the surface of the insulating layer 607-1. The two steps of the metal layer 608 are sequentially connected through other parts of the metal layer to form a whole.

[0073] exist Figure 6 In the embodiment, in a direction perpendicular to the first surface 205a of the semiconductor layer, below the lowest step 608a of the metal layer 608 is a stack of the polysilicon layer 606 and the insulating layer 205, and below the highest step 608b is a stack of the insulating layer 607-1, the polysilicon layer 606 and the insulating layer 205.

[0074] The height H1 of the lowest step 608a of the metal layer 608 from the first surface 205a of the semiconductor layer is the thickness of the metal layer 608 and the polysilicon layer 606. The height H1 of the lowest step 608a of the metal layer 608 from the first surface 205a of the semiconductor layer is the thickness of the metal layer 608 plus the thickness of the polysilicon layer 606. The height H3 of the highest step 608b of the metal layer 608 from the first surface 205a of the semiconductor layer is the thickness of the metal layer 608 plus the thickness of the polysilicon layer 606 and the thickness of the insulating layer 607-1. The highest height H4 of the passivation layer 609 from the first surface 205a of the semiconductor layer is the thickness of the passivation layer 509 plus the thickness of the metal layer 608 and the thickness of the polysilicon layer 606. Figure 6 In the embodiment, the highest height H4 of the passivation layer 609 from the first surface 205a of the semiconductor layer is smaller than the highest height of the metal layer 608, ie, smaller than the height H3 of the highest step 608b of the metal layer 608 from the first surface 205a of the semiconductor layer.

[0075] exist Figure 6 In the embodiment, the height difference between the lowest step 608a and the highest step 608b of the metal layer 608 is equal to the thickness of the insulating layer 607-1. The thickness of the passivation layer 609 is less than the thickness of the insulating layer 607-1.

[0076] Figure 7 FIG. 7 is a schematic diagram of a terminal structure 700 of a semiconductor device according to an embodiment of the present application. Figure 2 The terminal structure 200 of the embodiment is similar, except that Figure 7 In the embodiment, the semiconductor layer first surface 204a is the surface of the insulating layer 204. That is, in Figure 7 In the embodiment, the junction of the metal layer 708 and the passivation layer 709 is located above the insulating layer 204. The polysilicon layer 706 covers a portion of the first surface 204a of the semiconductor layer, that is, a portion of the insulating layer 204. The insulating layer 707-1 (first insulating layer) covers a portion of the polysilicon layer 706, exposing an edge region 706a of the polysilicon layer 706, thereby forming a step structure on the first surface 204a of the semiconductor layer, so that the metal layer 708 covered thereon also forms a corresponding step structure.

[0077] exist Figure 7 In the embodiment, in a direction perpendicular to the first surface 204a of the semiconductor layer, below the lowest step 708a of the metal layer 708 is the insulating layer 204, below the middle step 708c is the stack of the polysilicon layer 706 and the insulating layer 204, and below the highest step 708b is the stack of the insulating layer 707-1, the polysilicon layer 706, and the insulating layer 204.

[0078] exist Figure 7 In the embodiment, the height H1 of the lowest step 708a of the metal layer 708 from the first surface 204a of the semiconductor layer is the thickness of the metal layer 708. The height H2 of the middle step 708c of the metal layer 708 from the first surface 204a of the semiconductor layer is the thickness of the metal layer 708 plus the thickness of the polysilicon layer 706. The height H3 of the highest step 708b of the metal layer 708 from the first surface 204a of the semiconductor layer is the thickness of the metal layer 708 plus the thickness of the insulating layer 707-1 and the thickness of the polysilicon layer 706.

[0079] exist Figure 7 In the embodiment, the height difference between the lowest step 708a and the middle step 708c of the metal layer 708 is equal to the thickness of the polysilicon layer 706, the height difference between the middle step 708c and the highest step 708b is equal to the thickness of the insulating layer 707-1, and the height difference between the lowest step 708a and the highest step 708b is equal to the thickness of the polysilicon layer 706 superimposed on the thickness of the insulating layer 707-1.

[0080] exist Figure 7In the embodiment, the passivation layer 709 covers the first surface 204a of the semiconductor layer not covered by the metal layer 708, and extends to cover a portion of the lowest step 708a of the metal layer 708. The highest height H4 of the passivation layer 209 from the first surface 204a of the semiconductor layer is the thickness of the metal layer 708 plus the thickness of the passivation layer 709. Figure 7 In the embodiment, the highest height H4 of the passivation layer 709 from the first surface 204a of the semiconductor layer is smaller than the highest height of the metal layer 708, ie, smaller than the height H3 of the highest step 708b of the metal layer 708 from the first surface 204a of the semiconductor layer.

[0081] exist Figure 7 In an embodiment, the thickness of the passivation layer 709 is less than the sum of the thickness of the polysilicon layer 706 and the thickness of the insulating layer 707 - 1 .

[0082] Figure 8 FIG. 8 is a schematic diagram of a terminal structure 800 of a semiconductor device according to an embodiment of the present application. Figure 7 The terminal structure 700 of the embodiment is similar, except that Figure 8 In the embodiment, after the passivation layer 809 covers the lowest step 708 a of the metal layer 708 , it further extends to cover the middle step 708 c of the metal layer 708 .

[0083] exist Figure 8 In the embodiment, the maximum height H4 of the passivation layer 809 from the first surface 204a of the semiconductor layer is the thickness of the passivation layer 809 plus the thickness of the metal layer 708 and the thickness of the polysilicon layer 706. Figure 8 In the embodiment, the highest height H4 of the passivation layer 809 from the first surface 204a of the semiconductor layer is smaller than the highest height of the metal layer 708, ie, smaller than the height H3 of the highest step 708b of the metal layer 708 from the first surface 204a of the semiconductor layer.

[0084] exist Figure 8 In an embodiment, the thickness of the passivation layer 809 is less than the thickness of the insulating layer 707 - 1 .

[0085] Fig. 9 FIG. 9 is a schematic diagram of a terminal structure 900 of a semiconductor device according to an embodiment of the present application. Figure 7 The terminal structure 700 of the embodiment is similar, except that Fig. 9In the embodiment, the insulating layer 907-1 (first insulating layer) completely covers the polysilicon layer 906, and after covering the polysilicon layer 906, continues to extend to the first surface 204a of the semiconductor layer at the edge of the polysilicon layer 906, forming a step structure. That is, the first surface 204a of the semiconductor layer, the edge region 907-1a of the insulating layer 907-1, and the stack of the polysilicon layer 906 and the insulating layer 907-1 form a step structure, so that the metal layer 908 covered thereon also forms a corresponding step structure.

[0086] exist Fig. 9 In the embodiment, in a direction perpendicular to the first surface 204a of the semiconductor layer 201, below the lowest step 908a of the metal layer 908 is the insulating layer 204, below the middle step 908c is the stack of the insulating layer 907-1 and the insulating layer 204, and below the highest step 908b is the stack of the insulating layer 907-1, the polysilicon layer 906 and the insulating layer 204.

[0087] exist Fig. 9 In the embodiment, the height H1 of the lowest step 908a of the metal layer 908 from the first surface 204a of the semiconductor layer is the thickness of the metal layer 908. The height H2 of the middle step 908c of the metal layer 908 from the first surface 204a of the semiconductor layer is the thickness of the metal layer 908 plus the thickness of the insulating layer 907-1. The height H3 of the highest step 908b of the metal layer 908 from the first surface 204a of the semiconductor layer is the thickness of the metal layer 908 plus the thickness of the insulating layer 907-1 and the thickness of the polysilicon layer 906.

[0088] exist Fig. 9 In the embodiment, the height difference between the lowest step 908a and the middle step 908c of the metal layer 908 is equal to the thickness of the insulating layer 907-1, the height difference between the middle step 908c and the highest step 908b is equal to the thickness of the polysilicon layer 906, and the height difference between the lowest step 908a and the highest step 908b is equal to the thickness of the polysilicon layer 906 superimposed on the thickness of the insulating layer 907-1.

[0089] exist Fig. 9 In the embodiment, the passivation layer 709 covers the first surface 204a of the semiconductor layer not covered by the metal layer 908, and extends to cover a portion of the lowest step 908a of the metal layer 908. The highest height H4 of the passivation layer 709 from the first surface 204a of the semiconductor layer is the thickness of the metal layer 908 plus the thickness of the passivation layer 709. Fig. 9 In the embodiment, the highest height H4 of the passivation layer 709 from the first surface 204a of the semiconductor layer is smaller than the highest height of the metal layer 908, ie, smaller than the height H3 of the highest step 908b of the metal layer 908 from the first surface 204a of the semiconductor layer.

[0090] exist Fig. 9 In an embodiment, the thickness of the passivation layer 709 is less than the sum of the thickness of the polysilicon layer 906 and the thickness of the insulating layer 907 - 1 .

[0091] Fig.10 FIG. 1 is a schematic structural diagram of a terminal structure 1000 of a semiconductor device according to an embodiment of the present application. Fig.10 FIG. 1 is a schematic diagram of a terminal structure 1000 of a semiconductor device according to an embodiment of the present application. Fig. 9 The terminal structure 900 of the embodiment is similar, except that Fig.10 In the embodiment, after the passivation layer 1009 covers the lowest step 908 a of the metal layer 908 , it further extends to cover the middle step 908 c of the metal layer 908 .

[0092] exist Fig.10 In the embodiment, the highest height H4 of the passivation layer 1009 from the first surface 204a of the semiconductor layer is the thickness of the passivation layer 1009 plus the thickness of the metal layer 908 and the thickness of the insulating layer 907-1. Fig.10 In the embodiment, the highest height H4 of the passivation layer 1009 from the first surface 204a of the semiconductor layer is smaller than the highest height of the metal layer 908, ie, smaller than the height H3 of the highest step 908b of the metal layer 908 from the first surface 204a of the semiconductor layer.

[0093] exist Fig.10 In an embodiment, the thickness of the passivation layer 1009 is less than the thickness of the polysilicon layer 906 .

[0094] Fig.11 FIG. 1 is a schematic diagram of a terminal structure 1100 of a semiconductor device according to an embodiment of the present application. Figure 7 The terminal structure 700 of the embodiment is similar, except that Fig.11In the figure, the polysilicon layer 1106 extends outside the insulating layer 1107-1 (first insulating layer) and the metal layer 1108, and the edge region 1106a of the polysilicon layer 1106 passes through the metal layer 1108 and is located below the passivation layer 1109. Below the passivation layer 1109 and at a distance from the edge of the metal layer 1108, the edge region 1106a of the polysilicon layer 1106 is covered by the insulating layer 1107-2 (second insulating layer). The insulating layer 1107-2 covers a portion of the first surface 204a of the semiconductor layer and extends to cover the edge region 1106a of the polysilicon layer 1106. Due to the extension of the polysilicon layer 1106, the lowest point of the passivation layer 1109 is located on the polysilicon layer 1106, and at the junction of the metal layer 1108 and the passivation layer 1109, the metal layer 1108 forms a two-stage step. The metal layer 1108 covers the polysilicon layer 1106 and the insulating layer 1107-1. The lowest step 1108a of the metal layer 1108 is located on the surface of the polysilicon layer 1106, and the highest step 1108b is located on the surface of the insulating layer 1107-1. The two steps of the metal layer 1108 are sequentially connected through other parts of the metal layer to form a whole.

[0095] exist Fig.11 In the embodiment, in a direction perpendicular to the first surface 204a of the semiconductor layer, below the lowest step 1108a of the metal layer 1108 is a stack of the polysilicon layer 1106 and the insulating layer 204, and below the highest step 1108b is a stack of the insulating layer 1107-1, the polysilicon layer 1106 and the insulating layer 204.

[0096] The height H1 of the lowest step 1108a of the metal layer 1108 from the first surface 204a of the semiconductor layer is the thickness of the metal layer 1108 and the polysilicon layer 1106. The height H1 of the lowest step 1108a of the metal layer 1108 from the first surface 204a of the semiconductor layer is the thickness of the metal layer 1108 plus the thickness of the polysilicon layer 1106. The height H3 of the highest step 1108b of the metal layer 1108 from the first surface 204a of the semiconductor layer is the thickness of the metal layer 1108 plus the thickness of the polysilicon layer 1106 and the thickness of the insulating layer 1107-1. The highest height H4 of the passivation layer 1109 from the first surface 204a of the semiconductor layer is the thickness of the passivation layer 1109 plus the thickness of the metal layer 1108 and the thickness of the polysilicon layer 1106. Fig.11 In the embodiment, the highest height H4 of the passivation layer 1109 from the first surface 204a of the semiconductor layer is smaller than the highest height of the metal layer 1108, ie, smaller than the height H3 of the highest step 1108b of the metal layer 1108 from the first surface 204a of the semiconductor layer.

[0097] exist Fig.11In the embodiment, the height difference between the lowest step 1108a and the highest step 1108b of the metal layer 1108 is equal to the thickness of the insulating layer 1107-1. The thickness of the passivation layer 1109 is less than the thickness of the insulating layer 1107-1.

[0098] Fig.12 FIG. 1 is a schematic diagram of a terminal structure 1200 of a semiconductor device according to an embodiment of the present application. Figure 7 The terminal structure 700 of the embodiment is similar, except that Fig.12 In the embodiment, the terminal structure 1200 includes an insulating layer 1207-2 (second insulating layer) located between the passivation layer 1209 and the insulating layer 204, and an insulating layer 1205 (third insulating layer) is sandwiched between the insulating layer 1207-2 and the epitaxial layer 203. In one embodiment, the insulating layer 1205 is a field oxide, and is covered on the surface of the epitaxial layer 203 together with the insulating layer 204, and the two are in contact on the surface of the epitaxial layer 203. The thickness of the insulating layer 1205 is greater than the thickness of the insulating layer 204, so that the insulating layer 1207-2 and the passivation layer 1209 covered thereon are higher than the insulating layer 1207-2 and the passivation layer 1209 covered on the surface of the insulating layer 204.

[0099] In the embodiment of the present application, the sum of the thicknesses of the insulating layer 1205 and the insulating layer 1207 - 2 is less than the sum of the thicknesses of the metal layer 708 and the insulating layer 204 , so the highest height of the passivation layer 1209 is still at a position where it covers the metal step.

[0100] exist Fig.12 In an embodiment, the thickness of the passivation layer 1209 is less than the sum of the thickness of the polysilicon layer 706 and the thickness of the insulating layer 707 - 1 .

[0101] Fig.13 FIG. 1 is a schematic diagram of a terminal structure 1300 of a semiconductor device according to an embodiment of the present application. Fig.12 The terminal structure 1200 of the embodiment is similar, except that Fig.13 In the embodiment, after the passivation layer 1309 covers the lowest step 708 a of the metal layer 708 , it further extends to cover the middle step 708 c of the metal layer 708 .

[0102] exist Fig.13 In the embodiment, the maximum height H4 of the passivation layer 1309 from the first surface 204a of the semiconductor layer is the thickness of the passivation layer 1309 plus the thickness of the metal layer 708 and the thickness of the polysilicon layer 706. Fig.13In the embodiment, the highest height H4 of the passivation layer 1309 from the first surface 204a of the semiconductor layer is smaller than the highest height of the metal layer 708, ie, smaller than the height H3 of the highest step 708b of the metal layer 708 from the first surface 204a of the semiconductor layer.

[0103] exist Fig.13 In an embodiment, the thickness of the passivation layer 1309 is less than the thickness of the insulating layer 707 - 1 .

[0104] Fig.14 FIG. 1 is a schematic diagram of a terminal structure 1400 of a semiconductor device according to an embodiment of the present application. Fig.12 The terminal structure 1200 of the embodiment is similar, except that Fig.14 In the embodiment, the insulating layer 1407-1 (first insulating layer) completely covers the polysilicon layer 1406, and after covering the polysilicon layer 1406, continues to extend to the first surface 204a of the semiconductor layer at the edge of the polysilicon layer 1406, forming a step structure. That is, the first surface 204a of the semiconductor layer, the edge region 1407-1a of the insulating layer 1407-1, and the stack of the polysilicon layer 1406 and the insulating layer 1407-1 form a step structure, so that the metal layer 1408 covered thereon also forms a corresponding step structure.

[0105] exist Fig.14 In the embodiment, in a direction perpendicular to the first surface 204a of the semiconductor layer 201, below the lowest step 1408a of the metal layer 1408 is the insulating layer 204, below the middle step 1408c is the stack of the insulating layer 1407-1 and the insulating layer 204, and below the highest step 1408b is the stack of the insulating layer 1407-1, the polysilicon layer 1406 and the insulating layer 204.

[0106] exist Fig.14 In the embodiment, the height H1 of the lowest step 1408a of the metal layer 1408 from the first surface 204a of the semiconductor layer is the thickness of the metal layer 1408. The height H2 of the middle step 1408c of the metal layer 1408 from the first surface 204a of the semiconductor layer is the thickness of the metal layer 1408 plus the thickness of the insulating layer 1407-1. The height H3 of the highest step 1408b of the metal layer 1408 from the first surface 204a of the semiconductor layer is the thickness of the metal layer 1408 plus the thickness of the insulating layer 1407-1 and the thickness of the polysilicon layer 1406.

[0107] exist Fig.14In the embodiment, the height difference between the lowest step 1408a and the middle step 1408c of the metal layer 1408 is equal to the thickness of the insulating layer 1407-1, the height difference between the middle step 1408c and the highest step 1408b is equal to the thickness of the polysilicon layer 1406, and the height difference between the lowest step 1408a and the highest step 1408b is equal to the thickness of the polysilicon layer 1406 superimposed on the thickness of the insulating layer 1407-1.

[0108] exist Fig.14 In the embodiment, the passivation layer 1409 covers the first surface 204a of the semiconductor layer not covered by the metal layer 1408, and extends to cover a portion of the lowest step 14908a of the metal layer 1408. The highest height H4 of the passivation layer 1409 from the first surface 204a of the semiconductor layer is the thickness of the metal layer 1408 plus the thickness of the passivation layer 1409. Fig.14 In the embodiment, the highest height H4 of the passivation layer 1409 from the first surface 204a of the semiconductor layer is smaller than the highest height of the metal layer 1408, ie, smaller than the height H3 of the highest step 1408b of the metal layer 1408 from the first surface 204a of the semiconductor layer.

[0109] exist Fig.14 In the embodiment, the thickness of the passivation layer 1409 is less than the sum of the thickness of the polysilicon layer 1406 and the thickness of the insulating layer 1407-1. The sum of the thickness of the metal layer 1408 and the insulating layer 204 is greater than the sum of the thickness of the insulating layer 1407-2 (the second insulating layer) and the insulating layer 1205, so that the highest point of the passivation layer 1409 is located above the metal layer 1408.

[0110] Fig.15 FIG. 1 is a schematic diagram of a terminal structure 1500 of a semiconductor device according to an embodiment of the present application. Fig.14 The terminal structure 1400 of the embodiment is similar, except that Fig.15 In the embodiment, after the passivation layer 1509 covers the lowest step 1408 a of the metal layer 1408 , it further extends to cover the middle step 1408 c of the metal layer 1408 .

[0111] exist Fig.15 In the embodiment, the highest height H4 of the passivation layer 1509 from the first surface 204a of the semiconductor layer is the thickness of the passivation layer 1509 plus the thickness of the metal layer 1408 and the thickness of the insulating layer 1407-1. Fig.15 In the embodiment, the highest height H4 of the passivation layer 1509 from the first surface 204a of the semiconductor layer is smaller than the highest height of the metal layer 1408, ie, smaller than the height H3 of the highest step 1408b of the metal layer 1408 from the first surface 204a of the semiconductor layer.

[0112] exist Fig.15 In the embodiment, the thickness of the passivation layer 1509 is less than the thickness of the polysilicon layer 1406. The sum of the thicknesses of the metal layer 1408, the insulating layer 204, and the insulating layer 1407-1 is greater than the sum of the thicknesses of the insulating layer 1407-2 and the insulating layer 1205, so that the highest point of the passivation layer 1409 is located above the metal layer 1408.

[0113] Fig.16 FIG. 1 is a schematic diagram of a terminal structure 1600 of a semiconductor device according to an embodiment of the present application. Fig.11 The terminal structure 1100 of the embodiment is similar, except that Fig.16 In the embodiment, the terminal structure 1600 includes an insulating layer 1607-2 (second insulating layer) located between the passivation layer 1609 and the insulating layer 204, and an insulating layer 1205 is sandwiched between the insulating layer 1607-2 and the epitaxial layer 203. The insulating layer 1205 and the insulating layer 204 cover the surface of the epitaxial layer 203 together, and the two are in contact with each other on the surface of the epitaxial layer 203. The thickness of the insulating layer 1205 is greater than that of the insulating layer 204, so that the insulating layer 1607-2 and the passivation layer 1609 covering it are higher than the insulating layer 1607-2 and the passivation layer 1609 covering the surface of the insulating layer 204.

[0114] In the embodiment of the present application, the sum of the thicknesses of the insulating layer 1205 and the insulating layer 1607 - 2 is less than the sum of the thicknesses of the metal layer 1608 , the insulating layer 204 and the polysilicon layer 1606 , so the highest height of the passivation layer 1609 is still at a position where it covers the metal step.

[0115] exist Fig.16 In an embodiment, the thickness of the passivation layer 1609 is less than the thickness of the insulating layer 1607 - 1 .

[0116] It should be understood that the edge region described in the embodiments of the present application represents the edge of the corresponding material layer and the partial region connected to the edge.

[0117] The embodiments of the present application are described above, and these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A terminal structure of a semiconductor device, comprising: A semiconductor layer having a semiconductor layer first surface; a polysilicon layer, partially covering the first surface of the semiconductor layer; a first insulating layer, covering the polysilicon layer; a metal layer, covering at least the first insulating layer and the polysilicon layer, wherein the metal layer forms at least two steps on the first surface of the semiconductor layer, wherein the at least two steps include a highest step and a lowest step; as well as The passivation layer covers the first surface of the semiconductor layer not covered by the metal layer, and extends to cover a portion of the lowest step of the metal layer. 2 . The terminal structure of a semiconductor device as claimed in claim 1 , wherein the metal layer further comprises an intermediate step. 3 . The terminal structure of a semiconductor device as claimed in claim 2 , wherein the passivation layer extends to cover the lowest step of the metal layer, and further extends to cover a partial area of ​​the middle step of the metal layer.

4. The terminal structure of the semiconductor device according to claim 1, wherein: The first insulating layer covers a partial area of ​​the polysilicon layer, and the edge area of ​​the polysilicon layer is not covered by the first insulating layer. The lowest step of the metal layer covers the first surface of the semiconductor layer, and the highest step of the metal layer covers the first insulating layer and is located above the stack of the first insulating layer and the polysilicon layer. The metal layer also includes an intermediate step covering the edge area of ​​the polysilicon layer. The highest step, the intermediate step and the lowest step of the metal layer are connected in sequence through other parts of the metal layer. 5 . The terminal structure of a semiconductor device as claimed in claim 4 , wherein the sum of the thicknesses of the first insulating layer and the polysilicon layer is greater than the thickness of the passivation layer. 6 . The terminal structure of a semiconductor device as claimed in claim 4 , wherein the passivation layer extends to cover the lowest step of the metal layer, and further extends to cover a portion of the middle step of the metal layer. 7 . The terminal structure of a semiconductor device as claimed in claim 6 , wherein a thickness of the first insulating layer is greater than a thickness of the passivation layer.

8. The terminal structure of the semiconductor device according to claim 1, wherein: The first insulating layer covers the entire area of ​​the polysilicon layer, and the edge area of ​​the first insulating layer extends to cover the first surface of the semiconductor layer, the lowest step of the metal layer covers the first surface of the semiconductor layer, the highest step of the metal layer covers the first insulating layer and is located above the stack of the first insulating layer and the polysilicon layer, the metal layer also includes an intermediate step covering the edge area of ​​the first insulating layer, and the highest step, the intermediate step and the lowest step of the metal layer are connected in sequence through other parts of the metal layer. 9 . The terminal structure of a semiconductor device as claimed in claim 8 , wherein the passivation layer extends to cover the lowest step of the metal layer, and further extends to cover a portion of the middle step of the metal layer. 10 . The terminal structure of a semiconductor device as claimed in claim 9 , wherein a thickness of the polysilicon layer is greater than a thickness of the passivation layer.

11. The terminal structure of a semiconductor device according to claim 1, wherein: The first insulating layer covers a partial area of ​​the polysilicon layer, and the polysilicon layer extends between the lowest step of the metal layer and the first surface of the semiconductor layer, and between the passivation layer and the first surface of the semiconductor layer, the lowest step of the metal layer covers the polysilicon layer, the highest step of the metal layer covers the first insulating layer and is located above the stack of the first insulating layer and the polysilicon layer, and the highest step and the lowest step of the metal layer are connected through other parts of the metal layer.

12. The terminal structure of a semiconductor device according to any one of claims 1 to 11, wherein: A second insulating layer is further included between the passivation layer and the first surface of the semiconductor layer. The second insulating layer is completely covered by the passivation layer and does not overlap with the metal layer in a direction perpendicular to the first surface of the semiconductor layer.

13. The terminal structure of a semiconductor device according to claims 1 to 11, wherein the semiconductor layer comprises: substrate layer; an epitaxial layer, located on the substrate layer; as well as a third insulating layer, located on the epitaxial layer, and forming a stacked structure with the epitaxial layer and the substrate layer; The first surface of the semiconductor layer includes an outer surface of the third insulating layer, and the outer surface of the third insulating layer is parallel to and not in contact with the surface of the epitaxial layer.

14. The terminal structure of a semiconductor device according to claim 1, wherein the semiconductor layer comprises: substrate layer; an epitaxial layer, located on the substrate layer; as well as a fourth insulating layer, located on the epitaxial layer, and forming a stacked structure with the epitaxial layer and the substrate layer; The first surface of the semiconductor layer includes an outer surface of the fourth insulating layer, and the outer surface of the fourth insulating layer is parallel to and not in contact with the surface of the epitaxial layer.

15. The terminal structure of the semiconductor device according to claim 14, wherein: A second insulating layer is further included between the passivation layer and the first surface of the semiconductor layer. The second insulating layer is completely covered by the passivation layer and does not overlap with the metal layer in a direction perpendicular to the first surface of the semiconductor layer.

16. The terminal structure of a semiconductor device according to claim 15, wherein: A third insulating layer is further included between the second insulating layer and the epitaxial layer, and an edge of the third insulating layer is connected to an edge of the fourth insulating layer below the second insulating layer.

17. The terminal structure of a semiconductor device according to any one of claims 1 to 11, wherein: The thickness of the metal layer is greater than or equal to 0.5 μm.

18. The terminal structure of a semiconductor device according to any one of claims 1 to 11, wherein: The material of the metal layer includes any one of aluminum, silver, copper and gold, or a combination of at least two of them.

19. The terminal structure of a semiconductor device according to any one of claims 1 to 11, wherein the thickness of the second insulating layer is greater than or equal to 0.1 μm. 20 . The terminal structure of a semiconductor device according to claim 1 , wherein the thickness of the passivation layer is greater than or equal to 0.05 μm.

21. The terminal structure of a semiconductor device according to any one of claims 1 to 11, wherein the thickness of the polysilicon layer is greater than or equal to 0.1 μm.

22. The terminal structure of a semiconductor device according to any one of claims 1 to 11, wherein: The material of the passivation layer includes silicon oxide, silicon nitride or a stacked layer made of silicon oxide and silicon nitride.

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