3D IC self-adaptive heat dissipation structure based on shape memory alloy

Abstract

The invention discloses a shape memory alloy-based 3D IC self-adaptive heat dissipation structure, which comprises an upper cover plate, a first semiconductor device layer, a first liquid collection layer, a first fin layer, a second semiconductor device layer, a second liquid collection layer and a second fin layer, and is characterized in that the edge of each layer is provided with an inlet and an outlet; the first liquid collecting layer, the first fin layer, the second liquid collecting layer and the second fin layer are respectively provided with a concave cavity for guiding cooling liquid to flow, fin arrays are arranged on the concave cavity of the first fin layer and the concave cavity of the second fin layer, the fins are made of shape memory alloy, and when the change of the temperature of a heat source is sensed, the fin arrays are connected with the first fin layer and the second fin layer. The shape of the temperature-sensitive shape memory alloy is rapidly changed, so that the temperature-sensitive shape memory alloy is changed from a vertical state to a bending and twisting state, the size and the strength of vortexes near the fins are changed, and self-adaptive adjustment of the convection heat exchange coefficient of the channel wall surface is achieved accordingly. The micro-channel has the advantages that the local heat exchange coefficient of the micro-channel is automatically adjusted according to the working condition of a chip, and the working efficiency of the micro-channel is improved. And the high-heat-flux chip can be effectively cooled.

Description

Technical Field

[0001] The invention belongs to the technical field of three-dimensional stacked chip cooling, and in particular relates to a 3DIC adaptive heat dissipation structure based on shape memory alloy. Background Art

[0002] Three-dimensional stacked chip (3D IC) is an advanced integrated circuit technology that achieves higher integration and performance by stacking multiple chips together in the vertical direction. This technology can accommodate more functional units in a limited space, improve the performance and power efficiency of the chip, and reduce the size and complexity of the circuit board. Three-dimensional stacked chips have broad application prospects in cloud computing, artificial intelligence, the Internet of Things and other fields, and are regarded as one of the important directions for the development of integrated circuits in the future. However, due to factors such as small chip spacing, limited heat dissipation area and heat concentration, heat dissipation is difficult, and heat accumulation and hot spot concentration are prone to occur. Therefore, solving the heat dissipation problem of 3D IC is one of the key challenges to achieving its high performance and reliable operation.

[0003] Using a fin array heat sink to dissipate heat for 3D ICs is a common design. At present, the fin spoiler structure often adopts a fixed structural design. However, as the chip power continues to increase, the spoiler structure is relatively fixed, resulting in its local heat transfer coefficient being unable to respond to the changes in heat flux density and temperature at the local hot spot of the chip in a timely manner. The overall temperature field distribution uniformity is poor, so the high power at the chip hot spot can only be sacrificed to ensure the normal operation of the entire chip.

[0004] Based on the above considerations, if there is a heat sink with self-adjusting heat transfer coefficient that can adjust its internal turbulence structure according to the heat generation power and device distribution of the chip, so that the flow of the cooling medium and the enhanced heat transfer capacity are guided, then for various working conditions of high heat flux density chips, the use of this adaptive heat sink can make the heat dissipation of the chip more uniform, thereby improving the working efficiency and working life of the chip. Summary of the invention

[0005] In order to solve the above-mentioned deficiencies in the prior art, the purpose of the present invention is to provide a microchannel liquid cooling heat dissipation structure which can adaptively adjust the local heat transfer coefficient of the microchannel surface according to the 3DIC working condition. The structure includes a fin array made of shape memory alloy, which has the advantage of automatically adjusting the local heat transfer coefficient of the microchannel according to the chip working condition, and can effectively cool the high heat flux density chip.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] A 3D IC adaptive heat dissipation structure based on shape memory alloy, which includes, from top to bottom, an upper cover plate, a first semiconductor device layer, a first liquid collection layer, a first fin layer, a second semiconductor device layer, a second liquid collection layer, and a second fin layer. The upper cover plate, the first liquid collection layer, the first fin layer, the second liquid collection layer, and the second fin layer have corresponding length and width dimensions, and can be overlapped, aligned, and bonded in sequence from top to bottom.

[0008] The lower surface of the upper cover plate is provided with an upper cover plate groove, and the edge of the upper cover plate is provided with a first inlet and a first outlet;

[0009] The first liquid collection layer has a first liquid collection layer concave cavity on the lower surface, a second inlet and a second outlet are provided on the edge of the first liquid collection layer, the first semiconductor device layer is mechanically connected to the upper surface of the first liquid collection layer through its bottom microstructure, and the first semiconductor device layer is placed in the groove of the upper cover plate;

[0010] The upper surface of the first fin layer has a first fin layer cavity, a fin array is arranged on the first fin layer cavity, the lower surface of the first fin layer has a first fin layer groove, and a third inlet and a third outlet are arranged at the edge of the first fin layer;

[0011] The lower surface of the second liquid collection layer has a second liquid collection layer cavity, and the edge of the second liquid collection layer has a fourth inlet and a fourth outlet, the second semiconductor device layer is mechanically connected to the upper surface of the second liquid collection layer through its bottom microstructure, and the second semiconductor device layer is placed in the first fin layer groove;

[0012] The upper surface of the second fin layer is provided with a second fin layer cavity, a fin array is arranged on the second fin layer cavity, and a fifth inlet and a fifth outlet are provided at the edge of the second fin layer.

[0013] Furthermore, the length, width and height dimensions of the upper cover plate groove are greater than the corresponding length, width and height dimensions of the first semiconductor device layer, and the first inlet and the first outlet on the edge of the upper cover plate are not connected to the upper cover plate groove.

[0014] Furthermore, the upper surface of the first liquid collection layer is a smooth plane, and the second inlet and the second outlet on the edge of the first liquid collection layer are located at the vertical projection positions of the first inlet and the first outlet on the first liquid collection layer, respectively, and the second inlet and the second outlet are not connected to the concave cavity of the first liquid collection layer; the upper surface of the second liquid collection layer is a smooth plane, and the fourth inlet and the fourth outlet on the edge of the second liquid collection layer are located at the vertical projection positions of the third inlet and the third outlet on the second liquid collection layer, respectively, and the fourth inlet and the fourth outlet are not connected to the concave cavity of the second liquid collection layer.

[0015] Furthermore, the first semiconductor device layer is connected to the upper surface plane of the first liquid collection layer through its bottom microstructure by means of heating reflow soldering, and the second semiconductor device layer is connected to the upper surface plane of the second liquid collection layer through its bottom microstructure by means of heating reflow soldering.

[0016] Furthermore, a fin array is arranged at the core position of the first fin layer cavity, and the core position of the first fin layer cavity is the vertical projection area of ​​the first semiconductor device layer in the first fin layer cavity; a fin array is arranged at the core position of the second fin layer cavity, and the core position of the second fin layer cavity is the vertical projection area of ​​the second semiconductor device layer in the second fin layer cavity.

[0017] Furthermore, the length, width and height dimensions of the groove of the first fin layer are larger than the corresponding length, width and height dimensions of the second semiconductor device layer; the third inlet and the third outlet on the first fin layer are respectively located at the vertical projection positions of the second inlet and the second outlet on the first fin layer; the third inlet and the third outlet are interconnected with the concave cavity of the first fin layer; the third inlet and the third outlet are not connected with the groove of the first fin layer; the fifth inlet and the fifth outlet on the second fin layer are respectively located at the vertical projection positions of the fourth inlet and the fourth outlet on the second fin layer; the fifth inlet and the fifth outlet are interconnected with the concave cavity of the second fin layer.

[0018] Furthermore, the first fin layer cavity and the second fin layer cavity are designed with tenons, and the ribs in the fin array are installed in the tenons. The ribs are made of shape memory alloy, and the straight ribs can be transformed into a large pitch twisted state. The final linear pitch bending angle of the rib is 57 to 63°, that is, the angle between the upper edge and the lower edge of the rib is 57 to 63°.

[0019] Furthermore, the first inlet, the second inlet, the third inlet, the fourth inlet and the fifth inlet are interconnected from top to bottom to form a liquid inlet passage of the cooling structure, and the cooling medium enters from the external micropump via the first inlet, and the fifth outlet, the fourth outlet, the third outlet, the second outlet and the first outlet are interconnected from bottom to top to form a liquid outlet passage, and the cooling medium leaves the heat dissipation structure through the first outlet.

[0020] Furthermore, the rib has a height ranging from 0.5 to 2 mm, a width ranging from 1 to 2 mm, a thickness of 0.2 to 0.8 mm, a mortise depth of 1 mm, and the mortise width and thickness are consistent with the rib size.

[0021] Furthermore, the fin array is globally arranged in sequence or globally staggered or partially in reverse order, and the arrangement spacing of the fin array is 1 to 3 mm.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] 1. The present invention provides a 3D IC adaptive heat dissipation structure based on shape memory alloy, which replaces the traditional in-line fin structure with a memory alloy fin array arrangement structure. Its typical characteristics are that when the heat source temperature is higher than the phase transition temperature of the memory alloy, the fins quickly change from the in-line state to the twisted large pitch state, that is, the degree of distortion increases, so that the induced vortex strength increases and the heat exchange level improves; when the temperature is lower than the phase transition temperature of the memory alloy, the twisted fins will quickly return from the large pitch state to the in-line state, that is, the degree of distortion decreases, the vortex strength weakens, and the heat exchange level decreases. Through this structure, the heat generated by the high-temperature heat source can be taken away in time, and the uniformity of the temperature field of the entire chip can be effectively guaranteed.

[0024] 2. The fin array structure provided by the present invention has good flexibility, that is, the channel does not rely on the conventional fixed flow channel structure, but forms a plurality of flow channels by means of the arrangement and combination of the fins. At the same time, the arrangement of the fins has many combination schemes, including the arrangement order (sequential arrangement, cross arrangement, partial cross arrangement, etc.), arrangement density, etc., and a variety of enhanced heat exchange schemes can be realized for different cooling needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is an exploded schematic diagram of a 3D IC adaptive heat dissipation structure based on shape memory alloy according to the present invention;

[0026] Figure 2 This is a cross-sectional schematic diagram of a 3D IC adaptive heat dissipation structure based on shape memory alloy according to the present invention;

[0027] Figure 3 A schematic diagram of an upper cover plate of a 3D IC adaptive heat dissipation structure based on shape memory alloy according to the present invention;

[0028] Figure 4 It is a schematic diagram of the first liquid collection layer of a 3D IC adaptive heat dissipation structure based on shape memory alloy of the present invention;

[0029] Figure 5 This is a schematic diagram of the first fin layer of a 3D IC adaptive heat dissipation structure based on shape memory alloy according to the present invention;

[0030] Figure 6 It is a schematic diagram of the second liquid collection layer of a 3D IC adaptive heat dissipation structure based on shape memory alloy of the present invention;

[0031] Figure 7 This is a schematic diagram of a second fin layer of a 3D IC adaptive heat dissipation structure based on shape memory alloy according to the present invention;

[0032] Figure 8It is a schematic diagram of an embodiment of adjusting the fin arrangement of the first fin layer and the second fin layer of a 3D IC adaptive heat dissipation structure based on shape memory alloy according to the present invention;

[0033] Fig. 9 It is a schematic diagram of an embodiment of adjusting the arrangement of fins in a 3D IC adaptive heat dissipation structure based on shape memory alloy according to the present invention;

[0034] Fig.10 The variation law of the channel Nusselt number Nu and the pressure drop Δp with the Reynolds number at different fin heights and torsion angles of a 3D IC adaptive heat dissipation structure based on shape memory alloy of the present invention;

[0035] Fig.11 The temperature and heat transfer coefficient distribution diagram of the heat source surface of two types of fin arrays of a 3D IC adaptive heat dissipation structure based on shape memory alloy of the present invention.

[0036] In the figure, 1-upper cover plate, 101-first inlet, 102-first outlet, 103-upper cover plate groove, 2-first semiconductor device layer, 3-first liquid collection layer, 301-second inlet, 302-second outlet, 303-first liquid collection layer cavity, 4-first rib layer, 401-third inlet, 402-third outlet, 403-first rib layer cavity, 404-first rib layer groove, 5-second semiconductor device layer, 6-second liquid collection layer, 601-fourth inlet, 602-fourth outlet, 603-second liquid collection layer cavity, 7-second rib layer, 701-fifth inlet, 702-fifth outlet, 703-second rib layer cavity, 8-fin array, 9-fins, 10-mortise and tenon. DETAILED DESCRIPTION

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be selected and briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0038] It should be noted that the following descriptions are exemplary and are intended to provide further description of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present application belongs.

[0039] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. It should be noted that the technical solutions of the embodiments described below are only for some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] like Figure 1-7 As shown, a 3D IC adaptive heat dissipation structure based on shape memory alloy includes an upper cover plate 1, a first semiconductor device layer 2, a first liquid collection layer 3, a first fin layer 4, a second semiconductor device layer 5, a second liquid collection layer 6, and a second fin layer 7.

[0041] The length and width of the upper cover plate 1, the first liquid collection layer 3, the first fin layer 4, the second liquid collection layer 6, and the second fin layer 7 are equal and can be overlapped and aligned from top to bottom. The above layers are bonded and sealed in order from top to bottom.

[0042] A rectangular upper cover groove 103 is designed on the lower surface of the upper cover 1, and its height and length and width dimensions are slightly larger than the length, width and height dimensions corresponding to the first semiconductor device layer 2. A first inlet 101 and a first outlet 102 are designed on the edge of the upper cover 1. The first inlet 101 and the first outlet 102 are located in the edge area of ​​the upper cover 1, and are not connected to the rectangular upper cover groove 103, so as to prevent the cooling medium in the first inlet 11 and the first outlet 12 from entering the upper cover groove 103 and causing damage to the first semiconductor device layer 2.

[0043] The upper surface of the first liquid collection layer 3 is a smooth plane, and the lower surface has a first liquid collection layer cavity 303 and an edge. A second inlet 301 and a second outlet 302 are designed on the edge of the first liquid collection layer 3, and their positions are respectively the vertical projection positions of the first inlet 101 and the first outlet 102 on the first liquid collection layer 3, and the second inlet 301 and the second outlet 302 are not connected to the first liquid collection layer cavity 303. The first semiconductor device layer 2 is connected to the upper surface plane of the first liquid collection layer 3 through its bottom microstructure (such as micro-bumps, etc.) by heating and reflow soldering, so that the micro-bumps melt and metallurgically bond with the upper surface pad of the first liquid collection layer 3 to form a firm mechanical connection and provide a good heat conduction path. At the same time, due to the uneven small gap between the first semiconductor device layer 2 and the upper surface of the first liquid collection layer 3, the heat conduction is further enhanced by matching the thermal interface material. After the first semiconductor device layer 2 is matched and connected with the first liquid collection layer 3, it is placed in the groove 103 of the upper cover plate to protect it from external mechanical stress, environmental pollution and humidity. The outer edge of the upper cover plate groove 103 is bonded to the upper surface plane of the first liquid collection layer 3 .

[0044] The upper surface of the first fin layer 4 has a first fin layer cavity 403 and an edge, and a plurality of fin arrays 8 made of shape memory alloy are arranged at the core position of the first fin layer cavity 403. The core position of the first fin layer cavity 403 is the vertical projection area of ​​the first semiconductor device layer 2 in the first fin layer cavity 403. The edge of the first fin layer cavity 403 is bonded with the edge of the first liquid collection layer cavity 303, and the first fin layer cavity 403 and the first liquid collection layer cavity 303 are enclosed to form a first microchannel including the fin array 9.

[0045] A rectangular first fin layer groove 404 is designed on the lower surface of the first fin layer 4, and the height and length and width of the first fin layer groove 404 are slightly larger than the length, width and height of the second semiconductor device layer 5. A third inlet 401 and a third outlet 402 are designed at the edge of the first fin layer 4, and their positions are respectively the vertical projection positions of the second inlet 301 and the second outlet 302 on the first fin layer 4. The third inlet 401 and the third outlet 402 are interconnected with the first fin layer cavity 403 on the upper surface of the first fin layer 4, so that the cooling medium can enter the first microchannel. The third inlet 401 and the third outlet 402 are not connected to the first fin layer groove 404, so as to prevent the cooling medium from entering the groove and damaging the second semiconductor device layer 5.

[0046] The upper surface of the second liquid collection layer 6 is a smooth plane, and the lower surface has a second liquid collection layer cavity 603 and an edge. A fourth inlet 601 and a fourth outlet 602 are designed on the edge of the second liquid collection layer 6, and their positions are respectively the vertical projection positions of the third inlet 401 and the third outlet 402 on the second liquid collection layer 6, and the fourth inlet 601 and the fourth outlet 602 are not connected to the second liquid collection layer cavity 603. The second semiconductor device layer 5 is connected to the upper surface plane of the second liquid collection layer 6 by heating and reflow soldering through its bottom microstructure (such as micro-bumps, etc.), so that the micro-bumps melt and metallurgically bond with the upper surface pad of the second liquid collection layer 6 to form a firm mechanical connection, while providing a good heat conduction path. At the same time, due to the uneven small gap between the second semiconductor device layer 5 and the upper surface of the second liquid collection layer 6, the heat conduction is further enhanced by matching the thermal interface material. After the second semiconductor device layer 5 is matched and connected with the second liquid collection layer 6, it is placed in the first fin layer groove 404 to protect it from external mechanical stress, environmental pollution and humidity. The outer edge of the first fin layer groove 404 is bonded to the upper surface plane of the second liquid collection layer 6 .

[0047] The upper surface of the second fin layer 7 has a second fin layer cavity 703 and an edge, and a plurality of fin arrays 8 made of shape memory alloy are arranged at the core position of the second fin layer cavity 703. The core position of the second fin layer cavity 703 refers to the vertical projection area of ​​the second semiconductor device layer 5 in the second fin layer cavity 703. The edge of the second fin layer cavity 703 is bonded with the edge of the second liquid collection layer cavity 603, and the second fin layer cavity 703 and the second liquid collection layer cavity 603 are enclosed to form a second microchannel including the fin array 8.

[0048] A fifth inlet 701 and a fifth outlet 702 are designed at the edge of the second fin layer 7, and the positions of the fifth inlet 701 and the fifth outlet 702 are respectively the vertical projection positions of the fourth inlet 601 and the fourth outlet 602 of the second fin layer 7. The fourth inlet 601 and the fourth outlet 602 are interconnected with the second fin layer cavity 703, so that the cooling medium can enter the second microchannel.

[0049] The first inlet 101, the second inlet 301, the third inlet 401, the fourth inlet 601 and the fifth inlet 701 are interconnected from top to bottom in the vertical direction, so that the cooling medium can enter the microchannels between the layers from the external micropump via the first inlet 101. The fifth outlet 702, the fourth outlet 602, the third outlet 402, the second outlet 302 and the first outlet 102 are interconnected from bottom to top in the vertical direction, so that the cooling medium can leave the heat dissipation structure from the microchannels between the layers via the first outlet 102 and return to the constant temperature water tank through the pipeline for the next cycle.

[0050] The fins 9 in the fin array 8 in the first fin layer 4 and the second fin layer 7 are made of shape memory alloy, and need to be trained before use, so that when the working temperature reaches the phase transition temperature, the straight fins can be transformed into a large pitch twisted state.

[0051] The final linear pitch bending angle of the rib 9 is 57-63°, that is, the angle between the upper edge and the lower edge of the rib 9 is 57-63°.

[0052] The size of the fin 9 is limited by the size of the microchannel, and its height ranges from 0.5 to 2 mm, its width ranges from 1 to 2 mm, and its thickness ranges from 0.2 to 0.8 mm.

[0053] At the core position of the first fin layer cavity 403 and the second fin layer cavity 703, a plurality of mortises 10 with a depth of 1 mm, a width and a thickness consistent with the size of the fin 9, and a tolerance fit of clearance fit are designed. The shape memory alloy fin 9 is installed in the mortise and tenon 10 by ultrasonic welding or chemical deposition technology.

[0054] The fin array 8 can be selected as a fin array scheme of different combinations such as 4×6, 6×6 or 8×8 according to the chip size, and can be specifically applicable to chips with a size range of 4mm×6mm to 16mm×16mm. Specifically, for smaller chips (such as 4mm×6mm to 6mm×6mm), a 4×6 or 6×6 array can be used; for medium-sized chips (such as 6mm×6mm to 12mm×12mm), a 6×6 or 8×8 array can be used; and for larger chips (such as 12mm×12mm to 16mm×16mm), an 8×8 array is suitable. In addition, the spacing between the fins 9 can be adjusted to 1 to 3mm according to the heat dissipation requirements of the chip to ensure uniform heat diffusion and improve heat dissipation efficiency.

[0055] The arrangement of the fins 9 is not limited to the sequential arrangement proposed in the embodiment of the present invention, and the arrangement can be adjusted according to the distribution of heat sources in the 3D-IC.

[0056] In order to reduce the interlayer contact thermal resistance, high thermal conductivity materials such as graphene, aluminum nitride or thermal conductive adhesive are used as thermal interface layers on the outer surfaces of the first microchannel and the second microchannel, that is, the upper surfaces of the first liquid collection layer 3 and the second liquid collection layer 6, to fill uneven surfaces or tiny gaps, thereby ensuring that heat can be more effectively transferred from the chip to the heat dissipation structure.

[0057] A method for preparing a 3D IC adaptive heat dissipation structure based on shape memory alloy includes: arranging twisted fins made of temperature-sensitive memory alloy material in a microchannel heat sink, which can be adaptively adjusted according to temperature for cooling. The external heat sink structure provides mechanical support, external environmental protection and signal input and output functions for internal semiconductor devices.

[0058] The adaptive heat dissipation structure is connected with an external micro pump and a constant temperature water tank to form a circulating cooling system. The cooling medium in the system is drawn from the constant temperature water tank by the micro pump through the connecting pipeline, enters the heat dissipation structure through the first inlet 101, and then is divided into micro channels between layers, and then merged into the outlet channel, and returns to the constant temperature water tank through the first outlet 102, forming a complete circulating cooling loop.

[0059] The adaptive heat dissipation structure provides cooling for the internal stacked chips. The materials used for the upper cover plate 1, the first liquid collection layer 3, the second liquid collection layer 6, the first fin layer 4, and the second fin layer 7 should have high thermal conductivity, a linear thermal expansion coefficient that matches the semiconductor material, and good mechanical strength, ease of processing, and thermal stability. Preferred available materials include ceramic materials (aluminum oxide, beryllium oxide), metal materials (copper, molybdenum, tungsten and related alloys), and composite materials (copper-tungsten alloy). The materials can be used singly or in combination to achieve thermal-mechanical performance adaptation of the cooling structure semiconductor device.

[0060] Semiconductor device layer, including but not limited to main processing chip, logic circuit, transistor structure, inter-layer interconnection structure, etc.

[0061] The semiconductor device layer and the upper surface of the liquid collection layer are filled with high thermal conductivity materials to ensure efficient heat conduction. Appropriate pressure must be applied during the filling process and the vacuum degassing process must be used to eliminate interface gaps and ensure the continuity of the heat conduction path. The cooling structure layers must also be strictly connected and sealed.

[0062] The adaptive heat dissipation structure is not limited to the two layers of semiconductor device layers proposed in this embodiment, and can also be used in a stacking system with more than two layers.

[0063] The cooling medium of the microfluidic channel can be pure water, ethanol or deionized water with high thermal conductivity.

[0064] The arrangement of the fins is not limited to the present invention. Figure 5 and Figure 7 The order of arrangement shown in the fin layer can be adjusted according to the distribution of heat sources in the 3D IC. Figure 8 As shown, the arrangement of the ribs can be global sequential arrangement, global staggered arrangement, or local reverse arrangement. The arrangement spacing between the ribs can be equal spacing or can change in a gradient.

[0065] The twisted fin structure with adaptive cooling characteristics has one end fixed and the other free end twisted and deformed in a clockwise or counterclockwise manner to achieve the desired initial structure. The deformation can be measured by selecting a standard, such as the angle between the upper free end and the bottom fixed end edge, to define the degree of twisting.

[0066] like Fig. 9 The cross-arranged fin array with a 4×6 arrangement combination is shown in FIG. 1 . In order to compare the heat transfer capacity under different fin structure sizes, different structure sizes are calculated. The results are shown in FIG. Fig.10 shown. Fig.10 (a) is the distribution of Nusselt number (Nu) and pressure drop (Δp) at different torsion angles. It can be seen that under different flow conditions, the heat transfer capacity is always better when the torsion angle is 60°. However, with the increase of Reynolds number, the pressure drop difference at different torsion angles is also increasing. Fig.10(b) is the calculation result of different fin heights under the condition of a torsion angle of 60°, where the channel height H is also 2mm. The results show that when the fin height is less than the channel height, the channel pressure drop can be effectively reduced, but the heat transfer capacity will be significantly lost. When the fin height reaches the channel height, the heat transfer area increases and the heat transfer capacity is also enhanced, but at the cost of losing pump work. In summary, the torsion angle and fin height of the twisted fin have a great influence on the flow heat transfer. Among them, the optimal heat transfer capacity is achieved when the torsion angle is 60 degrees and the full channel height (H=2).

[0067] Different torsion angles have different heat exchange capabilities, which further corresponds to the deformation of the memory alloy fins when facing different temperatures. When facing high temperatures, the temperature reaches the phase transition temperature of the memory alloy, and the thermally induced deformation is large, corresponding to a larger torsion angle. The shape of the fins causes a certain disturbance to the incoming flow, and guides the incoming cooling medium along the fin wall to impact the heat source surface, thereby increasing the convection heat transfer coefficient of the wall there. Similarly, at low temperatures, the phase transition temperature of the memory alloy is not reached, the thermally induced deformation is small, and corresponding to a smaller torsion angle, the disturbance and guiding effect on the incoming flow is weakened, and the increase in the local wall convection heat transfer coefficient is not obvious. Furthermore, the temperature uniformity of the heat source surface is improved through the adaptive process.

[0068] The cooling scheme in the above 4×6 staggered fin array embodiment with a twist angle of 60° is compared with the general in-line fin array, ensuring that the fins are equal in height, diagonal size, and arrangement, and the two are calculated under the same cooling conditions. 2 , The temperature distribution cloud diagram of the heat source surface when the inlet Reynolds number is Re=3000 is as follows Fig.11 shown. Fig.11 (a) and (b) show the temperature distribution cloud diagrams of the straight fins and twisted fins, respectively. It can be found that the overall temperature distribution of the straight fins is relatively uniform, while the proposed twisted fin array cooling solution has obvious low temperature areas, especially in the rear half and the rear side of the fins. Fig.11 (c) and (d) show the heat transfer coefficient distribution cloud diagrams of the heat source surface of the straight fins and twisted fins, respectively. It can be found that a higher heat transfer area appears in the rear area of ​​the twisted fins, while the overall distribution of the straight fins is relatively uniform. This also explains that the twisted structure causes a strong disturbance to the working fluid, causing a violent vortex near the fins, which enhances the heat transfer in this area.

[0069] The data shown in Table 1 are numerical comparisons of heat transfer coefficient and heat source surface temperature of in-line fins and twisted fins under two working conditions.

[0070] Table 1 Heat dissipation results of different cooling structures

[0071]

[0072] It can be found from Table 1 that the memory alloy fins described in the present invention have better heat exchange performance in all aspects after changing from a straight-line shape to a twisted shape.

[0073] It is obvious to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-restrictive, and the scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims are included in the present invention. Any figure mark in the claims should not be regarded as limiting the claims involved. All equivalent changes or modifications made according to the spirit and essence of the present invention should be included in the scope of protection of the present invention.

Claims

1. A 3D IC adaptive heat dissipation structure based on shape memory alloy, characterized in that: It includes, from top to bottom, an upper cover plate, a first semiconductor device layer, a first liquid collection layer, a first fin layer, a second semiconductor device layer, a second liquid collection layer, and a second fin layer. The upper cover plate, the first liquid collection layer, the first fin layer, the second liquid collection layer, and the second fin layer have corresponding length and width dimensions, and can be overlapped, aligned, and bonded in sequence from top to bottom. The lower surface of the upper cover plate is provided with an upper cover plate groove, and the edge of the upper cover plate is provided with a first inlet and a first outlet; The first liquid collection layer has a first liquid collection layer concave cavity on the lower surface, a second inlet and a second outlet are provided on the edge of the first liquid collection layer, the first semiconductor device layer is mechanically connected to the upper surface of the first liquid collection layer through its bottom microstructure, and the first semiconductor device layer is placed in the groove of the upper cover plate; The upper surface of the first fin layer has a first fin layer cavity, a fin array is arranged on the first fin layer cavity, the lower surface of the first fin layer has a first fin layer groove, and a third inlet and a third outlet are arranged at the edge of the first fin layer; The lower surface of the second liquid collection layer has a second liquid collection layer cavity, and the edge of the second liquid collection layer has a fourth inlet and a fourth outlet, the second semiconductor device layer is mechanically connected to the upper surface of the second liquid collection layer through its bottom microstructure, and the second semiconductor device layer is placed in the first fin layer groove; The upper surface of the second fin layer is provided with a second fin layer cavity, a fin array is arranged on the second fin layer cavity, and a fifth inlet and a fifth outlet are provided at the edge of the second fin layer.

2. The 3D IC adaptive heat dissipation structure based on shape memory alloy according to claim 1, characterized in that: The length, width and height dimensions of the upper cover plate groove are greater than the corresponding length, width and height dimensions of the first semiconductor device layer, and the first inlet and the first outlet on the edge of the upper cover plate are not connected to the upper cover plate groove.

3. The 3D IC adaptive heat dissipation structure based on shape memory alloy according to claim 1, characterized in that: The upper surface of the first liquid collection layer is a smooth plane, and the second inlet and the second outlet on the edge of the first liquid collection layer are located at the vertical projection positions of the first inlet and the first outlet on the first liquid collection layer, respectively, and the second inlet and the second outlet are not connected to the concave cavity of the first liquid collection layer; the upper surface of the second liquid collection layer is a smooth plane, and the fourth inlet and the fourth outlet on the edge of the second liquid collection layer are located at the vertical projection positions of the third inlet and the third outlet on the second liquid collection layer, respectively, and the fourth inlet and the fourth outlet are not connected to the concave cavity of the second liquid collection layer.

4. The 3D IC adaptive heat dissipation structure based on shape memory alloy according to claim 1, characterized in that: The first semiconductor device layer is connected to the upper surface plane of the first liquid collection layer through its bottom microstructure by means of heating reflow soldering, and the second semiconductor device layer is connected to the upper surface plane of the second liquid collection layer through its bottom microstructure by means of heating reflow soldering.

5. The 3D IC adaptive heat dissipation structure based on shape memory alloy according to claim 1, characterized in that: A fin array is arranged at the core position of the first fin layer cavity, and the core position of the first fin layer cavity is the vertical projection area of ​​the first semiconductor device layer in the first fin layer cavity; a fin array is arranged at the core position of the second fin layer cavity, and the core position of the second fin layer cavity is the vertical projection area of ​​the second semiconductor device layer in the second fin layer cavity.

6. The 3D IC adaptive heat dissipation structure based on shape memory alloy according to claim 1, characterized in that: The length, width and height dimensions of the groove of the first fin layer are larger than the corresponding length, width and height dimensions of the second semiconductor device layer; the third inlet and the third outlet on the first fin layer are respectively located at the vertical projection positions of the second inlet and the second outlet on the first fin layer; the third inlet and the third outlet are interconnected with the concave cavity of the first fin layer; the third inlet and the third outlet are not connected with the groove of the first fin layer; the fifth inlet and the fifth outlet on the second fin layer are respectively located at the vertical projection positions of the fourth inlet and the fourth outlet on the second fin layer; the fifth inlet and the fifth outlet are interconnected with the concave cavity of the second fin layer.

7. The 3D IC adaptive heat dissipation structure based on shape memory alloy according to claim 1, characterized in that: The first fin layer cavity and the second fin layer cavity are designed with tenons, and the ribs in the fin array are installed in the tenons. The ribs are made of shape memory alloy, and the straight ribs can be transformed into a large pitch twisted state. The final linear pitch bending angle of the rib is 57 to 63°, that is, the angle between the upper edge and the lower edge of the rib is 57 to 63°.

8. The 3D IC adaptive heat dissipation structure based on shape memory alloy according to claim 1, characterized in that: The first inlet, the second inlet, the third inlet, the fourth inlet and the fifth inlet are interconnected from top to bottom to form a liquid inlet passage of the cooling structure, and the cooling medium enters from the external micropump through the first inlet. The fifth outlet, the fourth outlet, the third outlet, the second outlet and the first outlet are interconnected from bottom to top to form a liquid outlet passage, and the cooling medium leaves the heat dissipation structure through the first outlet.

9. The 3D IC adaptive heat dissipation structure based on shape memory alloy according to claim 7, characterized in that: The ribs have a height range of 0.5 to 2 mm, a width range of 1 to 2 mm, a thickness of 0.2 to 0.8 mm, a mortise depth of 1 mm, and the mortise width and thickness are consistent with the rib size.

10. The 3D IC adaptive heat dissipation structure based on shape memory alloy according to claim 1, characterized in that: The fin array is globally arranged in a sequential manner, globally staggered, or partially reversed, and the arrangement spacing of the fin array is 1 to 3 mm.

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