High-synchronism control protection device and method for valve-based controller of distributed IGBT (Insulated Gate Bipolar Translator) series valve

Abstract

The invention belongs to the technical field of power electronics, and particularly relates to a distributed IGBT series valve base controller high-synchronism control protection device and method, and the device comprises a main control case, a first valve base control case and a plurality of second valve base control cases. The first valve base control case comprises a first control panel; each second valve base control case comprises a second control panel; the first control panel comprises a first control chip; the second control panel comprises a second control chip; the first control chip is respectively connected with the main control case, each second control chip and the corresponding IGBT series valve; and the second control chip is connected with the corresponding IGBT series valve. According to the technical scheme provided by the invention, a one-master multi-slave valve base control case mode and synchronous control of a plurality of valve base control cases are adopted, so that all the valve base control cases modulate respectively and complete modulation synchronously, and then synchronous control of all the IGBT series valves is realized, the synchronous control precision of the IGBT series valves is improved, and the safety of the IGBT series valves is ensured.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronics, and in particular relates to a high-synchronization control protection device and method for a distributed IGBT series valve base controller. Background Art

[0002] IGBT series technology is the most direct technical means to increase the capacity and voltage level of power electronic converters. It is simple and reliable to control, and can significantly reduce the footprint and cost of converter valves. It is suitable for scenarios such as flexible DC transmission, high-voltage and large-capacity STATCOM, etc.

[0003] The traditional valve base controller uses a serial communication protocol to send PWM waves to multiple sub-unit controllers, which then trigger the IGBT devices separately. In this mode, since each sub-unit controller has an independent control chip and crystal oscillator, each IGBT is independently controlled by the sub-unit controller, which will result in low synchronization accuracy of all devices. In addition, each sub-unit controller needs to be equipped with a separate control chip and peripheral low-voltage circuit, and the economic cost of the hardware is high.

[0004] IGBT series valve technology has high requirements for the synchronous opening and closing accuracy of IGBT devices in the same series. If the IGBT driving signal of a certain IGBT in the IGBT series valve is not synchronized, it will cause uneven voltage distribution, and a single IGBT will be subjected to high voltage, causing the IGBT device to burn out. The asynchronous control of the upper and lower bridge arms of the single-phase bridge IGBT series valve will lead to a large dead time jitter range, and the upper and lower bridge arms may be directly short-circuited, resulting in the burning of IGBT devices.

[0005] The use of IGBT series valve technology requires a large number of control outlets of the controller. If the valve-based controllers all use a single control chip, although synchronization can be guaranteed, the IO outlets of the control chip are limited. It is not suitable for IGBT series valve scenarios with complex topology and large number. In addition, the software development of a single-chip valve-based controller is difficult, the chip resource occupancy rate is high, the reliability is reduced, and the degree of customization is high. It is not suitable for a replicable modular product architecture. Summary of the invention

[0006] In order to overcome the problems existing in the above-mentioned related technologies, the present invention provides a high-synchronization control and protection device and method for a distributed IGBT series valve base controller.

[0007] According to a first aspect of an embodiment of the present invention, there is provided a distributed IGBT series valve valve base controller high synchronization control protection device, comprising: a main control chassis, a first valve base control chassis and a plurality of second valve base control chassis;

[0008] The first valve base control chassis includes: a first control board; each of the second valve base control chassis includes: a second control board; the first control board includes: a first control chip; the second control board includes: a second control chip;

[0009] The first control chip is respectively connected to the main control chassis, each of the second control chips and its corresponding IGBT series valve; the second control chip is connected to its corresponding IGBT series valve;

[0010] The main control chassis is used to send a modulation wave to the first control board and each of the second control boards when receiving the information that the synchronization delay of the first control board is successful and the information that the synchronization delay of each of the second control boards is successful;

[0011] The first control board is used to generate a synchronization-related signal after it is powered on, send the synchronization-related signal to each of the second control boards, and perform a synchronization-related action corresponding to the synchronization-related signal; when it completes the execution of the synchronization-related action and receives the information that the execution of the synchronization-related action is completed sent by each of the second control boards, send the information that the execution of the synchronization-related action of all control boards is completed to the main control chassis; and when receiving the modulation wave, use the modulation wave to control the action of the corresponding IGBT series valve;

[0012] The second control board is used to execute the synchronization-related action corresponding to the synchronization-related signal when it receives the synchronization-related signal, and send the information of completion of the synchronization-related action to the first control board after the synchronization-related action is completed; and when the modulation wave is received, use the modulation wave to control the corresponding IGBT series valve action.

[0013] Preferably, the first control board further includes: a first control clock and a first protection clock; the second control board further includes: a second control clock and a second protection clock;

[0014] The first control chip is connected to the first control clock and the first protection clock respectively, and the second control chip is connected to the second control clock and the second protection clock respectively;

[0015] The first control clock is used to provide a clock signal for the first control board;

[0016] The second control clock is used to provide a clock signal for the second control board and is synchronized with the clock signal of the first control clock;

[0017] The first protection clock is used to provide a clock signal to the first control board when the first control clock loses the clock signal;

[0018] The second protection clock is used to provide a clock signal to the second control board when the second control clock loses the clock signal.

[0019] Preferably, the first control board further comprises: a plurality of first QSFP optical ports;

[0020] The second control board further includes: a plurality of second QSFP optical ports;

[0021] The first QSFP optical port is connected to the main control chassis and the second QSFP optical port respectively.

[0022] Preferably, the first QSFP optical port is connected to the main control chassis and the second QSFP optical port respectively through optical fibers.

[0023] Preferably, the first valve base control chassis further comprises: a first backplane, a first power supply board and a plurality of first optical head interface boards;

[0024] The plurality of first optical head interface boards are arranged on the first backplane in a plug-in card type, the first power board is respectively connected to the first control board and the first backplane, and the first optical head interface board is connected to the IGBT series valve;

[0025] The first backplane is used to provide communication between the plurality of first optical head interface boards and the first control board, and to supply power to the plurality of first optical head interface boards;

[0026] The plurality of first optical head interface boards are used for external communication of the first control board;

[0027] The first power board is used to supply power to the first control board and the first backplane.

[0028] Preferably, the second valve base control chassis further comprises: a second backplane, a second power supply board and a plurality of second optical head interface boards;

[0029] The plurality of second optical head interface boards are arranged on the second backplane in a plug-in card type, the second power board is connected to the second control board and the second backplane respectively, and the second optical head interface board is connected to the IGBT series valve;

[0030] The second backplane is used to provide communication between the plurality of second optical head interface boards and the second control board, and to supply power to the plurality of second optical head interface boards;

[0031] The plurality of second optical head interface boards are used for external communication of the second control board;

[0032] The second power board is used to supply power to the second control board and the second backboard.

[0033] Preferably, the first optical head interface board is connected to the second optical head interface board via an optical fiber;

[0034] The first optical head interface board is connected to the IGBT series valve via an optical fiber;

[0035] The second optical head interface board is connected to the IGBT series valve via an optical fiber.

[0036] Preferably, the synchronization-related signals include: a synchronization handshake signal and a synchronization start signal;

[0037] The synchronization-related actions include: sending a handshake response signal and a synchronization delay action to the first control board.

[0038] Preferably, the first control panel is specifically used for:

[0039] When it is powered on, it sends a synchronous handshake signal to each of the second control boards, and after receiving a handshake response signal sent by each of the second control boards, it sends a synchronous start signal to each of the second control boards;

[0040] When receiving the synchronization start signal handshake sent by each second control board, performing synchronization delay to synchronize with each second control board;

[0041] When the synchronization delay is successful and the information that the synchronization-related actions are executed successfully is received from each of the second control boards, the information that the synchronization-related actions of all control boards are executed successfully is sent to the main control chassis.

[0042] Preferably, the second control panel is specifically used for:

[0043] When receiving the synchronous handshake signal, sending a handshake response signal to the first control board;

[0044] When receiving the synchronization start signal, sending a synchronization start signal handshake to the first control board and performing synchronization delay to synchronize with the first control board;

[0045] When the synchronization delay is successful, information indicating that the synchronization-related actions are completed is sent to the first control board.

[0046] Preferably, the first control panel is further specifically used for:

[0047] Modulating the modulated wave according to a pre-generated first triangular carrier wave to obtain a first initial signal;

[0048] The first initial signal is subjected to pulse width processing and dead zone processing to obtain a first PWM signal, and the first PWM signal is used to control the action of the corresponding IGBT series valve.

[0049] Preferably, the second control panel is further specifically used for:

[0050] Modulating the modulated wave according to a pre-generated second triangular carrier wave to obtain a second initial signal;

[0051] The second initial signal is subjected to pulse width processing and dead zone processing to obtain a second PWM signal, and the second PWM signal is used to control the action of the corresponding IGBT series valve.

[0052] According to a second aspect of an embodiment of the present invention, a distributed IGBT series valve base controller high synchronization control protection method is applied to the distributed IGBT series valve base controller high synchronization control protection device, comprising:

[0053] When the first control board is powered on, it generates a synchronization-related signal, sends the synchronization-related signal to each second control board, and executes a synchronization-related action corresponding to the synchronization-related signal;

[0054] When the second control board receives the synchronization-related signal, it executes the synchronization-related action corresponding to the synchronization-related signal, and after the synchronization-related action is completed, it sends the information that the synchronization-related action is completed to the first control board;

[0055] When the first control board completes the synchronization-related actions and receives the information that the synchronization-related actions are completed sent by each second control board, the information that the synchronization-related actions of all control boards are completed is sent to the main control chassis;

[0056] Using the main control chassis to send modulated waves to the first control board and each second control board;

[0057] When the first control board receives the modulation wave, it uses the modulation wave to control the action of the corresponding IGBT series valve;

[0058] When the second control board receives the modulation wave, it uses the modulation wave to control the action of the corresponding IGBT series valve.

[0059] Preferably, the synchronization-related signals include: a synchronization handshake signal and a synchronization start signal;

[0060] The synchronization-related actions include: sending a handshake response signal and a synchronization delay action to the first control board.

[0061] Preferably, when the first control board is powered on, a synchronization-related signal is generated, the synchronization-related signal is sent to each second control board, and a synchronization-related action corresponding to the synchronization-related signal is executed, including:

[0062] When the first control board is powered on, the first control board is used to send a synchronous handshake signal to each of the second control boards, and after receiving a handshake response signal sent by each of the second control boards, a synchronous start signal is sent to each of the second control boards;

[0063] When the first control board receives the synchronization start signal handshake sent by each second control board, the first control board is used to perform synchronization delay so that the first control board is synchronized with each second control board.

[0064] Preferably, when the second control board receives the synchronization-related signal, executing the synchronization-related action corresponding to the synchronization-related signal includes:

[0065] When the second control board receives the synchronous handshake signal, the second control board sends a handshake response signal to the first control board;

[0066] When the second control board receives the synchronization start signal, the second control board sends a synchronization start signal handshake to the first control board, and performs synchronization delay, so that the second control board is synchronized with the first control board;

[0067] When the synchronization delay of the second control board succeeds, the second control board is used to send information indicating that the synchronization-related action is completed to the first control board.

[0068] Preferably, when the first control board completes the synchronization-related action and receives the information that the synchronization-related action is completed sent by each second control board, the information that the synchronization-related action of all control boards is completed is sent to the main control chassis, including:

[0069] When the synchronization delay of the first control board succeeds and the information of the completion of the synchronization-related actions sent by each of the second control boards is received, the first control board is used to send the information of the completion of the synchronization-related actions of all control boards to the main control chassis.

[0070] Preferably, when the first control board receives the modulation wave, the modulation wave is used to control the action of the corresponding IGBT series valve, including:

[0071] Using the first control board to modulate the modulation wave according to a pre-generated first triangular carrier wave to obtain a first initial signal;

[0072] The first control board is used to perform pulse width processing and dead zone processing on the first initial signal to obtain a first PWM signal, and the first PWM signal is used to control the action of the corresponding IGBT series valve.

[0073] Preferably, when the second control board receives the modulation wave, the modulation wave is used to control the action of the corresponding IGBT series valve, including:

[0074] Using the second control board to modulate the modulated wave according to a pre-generated second triangular carrier wave to obtain a second initial signal;

[0075] The second control board is used to perform pulse width processing and dead zone processing on the second initial signal to obtain a second PWM signal, and the second PWM signal is used to control the action of the corresponding IGBT series valve.

[0076] According to a third aspect of an embodiment of the present invention, there is provided an electronic device, comprising: at least one processor and a memory; the memory and the processor are connected via a bus;

[0077] The memory is used to store one or more programs;

[0078] When the one or more programs are executed by the at least one processor, the distributed IGBT series valve base controller high synchronization control and protection method is implemented.

[0079] According to a fourth aspect of an embodiment of the present invention, there is provided a readable storage medium having an execution program stored thereon, and when the execution program is executed, the distributed IGBT series valve base controller high synchronization control and protection method is implemented.

[0080] The technical solution provided by the present invention has the following beneficial effects:

[0081] A distributed IGBT series valve base controller high synchronization control protection device and method provided by the present invention comprises: a main control chassis, a first valve base control chassis and a plurality of second valve base control chassis; the first valve base control chassis comprises: a first control board; each second valve base control chassis comprises: a second control board; the first control board comprises: a first control chip; the second control board comprises: a second control chip; the first control chip is respectively connected to the main control chassis, each second control chip and the corresponding IGBT series valve; the second control chip is connected to the corresponding IGBT series valve; the main control chassis is used to send a modulation wave to the first control board and each second control board when receiving the information that the synchronization delay of the first control board is successful and the information that the synchronization delay of each second control board is successful; the first control board, It is used to generate synchronization-related signals after it is powered on, send synchronization-related signals to each second control board, and perform synchronization-related actions corresponding to the synchronization-related signals; when it completes the execution of the synchronization-related actions and receives the information that the execution of the synchronization-related actions sent by each second control board is completed, it sends the information that the execution of the synchronization-related actions of all control boards is completed to the main control chassis; and when receiving the modulation wave, it uses the modulation wave to control the corresponding IGBT series valve action; the second control board is used to perform the synchronization-related actions corresponding to the synchronization-related signals when receiving the synchronization-related signals, and after the execution of the synchronization-related actions is completed, it sends the information that the execution of the synchronization-related actions is completed to the first control board; and when receiving the modulation wave, it uses the modulation wave to control the corresponding IGBT series valve action. The technical solution provided by the present invention adopts a valve base control chassis mode of one master and multiple slaves to realize the configuration of different numbers of drive signals, with low economic cost and wide applicability; it adopts the synchronous control of multiple valve base control chassis, so that all valve base control chassis are modulated separately and synchronously complete the modulation, thereby realizing the synchronous control of all IGBT series valves, which not only improves the synchronous control accuracy of the IGBT series valves, but also ensures the safety of the IGBT series valves and reduces unnecessary economic losses. BRIEF DESCRIPTION OF THE DRAWINGS

[0082] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0083] Figure 1 It is a structural block diagram of a high-synchronization control and protection device of a distributed IGBT series valve base controller provided by an embodiment of the present invention;

[0084] Figure 2 It is a schematic diagram of the core board interface configuration of the valve base control chassis provided by an embodiment of the present invention;

[0085] Figure 3 is a schematic diagram of a valve base control chassis expansion architecture provided by an embodiment of the present invention;

[0086] Figure 4 It is a topological diagram of a three-phase bridge circuit and a valve base control chassis provided by an embodiment of the present invention;

[0087] Figure 5 is a processing flow chart of a valve base control chassis provided by an embodiment of the present invention;

[0088] Figure 6 This is a flow chart of a high synchronization control and protection method of a distributed IGBT series valve base controller provided by an embodiment of the present invention;

[0089] Figure 7 It is a structural block diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0090] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the following embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0091] Embodiment 1

[0092] The present invention provides a distributed IGBT series valve base controller high synchronization control protection device, such as Figure 1 As shown, it includes: a main control chassis, a first valve base control chassis and a plurality of second valve base control chassis;

[0093] The first valve base control chassis includes: a first control board; each second valve base control chassis includes: a second control board; the first control board includes: a first control chip; the second control board includes: a second control chip;

[0094] The first control chip is respectively connected to the main control chassis, each second control chip and its corresponding IGBT series valve; the second control chip is connected to its corresponding IGBT series valve;

[0095] The main control chassis is used to send a modulation wave to the first control board and each second control board when receiving the information that the synchronization delay of the first control board is successful and the information that the synchronization delay of each second control board is successful;

[0096] The first control board is used to generate a synchronization-related signal after it is powered on, send the synchronization-related signal to each second control board, and perform a synchronization-related action corresponding to the synchronization-related signal; when it completes the execution of the synchronization-related action and receives the information that the execution of the synchronization-related action is completed sent by each second control board, it sends the information that the execution of the synchronization-related action of all control boards is completed to the main control chassis; and when receiving the modulation wave, it uses the modulation wave to control the action of the corresponding IGBT series valve;

[0097] The second control board is used to execute the synchronization-related action corresponding to the synchronization-related signal when receiving the synchronization-related signal, and send the information of completion of the synchronization-related action to the first control board after the synchronization-related action is completed; and when receiving the modulation wave, use the modulation wave to control the corresponding IGBT series valve action.

[0098] The multi-valve base control chassis synchronization mode architecture provided by the present invention can meet the needs of different numbers of IGBT series valve devices and different numbers of IGBT series valve strings. The valve base control chassis are modulated separately to achieve high-precision distributed control of different valve base control chassis, reduce the power consumption of a single device, and improve parallel computing capabilities and the number of external interfaces.

[0099] Furthermore, the first control board further includes: a first control clock and a first protection clock; the second control board further includes: a second control clock and a second protection clock;

[0100] The first control chip is connected to the first control clock and the first protection clock respectively, and the second control chip is connected to the second control clock and the second protection clock respectively;

[0101] A first control clock, used to provide a clock signal for the first control board;

[0102] A second control clock, used for providing a clock signal to the second control board and synchronized with the clock signal of the first control clock;

[0103] A first protection clock, used for providing a clock signal to the first control board when the first control clock loses the clock signal;

[0104] The second protection clock is used to provide a clock signal to the second control board when the second control clock loses the clock signal.

[0105] It is understandable that the main control board adopts the design of FPGA plus dual clock to process the control function and protection function independently. Among them, valve base controller synchronization and PWM modulation belong to control functions, which are handled by the control clock; fault lockout belongs to protection function, which is handled by the protection clock. The purpose of this design is to prevent the main control board from not working properly due to the loss of the valve base controller control clock, which in turn causes the failure of the protection function. The use of an independent protection clock can ensure that the protection function continues uninterrupted. Even if the control clock is lost, the valve base controller can still perform the protection action normally.

[0106] In some embodiments, the control board of the present invention can be, but is not limited to, using FPGA as a control chip to implement all control and protection strategies. The present invention adopts a dual-clock design, which realizes control synchronization through a clock configuration chip, one clock is used for control, and one clock is used for protection; different extended high-speed QSFP optical heads can be configured on the control board according to project requirements to achieve the expansion of multiple valve base control chassis; the control clock can be, but is not limited to, using a configurable clock processing chip to achieve clock synchronization of all chassis; the protection clock can be, but is not limited to, using a basic crystal oscillator to monitor faults in real time to prevent the valve base controller from being unable to operate normally due to the loss of the clock signal in the case of a single clock, that is, to ensure that the FPGA can perform protection normally when the clock signal is lost when a fault occurs, and realize the real-time protection. In addition, the clock synchronization method can be applied to any other large-scale high-precision distributed computing or control.

[0107] In some embodiments, multiple valve base controllers of the present invention adopt a one-master-multiple-slave mode, use the encoded clock in the SRIO protocol, and use the FPGA output as the reference clock of the clock control chip to achieve clock synchronization of multiple valve base controllers.

[0108] The present invention can be applied to, but is not limited to, the design of crimped IGBT series valve controllers and the design of clock synchronization solutions between multiple valve base controllers. Series IGBTs are more suitable for high voltage levels and large capacity scenarios by connecting multiple IGBT devices in series to balance the voltage. IGBT series valves require valve base controllers to be able to synchronously control the IGBT devices in the same string to ensure that all IGBT devices have the same voltage balancing effect. IGBT series valves in different strings on different bridge arms are also required to be synchronously controlled to ensure the accuracy and reliability of control. The present invention uses multiple valve base control chassis for parallel control and synchronizes the clocks of multiple valve base control chassis to achieve distributed high-precision synchronous control of multiple valve base controllers.

[0109] Further, the first control board further includes: a plurality of first QSFP optical ports;

[0110] The second control board also includes: a plurality of second QSFP optical ports;

[0111] The first QSFP optical port is connected to the main control chassis and the second QSFP optical port respectively.

[0112] Specifically, the first QSFP optical port is connected to the main control chassis and the second QSFP optical port through optical fibers respectively.

[0113] It can be understood that the present invention adopts a high-speed QSFP optical port as an expansion interface, and can also be equipped with different numbers of QSFP optical ports according to project requirements to achieve expansion of different numbers of chassis; the QSFP optical port can be used as a clock synchronization channel, and can also realize a two-level synchronization mechanism of the valve base controller, the first level is handshake synchronization, and the second level is startup synchronization, and a two-way synchronization handshake mechanism is used to ensure the reliability of the synchronization signal.

[0114] The valve base controller of the present invention adopts a chassis-type expandable architecture. Further, the first valve base control chassis also includes: a first backplane, a first power board and a plurality of first optical head interface boards;

[0115] A plurality of first optical head interface boards are arranged on the first backplane in a plug-in card type, the first power supply board is respectively connected to the first control board and the first backplane, and the first optical head interface board is connected to the IGBT series valve;

[0116] A first backplane, used for providing communication between the plurality of first optical head interface boards and the first control board, and for supplying power to the plurality of first optical head interface boards;

[0117] A plurality of first optical head interface boards, used for external communication of the first control board;

[0118] The first power board is used to supply power to the first control board and the first backboard.

[0119] Further, the second valve base control chassis further includes: a second backplane, a second power supply board and a plurality of second optical head interface boards;

[0120] A plurality of second optical head interface boards are arranged on the second backplane in a plug-in card type, the second power supply board is connected to the second control board and the second backplane respectively, and the second optical head interface board is connected to the IGBT series valve;

[0121] A second backplane, used for providing communication between the plurality of second optical head interface boards and the second control board, and for supplying power to the plurality of second optical head interface boards;

[0122] A plurality of second optical head interface boards, used for external communication of the second control board;

[0123] The second power board is used to supply power to the second control board and the second backboard.

[0124] The present invention does not limit the first optical head interface board and the second optical head interface board, and the number of the optical head interface board and the second optical head interface board can be designed according to the project requirements and the chassis size, and multiple channel configurations can be realized through plug-in cards. The optical head interface board is used to expand the drive interface of the control board. The optical ports of an optical head interface board can be designed with different numbers according to the actual project requirements. The optical head interface board receives the PMW signal of the control board through the backplane, converts it into an optical signal, and sends it to the IGBT driver board through the optical port.

[0125] For example, Figure 2 As shown in the figure, taking the control board with 2 high-speed QSFP optical ports and each optical port board with 6 ST optical heads as an example, the control board and the optical port board communicate through the backplane channel. The chassis are expanded through QSFP high-speed optical heads between chassis, and 2 slave chassis can be expanded. The valve base controller communicates with the IGBT driver board through optical fiber to achieve synchronous driving of multiple IGBT series valves. The control chip uses FPGA, and the valve base controller chassis are synchronized through high-speed QSFP optical ports and clock control chips. The control board adopts dual clock mode to prevent the FPGA clock from being lost after the synchronous clock is disconnected, resulting in failure of normal protection. The dual clock mode can ensure that the valve base controller can perform protection actions normally when a fault occurs.

[0126] It can be understood that the present invention adopts a chassis backplane structure with a single control board and multiple optical port boards, and the number of output interfaces can be flexibly configured by plug-in card mode; the optical port board of the present invention uses the backplane as the optical port expansion board of the control board without a processing chip, and only performs photoelectric conversion of data, which can transmit data more efficiently and reliably, and the optical port board can be configured with different numbers of optical ports according to needs;

[0127] Further, the first optical head interface board is connected to the second optical head interface board via an optical fiber;

[0128] The first optical head interface board is connected to the IGBT series valve via an optical fiber;

[0129] The second optical head interface board is connected to the IGBT series valve via an optical fiber.

[0130] The present invention adopts a one-host-multiple-slave mode to realize different numbers of drive signal configurations, wherein the host is both a synchronization source and can also send PWM signals synchronously. The host (i.e., the first valve base control chassis) is interconnected with all slaves (i.e., the second valve base control chassis) through a high-speed QSFP optical port, and the high-speed QSFP optical port can execute the SRIO high-speed protocol. The host transmits synchronous data through SRIO, and the slave parses the clock in the SRIO data encoding and outputs it, and uses it as the reference clock of the clock control chip to achieve clock synchronization between the slave and the host. After clock synchronization, all valve base controller chassis can achieve synchronous modulation and complete synchronous control of all IGBT devices.

[0131] Further, the synchronization-related signals include: a synchronization handshake signal and a synchronization start signal;

[0132] The synchronization related actions include: sending a handshake response signal to the first control board and a synchronization delay action.

[0133] Furthermore, the first control panel is specifically used for:

[0134] When it is powered on, it sends a synchronous handshake signal to each second control board, and after receiving a handshake response signal sent by each second control board, it sends a synchronous start signal to each second control board;

[0135] When receiving the synchronization start signal handshake sent by each second control board, performing synchronization delay to synchronize with each second control board;

[0136] When the synchronization delay is successful and the information that the synchronization-related actions are completed is received from each second control board, the information that the synchronization-related actions of all control boards are completed is sent to the main control chassis.

[0137] Furthermore, the second control board is specifically used for:

[0138] When receiving the synchronous handshake signal, sending a handshake response signal to the first control board;

[0139] When receiving the synchronization start signal, sending a synchronization start signal handshake to the first control board and performing synchronization delay to synchronize with the first control board;

[0140] When the synchronization delay is successful, the information that the synchronization-related action is completed is sent to the first control board.

[0141] Furthermore, the first control panel is also specifically used for:

[0142] Modulating the modulation wave according to a pre-generated first triangular carrier wave to obtain a first initial signal;

[0143] The first initial signal is subjected to pulse width processing and dead zone processing to obtain a first PWM signal, and the first PWM signal is used to control the action of the corresponding IGBT series valve.

[0144] Furthermore, the second control board is also specifically used for:

[0145] Modulating the modulated wave according to a pre-generated second triangular carrier wave to obtain a second initial signal;

[0146] The second initial signal is subjected to pulse width processing and dead zone processing to obtain a second PWM signal, and the second PWM signal is used to control the action of the corresponding IGBT series valve.

[0147] It should be noted that the method of "generating a triangular carrier" involved in the embodiment of the present invention is well known to those skilled in the art, and therefore, its specific implementation method will not be described in detail. The triangular carrier is a periodic signal, and its amplitude changes linearly within a cycle. A counter is used to generate a triangular carrier. The counting clock and amplitude of the triangular carrier are set according to the switching frequency of the IGBT series valve, and it increases (or decreases) in each clock cycle. When the counter reaches a set maximum or minimum amplitude, the counting direction is changed, so that a triangular carrier signal can be obtained.

[0148] To further illustrate the above-mentioned distributed IGBT series valve base controller high synchronization control protection device, the present invention provides a specific example, such as Figure 3 and Figure 4 As shown in the figure, take a three-phase bridge with 18 IGBT devices as a series valve as an example. Each half bridge of the three-phase bridge has a series valve. The three-phase bridge has a total of 6 series valves, that is, 108 IGBT devices. Each IGBT corresponds to a driver board. The function of the driver board is to convert the PWM wave optical signal of the valve base controller into an electrical signal to drive the IGBT. The valve base controller needs to synchronously control 108 IGBTs. Each valve base control chassis can control 36 IGBT devices. A total of 3 valve base control chassis need to be configured, named A-phase valve base control chassis, B-phase valve base control chassis and C-phase valve base control chassis, respectively, to synchronously control the IGBTs of the ABC three-phase bridge arms, among which the A-phase valve base control chassis is the master controller and the other two are slave controllers. The ABC three-phase PWM waves are modulated and generated by the three chassis respectively. Among them, Q1 is the 18 IGBT series valves in the upper bridge arm of phase A, Q4 is the 18 IGBT series valves in the lower bridge arm of phase A, Q3 is the 18 IGBT series valves in the upper bridge arm of phase B, Q6 is the 18 IGBT series valves in the lower bridge arm of phase B, Q5 is the 18 IGBT series valves in the upper bridge arm of phase C, Q2 is the 18 IGBT series valves in the lower bridge arm of phase C, and C1 is a DC capacitor.

[0149] The A-phase valve base control chassis controls the two IGBT series valves of the upper and lower bridge arms of phase A, the B-phase valve base control chassis controls the two IGBT series valves of the upper and lower bridge arms of phase B, and the C-phase valve base control chassis controls the two IGBT series valves of the upper and lower bridge arms of phase C.

[0150] The A-phase valve base control chassis is used as a synchronization source, and sends synchronization data to the B-phase valve base control chassis and the C-phase valve base control chassis through QSFP. Since QSFP is a high-speed serial interface and the SRIO communication protocol is a high-speed serial protocol, in order to ensure reliable data communication in high-speed serial communication, the sender will encode the clock and data in the communication, and the receiver can parse the clock and data. After the slave receives the clock of the host, it will be output through the IO port. The clock is used as the reference clock of the clock control chip of the valve base controller processing board, so that the clock signal output by the clock control chip is synchronized with the reference clock. The clock output by the clock control chip is used as the input clock of the FPGA, and the FPGA sets the clock to a suitable control clock frequency through a phase-locked loop. After the control clocks of the three valve base control chassis ABC are synchronized, the three valve base control chassis are synchronously modulated through the synchronization data in SRIO, thus realizing the synchronous output of the PWM waves of the three phases ABC.

[0151] The clock input by the clock configuration chip is used as the control clock of the FPGA to generate PWM waves and output to the control logic of the IGBT. The basic crystal oscillator is used as the FPGA protection monitoring and protection action clock to ensure that the entire system can operate safely.

[0152] The control process flow of the valve base control box in the above example is as follows: Figure 5 As shown, the following steps are included:

[0153] Step 21: After the A-phase valve base control chassis is powered on, a synchronous handshake signal is sent to the B-phase and C-phase valve base control chassis respectively;

[0154] Step 22: After receiving the synchronous handshake signal, the B-phase and C-phase valve base control chassis transmit the handshake response signal back to the A-phase valve base control chassis;

[0155] Step 23: After the A-phase valve base control chassis receives the synchronous handshake signal response from the B-phase and C-phase valve base control chassis, it sends the start synchronization signal synchronously according to the control cycle. Since the sending of the start signal and the receiving of the start signal response are not synchronized, the A-phase valve base control chassis adjusts the synchronization delay by configuring parameters and starts to generate the first triangular carrier.

[0156] Step 24: After receiving the start synchronization signal, the B-phase and C-phase valve base control boxes return the start synchronization signal handshake, adjust the synchronization delay by configuring parameters, and generate the second triangular carrier;

[0157] Step 25: In the next synchronization cycle, the ABC three-phase valve base control chassis synchronously starts to receive the three-phase modulation wave sent by the main control chassis;

[0158] Step 26: After receiving the modulation wave, the three valve base control boxes ABC start to calculate and generate the corresponding upper and lower bridge arm PWM waves;

[0159] Step 27: The ABC three-phase valve base control chassis sends a PWM drive signal to the corresponding IGBT series valve.

[0160] The invention provides a distributed IGBT series valve valve base controller high synchronization control protection device. The valve base controller adopts a chassis architecture and is more flexible through the QSFP high-speed optical port expansion method. Different chassis quantities can be configured according to different project requirements. A large number of external interfaces can cope with the huge IGBT series valve architecture requirements.

[0161] The present invention can realize clock synchronization of different valve base controllers by using a high-speed serial protocol encoding clock as a reference clock of a clock configuration chip;

[0162] The present invention adopts a double handshake synchronization mechanism, and a power-on handshake mode realizes the power-on consistency of multiple valve base controllers. After the power-on handshake is successful, a startup synchronization handshake mode is adopted to realize the synchronous control of multiple valve base controllers and unify the pace;

[0163] The present invention adopts a two-way handshake mechanism to ensure the reliability of the handshake signal and monitor the status of the handshake signal in real time;

[0164] The present invention adopts a dual clock mode to ensure the synchronization of control while also ensuring the real-time and reliability of protection, thereby preventing the valve base controller from being unable to correctly perform protection actions due to clock loss;

[0165] The valve base controller chassis of the present invention adopts a backplane communication mode, which enables the control board to flexibly configure the output port through the backplane and the optical port board plug-in mode, and the appearance of the valve base controller can be more standardized;

[0166] Different chassis of the valve base controller of the present invention are modulated separately, which realizes distributed computing and control, and can meet the synchronous control requirements of different topological structures;

[0167] Experiments have shown that the valve base controller architecture and synchronization method of the present invention can achieve an on-off synchronization delay error of less than 1us for the IGBT devices in the IGBT series valve.

[0168] Embodiment 2

[0169] The present invention also provides a distributed IGBT series valve base controller high synchronization control protection method, which is applied to the distributed IGBT series valve base controller high synchronization control protection device of the above embodiment, such as Figure 6 As shown, including:

[0170] Step 11: When the first control board is powered on, it generates a synchronization-related signal, sends the synchronization-related signal to each second control board, and executes a synchronization-related action corresponding to the synchronization-related signal;

[0171] Step 12: When the second control board receives the synchronization-related signal, it executes the synchronization-related action corresponding to the synchronization-related signal, and after the synchronization-related action is completed, it sends the information that the synchronization-related action is completed to the first control board;

[0172] Step 13: When the first control board completes the synchronization-related actions and receives the information that the synchronization-related actions are completed from each second control board, the information that the synchronization-related actions of all control boards are completed is sent to the main control chassis;

[0173] Step 14: Use the main control chassis to send the modulated wave to the first control board and each second control board;

[0174] Step 15: When the first control board receives the modulation wave, it uses the modulation wave to control the action of the corresponding IGBT series valve;

[0175] Step 16: When the second control board receives the modulation wave, it uses the modulation wave to control the action of the corresponding IGBT series valve.

[0176] Further, the synchronization-related signals include: a synchronization handshake signal and a synchronization start signal;

[0177] The synchronization related actions include: sending a handshake response signal to the first control board and a synchronization delay action.

[0178] Further, step 11 includes:

[0179] Step 111: After the first control board is powered on, the first control board sends a synchronous handshake signal to each second control board, and after receiving the handshake response signal sent by each second control board, sends a synchronous start signal to each second control board;

[0180] Step 112: When the first control board receives the synchronization start signal handshake sent by each second control board, the first control board is used to perform synchronization delay so that the first control board is synchronized with each second control board.

[0181] Further, step 12 includes:

[0182] Step 121: When the second control board receives the synchronous handshake signal, the second control board sends a handshake response signal to the first control board;

[0183] Step 122: When the second control board receives the synchronization start signal, the second control board sends a synchronization start signal handshake to the first control board, and performs synchronization delay, so that the second control board is synchronized with the first control board;

[0184] Step 123: When the synchronization delay of the second control board succeeds, the second control board sends information indicating that the synchronization-related actions are completed to the first control board.

[0185] Further, step 13 includes:

[0186] Step 131: When the synchronization delay of the first control board succeeds and the synchronization-related action execution completion information sent by each second control board is received, the first control board is used to send the synchronization-related action execution completion information of all control boards to the main control chassis.

[0187] Further, step 15 includes:

[0188] Step 151: using a first control board to modulate a modulation wave according to a pre-generated first triangular carrier wave to obtain a first initial signal;

[0189] Step 152: Use the first control board to perform pulse width processing and dead zone processing on the first initial signal to obtain a first PWM signal, and use the first PWM signal to control the action of the corresponding IGBT series valve.

[0190] Further, step 16 includes:

[0191] Step 161: using a second control board to modulate the modulation wave according to a pre-generated second triangular carrier to obtain a second initial signal;

[0192] Step 162: Use the second control board to perform pulse width processing and dead zone processing on the second initial signal to obtain a second PWM signal, and use the second PWM signal to control the action of the corresponding IGBT series valve.

[0193] It can be understood that the method embodiment provided above corresponds to the device embodiment described above, and the corresponding specific contents can be referenced to each other and will not be repeated here.

[0194] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.

[0195] Embodiment 3

[0196] like Figure 7 As shown, the present invention also provides an electronic device, which may be a computer device, a single-chip device, an intelligent mobile device, etc. The electronic device in this embodiment may include a processor, a memory, a transceiver component, etc. The memory, the processor, and the transceiver component are connected via a bus; the memory may be used to store an execution program, and an exemplary execution program may include instructions; the processor is used to execute the instructions stored in the memory. The memory may also be used to store data, which may be called and / or modified when the instructions are executed.

[0197] The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. It is the computing core and control core of the terminal, and is suitable for implementing one or more instructions, specifically suitable for loading and executing one or more instructions in a storage medium to implement corresponding method flows or corresponding functions, so as to implement the steps of a high-synchronization control and protection method for a distributed IGBT series valve base controller in the above-mentioned embodiment.

[0198] Embodiment 4

[0199] Based on the same inventive concept, the present invention also provides a readable storage medium, specifically an electronic device readable storage medium (Memory), which is a memory device in an electronic device for storing programs and data. It can be understood that the storage medium here can include both built-in storage media in electronic devices and, of course, extended storage media supported by electronic devices. The storage medium provides a storage space, which stores the operating system of the terminal. In addition, one or more instructions suitable for being loaded and executed by a processor are also stored in the storage space, and these instructions can be one or more execution programs (including program codes). It should be noted that the storage medium here can be a high-speed RAM memory or a non-volatile memory, such as at least one disk memory. The processor loads and executes one or more instructions stored in the storage medium, which can implement the steps of a high-synchronization control and protection method of a distributed IGBT series valve base controller in the above embodiment.

[0200] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0201] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0202] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0203] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0204] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A distributed IGBT series valve base controller high synchronization control and protection device, characterized in that: include: A main control chassis, a first valve base control chassis and a plurality of second valve base control chassis; The first valve base control chassis includes: a first control board; each of the second valve base control chassis includes: a second control board; the first control board includes: a first control chip; the second control board includes: a second control chip; The first control chip is respectively connected to the main control chassis, each of the second control chips and its corresponding IGBT series valve; the second control chip is connected to its corresponding IGBT series valve; The main control chassis is used to send a modulation wave to the first control board and each of the second control boards when receiving the information that the synchronization delay of the first control board is successful and the information that the synchronization delay of each of the second control boards is successful; The first control board is used to generate a synchronization-related signal after it is powered on, send the synchronization-related signal to each of the second control boards, and perform a synchronization-related action corresponding to the synchronization-related signal; when it completes the execution of the synchronization-related action and receives the information that the execution of the synchronization-related action is completed sent by each of the second control boards, send the information that the execution of the synchronization-related action of all control boards is completed to the main control chassis; and when receiving the modulation wave, use the modulation wave to control the action of the corresponding IGBT series valve; The second control board is used to execute the synchronization-related action corresponding to the synchronization-related signal when it receives the synchronization-related signal, and send the information of completion of the synchronization-related action to the first control board after the synchronization-related action is completed; and when the modulation wave is received, use the modulation wave to control the corresponding IGBT series valve action.

2. The device according to claim 1, characterized in that The first control board further includes: a first control clock and a first protection clock; the second control board further includes: a second control clock and a second protection clock; The first control chip is connected to the first control clock and the first protection clock respectively, and the second control chip is connected to the second control clock and the second protection clock respectively; The first control clock is used to provide a clock signal for the first control board; The second control clock is used to provide a clock signal for the second control board and is synchronized with the clock signal of the first control clock; The first protection clock is used to provide a clock signal to the first control board when the first control clock loses the clock signal; The second protection clock is used to provide a clock signal to the second control board when the second control clock loses the clock signal.

3. The device according to claim 1, characterized in that The first control board further includes: a plurality of first QSFP optical ports; The second control board further includes: a plurality of second QSFP optical ports; The first QSFP optical port is connected to the main control chassis and the second QSFP optical port respectively.

4. The device according to claim 3, characterized in that The first QSFP optical port is connected to the main control chassis and the second QSFP optical port respectively through optical fibers.

5. The device according to claim 3, characterized in that The first valve base control chassis further includes: a first backplane, a first power supply board and a plurality of first optical head interface boards; The plurality of first optical head interface boards are arranged on the first backplane in a plug-in card type, the first power board is respectively connected to the first control board and the first backplane, and the first optical head interface board is connected to the IGBT series valve; The first backplane is used to provide communication between the plurality of first optical head interface boards and the first control board, and to supply power to the plurality of first optical head interface boards; The plurality of first optical head interface boards are used for external communication of the first control board; The first power board is used to supply power to the first control board and the first backplane.

6. The device according to claim 5, characterized in that The second valve base control chassis further includes: a second backplane, a second power supply board and a plurality of second optical head interface boards; The plurality of second optical head interface boards are arranged on the second backplane in a plug-in card type, the second power board is connected to the second control board and the second backplane respectively, and the second optical head interface board is connected to the IGBT series valve; The second backplane is used to provide communication between the plurality of second optical head interface boards and the second control board, and to supply power to the plurality of second optical head interface boards; The plurality of second optical head interface boards are used for external communication of the second control board; The second power board is used to supply power to the second control board and the second backboard.

7. The device according to claim 6, characterized in that The first optical head interface board is connected to the second optical head interface board via an optical fiber; The first optical head interface board is connected to the IGBT series valve via an optical fiber; The second optical head interface board is connected to the IGBT series valve via an optical fiber.

8. The device according to claim 1, characterized in that The synchronization related signals include: a synchronization handshake signal and a synchronization start signal; The synchronization-related actions include: sending a handshake response signal and a synchronization delay action to the first control board.

9. The device according to claim 8, characterized in that The first control panel is specifically used for: When it is powered on, it sends a synchronous handshake signal to each of the second control boards, and after receiving a handshake response signal sent by each of the second control boards, it sends a synchronous start signal to each of the second control boards; When receiving the synchronization start signal handshake sent by each second control board, performing synchronization delay to synchronize with each second control board; When the synchronization delay is successful and the information that the synchronization-related actions are executed successfully is received from each of the second control boards, the information that the synchronization-related actions of all control boards are executed successfully is sent to the main control chassis.

10. The device according to claim 9, characterized in that The second control panel is specifically used for: When receiving the synchronous handshake signal, sending a handshake response signal to the first control board; When receiving the synchronization start signal, sending a synchronization start signal handshake to the first control board and performing synchronization delay to synchronize with the first control board; When the synchronization delay is successful, information indicating that the synchronization-related actions are completed is sent to the first control board.

11. The device according to claim 1, characterized in that The first control panel is further specifically used for: Modulating the modulated wave according to a pre-generated first triangular carrier wave to obtain a first initial signal; The first initial signal is subjected to pulse width processing and dead zone processing to obtain a first PWM signal, and the first PWM signal is used to control the action of the corresponding IGBT series valve.

12. The device according to claim 1, characterized in that The second control panel is further specifically used for: Modulating the modulated wave according to a pre-generated second triangular carrier wave to obtain a second initial signal; The second initial signal is subjected to pulse width processing and dead zone processing to obtain a second PWM signal, and the second PWM signal is used to control the action of the corresponding IGBT series valve.

13. A distributed IGBT series valve base controller high synchronization control protection method, applied to the distributed IGBT series valve base controller high synchronization control protection device according to any one of claims 1 to 12, characterized in that: include: When the first control board is powered on, it generates a synchronization-related signal, sends the synchronization-related signal to each second control board, and executes a synchronization-related action corresponding to the synchronization-related signal; When the second control board receives the synchronization-related signal, it executes the synchronization-related action corresponding to the synchronization-related signal, and after the synchronization-related action is completed, it sends the information that the synchronization-related action is completed to the first control board; When the first control board completes the synchronization-related actions and receives the information that the synchronization-related actions are completed sent by each second control board, the information that the synchronization-related actions of all control boards are completed is sent to the main control chassis; Using the main control chassis to send modulated waves to the first control board and each second control board; When the first control board receives the modulation wave, it uses the modulation wave to control the action of the corresponding IGBT series valve; When the second control board receives the modulation wave, it uses the modulation wave to control the action of the corresponding IGBT series valve.

14. The method according to claim 13, characterized in that The synchronization related signals include: a synchronization handshake signal and a synchronization start signal; The synchronization-related actions include: sending a handshake response signal and a synchronization delay action to the first control board.

15. The method according to claim 14, characterized in that The first control board generates a synchronization-related signal after being powered on, sends the synchronization-related signal to each second control board, and executes a synchronization-related action corresponding to the synchronization-related signal, including: When the first control board is powered on, the first control board is used to send a synchronous handshake signal to each of the second control boards, and after receiving a handshake response signal sent by each of the second control boards, a synchronous start signal is sent to each of the second control boards; When the first control board receives the synchronization start signal handshake sent by each second control board, the first control board is used to perform synchronization delay so that the first control board is synchronized with each second control board.

16. The method according to claim 14, characterized in that When the second control board receives the synchronization-related signal, executing the synchronization-related action corresponding to the synchronization-related signal includes: When the second control board receives the synchronous handshake signal, the second control board sends a handshake response signal to the first control board; When the second control board receives the synchronization start signal, the second control board sends a synchronization start signal handshake to the first control board, and performs synchronization delay, so that the second control board is synchronized with the first control board; When the synchronization delay of the second control board succeeds, the second control board is used to send information indicating that the synchronization-related action is completed to the first control board.

17. The method according to claim 14, characterized in that When the first control board completes the synchronization-related action and receives the information that the synchronization-related action is completed from each second control board, the information that the synchronization-related action is completed from all control boards is sent to the main control chassis, including: When the synchronization delay of the first control board succeeds and the information of the completion of the synchronization-related actions sent by each of the second control boards is received, the first control board is used to send the information of the completion of the synchronization-related actions of all control boards to the main control chassis.

18. The method according to claim 14, characterized in that When the first control board receives the modulation wave, the modulation wave is used to control the action of the corresponding IGBT series valve, including: Using the first control board to modulate the modulation wave according to a pre-generated first triangular carrier wave to obtain a first initial signal; The first control board is used to perform pulse width processing and dead zone processing on the first initial signal to obtain a first PWM signal, and the first PWM signal is used to control the action of the corresponding IGBT series valve.

19. The method according to claim 14, characterized in that When the second control board receives the modulation wave, the modulation wave is used to control the action of the corresponding IGBT series valve, including: Using the second control board to modulate the modulated wave according to a pre-generated second triangular carrier wave to obtain a second initial signal; The second control board is used to perform pulse width processing and dead zone processing on the second initial signal to obtain a second PWM signal, and the second PWM signal is used to control the action of the corresponding IGBT series valve.

20. An electronic device, characterized in that: include: at least one processor and memory; The memory and the processor are connected via a bus; The memory is used to store one or more programs; When the one or more programs are executed by the at least one processor, the distributed IGBT series valve base controller high synchronization control and protection method according to any one of claims 13 to 19 is implemented.

21. A readable storage medium, characterized in that: An execution program is stored thereon, and when the execution program is executed, a high-synchronization control and protection method for a distributed IGBT series valve base controller as described in any one of claims 13 to 19 is implemented.

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