Power converter with current limiting protection mechanism

Abstract

The invention discloses a power converter with a current limiting protection mechanism. An error amplifier of the power converter multiplies a difference between an output voltage (divided voltage) of the power converter and a reference voltage by a gain to output an error amplification signal. A comparator of the power converter compares an error amplification signal with a ramp signal to output an on-time signal. A current limiting circuit of the power converter detects related data of an upper bridge switch and a lower bridge switch of the power converter. The current limiting circuit of the power converter compares the working period and the non-working period of the conduction time signal with the blank time to output a current limiting signal. The control circuit of the power converter determines whether to control the operation of the upper bridge switch and the lower bridge switch according to the detected data according to the current limiting indication signal.

Description

Technical Field

[0001] The invention relates to a power converter, and in particular to a power converter with a current limiting protection mechanism. Background Art

[0002] For electronic devices, power converters are indispensable devices for adjusting power and supplying the adjusted power to the electronic devices. The upper bridge switch and the lower bridge switch of the power converter need to be switched according to data such as the voltage or current of the circuit components of the power converter in order for the power converter to provide power to the load. However, the conventional control circuit of the power converter fails to effectively control the on and off time of the upper bridge switch and the lower bridge switch, resulting in low operating efficiency of the power converter. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a power converter with a current limiting protection mechanism in view of the deficiencies of the prior art. The power converter includes an upper bridge switch, a lower bridge switch, an error amplifier, a comparator, a current limiting circuit and a control circuit. The first end of the upper bridge switch is coupled to an input voltage. The first end of the lower bridge switch is connected to the second end of the upper bridge switch. The second end of the lower bridge switch is grounded. The first end of the lower bridge switch is connected to the first end of the inductor. The second end of the inductor is connected to the first end of the output capacitor. The second end of the output capacitor is grounded. The first end of the output capacitor serves as a feedback node. The first input end of the error amplifier is coupled to a reference voltage. The second input end of the error amplifier is connected to the feedback node. The first input end of the comparator is connected to the output end of the error amplifier. The second input end of the comparator is connected to an external ramp signal generator to receive a ramp signal from the external ramp signal generator. The current limiting circuit is connected to the first end of the upper bridge switch, the second end of the lower bridge switch and the output end of the comparator. The control circuit is connected to the current limiting circuit, the control end of the upper bridge switch and the control end of the lower bridge switch. The current limiting circuit detects data at the first end of the upper bridge switch to output an upper detection signal. The current limiting circuit compares a conduction time signal received from the comparator with an upper blank time signal to output an upper current limiting signal. The control circuit determines whether to control the upper bridge switch and the lower bridge switch according to the upper detection signal based on the upper current limiting signal. The current limiting circuit detects data at the second end of the lower bridge switch to output a lower detection signal. The current limiting circuit compares the conduction time signal received from the comparator with a lower blank time signal to output a lower current limiting signal. The control circuit determines whether to control the upper bridge switch and the lower bridge switch according to the lower detection signal based on the lower current limiting signal.

[0004] In an embodiment, the control circuit controls the upper bridge switch to be turned on within the duty cycle of the on-time signal. The current limiting circuit compares the duty cycle of the on-time signal received from the comparator with the duty cycle of the upper blank time signal to output the upper current limiting signal.

[0005] In an embodiment, the control circuit controls the lower bridge switch to be turned on during the non-working period of the conduction time signal. The current limiting circuit compares the non-working period of the conduction time signal received from the comparator with the non-working period of the lower blank time signal to output the lower current limiting signal.

[0006] In an embodiment, the control circuit controls the upper bridge switch to be turned on within the duty cycle of the on-time signal. When the current limiting circuit determines that the duty cycle of the on-time signal is less than the duty cycle of the upper blank time signal, the current limiting circuit determines that the data of the first end of the upper bridge switch detected within the duty cycle of the on-time signal is not used to control and switch the upper bridge switch and the lower bridge switch.

[0007] In an embodiment, the control circuit controls the lower bridge switch to be turned on during the non-operating period of the on-time signal. When the current limiting circuit determines that the non-operating period of the on-time signal received from the comparator is less than the non-operating period of the lower blank time signal, the current limiting circuit determines that the data of the second end of the lower bridge switch detected during the non-operating period of the on-time signal is not used to control and switch the upper bridge switch and the lower bridge switch.

[0008] In an embodiment, the current limiting circuit includes an upper current limiting detection circuit, an upper cycle comparison circuit, an upper current limiting indication circuit, a lower current limiting detection circuit, a lower cycle comparison circuit and a lower current limiting indication circuit. The upper current limiting detection circuit is connected to the first end of the upper bridge switch. The upper current limiting detection circuit is configured to detect data of the first end of the upper bridge switch to output the upper detection signal. The upper cycle comparison circuit is connected to the upper current limiting detection circuit and the output end of the comparator. The upper cycle comparison circuit is configured to compare the conduction time signal received from the comparator with the upper blank time signal received from the upper current limiting detection circuit to output an upper cycle comparison signal. The upper current limiting indication circuit is connected to the upper cycle comparison circuit and the control circuit. The upper current limiting indication circuit is configured to output the upper current limiting signal to the control circuit according to the upper cycle comparison signal received from the upper cycle comparison circuit. The lower current limiting detection circuit is connected to the second end of the lower bridge switch. The lower side current limiting detection circuit is configured to detect data at the second end of the lower bridge switch to output the lower side detection signal. The lower side cycle comparison circuit is connected to the lower side current limiting detection circuit and the output end of the comparator. The lower side cycle comparison circuit is configured to compare the working cycle of the conduction time signal received from the comparator with the lower side blank time signal received from the lower side current limiting detection circuit to output a lower side cycle comparison signal. The lower side current limiting indication circuit is connected to the lower side cycle comparison circuit and the control circuit. The lower side current limiting indication circuit is configured to output the lower side current limiting signal to the control circuit based on the lower side cycle comparison signal received from the lower side cycle comparison circuit.

[0009] In an embodiment, the upper current limiting detection circuit includes an upper blank time setting circuit and an upper detection circuit. The upper blank time setting circuit is connected to the upper period comparison circuit. The upper blank time setting circuit is configured to set and output the upper blank time signal to the upper period comparison circuit. The upper detection circuit is connected to the first end of the upper bridge switch and the upper current limiting indication circuit. The upper detection circuit is configured to detect data at the first end of the upper bridge switch to output the upper detection signal to the upper current limiting indication circuit. The upper current limiting indication circuit determines whether to transmit the upper detection signal received from the upper detection circuit to the control circuit based on the upper period comparison signal.

[0010] In an embodiment, the lower current limiting detection circuit includes a lower blank time setting circuit and a lower detection circuit. The lower blank time setting circuit is connected to the lower period comparison circuit. The lower blank time setting circuit is configured to set and output the lower blank time signal to the lower period comparison circuit. The lower detection circuit is connected to the second end of the lower bridge switch and the lower current limiting indication circuit. The lower detection circuit is configured to detect data at the second end of the lower bridge switch to output the lower detection signal to the lower current limiting indication circuit. The lower current limiting indication circuit determines whether to transmit the lower detection signal received from the lower detection circuit to the control circuit based on the lower period comparison signal.

[0011] In an embodiment, the upper detection circuit includes an upper comparator and a first upper AND gate. The upper comparator is a comparator. The first input of the upper comparator is coupled to an upper threshold voltage. The second input of the upper comparator is connected to the first end of the upper bridge switch. The first upper AND gate is an AND gate. The first input of the first upper AND gate is connected to the output of the upper blank time setting circuit. The second input of the first upper AND gate is connected to the output of the upper comparator. The output of the first upper AND gate is connected to the input of the upper current limiting indication circuit and the input of the lower current limiting indication circuit.

[0012] In an embodiment, the lower side detection circuit includes a lower side comparator and a first lower side AND gate. The lower side comparator is a comparator. The first input end of the lower side comparator is coupled to a lower side critical voltage. The second input end of the lower side comparator is connected to the second end of the lower bridge switch. The first lower side AND gate is an AND gate. The first input end of the first lower side AND gate is connected to the output end of the lower side blank time setting circuit. The second input end of the first lower side AND gate is connected to the output end of the lower side comparator. The output end of the first lower side AND gate is connected to the input end of the lower side current limiting indication circuit and the input end of the upper side current limiting indication circuit.

[0013] In an embodiment, the upper current limiting indication circuit comprises an upper OR gate, an upper flip-flop and a second upper AND gate. The upper OR gate is an OR gate. The first input end of the upper OR gate is connected to the output end of the upper period comparison circuit to receive an upper period inversion comparison signal. The second input end of the upper OR gate is connected to the output end of the first lower AND gate. The upper flip-flop is a flip-flop. The first input end of the upper flip-flop is connected to the output end of the upper period comparison circuit to receive the upper period comparison signal. The second input end of the upper flip-flop is connected to the output end of the upper OR gate. The second upper AND gate is an AND gate. The first input end of the second upper AND gate is connected to the output end of the first upper AND gate. The second input end of the second upper AND gate is connected to the inverting output end of the upper flip-flop. The output end of the second upper AND gate is connected to the input end of the control circuit.

[0014] In an embodiment, the lower current limiting indication circuit comprises a lower OR gate, a lower flip-flop and a second lower AND gate. The lower OR gate is an OR gate. The first input end of the lower OR gate is connected to the output end of the lower period comparison circuit to receive a lower period inversion comparison signal. The second input end of the lower OR gate is connected to the output end of the first upper AND gate. The lower flip-flop is a flip-flop. The first input end of the lower flip-flop is connected to the output end of the lower period comparison circuit to receive the lower period comparison signal. The second input end of the lower flip-flop is connected to the output end of the lower OR gate. The second lower AND gate is an AND gate. The first input end of the second lower AND gate is connected to the output end of the first lower AND gate. The second input end of the second lower AND gate is connected to the inverting output end of the lower flip-flop. The output end of the second lower AND gate is connected to the input end of the control circuit.

[0015] In an embodiment, the power converter with current limiting protection mechanism further comprises an input resistor and an input capacitor. The first end of the input resistor is connected to the output end of the error amplifier and the first input end of the comparator. The first end of the input capacitor is connected to the second end of the input resistor. The second end of the input capacitor is grounded.

[0016] In an embodiment, the power converter with current limiting protection mechanism further comprises a voltage divider circuit, wherein the input end of the voltage divider circuit is connected to a node between the second end of the inductor and the first end of the output capacitor, and the output end of the voltage divider circuit is connected to the second input end of the error amplifier.

[0017] In an embodiment, the voltage divider circuit comprises a first resistor and a second resistor. The first end of the first resistor is connected to a node between the second end of the inductor and the first end of the output capacitor. The first end of the second resistor is connected to the second end of the first resistor, the second end of the second resistor is grounded, and the node between the first end of the second resistor and the second end of the first resistor is connected to the second input end of the error amplifier.

[0018] As described above, the present invention provides a power converter with a current limiting protection mechanism. The power converter of the present invention can detect whether the data detection time of the upper bridge switch and the lower bridge switch falls within the time interval in which the voltage or current signal unexpectedly fluctuates after the upper bridge switch and the lower bridge switch are switched, so as to determine whether the detected data can be used as a basis for controlling the operation of the upper bridge switch and the lower bridge switch. The power converter of the present invention accurately switches and controls the upper bridge switch and the lower bridge switch based on the accurate data detected, especially when the load is heavy, it can accurately and quickly switch at high frequency, so as to effectively improve the overall operating efficiency of the power converter, so that the load obtains sufficient power, and at the same time prevents the power converter as a whole from overvoltage and overcurrent.

[0019] To further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are only for reference and description and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 FIG. 4 is a circuit diagram of a power converter with a current limiting protection mechanism according to a first embodiment of the present invention.

[0021] Figure 2 FIG. 4 is a circuit diagram of a power converter with a current limiting protection mechanism according to a second embodiment of the present invention.

[0022] Figure 3 FIG. 4 is a circuit diagram of a power converter with a current limiting protection mechanism according to a third embodiment of the present invention.

[0023] Figure 4 FIG. 4 is a circuit diagram of a power converter with a current limiting protection mechanism according to a fourth embodiment of the present invention.

[0024] Figure 5 FIG. 4 is a circuit diagram of a power converter with a current limiting protection mechanism according to a fifth embodiment of the present invention.

[0025] Figure 6 FIG. 4 is a waveform diagram of signals of a power converter with a current limiting protection mechanism according to a fifth embodiment of the present invention.

[0026] Figure 7FIG. 4 is a waveform diagram of signals of a power converter with a current limiting protection mechanism according to a fifth embodiment of the present invention.

[0027] Figure 8 FIG. 4 is a waveform diagram of signals of a power converter with a current limiting protection mechanism according to a fifth embodiment of the present invention.

[0028] Fig. 9 FIG. 4 is a waveform diagram of signals of a power converter with a current limiting protection mechanism according to a fifth embodiment of the present invention. DETAILED DESCRIPTION

[0029] The following is an explanation of the embodiments of the present invention through specific specific embodiments. Those skilled in the art can understand the advantages and effects of the present invention from the contents disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed in various ways based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only simple schematic illustrations and are not depicted according to actual dimensions. It is stated in advance. The following embodiments will further explain the relevant technical contents of the present invention in detail, but the disclosed contents are not intended to limit the scope of protection of the present invention. In addition, the term "or" used herein may include any one or more combinations of the associated listed items depending on the actual situation.

[0030] See also Figure 1 , which is a circuit diagram of a power converter with a current limiting protection mechanism according to a first embodiment of the present invention.

[0031] The power converter according to the first embodiment of the present invention comprises a high-bridge switch HS, a low-bridge switch LS, an error amplifier ER, a comparator CMP, a current limiting circuit CLC and a control circuit CTR.

[0032] The first end of the upper bridge switch HS is coupled to an input voltage VIN. The first end of the lower bridge switch LS is connected to the second end of the upper bridge switch HS. The second end of the lower bridge switch LS is grounded. The first end of the lower bridge switch LS is connected to the first end of the inductor L. The second end of the inductor L is connected to the first end of the output capacitor Cout. The second end of the output capacitor Cout is grounded.

[0033] A first input terminal, such as a non-inverting input terminal, of the error amplifier ER is coupled to a reference voltage VREF. A second input terminal, such as an inverting input terminal, of the error amplifier ER is connected to a node between the second terminal of the inductor L and the first terminal of the output capacitor Cout (this node is used as a feedback node in the first embodiment) to receive a feedback voltage VFB of the feedback node, i.e., the output voltage VOUT of the power converter of the present invention.

[0034] A first input terminal, such as an inverting input terminal, of the comparator CMP is connected to the output terminal of the error amplifier ER, and a second input terminal, such as a non-inverting input terminal, of the comparator CMP is connected to an external ramp signal generator to receive a ramp signal RAMP from the external ramp signal generator.

[0035] If necessary, the power converter of the first embodiment of the present invention can also be Figure 1 The circuit shown includes an input resistor Rc and an input capacitor Cc. The first end of the input resistor Rc is connected to the output end of the error amplifier ER and the first input end of the comparator CMP, such as the inverting input end. The first end of the input capacitor Cc is connected to the second end of the input resistor Rc. The second end of the input capacitor Cc is grounded.

[0036] The comparator CMP compares the voltage of an error amplified signal received from the output terminal of the error amplifier ER (or the voltage of the first terminal of the input resistor Rc) with a ramp signal RAMP received from an external ramp signal generator to output an on-time signal.

[0037] The current limiting circuit CLC is connected to the output end of the comparator CMP, the first end of the upper bridge switch HS and the second end of the lower bridge switch LS. The control circuit CTR is connected to the output end of the current limiting circuit CLC, the control end of the upper bridge switch HS and the control end of the lower bridge switch LS.

[0038] The current limiting circuit CLC can detect data such as a voltage or a current at the first end of the upper bridge switch HS to output an upper side detection signal.

[0039] It is worth noting that within a period of time after the upper bridge switch HS and the lower bridge switch LS are switched, the voltage signal and the current signal of the power converter will unexpectedly fluctuate, resulting in inaccurate data detected at this time. In this article, this period of time is defined as an upper blank time signal and a lower blank time signal. In the present invention, the control circuit CTR does not control the operation of the upper bridge switch HS and the lower bridge switch LS based on the data detected within an upper blank time signal and a lower blank time signal.

[0040] The current limiting circuit CLC compares a conduction time signal received from the comparator CMP with an upper blank time signal to output an upper current limiting signal. The control circuit CTR determines whether to control and switch the upper bridge switch HS and the lower bridge switch LS according to an upper current limiting signal received from the current limiting circuit CLC.

[0041] The control circuit CTR can control the upper bridge switch HS to be turned on within the working cycle of the on-time signal, and can control the lower bridge switch LS to be turned off within the working cycle of the on-time signal.

[0042] When the current limiting circuit CLC determines that the duty cycle of a conduction time signal received from the comparator CMP is less than the duty cycle of an upper blank time signal, the current limiting circuit CLC decides that the data of the first end of the upper bridge switch HS detected within the duty cycle of this conduction time signal is not used to control and switch the upper bridge switch HS and the lower bridge switch LS.

[0043] The current limiting circuit CLC may compare the on-time signal received from the comparator CMP with a lower-side blank time signal to output a lower-side current limiting signal.

[0044] The control circuit CTR decides whether to control and switch the lower bridge switch LS and the lower bridge switch LS according to the lower current limiting signal received from the current limiting circuit CLC, based on the data such as the voltage or current of the first end of the lower bridge switch LS currently detected contained in the lower detection signal received from the current limiting circuit CLC.

[0045] The control circuit CTR can control the lower bridge switch LS to be turned on during the non-operating period of the on-time signal, and can control the upper bridge switch HS to be turned off during the non-operating period of the on-time signal.

[0046] When the current limiting circuit CLC determines that the non-working period of a conduction time signal received from the comparator CMP is less than the non-working period of a lower blank time signal, the current limiting circuit CLC decides that the data at the second end of the lower bridge switch LS detected during the non-working period of the conduction time signal is not used to control and switch the upper bridge switch HS and the lower bridge switch LS.

[0047] See also Figure 2 , which is a circuit diagram of a power converter according to a second embodiment of the present invention. The second embodiment has the same contents as the first embodiment and will not be described in detail herein.

[0048] In the second embodiment of the present invention, the current limiting circuit of the power converter of the present invention includes an upper side current limiting detection circuit HSDR, an upper side cycle comparison circuit HSDT, an upper side current limiting indication circuit HSCL, a lower side current limiting detection circuit LSDR, a lower side cycle comparison circuit LSDT and a lower side current limiting indication circuit LSCL.

[0049] If necessary, the current limiting circuit of the power converter of the present invention may further include a voltage divider circuit DVR. The voltage divider circuit DVR may include a first resistor R1 and a second resistor R2.

[0050] The first end of the first resistor R1 is connected to a node between the second end of the inductor L and the first end of the output capacitor Cout. The first end of the second resistor R2 is connected to the second end of the first resistor R1. The second end of the second resistor R2 is grounded. The node between the first end of the second resistor R2 and the second end of the first resistor R1 is connected to a second input end of the error amplifier ER, for example, an inverting input end.

[0051] The upper current limiting detection circuit HSDR is connected to the first end of the upper bridge switch HS and detects data such as voltage or current at the first end of the upper bridge switch HS to output an upper detection signal HSOCP.

[0052] The upper cycle comparison circuit HSDT is connected to the upper current limiting detection circuit HSDR and the output terminal of the comparator CMP. The upper cycle comparison circuit HSDT compares an on-time signal TON received from the comparator CMP with an upper blank time signal HSBLK received from the upper current limiting detection circuit HSDR to output an upper cycle comparison signal.

[0053] The upper current limiting indicating circuit HSCL is connected to the upper cycle comparison circuit HSDT and the control circuit CTR. The upper current limiting indicating circuit HSCL outputs an upper current limiting signal to the control circuit CTR according to an upper cycle comparison signal received from the upper cycle comparison circuit HSDT.

[0054] The lower current limiting detection circuit LSDR is connected to the second end of the lower bridge switch LS. The lower current limiting detection circuit LSDR detects data such as a voltage or a current at the second end of the lower bridge switch LS to output a lower detection signal LSOCP.

[0055] The lower cycle comparison circuit LSDT is connected to the lower current limiting detection circuit LSDR and the output end of the comparator CMP. The lower cycle comparison circuit LSDT compares the working cycle of a turn-on time signal TON received from the comparator CMP with a lower blank time signal LSBLK received from the lower current limiting detection circuit LSDR to output a lower cycle comparison signal.

[0056] The lower current limiting indicating circuit LSCL is connected to the lower period comparison circuit LSDT and the control circuit CTR. The lower current limiting indicating circuit LSCL outputs a lower current limiting signal to the control circuit CTR according to a lower period comparison signal received from the lower period comparison circuit LSDT.

[0057] The control circuit CTR determines whether to control the operation of the upper bridge switch HS and the lower bridge switch LS according to an upper current limiting signal received from the upper current limiting indicating circuit HSCL and a lower current limiting signal received from the lower current limiting indicating circuit LSCL.

[0058] See also Figure 3 , which is a circuit diagram of a power converter with a current limiting protection mechanism according to a third embodiment of the present invention. The third embodiment of the present invention has the same contents as the first and second embodiments, and will not be described in detail herein.

[0059] In the current limiting circuit of the power converter of the present invention in the third embodiment of the present invention, the upper side current limiting detection circuit HSDR includes an upper side blank time setting circuit HSBK and an upper side detection circuit HSVD, and the lower side current limiting detection circuit LSDR includes a lower side blank time setting circuit LSBK and a lower side detection circuit LSVD.

[0060] The upper side blank time setting circuit HSBK is connected to the upper side cycle comparison circuit HSDT. The upper side detection circuit HSVD is connected to the first end of the upper bridge switch HS and the upper side current limiting indication circuit HSCL (and the lower side current limiting indication circuit LSCL). The lower side blank time setting circuit LSBK is connected to the lower side cycle comparison circuit LSDT. The lower side detection circuit LSVD is connected to the second end of the lower bridge switch LS and the lower side current limiting indication circuit LSCL (and the upper side current limiting indication circuit HSCL).

[0061] The upper side detection circuit HSVD detects data such as a voltage or a current at the first end of the upper bridge switch HS to output an upper side detection signal HSOCP to the upper side current limiting indication circuit HSCL.

[0062] The upper blank time setting circuit HSBK sets an upper blank time signal HSBLK to the upper cycle comparison circuit HSDT, and outputs the upper blank time signal HSBLK to the upper cycle comparison circuit HSDT.

[0063] The upper cycle comparison circuit HSDT compares an on-time signal TON received from the comparator CMP with an upper blank time signal HSBLK received from the upper blank time setting circuit HSBK to output an upper cycle comparison signal.

[0064] The upper current limit indicating circuit HSCL determines whether the upper bridge switch HS transmits an upper detection signal HSOCP received from the upper detection circuit HSVD to the control circuit CTR according to an upper cycle comparison signal received from the upper cycle comparison circuit HSDT.

[0065] The lower detection circuit LSVD detects data such as a voltage or a current at the second end of the lower bridge switch LS to output a lower detection signal LSOCP to the lower current limiting indicating circuit LSCL.

[0066] The lower blank time setting circuit LSBK sets a lower blank time signal LSBLK to the lower cycle comparison circuit LSDT, and outputs the lower blank time signal LSBLK to the lower cycle comparison circuit LSDT.

[0067] The lower cycle comparison circuit LSDT compares a duty cycle of an on-time signal TON received from the comparator CMP with a lower blank time signal LSBLK received from the lower blank time setting circuit LSBK to output a lower cycle comparison signal.

[0068] The lower current limiting indicating circuit LSCL determines whether to transmit a lower detection signal LSOCP received from the lower detection circuit LSVD to the control circuit CTR according to a lower period comparison signal received from the lower period comparison circuit LSDT.

[0069] The control circuit CTR controls and switches the upper bridge switch HS and the lower bridge switch LS according to receiving an upper detection signal HSOCP from the upper current limiting indicating circuit HSCL and receiving an upper detection signal LSOCP from the lower current limiting indicating circuit LSCL.

[0070] See also Figure 4 , which is a circuit diagram of a power converter with a current limiting protection mechanism according to a fourth embodiment of the present invention. The fourth embodiment of the present invention has the same contents as the first to third embodiments, and will not be described in detail herein.

[0071] In the high-side current limiting detection circuit HSDR of the power converter according to the fourth embodiment of the present invention, the high-side detection circuit HSVD includes a high-side comparator HSCM and a first high-side AND gate HSAND1 .

[0072] In the low-side current limiting detection circuit LSDR of the power converter according to the fourth embodiment of the present invention, the low-side detection circuit LSVD includes a low-side comparator LSCM and a first low-side AND gate LSAND1 .

[0073] If necessary, the power converter of the present invention can be Figure 4 The figure also includes a sensing resistor as an upper sensing resistor Rsen1 and another sensing resistor as a lower sensing resistor Rsen2.

[0074] The upper comparator HSCM is a comparator. A first input terminal, such as an inverting input terminal, of the upper comparator HSCM is coupled to an upper threshold voltage VTH1. A second input terminal, such as a non-inverting input terminal, of the upper comparator HSCM is connected to a first terminal of the upper bridge switch HS or a second terminal of the upper sensing resistor Rsen1.

[0075] The first upper AND gate HSAND1 is an AND gate. The first input terminal of the first upper AND gate HSAND1 is connected to the output terminal of the upper blank time setting circuit HSBK. The second input terminal of the first upper AND gate HSAND1 is connected to the output terminal of the upper comparator HSCM.

[0076] The output end of the first upper AND gate HSAND1 is connected to the input end of the upper current limiting indicating circuit HSCL and the input end of the lower current limiting indicating circuit LSCL.

[0077] The lower comparator LSCM is a comparator. A first input terminal, such as an inverting input terminal, of the lower comparator LSCM is coupled to a lower threshold voltage VTH2. A second input terminal, such as a non-inverting input terminal, of the lower comparator LSCM is connected to the second terminal of the lower bridge switch LS or the first terminal of the lower sensing resistor Rsen2.

[0078] The first lower AND gate LSAND1 is an AND gate. A first input terminal of the first lower AND gate LSAND1 is connected to the output terminal of the lower blank time setting circuit LSBK. A second input terminal of the first lower AND gate LSAND1 is connected to the output terminal of the lower comparator LSCM.

[0079] The output end of the first lower AND gate LSAND1 is connected to the input end of the lower current limiting indicating circuit LSCL and the input end of the upper current limiting indicating circuit HSCL.

[0080] See also Figures 5 to 9 ,in Figure 5 is a circuit diagram of a power converter with a current limiting protection mechanism according to a fifth embodiment of the present invention. Figures 6 to 9 1 is a waveform diagram of signals of a power converter with a current limiting protection mechanism according to a fifth embodiment of the present invention. The fifth embodiment of the present invention has the same contents as the first to fourth embodiments and will not be described in detail herein.

[0081] In the power converter of the fifth embodiment of the present invention, the high-side current limiting indicating circuit HSCL includes a high-side OR gate HSOR, a high-side flip-flop HSSR and a second high-side AND gate HSAND2.

[0082] The upper OR gate HSOR is an OR gate. A first input terminal of the upper OR gate HSOR is connected to the output terminal of the upper cycle comparison circuit HSDT to receive an upper cycle reverse comparison signal HSR from the upper cycle comparison circuit HSDT. A second input terminal of the upper OR gate HSOR is connected to the output terminal of the first lower AND gate LSAND1.

[0083] The upper flip-flop HSSR is a flip-flop, for example but not limited to an SR flip-flop. The first input terminal S of the upper flip-flop HSSR is connected to the output terminal of the upper cycle comparison circuit HSDT to receive an upper cycle comparison signal HSS from the upper cycle comparison circuit HSDT. The second input terminal R of the upper flip-flop HSSR is connected to the output terminal of the upper OR gate HSOR.

[0084] The level of an upper period comparison signal HSS described herein is opposite to the level of an upper period reverse comparison signal HSR, but the present invention is not limited thereto.

[0085] The second upper AND gate HSAND2 is an AND gate. The first input end of the second upper AND gate HSAND2 is connected to the output end of the first upper AND gate HSAND1. The second input end of the second upper AND gate HSAND2 is connected to the inverting output end QB of the upper flip-flop HSSR. The output end of the second upper AND gate HSAND2 is connected to the input end of the control circuit CTR to output an upper feedback signal HSOCPINT to the input end of the control circuit CTR.

[0086] In the power converter of the fifth embodiment of the present invention, the low-side current limiting indicating circuit LSCL comprises a low-side OR gate LSOR, a low-side flip-flop LSSR and a second low-side AND gate LSAND2.

[0087] The lower OR gate LSOR is an OR gate. A first input terminal of the lower OR gate LSOR is connected to the output terminal of the lower period comparison circuit LSDT to receive a lower period inverse comparison signal LSR from the lower period comparison circuit LSDT. A second input terminal of the lower OR gate LSOR is connected to the output terminal of the first upper AND gate HSAND1.

[0088] The lower flip-flop LSSR is a flip-flop. A first input terminal S of the lower flip-flop LSSR is connected to the output terminal of the lower cycle comparison circuit LSDT to receive a lower cycle comparison signal LSS from the lower cycle comparison circuit LSDT. A second input terminal R of the lower flip-flop LSSR is connected to the output terminal of the lower OR gate LSOR.

[0089] The level of the lower periodic reverse comparison signal LSR described herein is opposite to the level of the lower periodic comparison signal LSS described above, but the present invention is not limited thereto.

[0090] The second lower AND gate LSAND2 is an AND gate. The first input end of the second lower AND gate LSAND2 is connected to the output end of the first lower AND gate LSAND1. The second input end of the second lower AND gate LSAND2 is connected to the inverting output end QB of the lower flip-flop LSSR. The output end of the second lower AND gate LSAND2 is connected to the input end of the control circuit CTR to output a lower feedback signal LSOCPINT to the input end of the control circuit CTR.

[0091] The comparator CMP compares the voltage of an error amplified signal received from the output terminal of the error amplifier ER (or the voltage of the first terminal of the input resistor Rc) with a ramp signal RAMP received from an external ramp signal generator to output an on-time signal.

[0092] The control circuit controls the operation of the upper bridge switch HS according to an on-time signal TON received from the comparator CMP. The control circuit CTR controls the upper bridge switch HS to be turned on during a working cycle of the on-time signal TON, and to be turned off during a non-working cycle of the on-time signal TON. The control circuit CTR controls the lower bridge switch LS to be turned off during a working cycle of the on-time signal TON, and to be turned on during a non-working cycle of the on-time signal TON. That is, the control circuit CTR turns on the upper bridge switch HS and the lower bridge switch LS in turn.

[0093] like Figure 6 As shown, the duty cycle of the third waveform among the multiple waveforms of the on-time signal TON output by the comparator CMP is smaller than the duty cycle of an upper blank time signal HSBLK.

[0094] When the upper cycle comparison circuit HSDT determines that the duty cycle of an on-time signal TON received from the comparator CMP is less than the duty cycle of an upper blank time signal HSBLK received from the upper current limit detection circuit HSDR, the upper cycle comparison circuit HSDT is as follows: Figure 6 The circuit HS1 outputs an upper cycle comparison signal HSS having a high logic value "1" to the first input terminal S of the upper flip-flop HSSR, and outputs an upper cycle comparison signal HSR having a low logic value "0" to the second input terminal R of the upper flip-flop HSSR. As a result, the second input terminal of the second upper AND gate HSAND2 receives the low logic value "0" from the inverting output terminal QB of the upper flip-flop HSSR. At this time, regardless of the result output by the output terminal of the first upper AND gate HSAND1, the control circuit CTR receives the low logic value "0" from the output terminal of the second upper AND gate HSAND2.

[0095] That is to say, when the duty cycle of a turn-on time signal TON output by the comparator CMP is less than the duty cycle of an upper blank time signal HSBLK, the control circuit CTR does not control and switch the upper bridge switch HS based on the voltage at the first end of the upper bridge switch HS or the second end of the upper sensing resistor Rsen1 or the second end of the upper sensing resistor Rsen1 detected by the upper current limiting detection circuit HSDR.

[0096] In detail, in an upper blank time signal HSBLK after the upper bridge switch HS is switched, the (voltage) signal at the first end of the upper bridge switch HS or the second end of the upper sensing resistor Rsen1 will fluctuate due to the turning on of the upper bridge switch HS. Therefore, the (voltage) data of the (voltage) signal at the first end of the upper bridge switch HS or the second end of the upper sensing resistor Rsen1 detected in this upper blank time signal HSBLK is incorrect and cannot be used to control and switch the upper bridge switch HS.

[0097] The upper bridge switch HS is turned on within the working cycle of the on-time signal TON. The smaller the working cycle of the on-time signal TON, the shorter the on-time length of the upper bridge switch HS. When the working cycle of the on-time signal TON (i.e., the on-time length of the upper bridge switch HS) is too small and is smaller than an upper side blank time signal HSBLK after the upper bridge switch HS is turned on, the first end (voltage) signal of the upper bridge switch HS detected within the on-time of the upper bridge switch HS is incorrect (voltage) data and is not used to control and switch the upper bridge switch HS.

[0098] Furthermore, when the duty cycle of the on-time signal TON is short, the upper bridge switch HS is turned on for a short time, and the output current of the power converter is small. In this case, the circuit components such as the upper bridge switch HS of the power converter will not be burned due to overcurrent. At this time, the current limiting circuit does not need to control the operation of the upper bridge switch HS according to data such as the voltage at the first end of the upper bridge switch HS or the second end of the upper side sensing resistor Rsen1 to achieve the current limiting operation.

[0099] On the contrary, when the duty cycle of a turn-on time signal TON output by the comparator CMP is greater than the duty cycle of an upper blank time signal HSBLK, the control circuit CTR controls and switches the upper bridge switch HS according to the voltage at the first end of the upper bridge switch HS or the second end of the upper sensing resistor Rsen1 detected by the upper current limiting detection circuit HSDR.

[0100] On the other hand, when the lower cycle comparison circuit LSDT determines that the non-operating period of the on-time signal TON received from the comparator CMP is less than the non-operating period of the lower blank time signal LSBLK received from the lower current limiting detection circuit LSDR, the lower cycle comparison circuit LSDT outputs a lower cycle comparison signal LSS with a logic value of "1" to the first input terminal S of the lower flip-flop LSSR, and outputs a lower cycle inversion comparison signal LSR with a logic value of "0" to the second input terminal R of the lower flip-flop LSSR. As a result, the second input terminal of the second lower AND gate LSAND2 receives the logic value "0" from the inverting output terminal QB of the lower flip-flop LSSR. At this time, regardless of the result output by the output terminal of the first lower AND gate LSAND1, the control circuit CTR receives the logic value "0" from the output terminal of the second lower AND gate LSAND2.

[0101] When Figure 7 When the non-operating period of the on-time signal TON output by the comparator CMP shown is less than the non-operating period of the lower blank time signal LSBLK, the lower period comparison circuit LSDT outputs a lower period comparison signal LSS of a high logic level. As a result, the second lower AND gate LSAND2 outputs a lower feedback signal LSOCPINT of a low level to the control circuit CTR. In this way, it is equivalent to blocking the lower feedback signal LSOCPINT through the second lower AND gate LSAND2. The control circuit CTR does not control and switch the lower bridge switch LS based on the lower feedback signal LSOCPINT of a low level. That is, the control circuit CTR does not control and switch the lower bridge switch LS based on the voltage of the second end of the lower bridge switch LS or the first end of the lower sensing resistor Rsen detected by the lower current limiting detection circuit LSDR at this time.

[0102] like Figure 8 As shown, the second lower AND gate LSAND2 will not output a lower feedback signal LSOCPINT of a high logic level until the inductor current IL (i.e., the current of the inductor L) increases, so that the upper current limiting detection circuit HSDR outputs an upper detection signal HSOCP of a high logic level. The control circuit CTR controls and switches the lower bridge switch LS according to the lower feedback signal LSOCPINT of a high level. That is, the control circuit CTR controls and switches the lower bridge switch LS according to the voltage of the second end of the lower bridge switch LS or the first end of the lower sensing resistor Rsen detected by the lower current limiting detection circuit LSDR at this time.

[0103] On the contrary, Fig. 9As shown, when the upper current limiting detection circuit HSDR outputs an upper detection signal HSOCP of a high logic level, the second lower AND gate LSAND2 then outputs a lower feedback signal LSOCPINT of a high logic level. The control circuit CTR controls and switches the lower bridge switch LS according to the lower feedback signal LSOCPINT of a high level. Afterwards, when there is no decrease in the inductor current IL and the upper detection signal HSOCP is at a low logic level, and the non-operating period of the on-time signal TON output by the comparator CMP is less than the non-operating period of the lower blank time signal LSBLK, the lower cycle comparison circuit LSDT outputs a lower cycle comparison signal LSS of a high logic level. As a result, the second lower AND gate LSAND2 outputs a lower feedback signal LSOCPINT of a low level to the control circuit CTR. In this way, it is equivalent to blocking the lower feedback signal LSOCPINT through the second lower AND gate LSAND2. The control circuit CTR does not control and switch the lower bridge switch LS according to the lower feedback signal LSOCPINT of a low level.

[0104] like Figure 8 and Fig. 9 A minimum off-time signal TOFFMIN is shown as the minimum off-time of the high-bridge switch HS, and a switching frequency signal FQ is shown as the switching frequency of the low-bridge switch LS and the high-bridge switch HS.

[0105] In detail, in a lower blank time signal LSBLK after the lower bridge switch LS is turned on, the (voltage) signal at the second end of the lower bridge switch LS will fluctuate due to the turning on of the lower bridge switch LS. Therefore, the (voltage) data of the (voltage) signal at the second end of the lower bridge switch LS or the first end of the lower sensing resistor Rsen detected in this lower blank time signal LSBLK is incorrect and cannot be used to control and switch the lower bridge switch LS.

[0106] The lower bridge switch LS is turned on during the non-operating period of the on-time signal TON. The smaller the non-operating period of the on-time signal TON, the shorter the on-time length of the lower bridge switch LS. When the operating period of the on-time signal TON (i.e., the on-time length of the lower bridge switch LS) is too small and is less than a lower blank time signal LSBLK after the lower bridge switch LS is turned on, the (voltage) signal of the second end of the lower bridge switch LS or the first end of the lower sensing resistor Rsen detected during the on-time of the lower bridge switch LS is incorrect (voltage) data and is not used to control and switch the lower bridge switch LS.

[0107] On the contrary, when the duty cycle of the on-time signal TON output by the comparator CMP is greater than the duty cycle of the lower blank time signal LSBLK, the control circuit CTR controls and switches the lower bridge switch LS according to the voltage at the second end of the lower bridge switch LS or the first end of the lower sensing resistor Rsen or the second end of the lower sensing resistor Rsen1 detected by the lower current limiting detection circuit LSDR.

[0108] Furthermore, when the non-operating period of the on-time signal TON is short, the time for the lower bridge switch HS to be turned on is short, and the current flowing through the inductor L of the power converter and through the lower bridge switch LS to the ground is small. In this case, the circuit components such as the lower bridge switch LS of the power converter will not be burned due to overcurrent. At this time, the current limiting circuit does not need to control the operation of the upper bridge switch HS according to data such as the voltage of the second end of the lower bridge switch LS or the first end of the lower side sensing resistor Rsen2 to achieve the current limiting operation.

[0109] In summary, the present invention provides a power converter with a current limiting protection mechanism. The power converter of the present invention can detect whether the data detection time of the upper bridge switch and the lower bridge switch falls within the time interval in which the voltage or current signal unexpectedly fluctuates after the upper bridge switch and the lower bridge switch are switched, so as to determine whether the detected data can be used as a basis for controlling the operation of the upper bridge switch and the lower bridge switch. The power converter of the present invention accurately switches and controls the upper bridge switch and the lower bridge switch based on the accurate data detected, especially when the load is heavy, it can accurately and quickly switch at high frequency, so as to effectively improve the overall operating efficiency of the power converter, so that the load obtains sufficient power, and at the same time prevents the power converter as a whole from overvoltage and overcurrent.

[0110] The contents disclosed above are only preferred feasible embodiments of the present invention, and are not intended to limit the claims of the present invention. Therefore, all equivalent technical changes made using the contents of the present invention description and drawings are included in the claims of the present invention.

Claims

1. A power converter with a current limiting protection mechanism, It is characterized in that The power converter with current limiting protection mechanism comprises: An upper bridge switch, wherein a first end of the upper bridge switch is coupled to an input voltage; a lower bridge switch, wherein a first end of the lower bridge switch is connected to a second end of the upper bridge switch, the second end of the lower bridge switch is grounded, the first end of the lower bridge switch is connected to a first end of an inductor, the second end of the inductor is connected to a first end of an output capacitor, the second end of the output capacitor is grounded, and the first end of the output capacitor serves as a feedback node; an error amplifier, wherein a first input terminal of the error amplifier is coupled to a reference voltage, and a second input terminal of the error amplifier is connected to the feedback node; A comparator, wherein a first input terminal of the comparator is connected to the output terminal of the error amplifier, and a second input terminal of the comparator is connected to an external ramp signal generator to receive a ramp signal from the external ramp signal generator; a current limiting circuit, connected to the first end of the upper bridge switch, the second end of the lower bridge switch and the output end of the comparator; as well as A control circuit connected to the current limiting circuit, the control end of the upper bridge switch and the control end of the lower bridge switch; The current limiting circuit detects data of the first end of the upper bridge switch to output an upper detection signal, compares a conduction time signal received from the comparator with an upper blank time signal to output an upper current limiting signal, and the control circuit determines whether to control the upper bridge switch and the lower bridge switch according to the upper detection signal according to the upper current limiting signal; The current limiting circuit detects data from the second end of the lower bridge switch to output a lower detection signal, compares the on-time signal received from the comparator with a lower blank time signal to output a lower current limiting signal, and the control circuit decides whether to control the upper bridge switch and the lower bridge switch based on the lower detection signal based on the lower current limiting signal.

2. The power converter with current limiting protection mechanism according to claim 1, It is characterized in that The control circuit controls the upper bridge switch to turn on within the duty cycle of the on-time signal, and the current limiting circuit compares the duty cycle of the on-time signal received from the comparator with the duty cycle of the upper blank time signal to output the upper current limiting signal.

3. The power converter with current limiting protection mechanism according to claim 1, It is characterized in that The control circuit controls the lower bridge switch to turn on during the non-working period of the on-time signal, and the current limiting circuit compares the non-working period of the on-time signal received from the comparator with the non-working period of the lower blank time signal to output the lower current limiting signal.

4. The power converter with current limiting protection mechanism according to claim 1, It is characterized in that The control circuit controls the upper bridge switch to turn on within the working cycle of the conduction time signal; When the current limiting circuit determines that the duty cycle of the on-time signal is less than the duty cycle of the upper blank time signal, the current limiting circuit determines that the data at the first end of the upper bridge switch detected within the duty cycle of the on-time signal is not used to control and switch the upper bridge switch and the lower bridge switch.

5. The power converter with current limiting protection mechanism according to claim 1, It is characterized in that The control circuit controls the lower bridge switch to turn on during the non-working period of the conduction time signal; Among them, when the current limiting circuit determines that the non-working period of the on-time signal received from the comparator is less than the non-working period of the lower side blank time signal, the current limiting circuit decides that the data at the second end of the lower bridge switch detected during the non-working period of the on-time signal is not used to control and switch the upper bridge switch and the lower bridge switch.

6. The power converter with current limiting protection mechanism according to claim 1, It is characterized in that The current limiting circuit comprises: an upper-side current limiting detection circuit, connected to the first end of the upper bridge switch, configured to detect data of the first end of the upper bridge switch to output the upper-side detection signal; an upper side cycle comparison circuit, connected to the upper side current limiting detection circuit and the output end of the comparator, configured to compare the on-time signal received from the comparator with the upper side blank time signal received from the upper side current limiting detection circuit to output an upper side cycle comparison signal; an upper-side current limiting indication circuit, connected to the upper-side cycle comparison circuit and the control circuit, and configured to output the upper-side current limiting signal to the control circuit according to the upper-side cycle comparison signal received from the upper-side cycle comparison circuit; a lower-side current limiting detection circuit, connected to the second end of the lower bridge switch, configured to detect data at the second end of the lower bridge switch to output the lower-side detection signal; a lower side cycle comparison circuit, connected to the lower side current limiting detection circuit and the output end of the comparator, configured to compare the working cycle of the on-time signal received from the comparator with the lower side blank time signal received from the lower side current limiting detection circuit to output a lower side cycle comparison signal; and The lower current limiting indication circuit is connected to the lower cycle comparison circuit and the control circuit, and is configured to output the lower current limiting signal to the control circuit according to the lower cycle comparison signal received from the lower cycle comparison circuit.

7. The power converter with current limiting protection mechanism according to claim 6, It is characterized in that The upper current limiting detection circuit comprises: an upper blank time setting circuit, connected to the upper period comparison circuit, configured to set and output the upper blank time signal to the upper period comparison circuit; and an upper side detection circuit, connected to the first end of the upper bridge switch and the upper side current limiting indication circuit, configured to detect data of the first end of the upper bridge switch to output the upper side detection signal to the upper side current limiting indication circuit; The upper-side current limiting indication circuit determines whether to transmit the upper-side detection signal received from the upper-side detection circuit to the control circuit according to the upper-side period comparison signal.

8. The power converter with current limiting protection mechanism according to claim 7, It is characterized in that The lower current limiting detection circuit comprises: a lower blank time setting circuit, connected to the lower period comparison circuit, configured to set and output the lower blank time signal to the lower period comparison circuit; and a lower side detection circuit, connected to the second end of the lower bridge switch and the lower side current limiting indication circuit, configured to detect data of the second end of the lower bridge switch to output the lower side detection signal to the lower side current limiting indication circuit; The lower current limiting indication circuit determines whether to transmit the lower detection signal received from the lower detection circuit to the control circuit according to the lower period comparison signal.

9. The power converter with current limiting protection mechanism according to claim 8, It is characterized in that The upper detection circuit comprises: An upper comparator, wherein the upper comparator is a comparator, a first input terminal of the upper comparator is coupled to an upper threshold voltage, and a second input terminal of the upper comparator is connected to a first terminal of the upper bridge switch; and A first upper AND gate, wherein the first upper AND gate is an AND gate, wherein a first input end of the first upper AND gate is connected to an output end of the upper blank time setting circuit, a second input end of the first upper AND gate is connected to an output end of the upper comparator, and an output end of the first upper AND gate is connected to an input end of the upper current limiting indication circuit and an input end of the lower current limiting indication circuit.

10. The power converter with current limiting protection mechanism according to claim 9, It is characterized in that The lower detection circuit comprises: A lower comparator, wherein the lower comparator is a comparator, a first input terminal of the lower comparator is coupled to a lower critical voltage, and a second input terminal of the lower comparator is connected to a second terminal of the lower bridge switch; and A first lower AND gate, wherein the first lower AND gate is an AND gate, wherein a first input end of the first lower AND gate is connected to an output end of the lower blank time setting circuit, a second input end of the first lower AND gate is connected to an output end of the lower comparator, and an output end of the first lower AND gate is connected to an input end of the lower current limiting indication circuit and an input end of the upper current limiting indication circuit.

11. The power converter with current limiting protection mechanism according to claim 10, It is characterized in that The upper current limiting indication circuit comprises: An upper OR gate, wherein the upper OR gate is an OR gate, a first input end of the upper OR gate is connected to an output end of the upper period comparison circuit to receive an upper period inverse comparison signal, and a second input end of the upper OR gate is connected to an output end of the first lower AND gate; an upper flip-flop, wherein the upper flip-flop is a flip-flop, a first input end of the upper flip-flop is connected to the output end of the upper period comparison circuit to receive the upper period comparison signal, and a second input end of the upper flip-flop is connected to the output end of the upper OR gate; and A second upper AND gate, wherein the second upper AND gate is an AND gate, wherein a first input end of the second upper AND gate is connected to an output end of the first upper AND gate, a second input end of the second upper AND gate is connected to an inverting output end of the upper flip-flop, and an output end of the second upper AND gate is connected to an input end of the control circuit.

12. The power converter with current limiting protection mechanism according to claim 11, It is characterized in that The lower current limiting indicating circuit comprises: A lower side OR gate, wherein the lower side OR gate is an OR gate, a first input end of the lower side OR gate is connected to the output end of the lower side period comparison circuit to receive a lower side period inverse comparison signal, and a second input end of the lower side OR gate is connected to the output end of the first upper side AND gate; A bottom flip-flop, wherein the bottom flip-flop is a flip-flop, a first input end of the bottom flip-flop is connected to the output end of the bottom period comparison circuit to receive the bottom period comparison signal, and a second input end of the bottom flip-flop is connected to the output end of the bottom OR gate; and A second lower AND gate, wherein the second lower AND gate is an AND gate, wherein a first input terminal of the second lower AND gate is connected to an output terminal of the first lower AND gate, a second input terminal of the second lower AND gate is connected to an inverting output terminal of the lower flip-flop, and an output terminal of the second lower AND gate is connected to an input terminal of the control circuit.

13. The power converter with current limiting protection mechanism according to claim 1, It is characterized in that The power converter with current limiting protection mechanism further comprises: an input resistor, a first end of the input resistor being connected to an output end of the error amplifier and a first input end of the comparator; and An input capacitor, wherein a first end of the input capacitor is connected to a second end of the input resistor, and a second end of the input capacitor is grounded.

14. The power converter with current limiting protection mechanism according to claim 1, It is characterized in that The power converter with current limiting protection mechanism further comprises: A voltage divider circuit, wherein an input end of the voltage divider circuit is connected to a node between the second end of the inductor and the first end of the output capacitor, and an output end of the voltage divider circuit is connected to the second input end of the error amplifier.

15. The power converter with current limiting protection mechanism according to claim 14, It is characterized in that The voltage divider circuit comprises: a first resistor, a first end of the first resistor being connected to a node between the second end of the inductor and the first end of the output capacitor; as well as A second resistor, wherein a first end of the second resistor is connected to a second end of the first resistor, a second end of the second resistor is grounded, and a node between the first end of the second resistor and the second end of the first resistor is connected to a second input end of the error amplifier.

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