Seven-level inverter

Abstract

The invention discloses a seven-level inverter which comprises a direct-current input source, three direct-current bus capacitors connected in series and a three-phase circuit. Each phase of circuit is composed of ten full-control semiconductor devices and one flying capacitor, the ten full-control semiconductor devices are divided into five pairs, and each pair of full-control semiconductor devices act in a complementary mode. The output of seven levels is realized by controlling the on or off of the full-control semiconductor device; compared with an existing seven-level converter topology, each phase of circuit topology only needs ten full-control semiconductor device switch tubes and one flying capacitor, the number of power devices is reduced, the loss of the devices is reduced, and therefore the reliability of the device is improved. More importantly, through cascade connection of the four-level converter circuit with small device voltage stress and the H-bridge circuit, output of seven levels is achieved, and therefore the problems that the number of topological power devices of an existing seven-level inverter is large, and the voltage stress is large are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of inverters, and in particular to a seven-level inverter. Background Art

[0002] In low-voltage applications with an AC line voltage of 380V, multilevel converters have certain application value due to their advantages of low device voltage stress, few harmonics, and low switching losses. However, considering the device cost, designers hope that the selected multilevel inverter topology has a smaller number of power devices. Therefore, it has become a development trend to study multilevel inverters with a small number of devices and a large number of output levels. In 2019, researchers from Anhui University proposed a method such as Figure 2 The new seven-level inverter topology shown in the figure, each phase bridge arm of this circuit topology is composed of a four-level bridge arm and a two-level H-bridge in series, including 10 switching devices and 1 floating capacitor. However, the device voltage stress borne by the switch tubes SA2 and SA3 in this circuit topology is 2 / 3 of the DC bus voltage, and the device voltage stress is large, which will increase the cost and device loss.

[0003] The existing seven-level converter topology is mainly used in medium-high voltage and high-power applications. In order to make the voltage stress of all devices the same and overcome the problem of insufficient voltage resistance of power devices at high voltage levels, the existing topology is often complex in structure and has a large number of power devices. Therefore, the control of the inverter is difficult and the loss is large. In addition, too many power devices also reduce the reliability of the device. Summary of the invention

[0004] The present invention provides a seven-level inverter, which is used to solve the problems of a large number of power devices and large voltage stress in the existing seven-level inverter topology.

[0005] In view of this, the first aspect of the present invention provides a seven-level inverter, characterized in that it includes: a DC input source U dc , DC bus capacitor C 1 , DC bus capacitor C 2 and DC bus capacitor C 3 , and three-phase circuits;

[0006] Each phase circuit consists of 10 fully controlled semiconductor devices and 1 flying capacitor C fa The 10 fully controlled semiconductor devices are divided into 5 pairs of fully controlled semiconductor devices, including: the first pair of fully controlled semiconductor devices S a1 , S a1' , the second pair of fully controlled semiconductor devices S a2 , S a2' , the third pair of fully controlled semiconductor devices S a3 , S a3' , the fourth pair of fully controlled semiconductor devices Sa4 , S a4' , the fifth pair of fully controlled semiconductor devices S a5 , S a5' , and the actions of the fully controlled semiconductor devices between each pair are complementary;

[0007] Among them, the first pair of fully controlled semiconductor devices S a1 , S a1' , the second pair of fully controlled semiconductor devices S a2 , S a2' and the third pair of fully controlled semiconductor devices S a3 , S a3' A four-level converter circuit is formed, wherein the fourth pair of fully controlled semiconductor devices S a4 , S a4' , the fifth pair of fully controlled semiconductor devices S a5 , S a5' With the flying capacitor C fa An H-bridge circuit is formed, wherein the four-level converter circuit is cascaded with the H-bridge circuit;

[0008] The DC bus capacitor C 1 , the DC bus capacitor C 2 and the DC bus capacitor C 3 The capacitor voltage is maintained at U dc / 3, the flying capacitor C fa The voltage is maintained at U dc / 6;

[0009] By controlling each of the fully controlled semiconductor devices to be turned on or off, the levels output by the seven-level inverter include: dc / 2, U dc / 3、U dc / 6, 0, -U dc / 6, -U dc / 3 and -U dc / 2.

[0010] Optionally, in the four-level converter circuit: the DC bus capacitor C 1 , the DC bus capacitor C 2 and the DC bus capacitor C 3 Connect in series;

[0011] The fully controlled semiconductor device S a1 The first end is connected to the DC bus capacitor C 1 The positive pole and the DC input source U dc The positive terminal of the fully controlled semiconductor device S a3' The first end is connected to the DC bus capacitor C 3The negative pole and the DC input source U dc The negative terminal of the fully controlled semiconductor device S a2 The first end is connected to the DC bus capacitor C 1 The negative electrode of the fully controlled semiconductor device S a2' The first end is connected to the DC bus capacitor C 2 The negative electrode of the fully controlled semiconductor device S a2 and the fully controlled semiconductor device S a2' The second end is connected to the fully controlled semiconductor device S a3 The first end of the fully controlled semiconductor device S a3 The second end is connected to the fully controlled semiconductor device S a1' The first end of the fully controlled semiconductor device S a1' , the fully controlled semiconductor device S a1 And the fully controlled semiconductor device S a3' The second end of the fully controlled semiconductor device S a4 and the fully controlled semiconductor device S a4' connected to the first end of

[0012] In the H-bridge circuit cascade: the fully controlled semiconductor device S a4 and the fully controlled semiconductor device S a4' The fully controlled semiconductor device S a5 and the fully controlled semiconductor device S a5' A half bridge is formed; wherein the fully controlled semiconductor device S a4 and the fully controlled semiconductor device S a5 As the upper tube of the corresponding half bridge respectively; the flying capacitor C fa In parallel with the half bridge.

[0013] Optionally, when the level output by the seven-level inverter is U dc / 2, the on or off control of each of the fully controlled semiconductor devices includes:

[0014] Control fully controlled semiconductor devices S a1 , Fully controlled semiconductor devices S a2 , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4 , and fully controlled semiconductor devices S a5 All are conducting;

[0015] Or, control the fully controlled semiconductor device S a1 , Fully controlled semiconductor devices S a2 , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4', and fully controlled semiconductor devices S a5' All are conducting.

[0016] Optionally, when the level output by the seven-level inverter is U dc / 3, the on or off control of each of the fully controlled semiconductor devices includes:

[0017] Control fully controlled semiconductor devices S a1 , Fully controlled semiconductor devices S a2 , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4 , and fully controlled semiconductor devices S a5' All are conducting;

[0018] Or, control the fully controlled semiconductor device S a1' , Fully controlled semiconductor devices S a2 , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4' , and fully controlled semiconductor devices S a5 All are conducting.

[0019] Optionally, when the level output by the seven-level inverter is U dc / 6, the on or off control of each of the fully controlled semiconductor devices includes:

[0020] Control fully controlled semiconductor devices S a1' , Fully controlled semiconductor devices S a2 , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4 , and fully controlled semiconductor devices S a5 All are conducting;

[0021] Or, control the fully controlled semiconductor device S a1' , Fully controlled semiconductor devices S a2 , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4' , and fully controlled semiconductor devices S a5' All are conducting.

[0022] Optionally, when the level output by the seven-level inverter is 0, the controlling each of the fully-controlled semiconductor devices to be turned on or off includes:

[0023] Control fully controlled semiconductor devices S a1' , Fully controlled semiconductor devices S a2 , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4 , and fully controlled semiconductor devices S a5'All are conducting;

[0024] Or, control the fully controlled semiconductor device S a1' , Fully controlled semiconductor devices S a2' , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4' , and fully controlled semiconductor devices S a5 All are conducting.

[0025] Optionally, when the level output by the seven-level inverter is -U dc / 6, the on or off control of each of the fully controlled semiconductor devices includes:

[0026] Control fully controlled semiconductor devices S a1' , Fully controlled semiconductor devices S a2' , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4 , and fully controlled semiconductor devices S a5 All are conducting;

[0027] Or, control the fully controlled semiconductor device S a1' , Fully controlled semiconductor devices S a2' , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4' , and fully controlled semiconductor devices S a5' All are conducting.

[0028] Optionally, when the level output by the seven-level inverter is -U dc / 3, the on or off control of each of the fully controlled semiconductor devices includes:

[0029] Control fully controlled semiconductor devices S a1' , Fully controlled semiconductor devices S a2' , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4 , and fully controlled semiconductor devices S a5' All are conducting;

[0030] Or, control the fully controlled semiconductor device S a1' , Fully controlled semiconductor devices S a2' , Fully controlled semiconductor devices S a3' , Fully controlled semiconductor devices S a4' , and fully controlled semiconductor devices S a5 All are conducting.

[0031] Optionally, when the level output by the seven-level inverter is -U dc / 2, the on or off control of each of the fully controlled semiconductor devices includes:

[0032] Control fully controlled semiconductor devices S a1' , Fully controlled semiconductor devices S a2' , Fully controlled semiconductor devices S a3' , Fully controlled semiconductor devices S a4 , and fully controlled semiconductor devices S a5 All are conducting;

[0033] Or, control the fully controlled semiconductor device S a1' , Fully controlled semiconductor devices S a2' , Fully controlled semiconductor devices S a3' , Fully controlled semiconductor devices S a4' , and fully controlled semiconductor devices S a5' All are conducting.

[0034] Optionally, the fully-controlled semiconductor device includes: a Si-based semiconductor device or a wide bandgap semiconductor device.

[0035] It can be seen from the above technical solutions that the present invention has the following advantages:

[0036] The present invention proposes a seven-level converter topology, a DC input source, three series DC bus capacitors and a three-phase circuit; each phase circuit is composed of 10 fully controlled semiconductor devices and 1 flying capacitor, the 10 fully controlled semiconductor devices are divided into 5 pairs, and each pair of fully controlled semiconductor devices acts complementary, that is, when one fully controlled semiconductor device is turned on, the other fully controlled semiconductor device is turned off. By controlling the on or off of the fully controlled semiconductor devices, a seven-level output is achieved; compared with the existing seven-level converter topology, the present invention only requires 10 fully controlled semiconductor device switches and one flying capacitor per phase circuit topology, which reduces the number of power devices and reduces the loss of the devices, thereby improving the reliability of the device. More importantly, by cascading a four-level converter circuit with low device voltage stress and an H-bridge circuit, a seven-level output is achieved, thereby solving the problem of a large number of power devices and high voltage stress in the existing seven-level inverter topology. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0038] Figure 1 A seven-level inverter topology provided by an embodiment of the present invention;

[0039] Figure 2The output level provided by the embodiment of the present invention is 1 / 2U dc The equivalent circuit of 1;

[0040] Figure 3 The output level provided by the embodiment of the present invention is 1 / 2U dc The equivalent circuit 2;

[0041] Figure 4 The output level provided by the embodiment of the present invention is 1 / 3U dc The equivalent circuit of 1;

[0042] Figure 5 The output level provided by the embodiment of the present invention is 1 / 3U dc The equivalent circuit 2;

[0043] Figure 6 The output level provided by the embodiment of the present invention is 1 / 6U dc The equivalent circuit of 1;

[0044] Figure 7 The output level provided by the embodiment of the present invention is 1 / 6U dc The equivalent circuit 2;

[0045] Figure 8 An equivalent circuit 1 with an output level 0 provided by an embodiment of the present invention;

[0046] Fig. 9 An equivalent circuit 2 of output level 0 provided by an embodiment of the present invention;

[0047] Fig.10 Output level provided by the embodiment of the present invention - 1 / 6U dc The equivalent circuit of 1;

[0048] Fig.11 Output level provided by the embodiment of the present invention - 1 / 6U dc The equivalent circuit 2;

[0049] Fig.12 Output level provided by the embodiment of the present invention - 1 / 3U dc The equivalent circuit of 1;

[0050] Fig.13 Output level provided by the embodiment of the present invention - 1 / 3U dc The equivalent circuit 2;

[0051] Fig.14 Output level provided by the embodiment of the present invention - 1 / 2U dc The equivalent circuit of 1;

[0052] Fig.15 Output level provided by the embodiment of the present invention - 1 / 2Udc Equivalent circuit 2. DETAILED DESCRIPTION

[0053] In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described below are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0054] See also Figure 1 A seven-level inverter provided in an embodiment of the present invention includes: a DC input source U dc , DC bus capacitor C 1 , DC bus capacitor C 2 and DC bus capacitor C 3 , and three-phase circuits;

[0055] Each phase circuit consists of 10 fully controlled semiconductor devices and 1 flying capacitor C fa The 10 fully controlled semiconductor devices are divided into 5 pairs of fully controlled semiconductor devices, including: the first pair of fully controlled semiconductor devices S a1 , S a1' , the second pair of fully controlled semiconductor devices S a2 , S a2' , the third pair of fully controlled semiconductor devices S a3 , S a3' , the fourth pair of fully controlled semiconductor devices S a4 , S a4' , the fifth pair of fully controlled semiconductor devices S a5 , S a5' , and the actions of the fully-controlled semiconductor devices between each pair are complementary; wherein the fully-controlled semiconductor devices include: Si-based semiconductor devices or wide-bandgap semiconductor devices.

[0056] Among them, the first pair of fully controlled semiconductor devices S a1 , S a1' , the second pair of fully controlled semiconductor devices S a2 , S a2' and the third pair of fully controlled semiconductor devices S a3 , S a3' The fourth pair of fully controlled semiconductor devices S a4 , S a4' , the fifth pair of fully controlled semiconductor devices S a5 , S a5' With flying capacitor C fa An H-bridge circuit is formed, and a four-level converter circuit is cascaded with the H-bridge circuit;

[0057] DC bus capacitor C 1 , DC bus capacitor C 2 and DC bus capacitor C 3 The capacitor voltage is maintained at U dc / 3, flying capacitor C fa The voltage is maintained at U dc / 6;

[0058] By controlling the on or off of each fully controlled semiconductor device, the output levels of the seven-level inverter include: U dc / 2, U dc / 3、U dc / 6, 0, -U dc / 6, -U dc / 3 and -U dc / 2.

[0059] It should be noted that the seven-level inverter has a circuit structure such as Figure 1 The seven-level inverter of the present invention comprises a DC input source U dc , three series DC bus capacitors C 1 , C 2 , C 3 , and the corresponding three-phase (A phase, B phase, C phase) circuit. Each phase circuit consists of 10 fully controlled semiconductor devices and 1 flying capacitor. The 10 fully controlled semiconductor devices are divided into 5 pairs. Taking the A phase circuit as an example, that is, Figure 1 The switch tube (S a1 , S a1' )、(S a2 , S a2' )、(S a3 , S a3' )、(S a4 , S a4' )、(S a5 , S a5' ), each pair of fully controlled semiconductor devices act complementary to each other. It can be understood that when one fully controlled semiconductor device in each pair of fully controlled semiconductor devices is turned on, the other fully controlled semiconductor device is turned off. The voltage of the three series-connected DC bus capacitors is maintained at U dc / 3, the voltage of the flying capacitor is maintained at U dc / 6, by turning on or off each fully controlled semiconductor device, the inverter of the present invention outputs a total of -U dc / 2, -U dc / 3, -U dc / 6, 0, U dc / 6, U dc / 3、U dc / 2 seven levels.

[0060] It should be noted that a fully controlled semiconductor device is a semiconductor power electronic device that can fully control its conduction and shutdown. Unlike semi-controlled devices (such as ordinary thyristors, which can only control conduction but not shutdown), fully controlled devices can flexibly control their on and off states through signals on the control electrode. The fully controlled semiconductor device of the present invention can use any: Si-based semiconductor devices or wide bandgap semiconductor devices; including MOSFET, IGBT, etc.; wherein, Si-based semiconductor devices are semiconductor devices made of silicon (Si) as the basic material. Silicon is a commonly used semiconductor material with good electrical properties, thermal stability and mechanical properties, and is abundant in reserves and low in cost. Wide bandgap semiconductor materials refer to a class of semiconductor materials with a bandgap width greater than that of traditional semiconductor materials such as silicon (Si) and gallium arsenide (GaAs).

[0061] The present invention proposes a seven-level converter topology. Compared with the existing seven-level converter topology, each phase circuit topology only requires 10 fully controlled semiconductor devices (switches) and one flying capacitor, which reduces the number of power devices, reduces device losses, and improves the reliability of the device. More importantly, by cascading a four-level converter circuit with low device voltage stress and an H-bridge circuit, a seven-level output is achieved, solving the problem of a large number of power devices and high voltage stress in the existing seven-level inverter topology.

[0062] Furthermore, in one embodiment, in the four-level converter circuit, Figure 1 As shown:

[0063] DC bus capacitor C 1 , DC bus capacitor C 2 and DC bus capacitor C 3 Connect in series;

[0064] Fully controlled semiconductor devices a1 The first end is connected to the DC bus capacitor C 1 The positive pole and DC input source U dc The positive terminal of the fully controlled semiconductor device S a3' The first end is connected to the DC bus capacitor C 3 The negative pole and DC input source U dc The negative terminal of the fully controlled semiconductor device S a2 The first end is connected to the DC bus capacitor C 1 The negative electrode of the fully controlled semiconductor device S a2' The first end is connected to the DC bus capacitor C 2 The negative electrode of the fully controlled semiconductor device S a2 And fully controlled semiconductor devices S a2' The second end is connected to the fully controlled semiconductor device S a3 The first end of the fully controlled semiconductor device Sa3 The second end is connected to the fully controlled semiconductor device S a1' The first end of the fully controlled semiconductor device S a1' , Fully controlled semiconductor devices S a1 And fully controlled semiconductor devices S a3' The second end of the fully controlled semiconductor device S a4 And fully controlled semiconductor devices S a4' The first end is connected to the H bridge circuit cascade: the fully controlled semiconductor device S a4 And fully controlled semiconductor devices S a4' Form a half bridge, fully control the semiconductor device S a5 And fully controlled semiconductor devices S a5' A half bridge is formed; wherein the fully controlled semiconductor device S a4 And fully controlled semiconductor devices S a5 As the upper tube of the corresponding half bridge respectively; flying capacitor C fa In parallel with the half bridge.

[0065] It should be noted that this embodiment Figure 1 The fully controlled semiconductor device in the circuit is a switch tube, based on which the topological connection of each seven-level inverter is described:

[0066] In the four-level converter circuit: DC bus capacitor C 1 , DC bus capacitor C 2 and DC bus capacitor C 3 Connect in series;

[0067] Switching tube S a1 The drain is connected to the DC bus capacitor C 1 The positive pole and DC input source U dc The positive terminal of the switch tube S a3' The source is connected to the DC bus capacitor C 3 The negative pole and DC input source U dc The negative terminal of the switch tube S a2 The drain is connected to the DC bus capacitor C 1 The negative pole of the switch tube S a2' The source is connected to the DC bus capacitor C 2 The negative pole of the switch tube S a2 The source and switch tube S a2' The drain of the switch tube S a3 The drain of the switch tube S a3 The source of the switch is connected to the a1' The source of the switch tube S a1' The drain of the switch tube S a1 The source and switch tube S a3' The drain and switch tube S a4 The source and switch tube Sa4' The drain of is connected;

[0068] In the H-bridge circuit cascade: switch tube S a4 And switch tube S a4' Form a half bridge, switch tube S a5 And switch tube S a5' A half bridge is formed; wherein the switch tube S a4 And switch tube S a5 As the upper tube of the corresponding half bridge respectively; flying capacitor C fa In parallel with the half bridge.

[0069] Furthermore, in one embodiment, by controlling each fully-controlled semiconductor device to be turned on or off, the levels output by the seven-level inverter include: U dc / 2, U dc / 3、U dc / 6, 0, -U dc / 6, -U dc / 3 and -U dc / 2, including:

[0070] It should be noted that, taking the A phase circuit as an example, the switching state of the seven-level inverter is as follows: Figures 2 to 15 As shown, Figures 2 to 15 When the device is black, it is in the on state, and when the device is gray, it is in the off state. Figure 1 As shown, Figure 1 The fully controlled semiconductor device in the switch tube (S a1 , S a1' )、(S a2 , S a2' )、(S a3 , S a3' )、(S a4 , S a4' )、(S a5 , S a5' ), each pair of fully controlled semiconductor devices act complementary to each other. It can be understood that when one fully controlled semiconductor device in each pair of fully controlled semiconductor devices is turned on, the other fully controlled semiconductor device is turned off. a1 When conducting, S a1' It is in the off state.

[0071] The specific working principle is analyzed as follows 1) to 7):

[0072] 1) When the output level of the seven-level inverter is U dc / 2, by turning on or off each fully controlled semiconductor device, including:

[0073] Control fully controlled semiconductor devices S a1 , Fully controlled semiconductor devices Sa2 , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4 , and fully controlled semiconductor devices S a5 All are turned on; or, control the fully controlled semiconductor device S a1 , Fully controlled semiconductor devices S a2 , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4' , and fully controlled semiconductor devices S a5' All are conducting.

[0074] It should be noted that when the A phase circuit of the inverter is Figure 2 In the state shown, the AC output passes through the switch tube S a5 , S a4 , S a1 Connect to the DC bus capacitor C 1 The positive pole of the inverter is U dc / 2. At the same time, the switch tube S a2 Keep conducting to ensure that the switch tube S a1' The voltage to be borne is U dc / 3. When the inverter switches to Figure 3 In the state, the switch tube S a4 and S a5 Shutdown, the inverter still outputs U dc / 2.

[0075] 2) When the output level of the seven-level inverter is U dc / 3, by turning on or off each fully controlled semiconductor device, including:

[0076] Control fully controlled semiconductor devices S a1 , Fully controlled semiconductor devices S a2 , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4 , and fully controlled semiconductor devices S a5' All are turned on; or, control the fully controlled semiconductor device S a1' , Fully controlled semiconductor devices S a2 , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4' , and fully controlled semiconductor devices S a5 All are conducting.

[0077] It should be noted that when the inverter is in Figure 4 In the state shown, the AC output passes through the switch tube S a5' 、Flying capacitor C fa , switch tube S a4 , switch tube Sa1 Connect to DC side N 1 The output of the inverter is the DC side voltage U dc / 2Reverse series flying capacitor voltage U dc / 6, that is, the output voltage is U dc / 3. When the inverter is in Figure 5 In the state shown, the AC output passes through the switch tube S a5 、Flying capacitor C fa , switch tube S a4' , switch tube S a1' , switch tube S a3 , switch tube S a2 Connect to DC side N 1 End point, at this time the output of the inverter is the DC side voltage U dc / 6Forward series flying capacitor voltage U dc / 6, so the output voltage is U dc / 3.

[0078] 3) When the output level of the seven-level inverter is U dc / 6, by turning on or off each fully controlled semiconductor device, including:

[0079] Control fully controlled semiconductor devices S a1' , Fully controlled semiconductor devices S a2 , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4 , and fully controlled semiconductor devices S a5 All are turned on; or, control the fully controlled semiconductor device S a1' , Fully controlled semiconductor devices S a2 , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4' , and fully controlled semiconductor devices S a5' All are conducting.

[0080] It should be noted that when the inverter is in Figure 6 and 7 In the switching state shown, the AC output first passes through the switch tube S a5 , S a4 Or switch tube S a5' , S a4' , and then pass through the switch tube S a1' , S a3 , S a2 Connect to DC side N 1 The inverter output voltage is U dc / 6.

[0081] 4) When the output level of the seven-level inverter is 0, each fully controlled semiconductor device is turned on or off, including:

[0082] Control fully controlled semiconductor devices S a1' , Fully controlled semiconductor devices S a2 , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4 , and fully controlled semiconductor devices S a5' All are turned on; or, control the fully controlled semiconductor device S a1' , Fully controlled semiconductor devices S a2' , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4' , and fully controlled semiconductor devices S a5 All are conducting.

[0083] It should be noted that when the inverter is in Figure 8 and 9 In the switching state shown, the inverter output voltage is 0. Figure 8 The 0 level of the AC output is determined by the DC side U dc / 6Reverse series flying capacitor voltage U dc / 6 is generated, and the conducting switch is S a5' , S a4 , S a1' , S a3 , S a2 ;exist Fig. 9 The 0 level of the AC output is determined by the DC side -U dc / 6Forward series flying capacitor voltage U dc / 6 is generated, and the conducting switch is S a5 , S a4' , S a1' , S a3 , S a2' .

[0084] 5) When the output level of the seven-level inverter is -U dc / 6, by turning on or off each fully controlled semiconductor device, including:

[0085] Control fully controlled semiconductor devices S a1' , Fully controlled semiconductor devices S a2' , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4 , and fully controlled semiconductor devices S a5 All are turned on; or, control the fully controlled semiconductor device S a1' , Fully controlled semiconductor devices S a2' , Fully controlled semiconductor devices S a3, Fully controlled semiconductor devices S a4' , and fully controlled semiconductor devices S a5' All are conducting.

[0086] It should be noted that when the inverter is in Fig.10 and 11 When the switching state is shown, the inverter output voltage is -U dc / 6. The AC output first passes through the switch tube S a5 , S a4 Or switch tube S a5' , S a4' , and then pass through the switch tube S a1' , S a3 , S a2' Connect to DC side N 2 endpoint.

[0087] 6) When the output level of the seven-level inverter is -U dc / 3, by turning on or off each fully controlled semiconductor device, including:

[0088] Control fully controlled semiconductor devices S a1' , Fully controlled semiconductor devices S a2' , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4 , and fully controlled semiconductor devices S a5' All are turned on; or, control the fully controlled semiconductor device S a1' , Fully controlled semiconductor devices S a2' , Fully controlled semiconductor devices S a3' , Fully controlled semiconductor devices S a4' , and fully controlled semiconductor devices S a5 All are conducting.

[0089] It should be noted that when the inverter is in Fig.12 and 13 When the switching state is shown, the inverter output voltage is -U dc / 3. Fig.12 In the process, the AC output passes through the switch tube S a5' 、Flying capacitor C fa , switch tube S a4 , switch tube S a1' , switch tube S a3 , switch tube S a2' Connect to DC side N 2 End point, at this time the output of the inverter is the DC side voltage -U dc / 6Reverse series flying capacitor voltage U dc / 6, that is, the output voltage is -U dc / 3; and when the inverter is in Fig.13In the state shown, the AC output passes through the switch tube S a5 、Flying capacitor C fa , switch tube S a4' , switch tube S a3' Connect to DC side N 2 The output of the inverter is the DC side voltage -U dc / 2Forward series flying capacitor voltage U dc / 6, so the output voltage is also -U dc / 3.

[0090] 7) When the output level of the seven-level inverter is -U dc / 2, by turning on or off each fully controlled semiconductor device, including:

[0091] Control fully controlled semiconductor devices S a1' , Fully controlled semiconductor devices S a2' , Fully controlled semiconductor devices S a3' , Fully controlled semiconductor devices S a4 , and fully controlled semiconductor devices S a5 All are turned on; or, control the fully controlled semiconductor device S a1' , Fully controlled semiconductor devices S a2' , Fully controlled semiconductor devices S a3' , Fully controlled semiconductor devices S a4' , and fully controlled semiconductor devices S a5' All are conducting.

[0092] It should be noted that when the inverter is in Fig.14 and 15 When the switching state is shown, the inverter output voltage is -U dc / 2. The AC output passes through the switch tube S a5 , S a4 Or switch tube S a5' , S a4' , and then pass through the switch tube S a3' Connect to DC side N 2 endpoint.

[0093] Explanation of the impact of different inverter states and current directions on the flying capacitor voltage:

[0094] Assumptions Figure 1 The current direction shown is outflow. The influence of different inverter states and current directions on the flying capacitor voltage is shown in Table 1. It can be seen from the table that only ±U dcThe three levels of / 3 and 0 have an impact on the flying capacitor voltage, but in the same current direction, there are states with opposite effects on the flying capacitor. For example, when current flows out, the three states of B2, D2, and F2 will cause it to discharge, but the three states of B1, D1, and F1 will cause it to discharge. Therefore, the voltage balance of the flying capacitor is achieved by selecting different redundant switch states.

[0095]

[0096] The present invention proposes a seven-level converter topology, including: a DC input source, three series DC bus capacitors and a three-phase circuit; each phase circuit is composed of 10 fully controlled semiconductor devices and 1 flying capacitor, the 10 fully controlled semiconductor devices are divided into 5 pairs, and each pair of fully controlled semiconductor devices acts complementary, that is, when one fully controlled semiconductor device is turned on, the other fully controlled semiconductor device is turned off. By controlling the on or off of the fully controlled semiconductor devices, a seven-level output is achieved; compared with the existing seven-level converter topology, the present invention only requires 10 fully controlled semiconductor device switches and one flying capacitor per phase circuit topology, which reduces the number of power devices and reduces the loss of the devices, thereby improving the reliability of the device. More importantly, by cascading a four-level converter circuit with small device voltage stress and an H-bridge circuit, a seven-level output is achieved, thereby solving the problem of a large number of power devices and high voltage stress in the existing seven-level inverter topology.

[0097] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0098] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A seven-level inverter, characterized in that: include: DC input source U dc , a DC bus capacitor C1, a DC bus capacitor C2 and a DC bus capacitor C3, and a three-phase circuit; Each phase circuit consists of 10 fully controlled semiconductor devices and 1 flying capacitor C fa The 10 fully controlled semiconductor devices are divided into 5 pairs of fully controlled semiconductor devices, including: the first pair of fully controlled semiconductor devices S a1 , S a1' , the second pair of fully controlled semiconductor devices S a2 , S a2' , the third pair of fully controlled semiconductor devices S a3 , S a3' , the fourth pair of fully controlled semiconductor devices S a4 , S a4' , the fifth pair of fully controlled semiconductor devices S a5 , S a5' , and the actions of the fully controlled semiconductor devices between each pair are complementary; Among them, the first pair of fully controlled semiconductor devices S a1 , S a1' , the second pair of fully controlled semiconductor devices S a2 , S a2' and the third pair of fully controlled semiconductor devices S a3 , S a3' A four-level converter circuit is formed, wherein the fourth pair of fully controlled semiconductor devices S a4 , S a4' , the fifth pair of fully controlled semiconductor devices S a5 , S a5' With the flying capacitor C fa An H-bridge circuit is formed, wherein the four-level converter circuit is cascaded with the H-bridge circuit; The capacitor voltages of the DC bus capacitor C1, the DC bus capacitor C2, and the DC bus capacitor C3 are all maintained at U dc / 3, the flying capacitor C fa The voltage is maintained at U dc / 6; By controlling each of the fully controlled semiconductor devices to be turned on or off, the levels output by the seven-level inverter include: dc / 2, U dc / 3, U dc / 6, 0, -U dc / 6, -U dc / 3 and -U dc / 2.

2. The seven-level inverter according to claim 1, characterized in that: In the four-level converter circuit: The DC bus capacitor C1, the DC bus capacitor C2 and the DC bus capacitor C3 are connected in series in sequence; The fully controlled semiconductor device S a1 The first end is connected to the positive electrode of the DC bus capacitor C1 and the DC input source U dc The positive terminal of the fully controlled semiconductor device S a3' The first end is connected to the negative electrode of the DC bus capacitor C3 and the DC input source U dc The negative terminal of the fully controlled semiconductor device S a2 The first end of the fully controlled semiconductor device S is connected to the negative electrode of the DC bus capacitor C1. a2' The first end of the fully controlled semiconductor device S is connected to the negative electrode of the DC bus capacitor C2. a2 and the fully controlled semiconductor device S a2' The second end is connected to the fully controlled semiconductor device S a3 The first end of the fully controlled semiconductor device S a3 The second end is connected to the fully controlled semiconductor device S a1' The first end of the fully controlled semiconductor device S a1' , the fully controlled semiconductor device S a1 And the fully controlled semiconductor device S a3' The second end of the fully controlled semiconductor device S a4 and the fully controlled semiconductor device S a4' connected to the first end of In the H-bridge circuit cascade: the fully controlled semiconductor device S a4 and the fully controlled semiconductor device S a4' The fully controlled semiconductor device S a5 and the fully controlled semiconductor device S a5' A half bridge is formed; wherein the fully controlled semiconductor device S a4 and the fully controlled semiconductor device S a5 As the upper tube of the corresponding half bridge respectively; the flying capacitor C fa In parallel with the half bridge.

3. The seven-level inverter according to claim 2, characterized in that: When the level of the seven-level inverter output is U dc / 2, the on or off control of each of the fully controlled semiconductor devices includes: Control fully controlled semiconductor devices S a1 , Fully controlled semiconductor devices S a2 , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4 , and fully controlled semiconductor devices S a5 All are conducting; Or, control the fully controlled semiconductor device S a1 , Fully controlled semiconductor devices S a2 , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4' , and fully controlled semiconductor devices S a5' All are conducting.

4. The seven-level inverter according to claim 2, characterized in that: When the level of the seven-level inverter output is U dc / 3, the on or off control of each of the fully controlled semiconductor devices includes: Control fully controlled semiconductor devices S a1 , Fully controlled semiconductor devices S a2 , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4 , and fully controlled semiconductor devices S a5' All are conducting; Or, control the fully controlled semiconductor device S a1' , Fully controlled semiconductor devices S a2 , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4' , and fully controlled semiconductor devices S a5 All are conducting.

5. The seven-level inverter according to claim 2, characterized in that: When the level of the seven-level inverter output is U dc / 6, the on or off control of each of the fully controlled semiconductor devices includes: Control fully controlled semiconductor devices S a1' , Fully controlled semiconductor devices S a2 , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4 , and fully controlled semiconductor devices S a5 All are conducting; Or, control the fully controlled semiconductor device S a1' , Fully controlled semiconductor devices S a2 , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4' , and fully controlled semiconductor devices S a5' All are conducting.

6. The seven-level inverter according to claim 2, characterized in that: When the level output by the seven-level inverter is 0, the control of turning on or off each of the fully-controlled semiconductor devices includes: Control fully controlled semiconductor devices S a1' , Fully controlled semiconductor devices S a2 , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4 , and fully controlled semiconductor devices S a5' All are conducting; Or, control the fully controlled semiconductor device S a1' , Fully controlled semiconductor devices S a2' , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4' , and fully controlled semiconductor devices S a5 All are conducting.

7. The seven-level inverter according to claim 2, characterized in that: When the output level of the seven-level inverter is -U dc / 6, the on or off control of each of the fully controlled semiconductor devices includes: Control fully controlled semiconductor devices S a1' , Fully controlled semiconductor devices S a2' , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4 , and fully controlled semiconductor devices S a5 All are conducting; Or, control the fully controlled semiconductor device S a1' , Fully controlled semiconductor devices S a2' , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4' , and fully controlled semiconductor devices S a5' All are conducting.

8. The seven-level inverter according to claim 2, characterized in that: When the output level of the seven-level inverter is -U dc / 3, the on or off control of each of the fully controlled semiconductor devices includes: Control fully controlled semiconductor devices S a1' , Fully controlled semiconductor devices S a2' , Fully controlled semiconductor devices S a3 , Fully controlled semiconductor devices S a4 , and fully controlled semiconductor devices S a5' All are conducting; Or, control the fully controlled semiconductor device S a1' , Fully controlled semiconductor devices S a2' , Fully controlled semiconductor devices S a3' , Fully controlled semiconductor devices S a4' , and fully controlled semiconductor devices S a5 All are conducting.

9. The seven-level inverter according to claim 2, characterized in that: When the output level of the seven-level inverter is -U dc / 2, the on or off control of each of the fully controlled semiconductor devices includes: Control fully controlled semiconductor devices S a1' , Fully controlled semiconductor devices S a2' , Fully controlled semiconductor devices S a3' , Fully controlled semiconductor devices S a4 , and fully controlled semiconductor devices S a5 All are conducting; Or, control the fully controlled semiconductor device S a1' , Fully controlled semiconductor devices S a2' , Fully controlled semiconductor devices S a3' , Fully controlled semiconductor devices S a4' , and fully controlled semiconductor devices S a5' All are conducting.

10. The seven-level inverter according to any one of claims 1 to 9, characterized in that: The fully controlled semiconductor device includes: a Si-based semiconductor device or a wide bandgap semiconductor device.

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