A fully differential wide common-mode input operational amplifier circuit

Abstract

The present invention provides a fully differential wide common-mode input operational amplifier circuit, which includes a differential common-mode operational amplifier OP, a first link, a second link, a resistor R1 and a resistor R2. One end of the resistor R1 and the resistor R2 are respectively connected to an input signal VIN and VIP. The other end of the resistor R1 is connected to the non-inverting input terminal of the differential common-mode operational amplifier OP and one end of the first link. The other end of the resistor R2 is connected to the inverting input terminal of the differential common-mode operational amplifier OP and one end of the second link. The inverting output terminal of the differential common-mode operational amplifier OP is connected to the other end of the first link. The non-inverting output terminal of the differential common-mode operational amplifier OP is connected to the other end of the second link. The differential common-mode operational amplifier OP uses a low-voltage differential input pair transistor. The present invention has strong driving ability, small occupied area and can reduce the offset of the system.

Description

Technical Field

[0001] The present invention relates to an operational amplifier circuit, in particular to a fully differential wide common-mode input operational amplifier circuit, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] Fully differential wide common-mode input operational amplifier circuits are widely used in various applications, and the wide common-mode input architecture can play an important role in high-precision current sampling applications. For example, in the current sampling circuit of a domain drive motor chip, the input common-mode range is required to satisfy -5V to 60V.

[0003] As Figure 7 shown is a traditional operational amplifier with a differential circuit using high-voltage MOS transistors as input pairs. Although this structure is simple in design, it has many deficiencies and defects:

[0004] 1. For extremely high-precision current sampling circuits, high-voltage differential input MOS pairs will introduce a relatively large offset;

[0005] 2. In high-precision current sampling circuits, a relatively large number of input pairs are required to ensure that the offset of the system can be made small. Since the area of a high-voltage transistor is much larger than that of a low-voltage transistor, if all high-voltage MOS transistors are used as input pairs, a large area will be occupied;

[0006] 3. The VTH of high-voltage MOS input pairs will be greater than that of low-voltage MOS transistors. Therefore, to achieve the same current driving ability, the number of high-voltage MOS input pairs required is obviously more. Generally, the total number of high-voltage MOS input pairs needs to be greater than 30, which will further increase the area of the chip.

[0007] In summary, high-voltage MOS input pairs will introduce a relatively large offset and increase the area of the circuit, which will have an adverse impact on the design performance and cost of the entire chip. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to provide a fully differential wide common-mode input operational amplifier circuit that uses low-voltage MOS input pairs and has strong driving ability and small occupied area.

[0009] To solve the above technical problem, the technical solution adopted by the present invention is:

[0010] A fully differential wide common-mode input operational amplifier circuit includes a differential common-mode operational amplifier OP, a first link, a second link, a resistor R1, and a resistor R2. One end of the resistor R1 is connected to the input signal VIN, and one end of the resistor R2 is connected to the input signal VIP. The other end of the resistor R1 is connected to the non-inverting input terminal of the differential common-mode operational amplifier OP and one end of the first link to generate a signal VIP1. The other end of the resistor R2 is connected to the inverting input terminal of the differential common-mode operational amplifier OP and one end of the second link to generate a signal VIN1. The inverting output terminal of the differential common-mode operational amplifier OP is connected to the other end of the first link to generate a signal VOUTN1. The non-inverting output terminal of the differential common-mode operational amplifier OP is connected to the other end of the second link to generate a signal VOUTP1. The differential common-mode operational amplifier OP uses a low-voltage differential input pair transistor.

[0011] Further, the first link includes a gain modulation module dm_gain_trim1, a high-voltage MOS transistor HVMOS1, and a resistor R3. One end of the gain modulation module dm_gain_trim1 is connected to the signal VOUTN1. The other end of the gain modulation module dm_gain_trim1 is connected to the source of the high-voltage MOS transistor HVMOS1. The gate of the high-voltage MOS transistor HVMOS1 is connected to the control signal EN1. The drain of the high-voltage MOS transistor HVMOS1 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the signal VIP1.

[0012] Further, the second link includes a gain modulation module dm_gain_trim2, a high-voltage MOS transistor HVMOS2, and a resistor R4. One end of the gain modulation module dm_gain_trim2 is connected to the signal VOUTP1. The other end of the gain modulation module dm_gain_trim2 is connected to the source of the high-voltage MOS transistor HVMOS2. The gate of the high-voltage MOS transistor HVMOS2 is connected to the control signal EN2. The drain of the high-voltage MOS transistor HVMOS2 is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to the signal VIN1.

[0013] Further, the differential common-mode operational amplifier OP includes a main control circuit, a bias circuit, a common-mode feedback circuit, and an Offset trimming circuit. The bias circuit provides bias current and bias voltage for the main control circuit, the common-mode feedback circuit, and the Offset trimming circuit. The main control circuit converts different high-voltage common-mode input signals into low-voltage common-mode output signals and performs differential amplification. The common-mode feedback circuit provides a common-mode output low voltage for the main control circuit. The Offset trimming circuit reduces the input Offset voltage of the main control circuit.

[0014] Further, the main control circuit includes a low-voltage NMOS transistor NM1, a low-voltage NMOS transistor NM2, a low-voltage NMOS transistor NM3, a high-voltage NMOS transistor HVNM1, a high-voltage NMOS transistor HVNM2, a high-voltage NMOS transistor HVNM3, a low-voltage PMOS transistor PM1, and a low-voltage PMOS transistor PM2. The gate of the low-voltage NMOS transistor NM1 is connected to the signal VIP1, the gate of the low-voltage NMOS transistor NM2 is connected to the signal VIN1. The gate of the low-voltage NMOS transistor NM1 is connected to the gates of the low-voltage NMOS transistor NM2 and the drain of the high-voltage NMOS transistor HVNM1 to generate a voltage signal V1. The gate of the high-voltage NMOS transistor HVNM1 is connected to the voltage signal VBN2. The source of the high-voltage NMOS transistor HVNM1 is connected to the drain of the low-voltage NMOS transistor NM3. The gate of the low-voltage NMOS transistor NM3 is connected to the voltage signal VBN1. The source of the low-voltage NMOS transistor NM3 is connected to the negative voltage power supply LVSS. The drain of the low-voltage NMOS transistor NM1 is connected to the source of the high-voltage NMOS transistor HVNM2 to generate a voltage signal V2. The drain of the low-voltage NMOS transistor NM2 is connected to the source of the high-voltage NMOS transistor HVNM3 to generate a voltage signal V3. The gates of the high-voltage NMOS transistor HVNM2 and the high-voltage NMOS transistor HVNM3 are connected to the voltage signal VBN3. The drain of the high-voltage NMOS transistor HVNM2 is connected to the drain of the low-voltage PMOS transistor PM1. The drain of the high-voltage NMOS transistor HVNM3 is connected to the drain of the low-voltage PMOS transistor PM2. The gates of the low-voltage PMOS transistor PM1 and the low-voltage PMOS transistor PM2 are connected to the voltage signal VBP1. The sources of the low-voltage PMOS transistor PM1 and the low-voltage PMOS transistor PM2 are connected to the high-voltage power supply HVDD.

[0015] Further, the main control circuit further includes a Zener diode D1 and a Zener diode D2. The anode of the Zener diode D1 is connected to the source of the low-voltage NMOS transistor NM1, and the cathode of the Zener diode D1 is connected to the gate of the low-voltage NMOS transistor NM1. The anode of the Zener diode D2 is connected to the source of the low-voltage NMOS transistor NM2, and the cathode of the Zener diode D2 is connected to the gate of the low-voltage NMOS transistor NM2.

[0016] Further, the main control circuit further includes a low-voltage NMOS transistor NM4, a low-voltage NMOS transistor NM5, a low-voltage NMOS transistor NM6, a high-voltage NMOS transistor HVNM4, a low-voltage PMOS transistor PM3, and a low-voltage PMOS transistor PM4. The source of the low-voltage NMOS transistor NM6 is connected to the negative voltage power supply LVSS. The gate of the low-voltage NMOS transistor NM6 generates a voltage signal VBN1. The drain of the low-voltage NMOS transistor NM6 is connected to the source of the high-voltage NMOS transistor HVNM4. The gate of the high-voltage NMOS transistor HVNM4 generates a voltage signal VBN2. The drain of the high-voltage NMOS transistor HVNM4 is connected to the source of the low-voltage NMOS transistor NM5 and the voltage signal V1. The gate of the low-voltage NMOS transistor NM5 is connected to the drain of the low-voltage NMOS transistor NM5 and the source of the low-voltage NMOS transistor NM4. The gate of the low-voltage NMOS transistor NM4 is connected to the drain of the low-voltage NMOS transistor NM4 and the drain of the low-voltage PMOS transistor PM4 and generates a voltage signal VBN3. The gate of the low-voltage PMOS transistor PM4 is connected to the voltage signal VBP3. The source of the low-voltage PMOS transistor PM4 is connected to the drain of the low-voltage PMOS transistor PM3. The gate of the low-voltage PMOS transistor PM3 is connected to the voltage signal VBP2. The source of the low-voltage PMOS transistor PM3 is connected to the high-voltage power supply HVDD.

[0017] Further, the main control circuit further includes a low-voltage NMOS transistor NM6, a low-voltage NMOS transistor NM7, a high-voltage NMOS transistor HVNM5, a high-voltage NMOS transistor HVNM6, and a resistor R5. One end of the resistor R5 is connected to the high-voltage power supply HVDD. The other end of the resistor R5 is connected to the drain of the high-voltage NMOS transistor HVNM6. The gate of the high-voltage NMOS transistor HVNM6 is connected to the voltage signal VBN3. The source of the high-voltage NMOS transistor HVNM6 is connected to the drain of the high-voltage NMOS transistor HVNM5 and generates a voltage signal ISO. The gate of the high-voltage NMOS transistor HVNM5 is connected to the voltage signal VBN6. The source of the high-voltage NMOS transistor HVNM5 is connected to the drain of the low-voltage NMOS transistor NM6. The gate of the low-voltage NMOS transistor NM6 is connected to the voltage signal VBN5. The source of the low-voltage NMOS transistor NM6 is connected to the drain of the low-voltage NMOS transistor NM7. The gate of the low-voltage NMOS transistor NM7 is connected to the voltage signal VBN4. The source of the low-voltage NMOS transistor NM7 is grounded.

[0018] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a fully differential wide common-mode input operational amplifier circuit. By using low-voltage MOS input pair transistors, the adverse effects brought by the traditional architecture can be effectively improved. First, the matching performance of the low-voltage MOS input pair transistors is good, and high-precision matching can be achieved to reduce the offset of the system. Second, the driving ability of the low-voltage MOS input pair transistors is strong and the occupied area is small, which is very helpful for the layout of the chip and the control of the cost. Description of the Drawings

[0019] Figure 1 It is a schematic diagram of a fully differential wide common-mode input operational amplifier circuit of the present invention.

[0020] Figure 2 It is a schematic diagram of the differential common-mode operational amplifier OP of the present invention.

[0021] Figure 3 It is a schematic of the main control circuit of the present invention Figure 1 .

[0022] Figure 4 It is a schematic of the main control circuit of the present invention Figure 2 .

[0023] Figure 5 It is a schematic of the main control circuit of the present invention Figure 3 .

[0024] Figure 6 It is a process cross-sectional view of the input low-voltage MOS pair transistors of an embodiment of the present invention.

[0025] Figure 7 It is a schematic diagram of a traditional high-voltage MOS input pair transistor circuit of the prior art. Detailed implementation manners

[0026] In order to elaborate in detail on the technical solutions adopted by the present invention to achieve the predetermined technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments. And, without creative efforts, the technical means or technical features in the embodiments of the present invention can be replaced. The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0027] As Figure 1 shown, a fully differential wide common-mode input operational amplifier circuit of the present invention includes a differential common-mode operational amplifier OP, a first link, a second link, a resistor R1, and a resistor R2. One end of the resistor R1 is connected to the input signal VIN, one end of the resistor R2 is connected to the input signal VIP. The other end of the resistor R1 is connected to the non-inverting input terminal of the differential common-mode operational amplifier OP and one end of the first link to generate a signal VIP1. The other end of the resistor R2 is connected to the inverting input terminal of the differential common-mode operational amplifier OP and one end of the second link to generate a signal VIN1. The inverting output terminal of the differential common-mode operational amplifier OP is connected to the other end of the first link to generate a signal VOUTN1. The non-inverting output terminal of the differential common-mode operational amplifier OP is connected to the other end of the second link to generate a signal VOUTP1. The differential common-mode operational amplifier OP uses low-voltage differential input pair transistors.

[0028] The first link includes a gain modulation module dm_gain_trim1, a high-voltage MOS transistor HVMOS1, and a resistor R3. One end of the gain modulation module dm_gain_trim1 is connected to the signal VOUTN1, the other end of the gain modulation module dm_gain_trim1 is connected to the source of the high-voltage MOS transistor HVMOS1, the gate of the high-voltage MOS transistor HVMOS1 is connected to the control signal EN1, the drain of the high-voltage MOS transistor HVMOS1 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the signal VIP1.

[0029] The second link includes a gain modulation module dm_gain_trim2, a high-voltage MOS transistor HVMOS2, and a resistor R4. One end of the gain modulation module dm_gain_trim2 is connected to the signal VOUTP1, the other end of the gain modulation module dm_gain_trim2 is connected to the source of the high-voltage MOS transistor HVMOS2, the gate of the high-voltage MOS transistor HVMOS2 is connected to the control signal EN2, the drain of the high-voltage MOS transistor HVMOS2 is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to the signal VIN1.

[0030] As Figure 2 shown, the differential common-mode operational amplifier OP includes a main control circuit, a bias circuit, a common-mode feedback circuit, and an Offset trimming circuit. The bias circuit provides bias current and bias voltage for the main control circuit, the common-mode feedback circuit, and the Offset trimming circuit. The main control circuit converts different high-voltage common-mode input signals into low-voltage common-mode output signals and performs differential-mode amplification. The common-mode feedback circuit provides a common-mode output low voltage for the main control circuit. The Offset trimming circuit reduces the input Offset voltage of the main control circuit. The present invention mainly relates to the improvement of the main control circuit part. The bias circuit, the common-mode feedback circuit, and the Offset trimming circuit all adopt existing technologies, so their specific circuit structures are not described in detail in this application.

[0031] As Figure 3As shown, the main control circuit includes a low-voltage NMOS transistor NM1, a low-voltage NMOS transistor NM2, a low-voltage NMOS transistor NM3, a high-voltage NMOS transistor HVNM1, a high-voltage NMOS transistor HVNM2, a high-voltage NMOS transistor HVNM3, a low-voltage PMOS transistor PM1, and a low-voltage PMOS transistor PM2. The gate of the low-voltage NMOS transistor NM1 is connected to the signal VIP1, the gate of the low-voltage NMOS transistor NM2 is connected to the signal VIN1. The gate of the low-voltage NMOS transistor NM1 is connected to the gates of the low-voltage NMOS transistor NM2 and the drain of the high-voltage NMOS transistor HVNM1 and generates a voltage signal V1. The gate of the high-voltage NMOS transistor HVNM1 is connected to the voltage signal VBN2. The source of the high-voltage NMOS transistor HVNM1 is connected to the drain of the low-voltage NMOS transistor NM3. The gate of the low-voltage NMOS transistor NM3 is connected to the voltage signal VBN1. The source of the low-voltage NMOS transistor NM3 is connected to the negative power supply LVSS. The drain of the low-voltage NMOS transistor NM1 is connected to the source of the high-voltage NMOS transistor HVNM2 and generates a voltage signal V2. The drain of the low-voltage NMOS transistor NM2 is connected to the source of the high-voltage NMOS transistor HVNM3 and generates a voltage signal V3. The gates of the high-voltage NMOS transistor HVNM2 and the high-voltage NMOS transistor HVNM3 are connected to the voltage signal VBN3. The drain of the high-voltage NMOS transistor HVNM2 is connected to the drain of the low-voltage PMOS transistor PM1. The drain of the high-voltage NMOS transistor HVNM3 is connected to the drain of the low-voltage PMOS transistor PM2. The gates of the low-voltage PMOS transistor PM1 and the low-voltage PMOS transistor PM2 are connected to the voltage signal VBP1. The sources of the low-voltage PMOS transistor PM1 and the low-voltage PMOS transistor PM2 are connected to the high-voltage power supply HVDD.

[0032] Among them, the low-voltage NMOS transistors NM1 and NM2 are low-voltage MOS input pair transistors. The functions of the high-voltage NMOS transistors HVNM2 and HVNM3 are to isolate the high voltage at the input end from the low-voltage NMOS transistors NM1 and NM2.

[0033] The main control circuit also includes a Zener diode D1 and a Zener diode D2. The anode of the Zener diode D1 is connected to the source of the low-voltage NMOS transistor NM1, and the cathode of the Zener diode D1 is connected to the gate of the low-voltage NMOS transistor NM1. The anode of the Zener diode D2 is connected to the source of the low-voltage NMOS transistor NM2, and the cathode of the Zener diode D2 is connected to the gate of the low-voltage NMOS transistor NM2. The Zener diode D1 and the Zener diode D2 are used to prevent overvoltage between different ends of the input pair transistors. Especially in some abnormal situations, such as when the input common-mode voltage difference is very large or there is abnormal voltage coupling.

[0034] Such as Figure 4As shown, the main control circuit further includes a low-voltage NMOS transistor NM4, a low-voltage NMOS transistor NM5, a low-voltage NMOS transistor NM6, a high-voltage NMOS transistor HVNM4, a low-voltage PMOS transistor PM3, and a low-voltage PMOS transistor PM4. The source of the low-voltage NMOS transistor NM6 is connected to the negative voltage power supply LVSS. The gate of the low-voltage NMOS transistor NM6 generates a voltage signal VBN1. The drain of the low-voltage NMOS transistor NM6 is connected to the source of the high-voltage NMOS transistor HVNM4. The gate of the high-voltage NMOS transistor HVNM4 generates a voltage signal VBN2. The drain of the high-voltage NMOS transistor HVNM4 is connected to the source of the low-voltage NMOS transistor NM5 and the voltage signal V1. The gate of the low-voltage NMOS transistor NM5 is connected to the drain of the low-voltage NMOS transistor NM5 and the source of the low-voltage NMOS transistor NM4. The gate of the low-voltage NMOS transistor NM4 is connected to the drain of the low-voltage NMOS transistor NM4 and the drain of the low-voltage PMOS transistor PM4 and generates a voltage signal VBN3. The gate of the low-voltage PMOS transistor PM4 is connected to the voltage signal VBP3. The source of the low-voltage PMOS transistor PM4 is connected to the drain of the low-voltage PMOS transistor PM3. The gate of the low-voltage PMOS transistor PM3 is connected to the voltage signal VBP2. The source of the low-voltage PMOS transistor PM3 is connected to the high-voltage power supply HVDD.

[0035] As Figure 4 shown, a good isolation effect can be achieved by selecting an appropriate voltage signal VBN3.

[0036] Through analysis, it can be obtained that the voltage signal VBN3 can be expressed as:

[0037] VBN3 = V1 + VGS nm5 + VGS nm4 (1)

[0038] wherein, V1 is the voltage value of the voltage signal V1, VGS nm5 is the gate-source voltage of the low-voltage NMOS transistor NM5, and VGS nm4 is the gate-source voltage of the low-voltage NMOS transistor NM4.

[0039] From this, it can be obtained that:

[0040] V2 = V1 + VGS nm5 + VGS nm4 - VGS hvnm2 (2)

[0041] wherein, V2 is the voltage value of the voltage signal V2, and VGS hvnm2 is the gate-source voltage of the high-voltage NMOS transistor HVNM2;

[0042] Similarly, it can be obtained that:

[0043] V3 = V1 + VGS nm5 + VGSnm4 -VGS hvnm3 (3)

[0044] Among them, V3 is the voltage value of the voltage signal V3, and VGS hvnm3 is the gate-source voltage of the high-voltage NMOS transistor HVNM3.

[0045] It can be found from formulas (1), (2), and (3) that the voltage signal V1 only differs from the voltage signal V2 and the voltage signal V3 by a value of VGS. By reasonably adjusting the VGS values of the low-voltage NMOS transistor NM5 and the low-voltage NMOS transistor NM4, it is possible to ensure that the input pair transistor does not operate in the linear region and that there is no risk of overvoltage of VDS for the input pair transistor.

[0046] As Figure 5 shown, the main control circuit further includes a low-voltage NMOS transistor NM6, a low-voltage NMOS transistor NM7, a high-voltage NMOS transistor HVNM5, a high-voltage NMOS transistor HVNM6, and a resistor R5. One end of the resistor R5 is connected to the high-voltage power supply HVDD, the other end of the resistor R5 is connected to the drain of the high-voltage NMOS transistor HVNM6, the gate of the high-voltage NMOS transistor HVNM6 is connected to the voltage signal VBN3, the source of the high-voltage NMOS transistor HVNM6 is connected to the drain of the high-voltage NMOS transistor HVNM5 and generates a voltage signal ISO, the gate of the high-voltage NMOS transistor HVNM5 is connected to the voltage signal VBN6, the source of the high-voltage NMOS transistor HVNM5 is connected to the drain of the low-voltage NMOS transistor NM6, the gate of the low-voltage NMOS transistor NM6 is connected to the voltage signal VBN5, the source of the low-voltage NMOS transistor NM6 is connected to the drain of the low-voltage NMOS transistor NM7, the gate of the low-voltage NMOS transistor NM7 is connected to the voltage signal VBN4, and the source of the low-voltage NMOS transistor NM7 is grounded.

[0047] It should be noted that the current flowing through the low-voltage PMOS transistor PM3 needs to be the same as the current flowing through the low-voltage NMOS transistor NM6, otherwise it will affect the current value flowing through the input pair transistor.

[0048] From Figure 6 it can be seen that the low-voltage input pair transistor has NBL in the process cross-section diagram, and P-EPI is surrounded in NBL. Since P-EPI and body are at the same potential, it is also necessary to pay attention to whether there is a risk of overvoltage between NBL and body. Since the potential of NBL is connected to ISO, it is necessary to set a suitable ISO voltage. It should be noted that the ISO voltage cannot be negative, otherwise there will be a large leakage between ISO and PSUB, and it is also easy to cause latch up. If LVSS is not negative, the ISO potential can borrow the potential of V2 or V3, but when LVSS is negative, it will cause V2 and V3 to possibly be negative, so it is not appropriate to borrow the potential of V2 or V3.

[0049] Therefore, the present application constructs a circuit structure as shown in Figure 5 to generate a voltage signal ISO, and

[0050] ISO = V1 + VGS nm5 + VGS nm4 - VGS hvnm6 (4)

[0051] wherein, VGS hvnm6 is the gate-source voltage of the high-voltage NMOS transistor HVNM3.

[0052] Thus, it can be obtained that the voltage signal ISO also differs from the voltage signal V1 by one VGS, which can not only ensure that the ISO voltage of the input differential pair is greater than the body voltage, but also ensure that there is no overvoltage risk between ISO and the body. By carefully analyzing Figure 5 the circuit architecture, it can be found that even if the voltage signal VBN3 is negative, it will not make the voltage signal ISO negative, and the minimum voltage value of the voltage signal ISO will be clamped to 0V. The function of the high-voltage NMOS transistor HVNM5 is also to isolate the low-voltage devices from the high voltage. It can be found that although the input differential pair becomes a low-voltage transistor, the negative impact is that five high-voltage transistors are added. However, since the high-voltage input differential pair in the traditional high-voltage input differential pair is actually composed of more than 30 high-voltage transistors, and the high-voltage transistors in the present application are all single high-voltage MOS transistors, after comprehensive calculation, it is found that the total circuit area is still much smaller than the traditional architecture, because at least 30 input high-voltage mos differential pairs can be saved, and the effect is quite remarkable.

[0053] The present invention cleverly realizes the transformation of the input differential pair from a high-voltage structure to a low-voltage structure by constructing the VBN3 and ISO voltages, which makes an important contribution to improving the performance of the chip, reducing the area and saving costs.

[0054] The present invention provides a fully differential wide common-mode input operational amplifier circuit, which adopts a low-voltage MOS input differential pair and can effectively improve the adverse effects brought by the traditional architecture; firstly, the low-voltage mos input differential pair has good matching performance and can achieve high-precision matching, so as to reduce the offset of the system. Secondly, the low-voltage mos input differential pair has strong driving ability and small occupied area, which is very helpful for the layout of the chip and the control of costs.

[0055] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art, without departing from the scope of the technical solution of the present invention, can make some changes or modifications to the above-disclosed technical content to obtain equivalent embodiments with equivalent changes. However, as long as it does not depart from the content of the technical solution of the present invention, any simple modifications, equivalent replacements, and improvements made to the above embodiments within the spirit and principles of the present invention still fall within the protection scope of the technical solution of the present invention.

Claims

1. A fully differential wide common-mode input operational amplifier circuit, characterized in that: It includes a differential common-mode operational amplifier OP, a first link, a second link, a resistor R1, and a resistor R2. One end of the resistor R1 is connected to the input signal VIN, one end of the resistor R2 is connected to the input signal VIP. The other end of the resistor R1 is connected to the non-inverting input terminal of the differential common-mode operational amplifier OP and one end of the first link to generate a signal VIP1. The other end of the resistor R2 is connected to the inverting input terminal of the differential common-mode operational amplifier OP and one end of the second link to generate a signal VIN1. The inverting output terminal of the differential common-mode operational amplifier OP is connected to the other end of the first link to generate a signal VOUTN1. The non-inverting output terminal of the differential common-mode operational amplifier OP is connected to the other end of the second link to generate a signal VOUTP1. The differential common-mode operational amplifier OP uses a low-voltage differential input pair tube; The differential common-mode operational amplifier OP includes a main control circuit, a bias circuit, a common-mode feedback circuit, and an Offset trimming circuit. The bias circuit provides bias current and bias voltage for the main control circuit, the common-mode feedback circuit, and the Offset trimming circuit. The main control circuit converts different high-voltage common-mode input signals into low-voltage common-mode output signals and performs differential mode amplification. The common-mode feedback circuit provides a common-mode output low voltage for the main control circuit. The Offset trimming circuit reduces the input Offset voltage of the main control circuit; The main control circuit includes a low-voltage NMOS transistor NM1, a low-voltage NMOS transistor NM2, a low-voltage NMOS transistor NM3, a high-voltage NMOS transistor HVNM1, a high-voltage NMOS transistor HVNM2, a high-voltage NMOS transistor HVNM3, a low-voltage PMOS transistor PM1, and a low-voltage PMOS transistor PM2. The gate of the low-voltage NMOS transistor NM1 is connected to the signal VIP1. The gate of the low-voltage NMOS transistor NM2 is connected to the signal VIN1. The source of the low-voltage NMOS transistor NM1 is connected to the source of the low-voltage NMOS transistor NM2 and the drain of the high-voltage NMOS transistor HVNM1 to generate a voltage signal V1. The gate of the high-voltage NMOS transistor HVNM1 is connected to the voltage signal VBN2. The source of the high-voltage NMOS transistor HVNM1 is connected to the drain of the low-voltage NMOS transistor NM3. The gate of the low-voltage NMOS transistor NM3 is connected to the voltage signal VBN1. The source of the low-voltage NMOS transistor NM3 is connected to the negative power supply LVSS. The drain of the low-voltage NMOS transistor NM1 is connected to the source of the high-voltage NMOS transistor HVNM2 to generate a voltage signal V2. The drain of the low-voltage NMOS transistor NM2 is connected to the source of the high-voltage NMOS transistor HVNM3 to generate a voltage signal V3. The gates of the high-voltage NMOS transistor HVNM2 and the high-voltage NMOS transistor HVNM3 are connected to the voltage signal VBN3. The drain of the high-voltage NMOS transistor HVNM2 is connected to the drain of the low-voltage PMOS transistor PM1. The drain of the high-voltage NMOS transistor HVNM3 is connected to the drain of the low-voltage PMOS transistor PM2. The gates of the low-voltage PMOS transistor PM1 and the low-voltage PMOS transistor PM2 are connected to the voltage signal VBP1. The sources of the low-voltage PMOS transistor PM1 and the low-voltage PMOS transistor PM2 are connected to the high-voltage power supply HVDD.

2. The fully differential wide common-mode input operational amplifier circuit according to claim 1, characterized in that: The first link includes a gain modulation module dm_gain_trim1, a high-voltage MOS transistor HVMOS1, and a resistor R3. One end of the gain modulation module dm_gain_trim1 is connected to the signal VOUTN1. The other end of the gain modulation module dm_gain_trim1 is connected to the source of the high-voltage MOS transistor HVMOS1. The gate of the high-voltage MOS transistor HVMOS1 is connected to the control signal EN1. The drain of the high-voltage MOS transistor HVMOS1 is connected to one end of the resistor R3. The other end of the resistor R3 is connected to the signal VIP1.

3. A fully differential wide common-mode input operational amplifier circuit according to claim 1, characterized in that: The second link includes a gain modulation module dm_gain_trim2, a high-voltage MOS transistor HVMOS2, and a resistor R4. One end of the gain modulation module dm_gain_trim2 is connected to the signal VOUTP1. The other end of the gain modulation module dm_gain_trim2 is connected to the source of the high-voltage MOS transistor HVMOS2. The gate of the high-voltage MOS transistor HVMOS2 is connected to the control signal EN2. The drain of the high-voltage MOS transistor HVMOS2 is connected to one end of the resistor R4. The other end of the resistor R4 is connected to the signal VIN1.

4. A fully differential wide common-mode input operational amplifier circuit according to claim 1, characterized in that: The main control circuit further includes a Zener diode D1 and a Zener diode D2. The anode of the Zener diode D1 is connected to the source of the low-voltage NMOS transistor NM1, and the cathode of the Zener diode D1 is connected to the gate of the low-voltage NMOS transistor NM1. The anode of the Zener diode D2 is connected to the source of the low-voltage NMOS transistor NM2, and the cathode of the Zener diode D2 is connected to the gate of the low-voltage NMOS transistor NM2.

5. A fully differential wide common-mode input operational amplifier circuit according to claim 1, characterized in that: The main control circuit further includes a low-voltage NMOS transistor NM4, a low-voltage NMOS transistor NM5, a low-voltage NMOS transistor NM6, a high-voltage NMOS transistor HVNM4, a low-voltage PMOS transistor PM3, and a low-voltage PMOS transistor PM4. The source of the low-voltage NMOS transistor NM6 is connected to the negative voltage power supply LVSS. The gate of the low-voltage NMOS transistor NM6 generates a voltage signal VBN1. The drain of the low-voltage NMOS transistor NM6 is connected to the source of the high-voltage NMOS transistor HVNM4. The gate of the high-voltage NMOS transistor HVNM4 generates a voltage signal VBN2. The drain of the high-voltage NMOS transistor HVNM4 is connected to the source of the low-voltage NMOS transistor NM5 and the voltage signal V1. The gate of the low-voltage NMOS transistor NM5 is connected to the drain of the low-voltage NMOS transistor NM5 and the source of the low-voltage NMOS transistor NM4. The gate of the low-voltage NMOS transistor NM4 is connected to the drain of the low-voltage NMOS transistor NM4 and the drain of the low-voltage PMOS transistor PM4 and generates a voltage signal VBN3. The gate of the low-voltage PMOS transistor PM4 is connected to the voltage signal VBP3. The source of the low-voltage PMOS transistor PM4 is connected to the drain of the low-voltage PMOS transistor PM3. The gate of the low-voltage PMOS transistor PM3 is connected to the voltage signal VBP2. The source of the low-voltage PMOS transistor PM3 is connected to the high-voltage power supply HVDD.

6. The fully differential wide common-mode input operational amplifier circuit according to claim 5, characterized in that: The main control circuit further includes a low-voltage NMOS transistor NM6, a low-voltage NMOS transistor NM7, a high-voltage NMOS transistor HVNM5, a high-voltage NMOS transistor HVNM6, and a resistor R5. One end of the resistor R5 is connected to the high-voltage power supply HVDD, and the other end of the resistor R5 is connected to the drain of the high-voltage NMOS transistor HVNM6. The gate of the high-voltage NMOS transistor HVNM6 is connected to the voltage signal VBN3. The source of the high-voltage NMOS transistor HVNM6 is connected to the drain of the high-voltage NMOS transistor HVNM5 and generates a voltage signal ISO. The gate of the high-voltage NMOS transistor HVNM5 is connected to the voltage signal VBN6. The source of the high-voltage NMOS transistor HVNM5 is connected to the drain of the low-voltage NMOS transistor NM6. The gate of the low-voltage NMOS transistor NM6 is connected to the voltage signal VBN5. The source of the low-voltage NMOS transistor NM6 is connected to the drain of the low-voltage NMOS transistor NM7. The gate of the low-voltage NMOS transistor NM7 is connected to the voltage signal VBN4. The source of the low-voltage NMOS transistor NM7 is grounded.

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