Operational amplifier clamping circuit

Abstract

The invention provides an operational amplifier clamping circuit. The operational amplifier clamping circuit comprises an operational amplifier, a clamping circuit and a clamping voltage control circuit. Wherein the clamping circuit is connected with the operational amplifier, and is configured to receive a first differential input signal, adjust the first differential input signal from a first voltage to a second voltage, and output the adjusted first differential input signal to the operational amplifier. And the clamping voltage control circuit is connected with the clamping circuit and is configured to adjust the voltage difference between the first voltage and the second voltage. Thus, the clamping circuit prevents the first differential input signal from exceeding the input voltage range of the operational amplifier by adjusting the voltage of the first differential input signal from the first voltage to the second voltage. Therefore, the reliability of the operational amplifier clamping circuit is improved, and faults caused by overvoltage or abnormal signals are reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to an operational amplifier clamping circuit. Background Art

[0002] The op amp clamp circuit mainly uses the characteristics of the operational amplifier to "clamp" or "limit" the input signal to ensure that the signal remains within the preset range. This circuit structure is widely used in various electronic devices to improve the stability and reliability of the circuit. Summary of the invention

[0003] In view of this, an embodiment of the present disclosure provides an operational amplifier clamping circuit to improve the reliability of the operational amplifier in an extreme working state.

[0004] The technical solution of the embodiment of the present disclosure is implemented as follows: An embodiment of the present disclosure provides an operational amplifier clamp circuit, comprising: an operational amplifier, a clamp circuit and a clamp voltage control circuit; wherein the clamp circuit is connected to the operational amplifier, configured to receive a first differential input signal, and adjust the first differential input signal from a first voltage to a second voltage, and output the adjusted first differential input signal to the operational amplifier; the clamp voltage control circuit is connected to the clamp circuit, and configured to adjust the voltage difference between the first voltage and the second voltage.

[0005] In the above scheme, the clamping circuit includes: a first step-down element and a first transistor; wherein the first end of the first step-down element receives the first differential input signal at the first voltage, and the second end of the first step-down element outputs the first differential input signal at the second voltage; the first end of the first transistor is connected to the second end of the first step-down element; the second end of the first transistor is grounded; the clamping voltage control circuit is connected to the control end of the first transistor and is configured to adjust the conduction degree of the first transistor; wherein the conduction degree of the first transistor is used to control the voltage difference between the first voltage and the second voltage.

[0006] In the above scheme, the clamping voltage control circuit is configured to turn on the first transistor when the difference between the first voltage and the power supply voltage is less than or equal to a preset value; or to turn off the first transistor when the difference between the first voltage and the power supply voltage is greater than a preset value.

[0007] In the above scheme, the clamping voltage control circuit also includes: a second transistor, a second voltage-dropping element and a first current source; wherein the first end of the second transistor receives the power supply voltage; the second end and the control end of the second transistor are both connected to the first end of the second voltage-dropping element; the second end of the second voltage-dropping element and the first end of the first current source are both connected to the control end of the first transistor; and the second end of the first current source is grounded.

[0008] In the above solution, the first voltage-dropping element and the second voltage-dropping element both include: any one of a resistor, a diode and a transistor.

[0009] In the above solution, the resistance values ​​of the first voltage drop element and the second voltage drop element are equal.

[0010] In the above solution, the equivalent sizes of the first transistor and the second transistor are equal.

[0011] In the above solution, the operational amplifier is a folding operational amplifier.

[0012] In the above scheme, the operational amplifier includes: a first differential input transistor, a second differential input transistor and a first current mirror; wherein the control end of the first differential input transistor is connected to the output end of the clamp circuit and receives the first differential input signal of the second voltage; the control end of the first differential input transistor receives the second differential input signal; the first ends of the first differential input transistor and the second differential input transistor are both grounded; and the second ends of the first differential input transistor and the second differential input transistor are both connected to the first current mirror.

[0013] In the above scheme, the operational amplifier clamp circuit is applied to a current mirror circuit; the current mirror circuit includes: a second current mirror, a second current source, and a load circuit; wherein the output end of the operational amplifier is respectively connected to the control ends of the input transistor and the output transistor in the second current mirror; the first differential input end of the operational amplifier is respectively connected to the second end of the input transistor in the second current mirror and the first end of the second current source; the second differential input end of the operational amplifier is respectively connected to the second end of the output transistor in the second current mirror and the first end of the load circuit; the first ends of the input transistor and the output transistor in the second current mirror receive the power supply voltage; the second ends of the load circuit and the second current source are grounded.

[0014] The embodiment of the present disclosure provides an operational amplifier clamp circuit including an operational amplifier, a clamp circuit and a clamp voltage control circuit. The clamp circuit is connected to the operational amplifier. The clamp circuit is configured to receive a first differential input signal, adjust the first differential input signal from a first voltage to a second voltage, and output the adjusted first differential input signal to the operational amplifier. The clamp voltage control circuit is configured to adjust the voltage difference between the first voltage and the second voltage. In this way, the clamp circuit prevents the first differential input signal from exceeding the input voltage range of the operational amplifier by adjusting the voltage of the first differential input signal from the first voltage to the second voltage (the second voltage is less than or equal to the first voltage). In this way, the clamp circuit can limit the amplitude of the differential input signal to a suitable range, reduce faults caused by overvoltage or abnormal signals, and improve the reliability of the operational amplifier clamp circuit. In addition, the clamp voltage control circuit accurately controls the voltage drop of the clamp circuit to the first differential input signal, thereby ensuring signal integrity and avoiding signal clipping or distortion caused by improper clamping. At the same time, the clamp voltage control circuit can optimize the voltage drop amplitude and reduce the energy consumption of the clamp circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of the structure of the operational amplifier clamp circuit provided in the embodiment of the present disclosure Figure 1 ; Figure 2 A schematic diagram of the structure of a clamping circuit provided in an embodiment of the present disclosure; Figure 3 A schematic diagram of the structure of a clamping voltage control circuit provided in an embodiment of the present disclosure; Figure 4 The structure of the operational amplifier provided in the embodiment of the present disclosure is shown in FIG. Figure 1 ; Figure 5 The structure of the operational amplifier provided in the embodiment of the present disclosure is shown in FIG. Figure 2 ; Figure 6 A schematic diagram of the structure of the operational amplifier clamp circuit provided in the embodiment of the present disclosure Figure 2 ; Figure 7 A schematic diagram of the structure of the current mirror circuit provided in the embodiment of the present disclosure Figure 1 ; Figure 8 A schematic diagram of the structure of the current mirror circuit provided in the embodiment of the present disclosure Figure 2 . DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0017] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0018] If similar descriptions of "first / second" appear in the application documents, the following description is added. In the following description, the terms "first / second / third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first / second / third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0020] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0021] Figure 1 is a schematic diagram of an optional operational amplifier clamp circuit 100 provided in an embodiment of the present disclosure, with reference to Figure 1 The operational amplifier clamp circuit 100 includes an operational amplifier 10. The operational amplifier 10 may be any one of a two-stage operational amplifier, a folded cascode operational amplifier, a fully differential operational amplifier, and the like.

[0022] It should be noted that the reference Figure 1, the operational amplifier 10 receives a first differential input signal and a second differential input signal. The operational amplifier 10 is used to amplify the voltage difference between the first differential input signal and the second differential input signal. Under the influence of power supply fluctuations or external interference, the first differential input signal may have an excessively high voltage, for example, the first differential input signal is close to the power supply voltage VDD. However, the operational amplifier 10 has certain limitations on the voltage tolerance range, and the voltage of the first differential input signal exceeds the input voltage range allowed by the operational amplifier 10, affecting the normal operation of the operational amplifier 10. At the same time, the voltage difference between the first differential input signal and the second differential input signal will be very large, resulting in output distortion and other abnormal operation.

[0023] In the embodiments of the present disclosure, reference Figure 1 , the operational amplifier clamp circuit 100 also includes a clamp circuit 20. The clamp circuit 20 is connected to the operational amplifier 10. The clamp circuit 20 is configured to receive a first differential input signal, adjust the first differential input signal from a first voltage to a second voltage, and output the adjusted first differential input signal to the operational amplifier 10. The second voltage may be less than or equal to the first voltage. The second voltage is within the allowable input voltage range of the operational amplifier 10. For example, the clamp circuit 20 may include components such as a diode, a Zener diode, or a transient voltage suppressor (TVS). The reverse breakdown voltage of the diode may be slightly lower than the maximum allowable input voltage, so that the clamp voltage of the operational amplifier clamp circuit 100 can limit the voltage of the first differential input signal. For another example, the clamp circuit 20 may include a resistor. The clamp circuit 20 changes the voltage of the first differential input signal by means of a resistor voltage divider, so that the first differential input signal is reduced from the first voltage to the second voltage.

[0024] That is, the clamp circuit 20 prevents the first differential input signal from exceeding the input voltage range of the operational amplifier 10 by adjusting the voltage of the first differential input signal from the first voltage to the second voltage (the second voltage is less than or equal to the first voltage). In this way, the clamp circuit 20 can limit the amplitude of the differential input signal to a suitable range. At the same time, the clamp circuit 20 can limit the voltage of the differential input signal to a safe range that the operational amplifier 10 can withstand, avoiding excessive voltage from causing damage to components such as transistors inside the operational amplifier 10, thereby extending the service life of the operational amplifier 10, improving the reliability of the op amp clamp circuit, and reducing failures caused by overvoltage or abnormal signals.

[0025] It should also be noted that the reference Figure 1, when the voltage of the first differential input signal is within the normal working range of the operational amplifier 10, if the clamping circuit 20 is continued to be used to clamp the voltage of the first differential input signal, the clamping circuit 20 may cause distortion or offset of the first differential input signal of the operational amplifier 10. For example, diodes and resistors may introduce additional leakage current, causing distortion or offset of the input signal.

[0026] In the embodiments of the present disclosure, reference Figure 1 , the op amp clamp circuit 100 also includes a clamp voltage control circuit 30. The clamp voltage control circuit 30 is configured to adjust the voltage difference between the first voltage and the second voltage. For example, the clamp voltage control circuit 30 can adjust the voltage drop by adjusting the equivalent resistance of the clamp circuit 20. The clamp circuit may include a transistor. The clamp voltage control circuit 30 can adjust the gate voltage of the transistor to change the degree of conduction of the transistor, and then adjust the resistance of the clamp circuit 20 to adjust the voltage difference between the first voltage and the second voltage. For another example, the clamp voltage control circuit 30 may include a digital-to-analog converter (DAC). The digital-to-analog converter outputs a programmable voltage, and the programmable voltage acts on the clamp circuit 20 to switch different step-down elements (e.g., TVS arrays) to adjust the voltage difference between the first voltage and the second voltage. In this way, the embodiment of the present disclosure can accurately control the voltage drop of the clamp circuit 20 to the first differential input signal through the clamp voltage control circuit 30, thereby ensuring signal integrity and avoiding signal clipping or distortion caused by improper clamping. At the same time, the clamping voltage control circuit 30 can optimize the voltage drop amplitude and reduce the energy consumption of the clamping circuit 20 .

[0027] Figure 2 is a schematic diagram of an optional clamping circuit provided in an embodiment of the present disclosure. It should be noted that: Figure 2 The first voltage-reducing element 21 is a resistor R1, and the first voltage-reducing element 21 may also be any one of a diode and a transistor, which is not limited here. The first input terminal Vn of the operational amplifier clamp circuit 100 is used to receive a first differential input signal at a first voltage, and the input terminal Va of the operational amplifier 10 is used to receive a first differential input signal at a second voltage. The second input terminal Vp of the operational amplifier clamp circuit 100 is used to receive a second differential input signal.

[0028] In some embodiments of the present disclosure, reference Figure 2 The clamp circuit 20 includes a first voltage drop element 21 and a first transistor M1. A first terminal of the first voltage drop element 21 receives a first differential input signal at a first voltage, and a second terminal of the first voltage drop element 21 outputs the first differential input signal at a second voltage.

[0029] In the embodiments of the present disclosure, reference Figure 2, the first end of the first transistor M1 is connected to the second end of the first voltage-reducing element 21. The second end of the first transistor M1 is grounded. The conduction degree of the first transistor M1 is used to control the voltage difference between the first voltage and the second voltage. In this way, when the first transistor M1 is turned on, the first transistor M1 and the first voltage-reducing element 21 perform a voltage drop on the first differential input signal; when the first transistor M1 is turned off, the first voltage-reducing element 21 does not flow with current, thereby preventing the first voltage-reducing element 21 from affecting the voltage of the first differential input signal.

[0030] In the embodiments of the present disclosure, reference Figure 2 , the clamping voltage control circuit 30 is connected to the control end of the first transistor M1. The clamping voltage control circuit 30 is configured to adjust the conduction degree of the first transistor M1. The conduction degree of the first transistor M1 is different, and the clamping circuit 20 has different resistances. For example, the clamping voltage control circuit 30 can adjust the bias voltage applied to the gate of the first transistor M1, thereby adjusting the conduction degree of the first transistor M1. In this way, the embodiment of the present disclosure can accurately control the voltage drop of the clamping circuit 20 to the first differential input signal through the clamping voltage control circuit 30, thereby ensuring signal integrity and avoiding signal clipping or distortion caused by improper clamping. At the same time, the clamping voltage control circuit 30 can optimize the voltage drop amplitude and reduce the energy consumption of the clamping circuit 20.

[0031] In some embodiments of the present disclosure, reference Figure 2 , the clamping voltage control circuit 30 is configured to turn on the first transistor M1 when the difference between the first voltage and the power supply voltage VDD is less than or equal to a preset value. For example, the voltage of the power supply voltage VDD can be 3~5V, and the preset value can be 100~200mV. When the difference between the first voltage and the power supply voltage VDD is less than or equal to the preset value, that is: the voltage of the first differential input signal is close to the power supply voltage VDD, at this time, the clamping voltage control circuit 30 can turn on the first transistor M1. In this way, the first voltage-reducing element 21 flows with current, which can convert the first differential input signal from the first voltage to a lower second voltage. Thereby, the voltage of the first differential input signal is prevented from exceeding the allowable range of the operational amplifier 10, thereby reducing the fault caused by overvoltage or abnormal signals.

[0032] In the embodiments of the present disclosure, reference Figure 2 , when the difference between the first voltage and the power supply voltage VDD is greater than the preset value, that is, the voltage of the first differential input signal does not exceed the range allowed by the operational amplifier 10, the clamping voltage control circuit 30 can turn off the first transistor M1. In this way, when the first transistor M1 is turned off, no current flows through the first voltage drop element 21, thereby preventing the first voltage drop element 21 from affecting the voltage of the first differential input signal.

[0033] Figure 3 is a schematic diagram of the structure of an optional clamping voltage control circuit 30 provided in an embodiment of the present disclosure. It should be noted that: Figure 3 The second voltage-dropping element 31 exemplified includes a second resistor R2 . The second voltage-dropping element 31 may also be any one of a diode and a transistor, which is not limited here.

[0034] In some embodiments of the present disclosure, reference Figure 3 The clamping voltage control circuit 30 includes a second transistor M2, a second voltage-reducing element 31 and a first current source 32. The first end of the second transistor M2 receives the power supply voltage VDD. The second end of the second voltage-reducing element 31 and the first end of the first current source 32 are both connected to the control end of the first transistor M1. The second end of the first current source 32 is grounded.

[0035] In the embodiments of the present disclosure, reference Figure 3 The clamping voltage control circuit 30 can form a mirror effect with the clamping circuit 20. When the voltage of the first differential input signal is close to the power supply voltage VDD, the bias voltage provided by the second transistor M2 can make the first transistor M1 in a conductive state, so that the first voltage-dropping element 21 and the first transistor M1 can divide the voltage of the first differential input signal to prevent the voltage of the first differential input signal from exceeding the allowable range of the operational amplifier 10, thereby reducing faults caused by overvoltage or abnormal signals.

[0036] In addition, when the voltage of the first differential input signal is less than the power supply voltage VDD, the drain voltage of the first transistor M1 may not be able to establish a sufficient gate-source voltage V GS , causing the first transistor M1 to be completely turned off. In this way, when the first transistor M1 is turned off, no current flows through the first voltage drop element 21, thereby preventing the first voltage drop element 21 from affecting the voltage of the first differential input signal.

[0037] In some embodiments of the present disclosure, reference Figure 3 , the resistance values ​​of the first voltage drop element 21 and the second voltage drop element 31 are equal. In this way, when the voltage of the first differential input signal received by the first transistor M1 is close to the power supply voltage VDD received by the second transistor M2, the gate-source voltage of the first transistor M1 is similar to that of the first transistor M2. At this time, the voltage drop amplitude caused by the first voltage drop element 21 and the second voltage drop element 31 is similar, and the current of the clamping voltage control circuit 30 is approximately equal to that of the clamping circuit 20. In some embodiments of the present disclosure, reference Figure 3, the equivalent sizes of the first transistor M1 and the second transistor M2 are equal. In this way, when the voltage of the first differential input signal received by the first transistor M1 is close to the power supply voltage VDD received by the second transistor M2 (considering the extreme value, equal to VDD), the gate-source voltage of the first transistor M1 is the same as that of the first transistor M2. At this time, the voltage drop amplitude caused by the first voltage drop element 21 and the second voltage drop element 31 is the same, and the current of the clamping voltage control circuit 30 is equal to that of the clamping circuit 20.

[0038] Figure 4 is a schematic diagram of the structure of an optional operational amplifier 10 provided in an embodiment of the present disclosure, Figure 4 The operational amplifier 10 only illustrates the first current mirror 11 and transistors M21 and M22 of the input stage of the operational amplifier 10. The remaining structure of the operational amplifier 10 can be understood by referring to any one of the corresponding operational amplifiers such as a two-stage operational amplifier, a folded cascode operational amplifier and a fully differential operational amplifier.

[0039] In some embodiments of the present disclosure, reference Figure 4 The operational amplifier 10 includes a first differential input transistor M21, a second differential input transistor M22 and a first current mirror 11. The control end of the first differential input transistor M21 is connected to the output end of the clamp circuit 20 and receives a first differential input signal of a second voltage. The control end of the first differential input transistor M21 receives a second differential input signal Vp. The first ends of the first differential input transistor M21 and the second differential input transistor M22 are both grounded. The second ends of the first differential input transistor M21 and the second differential input transistor M22 are both connected to the first current mirror 11.

[0040] Figure 5 is a schematic structural diagram of an optional folded cascode operational amplifier provided in an embodiment of the present disclosure, Figure 6 Specific examples are given Figure 5 FIG. 1 is a diagram showing a connection relationship between the folded cascode operational amplifier, the clamp circuit 20 and the clamp voltage control circuit 30. FIG.

[0041] It should be noted that Figure 5 The functions of transistors M25, M26, M29, M210, M211 and M212 can be understood with reference to current sources, which are used to provide tail currents. Bias voltages Vb2, Vb3 and Vb4 drive corresponding transistors respectively. Transistors M27 and M28 form the cascode stage of the operational amplifier 10, which is used to increase the gain and output impedance of the operational amplifier 10. The first current mirror 11 is composed of transistors M23 and M24.

[0042] Below Figure 5 and Figure 6 Taking the illustrated folded cascode operational amplifier as an example, the principles of the operational amplifier 10, the clamping circuit 20 and the clamping voltage control circuit 30 are explained: In the present disclosure, Figure 5 and Figure 6 In an ideal case, the two input terminals Vp and Vn of the operational amplifier have the same voltage to produce zero output. However, due to the mismatch in the actual circuit, such as differences in transistor size, threshold voltage, etc., there will be an input offset voltage ΔVoffset. When the voltage of the first differential input signal is close to the power supply voltage VDD, the first differential input transistor M21 and the second differential input transistor M22 may be in the linear region, and their transconductance (gm) will decrease significantly, which will further increase the impact of the input offset voltage. As a result, the operational amplifier 10 will have problems such as decreased open-loop gain and poor stability.

[0043] Furthermore, the clamping circuit 20 can perform a voltage drop on the first differential input signal when the voltage of the first differential input signal is close to the power supply voltage VDD, thereby limiting the amplitude of the differential input signal within an appropriate range and preventing the first differential input transistor M21 and the second differential input transistor M22 from entering the linear region, thereby ensuring that the operational amplifier 10 always operates in the linear region, improving the reliability of the operational amplifier clamping circuit, and reducing faults caused by overvoltage or abnormal signals.

[0044] In addition, when the voltage of the first differential input signal is far from the power supply voltage VDD, the clamping voltage control circuit 30 can turn off the first transistor M1 in the clamping circuit 20, so that no current flows through the first voltage drop element 21, thereby preventing the first voltage drop element 21 and the first transistor M1 from affecting the voltage of the first differential input signal. Thus, signal integrity is ensured and signal clipping or distortion caused by improper clamping is avoided.

[0045] Figure 7 is a schematic diagram of a structure of an operational amplifier clamp circuit 100 provided in an embodiment of the present disclosure applied to a current mirror circuit 200. It should be noted that: Figure 7 The example shows that the operational amplifier clamp circuit 100 is applied to the current mirror circuit 200. The operational amplifier clamp circuit 100 can also be applied to other types of circuits, such as interface circuits, etc., which is not limited here.

[0046] Figure 8 is a schematic diagram of a structure of an optional current mirror circuit 200 provided in an embodiment of the present disclosure. Figure 8 The current mirror circuit 200 is exemplified to explain the principle of the operation of the operational amplifier clamp circuit 100 on the current mirror circuit 200: In the present disclosure, Figure 7 and Figure 8 The current mirror circuit 200 includes a second current mirror 201, a second current source 202 and a load circuit 203. The output terminal Vo of the operational amplifier 10 is respectively connected to the control terminals of the input transistor M31 and the output transistor M32 in the second current mirror 201. The first differential input terminal of the operational amplifier 10 is respectively connected to the second terminal of the input transistor M31 in the second current mirror 201 and the first terminal of the second current source 202. The second differential input terminal of the operational amplifier 10 is respectively connected to the second terminal of the output transistor M32 in the second current mirror 201 and the first terminal of the load circuit 203. The first terminals of the input transistor M31 and the output transistor M32 in the second current mirror 201 receive the power supply voltage VDD. The second terminals of the second current source 202 and the load circuit 203 are grounded.

[0047] In the present disclosure, Figure 7 and Figure 8 , the inverting input terminal Vn of the op amp clamp circuit 100 can receive the first differential input signal. The non-inverting input terminal Vp of the op amp clamp circuit 100 can receive the second differential input signal. When the voltage of the first differential input signal is close to the power supply voltage VDD, the loop gain decreases significantly, and the differential input transistor in the op amp clamp circuit 100 may be close to its linear region, resulting in a decrease in transconductance and an increase in offset voltage. As a result, the mirror current Iout output by the second current mirror 201 in the current mirror circuit 200 will be amplified due to ΔVoffset in the op amp clamp circuit 100. The closer the voltage of the first differential input signal is to the power supply voltage VDD, the greater the amplification factor of the mirror current Iout, and as a result, excessive output current will damage the subsequent circuit. In other words, random mismatches (such as mismatches in transistor size) can cause the mirror ratio of the current mirror circuit 200 to deviate from the ideal value. When the loop gain of the current mirror circuit 200 drops to a certain level, the current mirror circuit 200 may not be able to effectively adjust to offset the random mismatch, causing the loop of the current mirror circuit 200 to enter a locked state.

[0048] Furthermore, when the voltage of the first differential input signal is close to the power supply voltage VDD, the clamp circuit in the op amp clamp circuit 100 can perform a voltage drop on the first differential input signal. In this way, the disclosed embodiment can prevent the current mirror circuit 200 from entering an extreme operating condition (such as excessive offset voltage, too low loop gain), thereby improving the reliability of the current mirror circuit 200 under extreme operating conditions.

[0049] The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0050] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. An operational amplifier clamp circuit, characterized in that: include: An operational amplifier, a clamping circuit and a clamping voltage control circuit; wherein, The clamp circuit is connected to the operational amplifier and is configured to receive a first differential input signal, adjust the first differential input signal from a first voltage to a second voltage, and output the adjusted first differential input signal to the operational amplifier; The clamp voltage control circuit is connected to the clamp circuit and is configured to adjust a voltage difference between the first voltage and the second voltage.

2. The operational amplifier clamp circuit according to claim 1, characterized in that: The clamping circuit comprises: a first voltage-dropping element and a first transistor; wherein, The first terminal of the first voltage-reducing element receives the first differential input signal at the first voltage, and the second terminal of the first voltage-reducing element outputs the first differential input signal at the second voltage; The first end of the first transistor is connected to the second end of the first voltage-dropping element; the second end of the first transistor is grounded; The clamping voltage control circuit is connected to the control terminal of the first transistor and is configured to adjust the conduction degree of the first transistor; wherein the conduction degree of the first transistor is used to control the voltage difference between the first voltage and the second voltage.

3. The operational amplifier clamp circuit according to claim 2, characterized in that: The clamping voltage control circuit is configured to turn on the first transistor when the difference between the first voltage and the power supply voltage is less than or equal to a preset value; or to turn off the first transistor when the difference between the first voltage and the power supply voltage is greater than a preset value.

4. The operational amplifier clamp circuit according to claim 3, characterized in that: The clamping voltage control circuit further includes: a second transistor, a second voltage-dropping element and a first current source; wherein, The first end of the second transistor receives the power supply voltage; the second end and the control end of the second transistor are both connected to the first end of the second step-down element; the second end of the second step-down element and the first end of the first current source are both connected to the control end of the first transistor; the second end of the first current source is grounded.

5. The operational amplifier clamp circuit according to claim 4, characterized in that: The first voltage-dropping element and the second voltage-dropping element each include any one of a resistor, a diode and a transistor.

6. The operational amplifier clamp circuit according to claim 5, characterized in that: The first voltage drop element and the second voltage drop element have the same resistance value.

7. The operational amplifier clamp circuit according to claim 6, characterized in that: The equivalent sizes of the first transistor and the second transistor are equal.

8. The operational amplifier clamp circuit according to claim 1, characterized in that: The operational amplifier is a folding operational amplifier.

9. The operational amplifier clamp circuit according to claim 8, characterized in that: The operational amplifier comprises: a first differential input transistor, a second differential input transistor and a first current mirror; wherein, The control terminal of the first differential input transistor is connected to the clamp circuit and receives the first differential input signal of the second voltage; The control terminal of the first differential input transistor receives a second differential input signal; wherein the voltage of the second differential input signal changes with the first differential input signal; The first terminals of the first differential input transistor and the second differential input transistor are both grounded; and the second terminals of the first differential input transistor and the second differential input transistor are both connected to the first current mirror.

10. The operational amplifier clamp circuit according to claim 1, characterized in that: The operational amplifier clamping circuit is applied to a current mirror circuit; The current mirror circuit comprises: a second current mirror, a second current source, and a load circuit; wherein, The output end of the operational amplifier is connected to the control end of the input transistor and the output transistor in the second current mirror respectively; The first differential input terminal of the operational amplifier is connected to the second terminal of the input transistor in the second current mirror and the first terminal of the second current source respectively; The second differential input terminal of the operational amplifier is connected to the second terminal of the output transistor in the second current mirror and the first terminal of the load circuit respectively; The first terminals of the input transistor and the output transistor in the second current mirror receive the power supply voltage; the second terminals of the load circuit and the second current source are grounded.

Images