High-precision pulse width modulator supporting adaptive calibration and application method thereof

Abstract

The present invention discloses a high-precision pulse width modulator supporting adaptive calibration and its application method. The present invention includes a delay and calibration unit for generating a high-precision PWM waveform. The delay and calibration unit includes a delay line, a first selector, a second selector, and a calibration module. The delay line is composed of N-1 stages of delay cells. The first selector and the second selector are both N-to-1 selectors. Both the first selector and the second selector are used to select one of N inputs based on a delay cell selection signal to obtain a high-precision PWM waveform output. The calibration module is used to calibrate the high-precision PWM waveform output by the second selector to generate an actual calibration value representing the number of delay cell stages required for the current delay of one clock cycle. The present invention allows users to directly observe the accuracy of the delay cells without the need for additional calculations. This can eliminate the delay cell accuracy calculation process, avoid errors caused by additional calculations, and improve usage efficiency.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit design, and in particular relates to a high-precision pulse width modulator supporting adaptive calibration and an application method thereof. Background Art

[0002] With the rapid advancement of semiconductor processing, digital control technology has become increasingly mature and widely used in power management, automatic control, and other fields. Pulse width modulation (PWM) is a key component of digital control technology. In integrated circuit design, the enhanced high-resolution pulse width modulator (eHRPWM), a key component in power electronics systems, can output complex waveforms, including high-precision PWM waveforms (pulse width modulation waveforms) with adjustable frequency and duty cycle. These waveforms are widely used in measurement, communications, and power control and conversion. As application demands increase, the requirements for PWM waveform output accuracy are also increasing. While using delay cells to achieve high-precision PWM waveform output, the accuracy of the delay cells cannot be directly observed by the user, requiring additional calculations. This can easily lead to errors in the delay cell accuracy calculation, and the process is cumbersome, affecting efficiency.

[0003] A major method of implementing pulse width modulation is to use a delay line composed of delay units. The pulse width modulator implemented by the delay line can achieve more accurate PWM waveform output and obtain a PWM waveform with a higher-precision duty cycle output. Combined with calibration technology, the accuracy of the delay unit can be observed in real time, improving the efficiency of use. At present, some research related to the technology of implementing high-precision pulse width modulation based on delay units has also emerged. For example: (1) Patent application document No. WO2022 / 121389A1 discloses a high-resolution pulse width modulation signal generation circuit, which aims to solve the problem that the accuracy of the PWM signal is limited by the clock frequency in the prior art. The circuit improves the resolution of the PWM signal without changing the counting clock; through the multiple relationship between the counting clock and the delay chain, the delay module is regarded as a lower-level extension of the PWM counting module, which is convenient for control and improves the accuracy of the PWM signal; using MUX as the minimum delay unit and delay selection logic of the delay chain reduces the inherent delay, which is conducive to reducing the error of the delay chain. However, the disadvantage of this circuit is that the calibration circuit measures the multiple relationship between the counting clock and the delay chain. Its focus is on solving the problem that the PWM signal accuracy is limited by the clock frequency in the existing technology, and it does not consider directly mapping the current delay unit accuracy to the register. While outputting a high-precision PWM waveform, the user cannot directly observe the current delay unit accuracy. (2) The patent application document with publication number CN106612111A discloses a system and method for high-precision delay clock calibration, the purpose of which is to solve the technical problem of delay clock calibration. Its implementation scheme includes a NAND gate, an AND gate, a delay chip, a multiplexer and a processing module, wherein the multiplexer includes a calibration output terminal and a clock output terminal, and the processing module includes a delay control terminal, a selection control terminal and a control switch terminal. However, the disadvantage of this scheme is that it only realizes high-precision delay calibration for the clock input. It focuses on solving the technical problem of delay clock calibration and realizes clock delay calibration by introducing a delay chip. The premise of the system's operation is that the clock input is a fixed duty cycle, and the situation of other complex waveform outputs is not considered. (3) Patent application publication number CN112187229A discloses a high-resolution pulse width modulation system with multi-phase delays. The purpose is to achieve high-precision modulation of pulse width signals. The implementation scheme includes a multi-phase delay locked loop system and a PWM signal post-processor, which can achieve pulse rising and falling edge modulation. However, after achieving high-precision pulse width modulation, the scheme does not mention a calibration method. The focus is on proposing a high-precision pulse width modulation method for pulse signals, without considering the calibration method. As a result, users cannot directly observe the accuracy of the delay unit.(4) Patent application document with publication number CN102386916A discloses a high-digital pulse width modulation circuit, which aims to solve the problems of high power consumption and large chip area of ​​digital pulse width modulators implemented by traditional delay units. The implementation scheme includes a ring oscillator, a digital phase-locked loop controller, and a pulse output circuit. The rise delay and fall delay of the delay unit are used to segmentally achieve high-bit precision and low-bit precision of pulse width modulation, and the phase difference between the rise delay and fall delay is corrected by the digital phase-locked loop, so that all falling edge delays are equal to one rising edge delay, thereby greatly reducing the number of delay units required and achieving the purpose of reducing power consumption and chip area. However, the scheme does not mention the calibration method. Its focus is on reducing power consumption and chip area by implementing a pulse width modulator based on the delay unit. It does not consider the calibration method and has not been applied to high-precision pulse width waveform output. Summary of the Invention

[0004] Technical problem to be solved by the present invention: In response to the above-mentioned problems in the prior art, a high-precision pulse width modulator supporting adaptive calibration and an application method thereof are provided. The present invention aims to generate a high-precision PWM waveform based on an ordinary PWM waveform. Through calibration, the user can directly observe the accuracy of the delay unit without the need for additional calculations, thereby eliminating the delay unit accuracy calculation process, avoiding errors caused by additional calculations, and improving usage efficiency.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0006] A high-precision pulse width modulator supporting adaptive calibration includes a delay and calibration unit for generating a high-precision PWM waveform from an input ordinary PWM waveform. The delay and calibration unit includes a delay line, a first selector, a second selector, and a calibration module. The delay line is composed of N-1 stages of delay cells. The input end of each stage of delay cells in the delay line and the output end of the last stage of delay cells are respectively connected to N input ends of the first selector and N input ends of the second selector. The first selector and the second selector are both N-to-one selectors. Both the first selector and the second selector are used to select one path from N input paths according to a delay cell selection signal to obtain a high-precision PWM waveform output. The input end of the calibration module is connected to the output end of the second selector to calibrate the high-precision PWM waveform output by the second selector in combination with the input ordinary PWM waveform to generate an actual calibration value representing the number of delay cell stages required for the current delay of one clock cycle.

[0007] Optionally, the calibration module includes a first D flip-flop, a first edge detection module, a second D flip-flop, a third D flip-flop, a second edge detection module, a calibration state judgment module, a summing module, and a fourth D flip-flop. The high-precision PWM waveform output by the first selector passes through the first D flip-flop and the first edge detection module in sequence to obtain a first edge detection result, and the ordinary PWM waveform passes through the second D flip-flop, the third D flip-flop, and the second edge detection module in sequence to obtain a second edge detection result. The first edge detection result and the second edge detection result serve as inputs of the calibration state judgment module, so that the calibration state judgment module compares the two edge detection results to determine whether the state of the current calibration value is increasing, decreasing, or maintaining. The summing module is used to update the current calibration value according to the state of the current calibration value and output it through the fourth D flip-flop until the actual calibration value tends to stabilize, so as to obtain an actual calibration value representing the number of delay unit stages required for the current delay of one clock cycle. The output of the fourth D flip-flop is connected to the input end of the summing module to provide the current calibration value.

[0008] Optionally, the summation module is used to update the current calibration value according to the state of the current calibration value, including: if the state of the current calibration value is increasing, then the actual calibration value is increased by 1; if the state of the current calibration value is decreasing, then the actual calibration value is reduced by 1; if the state of the current calibration value is unchanged, then the actual calibration value remains unchanged.

[0009] Optionally, the delay line is composed of 255-level delay units, and the summing module adopts a calibration default value as the current calibration value when the fourth D flip-flop has not output a current calibration value, and the calibration default value is 128.

[0010] Optionally, the present invention also includes a PWM register module for providing a delay unit selection signal to achieve selection of high-precision PWM waveform output, processing register read and write requests from the CPU, and register output control logic, the PWM register module includes four registers: a configuration register HRCNFG, used to achieve output mode selection of high-precision PWM waveform, the output mode including duty cycle control mode and phase control mode; a duty cycle extension register CMPAHR, used to provide a delay unit selection signal under duty cycle control mode; a phase extension register TBPHSHR, used to provide a delay unit selection signal under phase control mode; a calibration register HRREF, used to indicate the actual calibration value of the number of delay unit levels required to delay one clock cycle when the PWM waveform is output.

[0011] Optionally, the domain in the configuration register HRCNFG includes a 2-bit edge mode bit EDGMODE, a 1-bit control mode bit CTLMODE and a 1-bit mapping mode bit HRLOAD, the edge mode bit EDGMODE is used to configure the edge detection mode to one of high-precision PWM waveform output enable, edge-controlled rising edge, edge-controlled falling edge, edge-controlled rising edge and falling edge, the control mode bit CTLMODE is used to configure the output mode to duty cycle control mode or phase control mode, and the mapping mode bit HRLOAD is used to configure the mapping value loading event of the delay unit selection signal in the duty cycle control mode to the counter being equal to zero or a preset period PRD.

[0012] Optionally, the duty cycle extension register CMPAHR has a value range of 1 to N-1 for implementing 1 to N-1 levels of adjustable delay line in duty cycle control mode, where N-1 is the number of delay units in the delay line.

[0013] Optionally, the value range of the phase expansion register TBPHSHR is 1 to N-1 to achieve 1 to N-1 level adjustment of the delay line in the phase control mode, where N-1 is the number of delay units in the delay line.

[0014] Optionally, the input end of the delay and calibration unit is further connected to a common PWM waveform generator for generating a common PWM waveform.

[0015] In addition, the present invention also provides an application method of the aforementioned high-precision pulse width modulator supporting adaptive calibration, comprising the following steps:

[0016] S1, read the edge mode bit EDGMODE of the configuration register HRCNFG through the PWM register module to see if the high-precision PWM waveform output function is disabled. If the high-precision PWM waveform output function is not disabled, jump to step S2; otherwise, directly output the ordinary PWM waveform, end and exit;

[0017] S2, determining the output mode of the high-precision PWM waveform according to the control mode bit CTLMODE of the configuration register HRCNFG. If the output mode of the high-precision PWM waveform is the duty cycle control mode, the duty cycle extension register CMPAHR is selected to provide a delay unit selection signal in the duty cycle control mode; if the output mode of the high-precision PWM waveform is the phase control mode, the phase extension register TBPHSHR is selected to provide a delay unit selection signal in the phase control mode;

[0018] S3, performing delay and calibration processing by the delay and calibration unit, including: delaying the input common PWM waveform by using the N-1-stage delay unit in the delay line, and selecting one path from the N input paths by using the first selector and the second selector in combination with the mapping mode bit HRLOAD and the delay unit selection signal to obtain a high-precision PWM waveform output; calibrating the high-precision PWM waveform output by the second selector and the input common PWM waveform by using the calibration module in combination with the edge detection mode configured by the edge mode bit EDGMODE to generate an actual calibration value representing the number of delay unit stages required for the current delay of one clock cycle, and writing the value into the calibration register HRREF until the actual calibration value stabilizes;

[0019] S4, responding to the user's read request through the PWM register module, and returning the actual calibration value written into the calibration register HRREF, which represents the number of delay unit stages required for the current delay of one clock cycle.

[0020] Compared with the existing technology, the present invention has the following main advantages: on the basis of realizing high-precision PWM waveform output, the present invention combines a calibration module to realize a high-precision pulse width modulation method that supports adaptive calibration. Through adaptive calibration, while outputting a high-precision PWM waveform, the present invention instantly generates an actual calibration value representing the number of delay unit stages required for the current delay of one clock cycle. The user can instantly observe the number of delay unit stages required for a delay of one clock cycle, eliminate the delay unit accuracy calculation process, avoid errors caused by extra calculations, and improve usage efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Schematic diagram of the overall structure of a high-precision pulse width modulator in an embodiment of the present invention.

[0022] Figure 2 Schematic diagram of the structure of the delay and calibration unit in an embodiment of the present invention.

[0023] Figure 3 Schematic diagram of the structure of the calibration module in an embodiment of the present invention.

[0024] Figure 4 Schematic diagram of the working process of the high-precision pulse width modulator in an embodiment of the present invention.

[0025] Legend: 1. Delay line; 2. First selector; 3. Second selector; 4. Calibration module; 41. First D flip-flop; 42. First edge detection module; 43. Second D flip-flop; 44. Third D flip-flop; 45. Second edge detection module; 46. Calibration status judgment module; 47. Summing module; 48. Fourth D flip-flop. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution of the present invention will be further described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0027] like Figure 1 As shown in FIG, the high-precision pulse width modulator supporting adaptive calibration in this embodiment includes a delay and calibration unit for generating a high-precision PWM waveform from an input ordinary PWM waveform. The high-precision pulse width modulator supporting adaptive calibration in this embodiment combines delay line and calibration technology to design a high-precision pulse width modulator supporting adaptive calibration (eHRPWM component) including two parts: an ordinary PWM waveform generator and a delay and calibration unit. Figure 1 As shown, the input of the delay and calibration unit is connected to a conventional PWM waveform generator for generating a conventional PWM waveform. This embodiment of the high-precision pulse width modulator, which supports adaptive calibration, is a key component in power electronics systems. Its ability to achieve higher-precision PWM waveforms with adjustable frequency and duty cycle has wide applications in measurement, communications, power control, and conversion.

[0028] like Figure 2 As shown, the delay and calibration unit of this embodiment includes a delay line 1, a first selector 2, a second selector 3 and a calibration module 4. The delay line 1 is composed of N-1 stages of delay units, thereby achieving a higher-precision PWM waveform output. The input end of each stage of delay units in the delay line 1 and the output end of the last stage of delay units are respectively connected to the N input ends of the first selector 2 and the N input ends of the second selector 3. The first selector 2 and the second selector 3 are both N-to-one selectors with the same structure. Both the first selector 2 and the second selector 3 are used to select one path from the N input paths according to the delay unit selection signal select[7:0] to obtain a high-precision PWM waveform output. The input end of the calibration module 4 is connected to the output end of the second selector 3 for calibrating the high-precision PWM waveform output by the second selector 3 in combination with the input ordinary PWM waveform to generate an actual calibration value REF[7:0] representing the number of delay unit stages required for the current delay of one clock cycle.

[0029] like Figure 3As shown, the calibration module 4 of this embodiment includes a first D flip-flop 41, a first edge detection module 42, a second D flip-flop 43, a third D flip-flop 44, a second edge detection module 45, a calibration state judgment module 46, a summing module 47, and a fourth D flip-flop 48. The high-precision PWM waveform output by the first selector 2 sequentially passes through the first D flip-flop 41 and the first edge detection module 42 to obtain a first edge detection result, and the ordinary PWM waveform sequentially passes through the second D flip-flop 43, the third D flip-flop 44, and the second edge detection module 45 to obtain a second edge detection result. The first edge detection result and the second edge detection result serve as inputs of the calibration state judgment module 46. The calibration state judgment module 46 compares the two edge detection results to determine whether the state of the current calibration value is incrementing, decrementing, or maintaining. The summing module 47 is configured to update the current calibration value according to the state of the current calibration value and output it through the fourth D flip-flop 48 until the actual calibration value tends to stabilize, thereby obtaining an actual calibration value representing the number of delay unit stages required for the current delay of one clock cycle. The output of the fourth D flip-flop 48 is connected to the input of the summing module 47 to provide the current calibration value. After a standard PWM waveform is input, it sequentially enters the second and third D flip-flops 43 and 44, where edge detection is performed on the input waveform. Simultaneously, the high-precision PWM waveform, processed by the delay unit, enters the first D flip-flop 41 for edge detection. Comparing the edge detection results determines the current calibration value status (increment, decrement, or hold). Based on the calibration default value and the current calibration value, the actual calibration value is determined and written to the HRREF register. The HRREF register is automatically updated on both the rising and falling edges of the standard PWM input signal. Calibration begins upon reset, and the time from reset to completion is less than 256 clock cycles. Calibration is performed on both the rising and falling edges of the input, resulting in a fast calibration rate. While outputting the high-precision PWM waveform, the user can read the value of the HRREF register to determine the number of delay units required for one clock cycle delay.

[0030] In this embodiment, summing module 47 updates the current calibration value based on the current calibration value status. If the current calibration value status is increasing, then the actual calibration value is incremented by 1, i.e., actual calibration value = original actual calibration value + 0x1; if the current calibration value status is decreasing, then the actual calibration value is decremented by 1, i.e., actual calibration value = original actual calibration value - 0x1; and if the current calibration value status is unchanged, then the actual calibration value is left unchanged, i.e., actual calibration value = original actual calibration value. This process continues until the actual calibration value stabilizes, which is the actual number of delay unit stages required for the current delay unit to delay one clock cycle.

[0031] As an optional implementation, in this embodiment, delay line 1 consists of 255 delay units (i.e., N=256). To improve the efficiency of the calibration module, summing module 47 uses a default calibration value of 128 (0x80) as the current calibration value when the fourth D-flip-flop 48 has not yet output the current calibration value. Calibration is initiated based on the current delay unit accuracy, approaching the actual number of delay units required to delay one clock cycle. When N=256, both first selector 2 and second selector 3 are N-to-1 selectors, i.e., 256 / 1 selectors. When a standard PWM waveform is input, the delay line implemented with 255 delay units processes the input standard PWM waveform based on the delay unit selection in the first 256 / 1 selector, generating a high-precision PWM output waveform. The second 256 / 1 selector also generates a high-precision PWM output waveform based on the delay unit selection, and simultaneously enters the calibration module.

[0032] As an optional implementation, this embodiment also includes a PWM register module for providing a delay unit selection signal to achieve high-precision PWM waveform output selection, processing register read and write requests from the CPU, and register output control logic. The PWM register module includes four registers: a configuration register HRCNFG, used to achieve high-precision PWM waveform output mode selection, the output mode includes a duty cycle control mode and a phase control mode; a duty cycle extension register CMPAHR, used to provide a delay unit selection signal in the duty cycle control mode; a phase extension register TBPHSHR, used to provide a delay unit selection signal in the phase control mode; and a calibration register HRREF, used to indicate the actual calibration value of the number of delay unit levels required to delay one clock cycle when the PWM waveform is output. The configuration register HRCNFG enables selection of high-precision PWM waveform output modes, including duty cycle control and phase control. In duty cycle control mode, the duty cycle expansion register CMPAHR is selected to provide a delay unit selection signal; in phase control mode, the phase expansion register TBPHSHR is selected to provide a delay unit selection signal. In addition to enabling complex waveform output, the high-precision pulse width modulator (PWM) in this embodiment, which supports adaptive calibration, includes duty cycle expansion (including rising and falling edge control) and phase control (i.e., dual-edge control). The calibration module automatically activates after reset, with the time from reset to calibration completion less than 256 clock cycles. Calibration is performed on both the rising and falling edges of the input signal to ensure the accuracy of the calibration value. The user can read the actual calibration value instantly by reading the calibration register HRREF.

[0033] In this embodiment, the domain in the configuration register HRCNFG includes a 2-bit edge mode bit EDGMODE, a 1-bit control mode bit CTLMODE, and a 1-bit mapping mode bit HRLOAD. The edge mode bit EDGMODE is used to configure the edge detection mode to be one of high-precision PWM waveform output enable, edge-controlled rising edge, edge-controlled falling edge, and edge-controlled rising and falling edge. The control mode bit CTLMODE is used to configure the output mode to be a duty cycle control mode or a phase control mode. The mapping mode bit HRLOAD is used to configure the mapping value loading event of the delay unit selection signal in the duty cycle control mode to be the counter equal to zero or the preset period PRD. The mapping value load event is selected based on the mapping mode bit HRLOAD. This bit field selects the conditions for mapping and loading the duty cycle extension register CMPAHR. If the mapping mode bit HRLOAD is 0x0, the duty cycle extension register CMPAHR is loaded when the counter value is 0x0. If the mapping mode bit HRLOAD is 0x1, the duty cycle extension register CMPAHR is loaded when the counter value is equal to the period value. Furthermore, in this embodiment, the fields in the configuration register HRCNFG include 12 reserved bits. The information table of the fields in the configuration register HRCNFG is shown in Table 1.

[0034] Table 1: Information table of fields in configuration register HRCNFG

[0035]

[0036] In Table 1, the "R" in the Domain Control field indicates read-only, and the "R / W" field indicates read-write. The edge mode bit, EDGMODE, defaults to 0x0, indicating that the high-precision PWM function is disabled and a standard PWM waveform is output. A non-zero value indicates that the high-precision PWM function is enabled and a high-precision PWM waveform is output.

[0037] In this embodiment, the duty cycle extension register CMPAHR has a value range of 1 to N-1, which is used to implement 1 to N-1 adjustable levels of delay line 1 in the duty cycle control mode, where N-1 is the number of delay units in delay line 1. In this embodiment, the information table of the fields in the duty cycle extension register CMPAHR is specifically shown in Table 2.

[0038] Table 2: Information table of fields in the duty cycle extension register CMPAHR

[0039]

[0040] In this embodiment, the phase expansion register TBPHSHR has a value range of 1 to N-1, which is used to implement 1 to N-1 adjustable levels of delay line 1 in phase control mode, where N-1 is the number of delay units in delay line 1. In this embodiment, the information table of the fields in the phase expansion register TBPHSHR is specifically shown in Table 3.

[0041] Table 3: Information table of fields in the phase extension register TBPHSHR

[0042]

[0043] The calibration register HRREF is used to indicate the actual calibration value of the number of delay unit stages required to delay one clock cycle when outputting the PWM waveform. In this embodiment, the information table of the fields in the calibration register HRREF is specifically shown in Table 4.

[0044] Table 4: Information table of fields in the calibration register HRREF

[0045]

[0046] like Figure 4 As shown, this embodiment further provides an application method of the aforementioned high-precision pulse width modulator supporting adaptive calibration, comprising the following steps:

[0047] S1, read the edge mode bit EDGMODE of the configuration register HRCNFG through the PWM register module to see if the high-precision PWM waveform output function is disabled (i.e., whether it is equal to 0x0). If the high-precision PWM waveform output function is not disabled, jump to step S2; otherwise, directly output the normal PWM waveform, end and exit;

[0048] S2, determining the output mode of the high-precision PWM waveform according to the control mode bit CTLMODE of the configuration register HRCNFG. If the output mode of the high-precision PWM waveform is the duty cycle control mode, the duty cycle extension register CMPAHR is selected to provide a delay unit selection signal in the duty cycle control mode; if the output mode of the high-precision PWM waveform is the phase control mode, the phase extension register TBPHSHR is selected to provide a delay unit selection signal in the phase control mode;

[0049] S3, performing delay and calibration processing by the delay and calibration unit, including: delaying the input ordinary PWM waveform by the N-1-stage delay unit in the delay line 1, and selecting one path from the N input paths by combining the mapping mode bit HRLOAD and the delay unit selection signal to obtain a high-precision PWM waveform output; calibrating the high-precision PWM waveform output by the second selector 3 and the input ordinary PWM waveform by combining the edge detection mode configured by the edge mode bit EDGMODE by the calibration module 4 to generate an actual calibration value representing the number of delay unit stages required for the current delay of one clock cycle, and writing the value into the calibration register HRREF until the actual calibration value stabilizes;

[0050] S4, responding to the user's read request through the PWM register module, and returning the actual calibration value written into the calibration register HRREF, which represents the number of delay unit stages required for the current delay of one clock cycle.

[0051] In summary, the high-precision pulse width modulator supporting adaptive calibration in this embodiment achieves high-precision pulse width modulation through a delay line and, in combination with calibration technology, enables instant calibration of delay units. After selecting the high-precision control mode via the configuration register HRCNFG, the user selects the duty cycle expansion register CMPAHR / phase expansion register TBPHSHR as the delay unit selection. The delay units are adjustable from 1 to 255 levels. When a standard PWM waveform is input, a high-precision PWM waveform is output. Simultaneously, the HRREF register can be read to determine the number of delay units required for the current delay of one clock cycle. The high-precision mode of the high-precision pulse width modulator supporting adaptive calibration in this embodiment is divided into a duty cycle mode and a phase control mode. The user can configure the delay unit registers according to the high-precision mode selection. This configuration is simple and enables adjustable delay units from 0 to 255 levels. This provides high configuration flexibility. While outputting a high-precision PWM waveform, the actual delay unit accuracy can be read, avoiding additional calculation errors. This provides high flexibility and improves efficiency. In this embodiment, the default value of the actual calibration value of the high-precision pulse width modulator that supports adaptive calibration is 128. Calibration is automatically started after reset, and the time from reset to calibration completion is less than 256 PWM cycles. Calibration is performed on both the rising and falling edges of the input. The calibration value is incremented / decremented / held according to the actual calibration situation and the actual calibration value is updated in real time until the calibration value stabilizes. This can improve calibration efficiency, and the user can immediately obtain the number of delay unit stages currently delayed by one clock cycle.

[0052] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiment. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A high-precision pulse width modulator supporting adaptive calibration, characterized in that: The invention comprises a delay and calibration unit for generating a high-precision PWM waveform from an input ordinary PWM waveform, wherein the delay and calibration unit comprises a delay line (1), a first selector (2), a second selector (3) and a calibration module (4), wherein the delay line (1) is composed of N-1 levels of delay units, wherein the input end of each level of delay unit in the delay line (1) and the output end of the last level of delay unit are respectively connected to the N input ends of the first selector (2) and the N input ends of the second selector (3), wherein the first selector (2) and the second selector (3) are both N-select one select The first selector (2) and the second selector (3) are both used to select one path from N input paths according to a delay unit selection signal to obtain a high-precision PWM waveform output. The input end of the calibration module (4) is connected to the output end of the second selector (3) to calibrate the high-precision PWM waveform output by the second selector (3) in combination with the input common PWM waveform to generate an actual calibration value representing the number of delay unit stages required for the current delay of one clock cycle. The calibration module (4) includes a first D flip-flop (41), a first edge detection module (42), a second D flip-flop (43), a third D flip-flop (44), a second edge detection module (45), a calibration state judgment module (46), a summing module (47) and a fourth D flip-flop (48). The high-precision PWM waveform output by the first selector (2) passes through the first D flip-flop (41) and the first edge detection module (42) in sequence to obtain a first edge detection result. The common PWM waveform passes through the second D flip-flop (43), the third D flip-flop (44) and the second edge detection module (45) in sequence to obtain a second edge detection result. The first edge detection result and the second edge detection result are respectively The detection result is used as the input of the calibration state judgment module (46) to compare the two edge detection results through the calibration state judgment module (46) to determine whether the state of the current calibration value is increasing, decreasing or maintaining. The summing module (47) is used to update the current calibration value according to the state of the current calibration value and output it through the fourth D flip-flop (48) until the actual calibration value tends to be stable to obtain the actual calibration value representing the number of delay unit stages required for the current delay of one clock cycle. The output of the fourth D flip-flop (48) is connected to the input end of the summing module (47) to provide the current calibration value.

2. The high-precision pulse width modulator supporting adaptive calibration according to claim 1, characterized in that: The summing module (47) is used to update the current calibration value according to the state of the current calibration value, including: if the state of the current calibration value is increasing, then the actual calibration value is increased by 1; if the state of the current calibration value is decreasing, then the actual calibration value is decreased by 1; if the state of the current calibration value is unchanged, then the actual calibration value remains unchanged.

3. The high-precision pulse width modulator supporting adaptive calibration according to claim 2, characterized in that: The delay line (1) is composed of 255-level delay units. When the fourth D flip-flop (48) has not yet output a current calibration value, the summing module (47) uses a calibration default value as the current calibration value, and the calibration default value is 128.

4. The high-precision pulse width modulator supporting adaptive calibration according to any one of claims 1 to 3, characterized in that: The PWM register module is further configured to provide a delay unit selection signal to select a high-precision PWM waveform output, process register read and write requests from the CPU, and control register output logic. The PWM register module includes four registers: a configuration register HRCNFG, configured to select an output mode of a high-precision PWM waveform, wherein the output modes include a duty cycle control mode and a phase control mode; a duty cycle extension register CMPAHR, configured to provide a delay unit selection signal in the duty cycle control mode; The phase expansion register TBPHSHR is used to provide the delay unit selection signal in the phase control mode; the calibration register HRREF is used to indicate the actual calibration value of the number of delay unit stages required to delay one clock cycle when the PWM waveform is output.

5. The high-precision pulse width modulator supporting adaptive calibration according to claim 4, characterized in that: The domain in the configuration register HRCNFG includes a 2-bit edge mode bit EDGMODE, a 1-bit control mode bit CTLMODE and a 1-bit mapping mode bit HRLOAD. The edge mode bit EDGMODE is used to configure the edge detection mode to be one of high-precision PWM waveform output enable, edge-controlled rising edge, edge-controlled falling edge, edge-controlled rising edge and falling edge. The control mode bit CTLMODE is used to configure the output mode to be a duty cycle control mode or a phase control mode. The mapping mode bit HRLOAD is used to configure the mapping value loading event of the delay unit selection signal in the duty cycle control mode to be a counter equal to zero or a preset period PRD.

6. The high-precision pulse width modulator supporting adaptive calibration according to claim 5, characterized in that: The duty cycle extension register CMPAHR has a value range of 1 to N-1 for realizing 1 to N-1 level adjustment of the delay line (1) in a duty cycle control mode, wherein N-1 is the number of delay units in the delay line (1).

7. The high-precision pulse width modulator supporting adaptive calibration according to claim 4, characterized in that: The phase expansion register TBPHSHR has a value range of 1 to N-1 for realizing 1 to N-1 level adjustment of the delay line (1) in a phase control mode, wherein N-1 is the number of delay units in the delay line (1).

8. The high-precision pulse width modulator supporting adaptive calibration according to claim 1, characterized in that: The input end of the delay and calibration unit is also connected to a common PWM waveform generator for generating a common PWM waveform.

9. An application method of the high-precision pulse width modulator supporting adaptive calibration according to claim 5, characterized in that: The steps include: S1, read the edge mode bit EDGMODE of the configuration register HRCNFG through the PWM register module to see if the high-precision PWM waveform output function is disabled. If the high-precision PWM waveform output function is not disabled, jump to step S2; otherwise, directly output the ordinary PWM waveform, end and exit; S2, determining the output mode of the high-precision PWM waveform according to the control mode bit CTLMODE of the configuration register HRCNFG. If the output mode of the high-precision PWM waveform is the duty cycle control mode, selecting the duty cycle extension register CMPAHR to provide a delay unit selection signal under the duty cycle control mode; If the output mode of the high-precision PWM waveform is the phase control mode, the phase expansion register TBPHSHR is selected to provide a delay unit selection signal in the phase control mode; S3, performing delay and calibration processing through the delay and calibration unit, including: delaying the input common PWM waveform through the N-1 level delay unit in the delay line (1), and selecting one path from the N-path inputs through the first selector (2) and the second selector (3) in combination with the mapping mode bit HRLOAD and the delay unit selection signal to obtain a high-precision PWM waveform output; calibrating the high-precision PWM waveform output by the second selector (3) and the input common PWM waveform through the calibration module (4) in combination with the edge detection mode configured by the edge mode bit EDGMODE to generate an actual calibration value representing the number of delay unit levels required for the current delay of one clock cycle and writing it into the calibration register HRREF until the actual calibration value is stable; S4, responding to the user's read request through the PWM register module, and returning the actual calibration value written into the calibration register HRREF, which represents the number of delay unit stages required for the current delay of one clock cycle.

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