Low-power integrator for continuous-time delta-sigma analog-to-digital converter

Abstract

The invention relates to a low-power integrator for a continuous-time delta-sigma analog-to-digital converter. The integrator for the continuous time delta sigma analog-to-digital converter comprises a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, an operational transconductance amplifier, a first capacitor, a second capacitor and a third capacitor. According to the integrator disclosed by the embodiment of the invention, the first capacitor or the second capacitor is utilized by turns to directly dump the integral charge formed by accumulating the input current within a certain time length to the third capacitor of the integrator by controlling the on and off of the first to eighth switches; the integration is realized through charge sharing of the first capacitor or the second capacitor and the third capacitor, the operation transconductance amplifier does not need to provide large current to charge the integrating capacitor, the requirement for a high-performance active device is reduced, the power consumption of the integrator is reduced, and the power consumption of the continuous time delta sigma analog-to-digital converter is further reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic technology, and in particular to a low-power integrator for a continuous-time ΔΣ analog-to-digital converter. Background Art

[0002] Continuous-Time Delta-Sigma Analog to Digital Converter (CTΔΣADC) is easy to drive, consumes less power than Discrete-Time Delta-Sigma Analog to Digital Converter (DTΔΣADC), and has built-in anti-aliasing function. Therefore, broadband continuous-time ΔΣ analog to digital converters are widely used in communication systems. Figure 1 FIG. 4 is a circuit diagram showing two commonly used integrators for continuous-time ΔΣ analog-to-digital converters in the related art. Figure 1 As shown, the left part is the active RC integrator and the right part is G m -C integrator, where V IN Represents the input voltage of the integrator, V OUT represents the input voltage of the integrator, R INT Represents the input resistance, C INT represents the integrating capacitor, OTA represents the active device of the integrator, Operational Transconductance Amplifier (OTA), G m is the transconductance of the operational transconductance amplifier OTA. The integrator in the related art needs to rely on the active device operational transconductance amplifier OTA to complete the integration, and the operational transconductance amplifier OTA provides current to the integration capacitor C INT For charging, the operational transconductance amplifier OTA involved in integration needs to consume higher power consumption, especially when the input of the operational transconductance amplifier OTA is a broadband signal, it will consume higher power consumption. Summary of the invention

[0003] In view of this, the present disclosure proposes a low power integrator for a continuous-time ΔΣ analog-to-digital converter.

[0004] According to one aspect of the present disclosure, an integrator is provided, the integrator comprising a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, an operational transconductance amplifier, a first capacitor, a second capacitor, and a third capacitor, wherein a first end of the first switch is connected to a first end of the seventh switch as an input end of the integrator for receiving an input current, a second end of the first switch and a first end of the fifth switch are connected to a first end of the first capacitor, a second end of the first capacitor and a first end of the sixth switch are connected to a first end of the second switch, a second end of the second switch is used to receive a first voltage, and the sixth switch The second end of the third switch, the first end of the third capacitor, and the first end of the fourth switch are connected to the inverting input terminal of the operational transconductance amplifier, the non-inverting input terminal of the operational transconductance amplifier is connected to the input common mode voltage, the second end of the third capacitor, the second end of the fifth switch, and the first end of the third switch are connected to the non-inverting output terminal of the operational transconductance amplifier as the output terminal of the integrator for providing an output voltage, the second end of the third switch and the second end of the seventh switch are connected to the first end of the second capacitor, the second end of the second capacitor and the second end of the fourth switch are connected to the first end of the eighth switch, and the second end of the eighth switch is used to receive a second voltage.

[0005] In a possible implementation, the first switch, the second switch, the third switch, and the fourth switch receive a first switch control signal, and in response to the first switch control signal being a first level, the first switch, the second switch, the third switch, and the fourth switch are closed; in response to the first switch control signal being a second level, the first switch, the second switch, the third switch, and the fourth switch are opened; the fifth switch, the sixth switch, the seventh switch, and the eighth switch receive a second switch control signal, and in response to the second switch control signal being a first level, the fifth switch, the sixth switch, the seventh switch, and the eighth switch are closed; in response to the second switch control signal being a second level, the fifth switch, the sixth switch, the seventh switch, and the eighth switch are opened; wherein the first switch control signal and the second switch control signal are non-overlapping signals.

[0006] In a possible implementation, in response to the first switch control signal changing from the first level to the second level and the second switch control signal changing from the second level to the first level, the first capacitor and the third capacitor are connected in parallel to form an integrating capacitor with a total capacitance value of a preset value, the charge accumulated in the first capacitor and the charge on the third capacitor together constitute the charge amount of the integrating capacitor (that is, the charge accumulated in the first capacitor and the existing charge on the third capacitor together constitute the charge amount that should be on the integrating capacitor when the second switch control signal changes from the second level to the first level), and the charge carried by the input current of the integrator begins to accumulate on the second capacitor; in response to the first switch control signal changing from the second level to the first level and the second switch control signal changing from the first level to the second level, the second capacitor and the third capacitor are connected in parallel to form an integrating capacitor with a total capacitance value of a preset value, the charge accumulated in the second capacitor and the charge on the third capacitor together constitute the charge amount of the integrating capacitor (that is, the charge accumulated in the second capacitor and the existing charge on the third capacitor together constitute the charge amount that should be on the integrating capacitor when the first switch control signal changes from the second level to the first level), and the charge carried by the input current of the integrator begins to accumulate on the first capacitor.

[0007] In a possible implementation, the integrator also includes a compensation circuit, which is used to compensate for part of the integrated charge carried away when the parallel connection between the first capacitor or the second capacitor and the third capacitor is disconnected, and the compensation circuit includes a first sampling and holding circuit, a second sampling and holding circuit and the operational transconductance amplifier, the inverting output end of the operational transconductance amplifier is connected to the input end of the first sampling and holding circuit and the input end of the second sampling and holding circuit, the output end of the first sampling and holding circuit is connected to the second end of the second switch for providing the first voltage, and the output end of the second sampling and holding circuit is connected to the second end of the eighth switch for providing the second voltage.

[0008] In a possible implementation, each sampling and holding circuit includes a sampling switch, a sampling and holding capacitor, and a voltage buffer. The first end of the sampling switch serves as the input end of the sampling and holding circuit, the second end of the sampling switch and the first end of the sampling and holding capacitor are connected to the input end of the voltage buffer, the second end of the sampling and holding capacitor is connected to the output common-mode voltage of the operational transconductance amplifier, and the output end of the voltage buffer serves as the output end of the sampling and holding circuit.

[0009] In a possible implementation, in response to the first switch control signal changing from the first level to the second level and the second switch control signal changing from the second level to the first level, the first capacitor and the third capacitor are connected in parallel to form an integrating capacitor with a total capacitance value of a preset value, and the charge accumulated in the first capacitor and the charge on the third capacitor together constitute the charge amount of the integrating capacitor (that is, the charge amount that should be on the integrating capacitor when the second switch control signal changes from the second level to the first level), the second capacitor is disconnected from the parallel connection with the third capacitor and takes away part of the integrated charge, and the charge carried by the input current of the integrator and the loss charge compensated by the second voltage output by the second sampling and holding circuit begin to accumulate in the on the second capacitor; in response to the first switch control signal changing from the second level to the first level and the second switch control signal changing from the first level to the second level, the second capacitor and the third capacitor are connected in parallel to form an integrating capacitor with a total capacitance value of a preset value, the charge accumulated in the second capacitor and the charge on the third capacitor together constitute the charge amount of the integrating capacitor (that is, the charge amount that should be on the integrating capacitor when the first switch control signal changes from the second level to the first level), the first capacitor and the third capacitor are disconnected in parallel to take away part of the integrated charge, and the charge carried by the input current of the integrator and the loss charge compensated by the first voltage output by the first sampling and holding circuit begin to accumulate on the first capacitor.

[0010] In a possible implementation, the charge accumulated by the first capacitor includes the charge accumulated by the input current and the part of the integrated charge taken away by the second capacitor when the second switch control signal changes from the first level to the second level half a sampling clock period ago; the charge accumulated by the second capacitor includes the charge accumulated by the input current and the part of the integrated charge taken away by the first capacitor when the first switch control signal changes from the first level to the second level half a sampling clock period ago.

[0011] In a possible implementation manner, the first voltage and the second voltage are an input common mode voltage (signal ground) of the operational transconductance amplifier.

[0012] According to one aspect of the present disclosure, an analog-to-digital converter is provided, which includes a first resistor, a first current buffer, a second current buffer, a digital-to-analog converter, a quantizer, and an integrator as described above, wherein the first end of the first resistor is used to receive an analog voltage, the second end of the first resistor is connected to the input end of the first current buffer, the output end of the first current buffer is connected to the input end of the integrator and the output end of the second current buffer, the output end of the integrator is connected to the input end of the quantizer, the quantizer outputs the digital output of the analog-to-digital converter, and at the same time, the output end of the quantizer is connected to the control end of the digital-to-analog converter, and the output end of the digital-to-analog converter is connected to the input end of the second current buffer.

[0013] According to an aspect of the present disclosure, an electronic device is provided, wherein the electronic device includes the integrator as described above.

[0014] The integrator of the disclosed embodiment can control the opening and closing of the first switch to the eighth switch to realize the use of the first capacitor or the second capacitor in turn, and directly "dump" the integrated charge accumulated by the input current within a certain length of time onto the third capacitor of the integrator. Integration is achieved through charge sharing between the first capacitor or the second capacitor and the third capacitor. There is no need for an operational transconductance amplifier to provide a large current to charge the integration capacitor, which reduces the demand for high-performance (i.e., high-speed, high-gain) active devices, reduces the power consumption of the integrator, and thus helps to reduce the power consumption of the continuous-time ΔΣ analog-to-digital converter.

[0015] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0017] Figure 1 A circuit diagram of an integrator used in a continuous-time ΔΣ analog-to-digital converter in the related art is shown.

[0018] Figure 2 A circuit diagram of an integrator according to an embodiment of the present disclosure is shown.

[0019] Figure 3 A circuit diagram of an integrator with a compensation circuit according to an embodiment of the present disclosure is shown.

[0020] Figure 4A schematic diagram of a sample-and-hold circuit for compensation according to an embodiment of the present disclosure is shown.

[0021] Figure 5 A circuit diagram of an integrator without a compensation circuit according to an embodiment of the present disclosure is shown.

[0022] Figure 6 A circuit diagram of a continuous-time ΔΣ analog-to-digital converter using an integrator proposed in the present disclosure according to an embodiment of the present disclosure is shown.

[0023] Figure 7 A schematic diagram of a timing generation circuit according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0024] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0025] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0026] In the description of the present disclosure, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0027] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0028] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0029] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected between" two nodes, it may be directly coupled or connected to another element or there may be an intermediate element, and the connection between the elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0030] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0031] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0032] Figure 2 A circuit diagram of an integrator according to an embodiment of the present disclosure is shown. Figure 2 As shown, the integrator includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, an operational transconductance amplifier OTA, a first capacitor C ACC,A , the second capacitor C ACC,B , the third capacitor C FIX , wherein the first end of the first switch S1 is connected to the first end of the seventh switch S7 as the input end of the integrator for receiving the input current IIN The second end of the first switch S1, the first end of the fifth switch S5 and the first capacitor C ACC,A The first end of the first capacitor C ACC,A The second end of the sixth switch S6 is connected to the first end of the second switch S2, and the second end of the second switch S2 is used to receive the first voltage V S,A , the second end of the sixth switch S6, the third capacitor C FIX The first end of the fourth switch S4 is connected to the inverting input end of the operational transconductance amplifier OTA, the non-inverting input end of the operational transconductance amplifier OTA is connected to the input common mode voltage (also called: signal ground), the third capacitor C FIX The second end of the fifth switch S5, the second end of the third switch S3 and the in-phase output end of the operational transconductance amplifier OTA are connected as the output end of the integrator to provide an output voltage V OUT The second end of the third switch S3, the second end of the seventh switch S7 and the second capacitor C ACC,B The first end of the second capacitor C ACC,B The second end of the fourth switch S4 is connected to the first end of the eighth switch S8, and the second end of the eighth switch S8 is used to receive the second voltage V S,B .

[0033] The integrator of the disclosed embodiment can control the opening and closing of the first switch to the eighth switch to realize the use of the first capacitor or the second capacitor in turn, and directly "dump" the integrated charge accumulated by the input current within a certain length of time onto the third capacitor of the integrator. Integration is achieved through charge sharing between the first capacitor or the second capacitor and the third capacitor. There is no need for an operational transconductance amplifier to provide a large current to charge the integration capacitor, which reduces the demand for high-performance (i.e., high-speed, high-gain) active devices, reduces the power consumption of the integrator, and thus helps to reduce the power consumption of the continuous-time ΔΣ analog-to-digital converter.

[0034] In a possible implementation, the integrator may be at least one of a transistor-level integrated circuit and a printed circuit board, and the present disclosure does not limit the implementation form of the integrator.

[0035] In one possible implementation, the integrator can be applied to a continuous-time Delta-Sigma Analog to Digital Converter (CTΔΣADC) to perform integration processing on an unknown analog signal so as to convert it into a low quantization noise, digitally represented signal in combination with a quantizer and a feedback digital-to-analog converter.

[0036] In a possible implementation, the operational transconductance amplifier OTA of the integrator is a fully differential operational transconductance amplifier.

[0037] In a possible implementation, the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 can be an N-type channel metal-oxide semiconductor field effect transistor or a P-type channel metal-oxide semiconductor field effect transistor. Since the switching speed of the N-type channel metal-oxide semiconductor field effect transistor is higher than that of the P-type channel metal-oxide semiconductor field effect transistor, the N-type channel metal-oxide semiconductor field effect transistor is preferred. The control end of these switch transistors is the gate, the first end can be the source, and the second end can be the drain; or, the first end can be the drain, and the second end can be the source, and no specific distinction is made here. Further, in a specific implementation, the N-type switch tube is turned on under the action of a high-level signal and turned off under the action of a low-level signal. The P-type switch tube is turned off under the action of a high-level signal and turned on under the action of a low-level signal. It should be understood that the high-level signal and the low-level signal are logic levels, which are only used to better explain the specific working process of the embodiment of the present disclosure. The present disclosure does not limit the voltage applied to the gate of each transistor during the specific implementation.

[0038] In a possible implementation, the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 receive a first switch control signal Φ1, and in response to the first switch control signal Φ1 being at a first level (for example, a high level), the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are closed, and in response to the first switch control signal Φ1 being at a second level (for example, a low level), the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are opened;

[0039] The fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 receive a second switch control signal Φ2. In response to the second switch control signal Φ2 being at a first level (e.g., a high level), the fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 are closed. In response to the second switch control signal Φ2 being at a second level (e.g., a low level), the fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 are opened.

[0040] The first switch control signal Φ1 and the second switch control signal Φ2 are non-overlapping signals. The first switch control signal Φ1 and the second switch control signal Φ2 will not be at the first level (e.g., high level) at the same time, thereby avoiding potential conflicts or short circuits between switches, which is beneficial to improving the stability and safety of the integrator circuit.

[0041] By setting a non-overlapping first switch control signal Φ1 and a second switch control signal Φ2, the present disclosure sets the switch operation to a "ping-pong" working mode, that is, two-way time interleaving, thereby reducing aliasing caused by switching operations in the early stage of the loop filter, thereby reducing the power consumption of the integrator in the continuous-time ΔΣ analog-to-digital converter by using the technology proposed in the present disclosure without affecting the anti-aliasing function of the continuous-time ΔΣ analog-to-digital converter.

[0042] In a possible implementation, in response to the first switch control signal Φ1 changing from the first level to the second level and the second switch control signal Φ2 changing from the second level to the first level, the first capacitor C ACC,A The third capacitor C FIX The total capacitance value formed by parallel connection is the preset value C INT The integrating capacitor, the first capacitor C ACC,A The accumulated charge and the third capacitor C FIX The original charges on the capacitor together constitute the charge that should be on the equivalent integrating capacitor when the second switch control signal Φ2 changes from the second level to the first level. Here, the capacitance value of the equivalent integrating capacitor is C INT , the integrator input current I IN The charge carried begins to accumulate in the second capacitor C ACC,B superior;

[0043] In response to the first switch control signal Φ1 changing from the second level to the first level and the second switch control signal Φ2 changing from the first level to the second level, the second capacitor C ACC,B The third capacitor C FIX The total capacitance value formed by parallel connection is the preset value C INT The integrating capacitor, the second capacitor C ACC,B The accumulated charge and the third capacitor C FIX The original charges on the first switch control signal Φ1 together constitute the charge that should be on the equivalent integrating capacitor when the first switch control signal Φ1 changes from the second level to the first level. Here, the capacitance value of the equivalent integrating capacitor is C INT , the integrator input current I IN The charge carried begins to accumulate in the first capacitor C ACC,A .

[0044] In this way, the integrator input current I IN The accumulated integrated charge is directly “dumped” to the third capacitor C of the integrator. FIX On, through the first capacitor C ACC,A Or the second capacitor C ACC,B The charge sharing with the third capacitor realizes the integration of the input signal, and the process does not require the participation of the active device operational transconductance amplifier OTA. In order to avoid aliasing caused by the switching operation in the process, the "charge dumping" operation is performed in a "ping-pong" manner. Therefore, the integrator can reduce the power consumption of the integrator in the continuous-time ΔΣ analog-to-digital converter while maintaining the anti-aliasing function of the continuous-time ΔΣ analog-to-digital converter.

[0045] like Figure 2 As shown, I IN represents the input current of the integrator, OTA represents the fully differential operational transconductance amplifier, Gm is the transconductance of the operational transconductance amplifier OTA, and the first capacitor C ACC,A and the second capacitor C ACC,B To accommodate the input current I IN The accumulated charge within 0.5 sampling clock cycle, the capacitance values ​​of the two are equal, that is: C ACC,A =C ACC,B , C INT Represents the integrating capacitance value of the integrator, V OUT represents the output voltage of the integrator, the first switch control signal Φ1 and the second switch control signal Φ2 are non-overlapping clocks, and their period is the sampling clock period T of the continuous time ΔΣ analog-to-digital converter S , C ACC,A / B Represents the first capacitor C ACC,A and the second capacitor C ACC,B Capacitance value, V S,A Represents the first voltage, V S,B represents the second voltage.

[0046] Optionally, the specific operation process of the integrator is as follows:

[0047] When the first switch control signal Φ1 is at a first level (eg, a high level) and the second switch control signal Φ2 is at a second level (eg, a low level), the input current I IN The accumulated first capacitor C ACC,A At the same time, the second capacitor C ACC,B With the third capacitor C FIX Connect in parallel to form a total capacitance value of preset value C INT The integrating capacitor;

[0048] When the first switch control signal Φ1 changes from the first level (e.g., high level) to the second level (e.g., low level), and the second switch control signal Φ2 changes from the second level (e.g., low level) to the first level (e.g., high level), the first capacitor C ACC,A With the third capacitor C FIX The capacitance value formed by parallel connection is the preset value C INT The parallel operation makes the input current I IN In the 0.5 clock cycle before the current moment, the accumulated ACC,A The charge on the capacitor is “dumped” into the third capacitor C FIX The integrator completes the input current I IN The integration within 0.5 clock cycle, at the same time, the second capacitor C ACC,B Repeat the first capacitor C ACC,A The operation during the period when the first switch control signal Φ1 is at the first level (eg, high level), that is, the input current I IN The second capacitor C ACC,B Accumulate on.

[0049] When the first switch control signal Φ1 changes from the second level (e.g., low level) to the first level (e.g., high level), and the second switch control signal Φ2 changes from the first level (e.g., high level) to the second level (e.g., low level), the input current I IN The integrated value obtained within 0.5 clock cycle and deposited into the second capacitor C ACC,B The charge on the capacitor is dumped into the third capacitor C FIX The integrator completes the input current I IN The integration in the second 0.5 clock cycle shows that the input current I IN The integration within one sampling clock cycle is completed. After that, the above steps are repeated in sequence.

[0050] In this way, the first capacitor C ACC,A and the second capacitor C ACC,B In a "bing-pong" manner, two operations are performed: IN The accumulation of the input current I IN The accumulated charge is dumped into the third capacitor C FIX , so that the switching operation in the integrator does not introduce aliasing, which is beneficial to retaining the anti-aliasing advantage of the continuous-time ΔΣ analog-to-digital converter.

[0051] In the integrator of the present disclosure, the operational transconductance amplifier OTA does not participate in the input current I IN In the integrating capacitor (for example, the first capacitor C ACC,A With the third capacitor C FIXThe integrating capacitor formed in parallel, or the second capacitor C ACC,B With the third capacitor C FIX The integration capacitor formed by parallel connection) is integrated, that is, the operational transconductance amplifier OTA does not need to be like in Figure 1 As in the traditional integrator in INT Provide current to help it integrate, but through the first capacitor C ACC,A (or the second capacitor C ACC,B ) and the third capacitor C FIX The operational transconductance amplifier OTA only participates in compensating the first capacitor C ACC,A (or the second capacitor C ACC,B ) and the third capacitor C FIX The integrated charge is taken away when the parallel connection is disconnected; since the compensation does not require high precision, the operational transconductance amplifier OTA in the integrator has low power consumption. Therefore, the integrator of the embodiment of the present disclosure effectively reduces the power consumption of active devices in the active integrator of the continuous-time ΔΣ analog-to-digital converter.

[0052] like Figure 2 As shown, when the first capacitor C ACC,A (or the second capacitor C ACC,B ) and the third capacitor C FIX When the parallel connection is disconnected, the first capacitor C ACC,A (or the second capacitor C ACC,B ) will take away the third capacitor C FIX The partial integrated charge on the integrator leads to an integration loss of the integrator. In order to compensate for the integration loss, a compensation circuit can be set in the integrator.

[0053] Figure 3 FIG. 2 shows a circuit diagram of an integrator with a compensation circuit according to an embodiment of the present disclosure. Figure 3 As shown, the integrator also includes a compensation circuit, and the compensation circuit is used to compensate the first capacitor C ACC,A or the second capacitor C ACC,B The third capacitor C FIX The partial integrated charge taken away when the parallel connection is disconnected.

[0054] like Figure 3 As shown, the integrator includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, an operational transconductance amplifier OTA, a first capacitor C ACC,A , the second capacitor C ACC,B , the third capacitor C FIXThe integrator also includes a compensation circuit, which includes a first sample-and-hold circuit A, a second sample-and-hold circuit B and the operational transconductance amplifier OTA.

[0055] The first end of the first switch S1 is connected to the first end of the seventh switch S7 as the input end of the integrator for receiving the input current I IN The second end of the first switch S1, the first end of the fifth switch S5 and the first capacitor C ACC,A The first end of the first capacitor C ACC,A The second end of the sixth switch S6 and the first end of the sixth switch S6 are connected to the first end of the second switch S2, and the second end of the sixth switch S6 and the third capacitor C FIX The first end of the fourth switch S4 is connected to the inverting input end of the operational transconductance amplifier OTA, the non-inverting input end of the operational transconductance amplifier OTA is connected to the input common mode voltage (also called: signal ground) of the operational transconductance amplifier OTA, and the third capacitor C FIX The second end of the fifth switch S5, the second end of the third switch S3 and the in-phase output end of the operational transconductance amplifier OTA are connected as the output end of the integrator to provide an output voltage V OUT The inverting output terminal of the operational transconductance amplifier OTA is connected to the input terminal of the first sampling and holding circuit A and the input terminal of the second sampling and holding circuit B, and the output terminal of the first sampling and holding circuit A is connected to the second terminal of the second switch S2 for providing the first voltage V S,A The output end of the second sampling and holding circuit B is connected to the second end of the eighth switch S8 for providing the second voltage V S,B The second end of the third switch S3, the second end of the seventh switch S7 and the second capacitor C ACC,B The first end of the second capacitor C ACC,B The second end of the fourth switch S4, the second end of the fourth switch S4 and the first end of the eighth switch S8 are connected.

[0056] In a possible implementation, in response to the first switch control signal Φ1 changing from a first level (e.g., a high level) to a second level (e.g., a low level), and the second switch control signal Φ2 changing from a second level (e.g., a low level) to a first level (e.g., a high level), the first capacitor C ACC,A The third capacitor C FIX The total capacitance value formed by parallel connection is the preset value C INT The integrating capacitor, the first capacitor C ACC,A The accumulated charge and the third capacitor C FIXThe original charges on the capacitor together constitute the charge that should be on the equivalent integrating capacitor when the second switch control signal Φ2 changes from the second level to the first level. Here, the capacitance value of the equivalent integrating capacitor is C INT , the second capacitor C ACC,B The third capacitor C FIX The parallel connection is disconnected and takes away part of the integrated charge, and the input current I IN The charge carried by the second sampling and holding circuit B outputs a second voltage V S,B The lost charge starts to accumulate in the second capacitor C ACC,B wherein the first capacitor C ACC,A The accumulated charge includes the input current I IN The accumulated charge and the second switch control signal Φ2 half a sampling clock cycle ago change from the first level to the second level by the second capacitor C ACC,B the portion of the integrated charge taken away;

[0057] In response to the first switch control signal Φ1 changing from the second level (e.g., low level) to the first level (e.g., high level), and the second switch control signal Φ2 changing from the first level (e.g., high level) to the second level (e.g., low level), the second capacitor C ACC,B The third capacitor C FIX The total capacitance value formed by parallel connection is the preset value C INT The integrating capacitor, the second capacitor C ACC,B The accumulated charge and the third capacitor C FIX The original charges on the first switch control signal Φ1 together constitute the charge that should be on the equivalent integrating capacitor when the first switch control signal Φ1 changes from the second level to the first level. Here, the capacitance value of the equivalent integrating capacitor is C INT , the first capacitor C ACC,A The third capacitor C FIX The parallel connection is disconnected and takes away part of the integrated charge, and the input current I IN The charge carried by the first sampling and holding circuit A outputs a first voltage V S,A The charge that compensates for the loss begins to accumulate in the first capacitor C ACC,A ; Wherein, the second capacitor C ACC,B The accumulated charge includes the input current I IN The accumulated charge and the first switch control signal Φ1 half a sampling clock cycle ago are changed from the first level to the second level by the first capacitor C ACC,A The partial integrated charge taken away.

[0058] Below Figure 3 Taking the example of FIG. 1 as an example, the compensation technology of the embodiment of the present disclosure is described. Figure 3The circuits in the upper and lower red boxes together constitute the integration circuit of the embodiment of the present disclosure, and the two circuits work in a "ping-pong" manner.

[0059] like Figure 3 Taking the circuit in the red frame in the upper middle part as an example, the time when the second switch control signal Φ2 is converted from the first level (e.g., high level) to the second level (e.g., low level) is recorded as t sw , at this time, the output voltage of the integrator is V OUT (t sw ), therefore, the first capacitor C ACC,A The part of the integrated charge taken away from the integrating capacitor is C ACC,A *V OUT (t sw ). In order to ACC,A The partial integrated charge taken away is compensated at the falling edge of the second switch control signal Φ2, i.e., at time t sw , use the sample-and-hold circuit A to sample the inverting differential output of the operational transconductance amplifier OTA, that is: V OUT,N The voltage sampled is recorded as V OUT,N (t sw ), and in the next 0.5 clock cycles, that is: from time t sw Start until time t sw +0.5T S (Note: T S is the clock cycle), that is Figure 3 In the left timing diagram, during the period when the first switch control signal Φ1 is at the first level (eg, high level), Figure 3 The first capacitor C ACC,A The right plate is connected to the voltage V OUT,N (t sw ). Therefore, at time t sw +0.5T S ,Right now: Figure 3 In the timing diagram, when the first switch control signal Φ1 changes from the first level (e.g., high level) to the second level (e.g., low level), and the second switch control signal Φ2 changes from the second level (e.g., low level) to the first level (e.g., high level), the accumulated current in the first capacitor C ACC,A The charge on is: Q ACC =C ACC,A *(V AVE -V OUT,N (t SW )),in, In this calculation formula, the numerator is the SW At time t SW +0.5T sThe amount of charge generated by integrating the input current during this period; that is, the amount of charge generated by the input current I IN The accumulated current should be deposited on the integrating capacitor C INT The charge on ACC,0 =C ACC,A *V AVE , and at t sw At the moment the first capacitor C ACC,A The partial integrated charge taken away from the integrating capacitor is: Q LOSS =C ACC,A *V OUT (t sw ), due to V OUT and V OUT,N are the two differential output terminals of the fully differential operational transconductance amplifier OTA. Therefore, in terms of signal, V OUT =-V OUT，N , so, Q LOSS =C ACC,A *(-V OUT，N (t sw )). In order to compensate for the sw At the moment the first capacitor C ACC,A The partial integrated charge taken away from the integrating capacitor at t sw +0.5T S At this moment, the total amount should be deposited on the integrating capacitor C INT The charge on TOT =Q ACC,0 +Q LOSS =C ACC,A *V AVE +C ACC,A *(-V OUT，N (t sw ))=C ACC,A *(V AVE -V OUT，N (t sw )), the charge is also the first capacitor C ACC,A The right plate is connected to V OUT，N (t sw ) voltage value, in the time period [t sw ,t sw +0.5T S ]The first internal capacitor C ACC,A The total amount of charge accumulated on the

[0060] Therefore, using the above compensation method, the first capacitor C ACC,A (or the second capacitor C ACC,B ) can be obtained by inputting the current I IN The accumulated charges and their interaction with the third capacitor C FIXWhen the parallel connection is disconnected, part of the integrated charge carried away is deposited on the integrating capacitor, avoiding the first capacitor C ACC,A (or the second capacitor C ACC,B ) and the third capacitor C FIX The integral loss caused by taking away part of the integral charge when ending the parallel connection. Figure 3 The circuit in the red box in the lower middle part also uses the above charge compensation method, which will not be described here. Figure 3 The circuit in the red box in the upper half and the circuit in the red box in the lower half adopt a "ping-pong" operation, and the clock control signal of the lower half circuit has a phase difference of 180 degrees with the clock control signal of the upper half circuit.

[0061] In a possible implementation, each sampling and holding circuit includes a sampling switch, a sampling and holding capacitor, and a voltage buffer. The first end of the sampling switch serves as the input end of the sampling and holding circuit, the second end of the sampling switch and the first end of the sampling and holding capacitor are connected to the input end of the voltage buffer, the second end of the sampling and holding capacitor is connected to the output common mode voltage (e.g., signal ground) of the operational transconductance amplifier, and the output end of the voltage buffer serves as the output end of the sampling and holding circuit.

[0062] Figure 4 A schematic diagram of a sample-and-hold circuit for compensation according to an embodiment of the present disclosure is shown. Figure 4 As shown, the first sampling and holding circuit A includes a sampling switch SW C,A , sampling and holding capacitor C H,A 、Voltage buffer B A , the sampling switch SW C,A The first end of the sampling switch SW is used as the input end of the first sampling and holding circuit A. C,A The second end of the sampling and holding capacitor C H,A The first end of the voltage buffer B A The input terminal is connected to the sampling and holding capacitor C H,A The second terminal is connected to the output common mode voltage of the operational transconductance amplifier, and the voltage buffer B A The output end of is used as the output end of the first sampling and holding circuit A.

[0063] The second sample-and-hold circuit B includes a sampling switch SW C,B , sampling and holding capacitor C H,B 、Voltage buffer B B , the sampling switch SW C,B The first end of the sampling switch SW is used as the input end of the second sampling and holding circuit B. C,B The second end of the sampling and holding capacitor C H,BThe first end of the voltage buffer B B The input terminal is connected to the sampling and holding capacitor C H,B The second terminal is connected to the output common mode voltage of the operational transconductance amplifier, and the voltage buffer B B The output end of is used as the output end of the second sampling and holding circuit B.

[0064] It should be understood that Figure 4 The example shown is only an example of the sampling and holding circuit of the embodiment of the present disclosure. At any time when the second switch control signal Φ2 falls, that is, at time t sw , the inverting output voltage V of the differential output terminal of the operational transconductance amplifier OTA can be OUT,N Any circuit that performs sampling and holding can be used as the sampling and holding circuit A. Any circuit that performs sampling and holding can be used at the falling edge of the first switch control signal Φ1, that is, at time t sw +0.5T S , the inverting output voltage V of the differential output terminal of the operational transconductance amplifier OTA can be OUT,N Any circuit that performs sampling and holding can be used as the sampling and holding circuit B. The embodiments of the present disclosure do not limit the specific form of the sampling and holding circuit.

[0065] By setting a sampling and holding circuit, the first capacitor C ACC,A (or the second capacitor C ACC,B ) and the third capacitor C FIX The parallel connection is disconnected when the third capacitor C is taken away FIX To compensate for the partial integrated charge on the sample-hold capacitor C, the operational transconductance amplifier OTA only needs to H,A or C H，B The charging is used for compensation operation, and the accuracy required for compensation operation is lower than that required by the entire integrator. Therefore, the power consumption of the operational transconductance amplifier OTA is much lower than Figure 1 Figure 2 shows the power consumption of OTA in a conventional active continuous-time integrator.

[0066] In a possible implementation, when the first capacitor C ACC,A (or the second capacitor C ACC,B ) is much smaller than the capacitance of the integrating capacitor C INT (In this case, the first capacitor C ACC,A Or the second capacitor C ACC,B With the third capacitor C FIX After the parallel connection is disconnected, the first capacitor C ACC,A Or the second capacitor C ACC,B The integrated charge carried away is much smaller than the total integrated charge), or the analog-to-digital conversion accuracy requirement is not high and the first capacitor C can be tolerated. ACC,A (or the second capacitor CACC,B ) When leaving the integral capacitor, there is no need to take away the charge and cause the integral loss. ACC,A (or the second capacitor C ACC,B ) is used to compensate for the charge taken away when it leaves the integrating capacitor. For this situation where there is no need for compensation, Figure 2 The first voltage V S,A and the second voltage V S,B Connect directly to the input common-mode voltage (also known as signal ground) of the operational transconductance amplifier OTA.

[0067] Figure 5 A circuit diagram of an integrator without a compensation circuit according to an embodiment of the present disclosure is shown. Figure 5 As shown, the first end of the first switch S1 is connected to the first end of the seventh switch S7 as the input end of the integrator for receiving the input current I IN The second end of the first switch S1, the first end of the fifth switch S5 and the first capacitor C ACC,A The first end of the first capacitor C ACC,A The second end of the sixth switch S6 and the first end of the sixth switch S6 are connected to the first end of the second switch S2, the second end of the second switch S2 is connected to the input common mode voltage of the operational transconductance amplifier OTA (that is, the signal ground), the second end of the sixth switch S6 and the third capacitor C FIX The first end of the fourth switch S4 is connected to the inverting input end of the operational transconductance amplifier OTA, the non-inverting input end of the operational transconductance amplifier OTA is connected to the input common mode voltage of the operational transconductance amplifier OTA, and the third capacitor C FIX The second end of the fifth switch S5, the second end of the third switch S3 and the in-phase output end of the operational transconductance amplifier OTA are connected as the output end of the integrator to provide an output voltage V OUT , the inverting output terminal of the operational transconductance amplifier OTA provides a reverse output voltage V OUT,N , where V OUT =-V OUT,N The second end of the third switch S3, the second end of the seventh switch S7 and the second capacitor C ACC,B The first end of the second capacitor C ACC,B The second end of the fourth switch S4 and the first end of the eighth switch S8 are connected, and the second end of the eighth switch S8 is connected to the input common mode voltage (ie, signal ground) of the operational transconductance amplifier OTA.

[0068] Figure 6FIG. 1 shows a circuit diagram of a continuous-time ΔΣ analog-to-digital converter using an integrator proposed in the present disclosure according to an embodiment of the present disclosure, that is, a circuit diagram of a continuous-time ΔΣ analog-to-digital converter using an integrator of the present disclosure, as shown in FIG. Figure 6 As shown, the analog-to-digital converter includes a first resistor R IN , a first current buffer buffer1, a second current buffer buffer2, a 1-bit resistive digital to analog converter RDAC (Resistive Digital to Analog Converter), a 1-bit quantizer (ie: 1-bit quantizer), and the integrator as described above, wherein the first resistor R IN The first end is used to receive the input analog voltage V IN,ADC , the first resistor R IN The second end of is connected to the input end of the first current buffer buffer1, the output end of the first current buffer buffer1 is connected to the input end of the integrator and the output end of the second current buffer buffer2, the output end of the integrator is connected to the input end of the quantizer, the output end of the quantizer outputs the digital output of the analog-to-digital converter, and at the same time, the output end of the quantizer is connected to the control end of the resistance-type digital-to-analog converter RDAC, and the output end of the resistance-type digital-to-analog converter RDAC is connected to the input end of the second current buffer buffer2. The 1-bit resistance-type digital-to-analog converter RDAC may include a resistor R FB and two switches.

[0069] Optionally, the first current buffer buffer1 includes two metal-oxide semiconductor field effect transistors (MOSFET), namely: transistor M 1 and transistor M 2 (Transistor M 1 For N-type MOSFET, transistor M 2 is a P-type MOSFET), and three current sources. Among them, the current size is 2I B The current source 2I B The first terminal is connected to the supply voltage, the current source 2I B The second end of transistor M 1 The drain of transistor M 2 The source of transistor M is connected 1 The gate is used to receive the corresponding bias voltage V B1 , transistor M 2 The gate is used to receive the corresponding bias voltage V B2 , transistor M 1 The source of the current source I B ( Figure 6The first end of the current source on the left side of the first current buffer buffer1 is used as the input end of the first current buffer buffer1, and the transistor M 2 The drain of the device is connected to a current source I B ( Figure 6 The first end of the current source on the right side of the first current buffer buffer1 is used as the output end of the first current buffer buffer1, Figure 6 The two current sources I on the left and right sides of the first current buffer buffer1 B The second end of each is connected to a negative supply voltage, usually a ground with a potential of 0V.

[0070] Optionally, the second current buffer buffer2 also includes two MOSFETs, namely: transistor M 3 and transistor M 4 (Transistor M 3 For P-type MOSFET, transistor M 4 is an N-type MOSFET), and three current sources. Among them, the current size is 2I BFB The current source 2I BFB The first terminal is connected to the supply voltage, the current source 2I BFB The second end of transistor M 3 The source of transistor M 4 The drain of transistor M 3 The gate is used to receive the corresponding bias voltage V B3 , transistor M 4 The gate is used to receive the corresponding bias voltage V B4 , transistor M 3 The drain connection current is I BFB The current source I BFB ( Figure 6 The first end of the current source on the left side of the second current buffer buffer2 is used as the output end of the second current buffer buffer2, and the transistor M 4 The source connection current is I BFB The current source I BFB ( Figure 6 The first end of the current source on the right side of the second current buffer buffer2 is used as the input end of the second current buffer buffer2, Figure 6 The two current sources I on the left and right sides of the second current buffer buffer2 BFB The second ends of the pins are connected to a negative supply voltage, usually a ground with a potential of 0V.

[0071] The four bias voltages V in the first current buffer buffer1 and the second current buffer buffer2 B1， V B2， VB3， V B4 The size of should be selected to ensure that the corresponding MOSFET operates in the saturation region.

[0072] Optionally, a 1-bit quantizer is a circuit that quantizes its input signal and outputs a 1-bit digital code (for example, 0 or 1), and may be composed of a comparator. The embodiments of the present disclosure do not limit the circuit structure of the 1-bit quantizer.

[0073] Optional, 1-bit resistor-based digital-to-analog converter RDAC FB The left end (first end) is connected to the transistor M in the second current buffer buffer2 4 The source of the common-gate transistor M working in the saturation region 4 The internal negative feedback makes R FB The first end sees an equivalent signal ground, and the control end of the 1-bit resistor digital-to-analog converter RDAC is connected to the output end of the 1-bit quantizer. If the control end of the 1-bit resistor digital-to-analog converter RDAC receives the digital signal 1 from the 1-bit quantizer, the reference voltage V REF+ Connecting to R FB The second end (ie: R FB If the control end of the 1-bit resistive digital-to-analog converter RDAC receives a digital signal 0 from the 1-bit quantizer, the reference voltage V REF- Connecting to R FB The second end (ie: R FB V REF+ is the positive reference voltage, V REF- It should be understood that the resistor-based digital-to-analog converter RDAC may also be a switched capacitor digital-to-analog converter or a current steering digital-to-analog converter, and the embodiments of the present disclosure do not limit the type of digital-to-analog converter.

[0074] like Figure 6 As shown, this embodiment is a 1st order, 1-bit continuous time ΔΣ analog-to-digital converter. Figure 6 The red dashed box in the middle is the integrator proposed in the embodiment of the present disclosure. The input analog voltage V IN,ADC Through the first resistor R IN Can be converted into input current I IN , through the first current buffer buffer1 based on the MOSFET common gate stage, the input current I IN Enter the integrator. The output voltage of this first-order integration is VOUT , at the sampling clock CK Q The rising edge of the integrator of the embodiment of the present disclosure can OUT The sample is sampled and quantized by a 1-bit quantizer. The quantization result is D OUT,ADC This is the output of the continuous-time ΔΣ analog-to-digital converter. OUT,ADC It also serves as the input of the feedback digital-to-analog converter DAC (Digital to Analog Converter).

[0075] In this embodiment, the digital-to-analog converter DAC can be a resistor-based digital-to-analog converter (RDAC), and the output current of the digital-to-analog converter enters the loop filter after passing through the second current buffer buffer2 based on the MOSFET common gate stage, and is combined with the input current I IN The residual current is obtained by subtraction and then enters the input end of the integrator. The subtraction operation of the two currents can be achieved by inverting the output current of the RDAC and then directly connecting it to the input current; and the inversion of the output current of the RDAC can be achieved by inverting the control signal, that is, if the control end of the 1-bit resistive digital-to-analog converter RDAC receives a digital signal 0 from a 1-bit quantizer, the reference voltage V REF+ Connecting to R FB The second end (ie: R FB If the control end of the 1-bit resistive digital-to-analog converter RDAC receives a digital signal 1 from a 1-bit quantizer, the reference voltage V REF- Connecting to R FB The second end (ie: R FB on the right side of the screen).

[0076] In a possible implementation, the two clock signals (i.e., the first switch control signal Φ1 and the second switch control signal Φ2) of the embodiment of the present disclosure are non-overlapping clocks, and their periods T S With sampling clock CK Q The cycle is the same, that is, the sampling clock CK Q The frequency is denoted as f Q , then T S =1 / f Q ; However, the phase of the first switch control signal Φ1 is earlier than the sampling clock π / 2 (ie: 90 degrees), and the phase of the second switch control signal Φ2 is later than the sampling clock π / 2 (ie: 90 degrees), such as Figure 6 The timing diagram on the left is shown.

[0077] In a possible implementation, a master clock may be used as input and then pass through a series of digital logic circuits to generate the timing control signals required in the embodiment of the present disclosure, namely, the first switch control signal Φ1 and the second switch control signal Φ2.

[0078] Figure 7 A schematic diagram of a timing generation circuit according to an embodiment of the present disclosure is shown. Figure 7 As shown, the timing generation circuit is used to generate a non-overlapping first switch control signal Φ1 and a second switch control signal Φ2, so as to control the order in which the switches in the integrator circuit are turned on or off, thereby realizing the timing control of the switches in the integrator circuit. Figure 7 It also shows Figure 6 The sampling clock CK of the quantizer in the embodiment of the present disclosure is shown as follows: Q Possible generation methods.

[0079] like Figure 7 As shown, the timing generation circuit includes a first D-type flip-flop D-FF1, a second D-type flip-flop D-FF2, a first inverter D1, a first NAND gate circuit NAND1, a second NAND gate circuit NAND2, 2N second inverters D2, 2N third inverters D3, a fourth inverter D4, a fifth inverter D5, and a sixth inverter D6, where N is an integer greater than or equal to 1;

[0080] The input end of the sixth inverter D6 is connected to the clock input end of the first D-type flip-flop D-FF1 for receiving the first clock signal CK 0 , the first clock signal CK 0 The frequency is twice the sampling frequency, that is: 2f SThe data input end of the first D-type flip-flop D-FF1 is connected to the inverting output end of the first D-type flip-flop D-FF1, the forward output end of the first D-type flip-flop D-FF1, the input end of the first inverter D1, and the second input end of the second NAND gate circuit NAND2 are connected, the output end of the first inverter D1 is connected to the first input end of the first NAND gate circuit NAND1, the output end of the first NAND gate circuit NAND1 is connected to the input end of 2N second inverters D2 connected in series, and the 2N second inverters D2 connected in series are connected. The output end of the fourth inverter D4 is connected to the input end of the fourth inverter D4 and the first input end of the second NAND gate circuit NAND2, the output end of the second NAND gate circuit NAND2 is connected to the input end of 2N third inverters D3 connected in series, the output end of the 2N third inverters D3 connected in series is connected to the input end of the fifth inverter D5 and the second input end of the first NAND gate circuit NAND1, the output end of the fourth inverter D4 is used to provide a first switch control signal Φ1, and the output end of the fifth inverter D5 is used to provide a second switch control signal Φ2;

[0081] The output end of the sixth inverter D6 is connected to the clock input end of the second D-type flip-flop D-FF2, the data input end of the second D-type flip-flop D-FF2 is connected to the inverting output end of the second D-type flip-flop D-FF2, and the positive output end of the second D-type flip-flop D-FF2 is used to provide a second clock signal CK Q , the second clock signal CK Q Available as Figure 6 The sampling clock of the quantizer, the second clock signal CK Q The frequency of the first clock signal CK 0 Half the frequency, that is: f S .

[0082] The number 2N of the second inverter D2 and the third inverter D3 connected in series is the same, N is an integer greater than or equal to 1, the larger the value of N, the longer the non-overlap time of the first switch control signal Φ1 and the second switch control signal Φ2; the smaller the value of N, the shorter the non-overlap time of the first switch control signal Φ1 and the second switch control signal Φ2. The present disclosure does not limit the specific value of N, which can be set according to the actual application scenario.

[0083] In a possible implementation, the timing generation circuit may be a controller (eg, a single chip microcomputer, a processor, etc.), which may generate timing control signals according to a preset program code, namely, a first switch control signal Φ1 and a second switch control signal Φ2.

[0084] The timing generation circuit for providing the first switch control signal Φ1 and the second switch control signal Φ2 for the integrator proposed in the present disclosure is not unique. The present disclosure does not limit the specific circuit structure for generating the first switch control signal Φ1 and the second switch control signal Φ2.

[0085] In summary, the integrator for the continuous-time ΔΣ analog-to-digital converter proposed in the present disclosure can convert the input current I IN Within a certain time period (e.g. 0.5T S ) The accumulated integrated charge is directly "dumped" onto the integrating capacitor of the integrator to realize passive integration of the signal. This process does not require the participation of the active device operational transconductance amplifier OTA; in addition, in order to avoid aliasing caused by the switching operation in this process, the "charge dumping" operation is performed in a "ping-pong" manner, thereby avoiding aliasing caused by switching operations in the early stage of the loop filter, thereby reducing the power consumption of the integrator in the continuous-time ΔΣ analog-to-digital converter without affecting the anti-aliasing function of the continuous-time ΔΣ analog-to-digital converter. Furthermore, a compensation circuit can also be set in the integrator. When the first capacitor C ACC,A (or the second capacitor C ACC,B ) and the third capacitor C FIX When the parallel connection is disconnected, the first capacitor C ACC,A (or the second capacitor C ACC,B ) is used to compensate for part of the integrated charge taken away by the integral capacitor (that is, the charge loss of the integral capacitor). Since the operational transconductance amplifier OTA only participates in the compensation operation and the accuracy required for the compensation operation is lower than the accuracy required for the entire integration operation, the power consumption of the operational transconductance amplifier OTA in the present disclosure is lower than that of the operational transconductance amplifier OTA in the traditional active integrator.

[0086] Since the integrator realizes integration through charge sharing and does not need the operational transconductance amplifier OTA to provide a large current to charge the integration capacitor; the operational transconductance amplifier OTA can participate in compensation in the integrator, and the compensation circuit can tolerate higher errors than the integration circuit. Therefore, the power consumption of the operational transconductance amplifier OTA used in the integrator proposed in the present invention is lower than the power consumption of the operational transconductance amplifier OTA in the active and continuous-time integrator in the related prior art. The power consumption of the operational transconductance amplifier OTA is the dominant component of the power consumption of the active and continuous-time integrator. Therefore, the power consumption of the integrator in the embodiment of the present invention is lower than the power consumption of the continuous-time integrator in the related technology.

[0087] The integrator of the present disclosure is used for a broadband continuous-time ΔΣ analog-to-digital converter, considering that the broadband continuous-time ΔΣ analog-to-digital converter tends to be designed using advanced CMOS processes, and in advanced CMOS processes, it is difficult to design a high-gain operational transconductance amplifier OTA, but the advanced CMOS process is conducive to the realization of high-speed switching. If the broadband continuous-time ΔΣ analog-to-digital converter uses a conventional active integrator, the operational transconductance amplifier OTA therein needs to have a high gain-bandwidth product, and the realization of a high-speed operational transconductance amplifier OTA requires high power consumption. The integrator proposed in the present disclosure makes full use of the advantages of advanced CMOS processes that are conducive to the realization of high-speed switching, and realizes "passive" integration without integral loss through the passive method of "charge dumping", avoiding the need for high-performance (i.e.: high-speed, high-gain) active devices, reducing the power consumption of the integrator, and thus helping to reduce the power consumption of the entire broadband continuous-time ΔΣ analog-to-digital converter.

[0088] In terms of application, the broadband continuous-time ΔΣ analog-to-digital converter can be used in portable communication devices; if the integrator proposed in the present disclosure is applied to the broadband continuous-time ΔΣ analog-to-digital converter in such portable communication devices, the integrator can significantly reduce the power consumption of the broadband continuous-time ΔΣ analog-to-digital converter, which is beneficial to extend the usage time of such portable communication devices after each charge.

[0089] It should be understood that for the sake of simplicity and clarity, the figures only show single-ended circuit implementations; however, the present technology is also applicable to differential circuits.

[0090] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, rather than limiting the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of the present disclosure with reference to the accompanying drawings.

[0091] It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not repeat them. It can be understood by those skilled in the art that in the above-mentioned method of the specific implementation method, the specific execution order of each step should be determined according to its function and possible internal logic.

[0092] The disclosed embodiment also provides an electronic device, which includes the integrator circuit for the continuous-time ΔΣ analog-to-digital converter as described above.

[0093] The electronic device may be provided as a terminal, a server or other form of device. Among them, the terminal device may be a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, etc.

[0094] The above description of various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced to each other, and for the sake of brevity, they will not be repeated herein.

[0095] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0096] If the technical solution of this application involves personal information, the product using the technical solution of this application has clearly informed the personal information processing rules and obtained the individual's voluntary consent before processing the personal information. If the technical solution of this application involves sensitive personal information, the product using the technical solution of this application has obtained the individual's separate consent before processing the sensitive personal information, and at the same time meets the "explicit consent" requirement. For example, on personal information collection devices such as cameras, clear and prominent signs are set to inform that the personal information collection scope has been entered and personal information will be collected. If the individual voluntarily enters the collection scope, it is deemed that he or she agrees to the collection of his or her personal information; or on the device that processes personal information, the personal information processing rules are notified by obvious signs / information, and the individual's authorization is obtained through pop-up information or by asking the individual to upload his or her personal information; among them, the personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the type of personal information processed.

[0097] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. An integrator, characterized in that: The integrator includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, an operational transconductance amplifier, a first capacitor, a second capacitor, and a third capacitor, wherein: The first end of the first switch is connected to the first end of the seventh switch as the input end of the integrator for receiving the input current, the second end of the first switch and the first end of the fifth switch are connected to the first end of the first capacitor, the second end of the first capacitor and the first end of the sixth switch are connected to the first end of the second switch, the second end of the second switch is used to receive the first voltage, the second end of the sixth switch, the first end of the third capacitor and the first end of the fourth switch are connected to the inverting input end of the operational transconductance amplifier, the non-inverting input end of the operational transconductance amplifier is connected to the input common mode voltage, the second end of the third capacitor, the second end of the fifth switch and the first end of the third switch are connected to the non-inverting output end of the operational transconductance amplifier as the output end of the integrator for providing the output voltage, the second end of the third switch and the second end of the seventh switch are connected to the first end of the second capacitor, the second end of the second capacitor and the second end of the fourth switch are connected to the first end of the eighth switch, and the second end of the eighth switch is used to receive the second voltage.

2. The integrator according to claim 1, characterized in that The first switch, the second switch, the third switch, and the fourth switch receive a first switch control signal, and in response to the first switch control signal being at a first level, the first switch, the second switch, the third switch, and the fourth switch are closed; In response to the first switch control signal being at a second level, the first switch, the second switch, the third switch, and the fourth switch are turned off; The fifth switch, the sixth switch, the seventh switch, and the eighth switch receive a second switch control signal, and in response to the second switch control signal being at a first level, the fifth switch, the sixth switch, the seventh switch, and the eighth switch are closed; In response to the second switch control signal being at a second level, the fifth switch, the sixth switch, the seventh switch, and the eighth switch are turned off; The first switch control signal and the second switch control signal are non-overlapping signals.

3. The integrator according to claim 2, characterized in that In response to the first switch control signal changing from the first level to the second level and the second switch control signal changing from the second level to the first level, the first capacitor and the third capacitor are connected in parallel to form an integrating capacitor with a total capacitance of a preset value, the charge accumulated in the first capacitor and the charge on the third capacitor together constitute the charge amount of the integrating capacitor, and the charge carried by the input current of the integrator begins to accumulate on the second capacitor; In response to the first switch control signal changing from the second level to the first level and the second switch control signal changing from the first level to the second level, the second capacitor and the third capacitor are connected in parallel to form an integrating capacitor with a total capacitance value of a preset value, the charge accumulated in the second capacitor and the charge on the third capacitor together constitute the charge amount of the integrating capacitor, and the charge carried by the input current of the integrator begins to accumulate in the first capacitor.

4. The integrator according to any one of claims 1 to 3, characterized in that The integrator further includes a compensation circuit, which is used to compensate for part of the integrated charge taken away when the parallel connection between the first capacitor or the second capacitor and the third capacitor is disconnected, and the compensation circuit includes a first sample-and-hold circuit, a second sample-and-hold circuit and the operational transconductance amplifier. The inverting output terminal of the operational transconductance amplifier is connected to the input terminal of the first sampling and holding circuit and the input terminal of the second sampling and holding circuit, the output terminal of the first sampling and holding circuit is connected to the second terminal of the second switch for providing the first voltage, and the output terminal of the second sampling and holding circuit is connected to the second terminal of the eighth switch for providing the second voltage.

5. The integrator according to claim 4, characterized in that Each sample-and-hold circuit includes a sampling switch, a sample-and-hold capacitor, and a voltage buffer. The first end of the sampling switch serves as the input end of the sampling and holding circuit, the second end of the sampling switch and the first end of the sampling and holding capacitor are connected to the input end of the voltage buffer, the second end of the sampling and holding capacitor is connected to the output common mode voltage of the operational transconductance amplifier, and the output end of the voltage buffer serves as the output end of the sampling and holding circuit.

6. The integrator according to claim 4, characterized in that In response to the first switch control signal changing from the first level to the second level and the second switch control signal changing from the second level to the first level, the first capacitor and the third capacitor are connected in parallel to form an integrating capacitor with a total capacitance value of a preset value, the charge accumulated in the first capacitor and the charge on the third capacitor together constitute the charge amount of the integrating capacitor, the second capacitor is disconnected from the parallel connection with the third capacitor to take away part of the integrated charge, and the charge carried by the input current of the integrator and the loss charge compensated by the second voltage output by the second sampling and holding circuit begin to accumulate on the second capacitor; In response to the first switch control signal changing from the second level to the first level and the second switch control signal changing from the first level to the second level, the second capacitor and the third capacitor are connected in parallel to form an integrating capacitor with a total capacitance value of a preset value, the charge accumulated in the second capacitor and the charge on the third capacitor together constitute the charge amount of the integrating capacitor, the first capacitor and the third capacitor are disconnected in parallel to take away part of the integrated charge, and the charge carried by the input current of the integrator and the loss charge compensated by the first voltage output by the first sampling and holding circuit begin to accumulate in the first capacitor.

7. The integrator according to claim 6, characterized in that The charge accumulated by the first capacitor includes the charge accumulated by the input current and the part of the integrated charge taken away by the second capacitor when the second switch control signal changes from the first level to the second level half a sampling clock period ago; The charge accumulated in the second capacitor includes the charge accumulated by the input current and the part of the integrated charge taken away by the first capacitor when the first switch control signal changes from the first level to the second level half a sampling clock period ago.

8. The integrator according to any one of claims 1 to 3, characterized in that The first voltage and the second voltage are input common mode voltages of the operational transconductance amplifier.

9. An analog-to-digital converter, characterized in that: The analog-to-digital converter comprises a first resistor, a first current buffer, a second current buffer, a digital-to-analog converter, a quantizer, and an integrator as claimed in any one of claims 1 to 8, The first end of the first resistor is used to receive an analog voltage, the second end of the first resistor is connected to the input end of the first current buffer, the output end of the first current buffer is connected to the input end of the integrator and the output end of the second current buffer, the output end of the integrator is connected to the input end of the quantizer, and the output end of the quantizer outputs the digital output of the analog-to-digital converter. At the same time, the output end of the quantizer is connected to the control end of the digital-to-analog converter, and the output end of the digital-to-analog converter is connected to the input end of the second current buffer.

10. An electronic device, characterized in that: The electronic device comprises an integrator as claimed in any one of claims 1 to 8.

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