Data identification and latch reconstruction control method and circuit, LED driving chip and lamp strip

Abstract

The invention provides a data identification and latch reconstruction control method and circuit, an LED driving chip and a lamp strip, and the data identification and latch reconstruction control method comprises the steps: carrying out the rising edge detection of an input signal, enabling a clock oscillator when the rising edge of the input signal is detected, and enabling the clock oscillator to generate a clock signal; identifying the validity of the input signal by means of the clock signal to determine whether the input signal is an invalid data signal or a valid data signal; and when the input signal is a valid data signal, performing data '0' code or data '1' code judgment on the valid data signal, and performing data sampling latching and data reconstruction control on the valid data signal according to a judgment result. According to the invention, the problem that interference signals and abnormal signals on a data line cannot be discriminated when an existing LED driving chip carries out data transmission is solved.

Description

Technical Field

[0001] The present invention relates to the field of LED driving technology, and in particular to a data identification and latch reconstruction control method, circuit, LED driving chip and light strip. Background Art

[0002] The existing mainstream LED color light driving solution mainly uses the single-line return-to-zero code transmission protocol for data transmission. After receiving the single-line return-to-zero code data, each LED driver chip will intercept and save the header data in the data frame to light up the LED driven by this LED driver chip, and then forward the remaining data to the next LED driver chip on the cascade line.

[0003] However, the data latch reconstruction control circuit inside the current LED driver chip lacks the function of identifying interference signals and abnormal signals on the data line. Once the data line is interfered with and a spike glitch signal (i.e., interference signal) appears, or the controller mistakenly sends an abnormal narrow pulse signal (i.e., abnormal signal), the data latch reconstruction control circuit will identify these spike glitch signals or narrow pulse signals as one bit of data, and perform data latching and data waveform reconstruction on them to drive the LED at this level or the next level, thereby causing these erroneous signals to be transmitted on the entire cascaded LED light strip data link, resulting in display errors on the entire LED light strip. Summary of the invention

[0004] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a data recognition and latch reconstruction control method, circuit, LED driver chip and light strip, which are used to solve the problem that the existing LED driver chip cannot identify interference signals and abnormal signals on the data line during data transmission.

[0005] To achieve the above objectives and other related objectives, the present invention provides a data identification and latch reconstruction control method, comprising:

[0006] Performing rising edge detection on an input signal, and enabling a clock oscillator when a rising edge of the input signal is detected, the clock oscillator starts and generates a clock signal;

[0007] Performing validity identification on the input signal by means of the clock signal to determine whether the input signal is an invalid data signal or a valid data signal;

[0008] When the input signal is the valid data signal, a data "0" code or a data "1" code is determined for the valid data signal, and data sampling, latching and data reconstruction control are performed on the valid data signal according to the determination result.

[0009] Optionally, the method for identifying the validity of an input signal by means of a clock signal includes:

[0010] Recording the first edge change moment of the clock signal as a first edge change moment, and detecting the level of the input signal at the first edge change moment;

[0011] If the level of the input signal at the first edge change moment is a low level, the input signal is determined to be the invalid data signal; otherwise, the input signal is determined to be the valid data signal.

[0012] Optionally, the second edge change moment of the clock signal is recorded as the second edge change moment; when the input signal is determined to be the invalid data signal, the generation of the reconstructed data signal is prohibited at the first edge change moment, and the clock oscillator is stopped at the second edge change moment to prohibit the generation of the sampling control signal and the latch control signal.

[0013] Optionally, the method for determining whether a valid data signal is a data "0" code or a data "1" code includes:

[0014] Setting a sampling time according to the pulse width time of the data "0" code and the data "1" code, and detecting the level of the valid data signal at the sampling time;

[0015] If the level of the valid data signal at the sampling time is low, the valid data signal is determined to be a data "0" code; otherwise, the valid data signal is determined to be a data "1" code;

[0016] The first edge change moment of the clock signal is recorded as the first edge change moment, the second edge change moment of the clock signal is recorded as the second edge change moment, and the sampling moment is located after the second edge change moment.

[0017] Optionally, the method of performing data sampling, latching and data reconstruction control on the valid data signal according to the determination result includes:

[0018] When the input signal is the valid data signal, starting to generate a reconstructed data signal at the first edge change moment;

[0019] If it is determined that the valid data signal is a data "0" code, then: starting to generate a sampling control signal at the sampling time, starting to generate a latch control signal at the latch time, and stopping generating the reconstructed data signal according to the time of the falling edge of the valid data signal;

[0020] If it is determined that the valid data signal is a data "1" code, then: the sampling control signal starts to be generated at the sampling time, the latch control signal starts to be generated at the latching time, and the reconstructed data signal stops to be generated at the pre-binding time;

[0021] The latching time is after the sampling time, and the pre-locking time is after the sampling time.

[0022] Optionally, the method of stopping generating the reconstructed data signal according to the time at which the falling edge of the valid data signal occurs includes:

[0023] Setting an intermediate time between the second edge change time and the sampling time, and detecting the level of the valid data signal at the intermediate time;

[0024] If the level of the valid data signal at the intermediate moment is a low level, then: determining in advance that the valid data signal is a data "0" code, and stopping generating the reconstructed data signal at the intermediate moment;

[0025] If the level of the valid data signal at the intermediate moment is a high level, performing falling edge detection on the valid data signal between the intermediate moment and the sampling moment;

[0026] If a falling edge is detected, then: determining in advance that the valid data signal is a data "0" code, and stopping generating the reconstructed data signal at the time of the falling edge;

[0027] If no falling edge is detected, then: stopping generating the reconstructed data signal at the sampling time.

[0028] Optionally, an end time is set, and the clock oscillator is stopped at the end time; wherein the end time is the same as the pre-closing time or the end time is after the pre-closing time.

[0029] Optionally, the end moment is after the pre-closure moment, the intermediate moment differs from the second edge change moment by at least half a clock cycle, the sampling moment differs from the intermediate moment by at least half a clock cycle, the latching moment differs from the sampling moment by at least one clock cycle, the pre-closure moment differs from the latching moment by at least half a clock cycle, and the end moment differs from the pre-closure moment by at least half a clock cycle.

[0030] The present invention also provides a data identification and latch reconstruction control circuit, comprising an identification and latch reconstruction control module and a clock oscillator, wherein the identification and latch reconstruction control module executes the data identification and latch reconstruction control method as described above with the aid of the clock oscillator.

[0031] The present invention also provides an LED driving chip, comprising the data recognition and latch reconstruction control circuit as described above.

[0032] The present invention also provides an LED light strip, comprising the LED driving chip as described above.

[0033] As described above, the data identification and latch reconstruction control method, circuit, LED driver chip and light strip of the present invention can identify invalid data signals (such as spike glitch signals or narrow pulse signals, etc.) when these invalid data signals appear on the data line, and only perform data sampling, latching and data reconstruction and forwarding on valid data signals (such as single-line return-to-zero code data signals), thereby avoiding the transmission of invalid data signals on the LED light strip data link, ensuring the correctness of the data link transmission, and thus avoiding display errors of the LED light strip. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a flow chart of the data identification and latch reconstruction control method in the first embodiment.

[0035] Figure 2 Display as Figure 1 Specific flow chart.

[0036] Figure 3 It shows a timing diagram of invalid data signal transmission in the first embodiment.

[0037] Figure 4-Figure 7 The timing diagram of the effective data signal transmission in the first embodiment is shown, wherein: Figure 4-Figure 6 Different timing diagrams for data "0" code transmission. Figure 7 This is the timing diagram of data "1" code transmission.

[0038] Figure 8 The waveform diagram of the single-line return-to-zero code data signal in the first embodiment is shown.

[0039] Fig. 9 It is a schematic diagram showing the structure of the data recognition and latch reconstruction control circuit in the second embodiment.

[0040] Fig.10 It shows a schematic diagram of the structure of the LED driver chip in the third embodiment.

[0041] Fig.11 and Fig.12 Shown are schematic diagrams of different structures of the LED light strip in the fourth embodiment.

[0042] Component number description

[0043] 100 LED driver chip

[0044] 110 Data recognition and latch reconstruction control circuit

[0045] 111 Identify and latch reconstruction control module

[0046] 111a Identify and reconstruct control unit

[0047] 111b forwarding unit

[0048] 111c Sampling Unit

[0049] 111d Latch unit

[0050] 112 Clock Oscillator

[0051] 120 Controller

[0052] 130 LED drive circuit

[0053] 200 LED light strings DETAILED DESCRIPTION

[0054] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0055] See also Figures 1 to 12 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the form, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0056] Embodiment 1

[0057] like Figure 1 and Figure 2 As shown, this embodiment provides a data identification and latch reconstruction control method, including step S1, step S2 and step S3.

[0058] Step S1: Perform rising edge detection on an input signal, and enable a clock oscillator when a rising edge of the input signal is detected. The clock oscillator starts and generates a clock signal.

[0059] In this step, when the input signal has a rising edge, no matter whether the input signal is an invalid data signal or a valid data signal, the clock oscillator is enabled, so that the clock oscillator starts and generates a clock signal, such as Figure 3-Figure 7 As shown; wherein, the moment when the rising edge of the input signal is detected is recorded as the starting moment, that is, moment t0.

[0060] Step S2: Using the clock signal, the validity of the input signal is identified to determine whether the input signal is an invalid data signal or a valid data signal.

[0061] In fact, due to the influence of interference and controller abnormality, spike glitch signals caused by interference or narrow pulse signals caused by controller abnormality will appear on the data line. The spike glitch signals, narrow pulse signals and single-line return-to-zero code data signals can all be used as input signals, but the spike glitch signals and narrow pulse signals are invalid data signals, and the single-line return-to-zero code data signal is a valid data signal. By identifying the validity of the input signal, the spike glitch signals and narrow pulse signals can be identified, and only the single-line return-to-zero code data signal is used as a valid input.

[0062] Specifically, the method for identifying the validity of an input signal with the help of a clock signal includes the following steps: recording the first edge change moment of the clock signal as the first edge change moment, i.e., moment t1, detecting the level of the input signal at the first edge change moment (i.e., moment t1), and determining whether the input signal is an invalid data signal or a valid data signal based on the detection result, thereby identifying invalid data signals such as spike glitch signals and narrow pulse signals and shielding them.

[0063] If the level of the input signal at the first edge change moment (i.e., moment t1) is low, the input signal is determined to be an invalid data signal. Further, the second edge change moment of the clock signal is recorded as the second edge change moment, i.e., moment t2; when the input signal is determined to be an invalid data signal, the generation of the reconstructed data signal Data_out is prohibited at the first edge change moment (i.e., moment t1), and the clock oscillator is stopped at the second edge change moment (i.e., moment t2) so that the clock oscillator no longer generates a clock signal, so as to prohibit the generation of the sampling control signal Data_sample and the latch control signal Data_lock.

[0064] like Figure 3 As shown, at the first edge change moment (i.e., moment t1), the reconstructed data signal Data_out does not jump to a high level, but always remains at a low level; at the second edge change moment (i.e., moment t2), the clock oscillator is stopped to no longer generate a clock signal, and the sampling control signal Data_sample and the latch control signal Data_lock cannot jump to a high level, but always remain at a low level.

[0065] If the input signal is at a high level at the first edge change moment (i.e., moment t1), the input signal is determined to be a valid data signal. At this time, the valid data signal is determined to be a data "0" code or a data "1" code, and data sampling, latching, and data reconstruction control are performed on the valid data signal according to the determination result. During this process, the clock oscillator always remains enabled until the end moment, i.e., moment t7.

[0066] Step S3: When the input signal is a valid data signal, the valid data signal is judged as a data "0" code or a data "1" code, and data sampling, latching and data reconstruction control are performed on the valid data signal according to the judgment result.

[0067] When the input signal is determined to be a valid data signal, the reconstructed data signal Data_out is generated at the first edge change moment (ie, moment t1); Figure 4-Figure 7 As shown, the reconstructed data signal Data_out jumps to a high level at the first edge change moment (ie, moment t1).

[0068] Specifically, the method for determining whether a valid data signal is a data "0" code or a data "1" code includes the following steps: setting a sampling time, i.e., time t4, according to the pulse width time of the data "0" code and the data "1" code, and detecting the level of the valid data signal at the sampling time (i.e., time t4) to determine whether the valid data signal is a data "0" code or a data "1" code according to the detection result.

[0069] If the level of the valid data signal at the sampling time (i.e., time t4) is low, the valid data signal is determined to be a data "0" code; if the level of the valid data signal at the sampling time (i.e., time t4) is high, the valid data signal is determined to be a data "1" code. The sampling time (i.e., time t4) is after the second edge change time (i.e., time t2).

[0070] In fact, the pulse width time (i.e., high level duration) of the data "0" code and the data "1" code in the data cycle is a preset fixed value, which is determined by the specific application requirements; Figure 8 As shown, taking the pulse width time of the data "0" code in the data cycle as Tpulse_0 and the pulse width time of the data "1" code in the data cycle as Tpulse_1 as an example, usually, Tpulse_1≥1.5*Tpulse_0, such as Tpulse_0=300ns, Tpulse_1=600ns, etc.

[0071] When setting the sampling time (i.e., time t4), it should be ensured that the time period formed by the sampling time (i.e., time t4) and the start time (i.e., time t0) is greater than Tpulse_0 and less than Tpulse_1, that is, Tpulse_0<t4-t0<Tpulse_1, such as, t4-t0=(Tpulse_0+Tpulse_1) / 2; taking Tpulse_0=300ns and Tpulse_1=600ns as an example, t4-t0=450ns. Of course, it is also feasible to select other values ​​of t4-t0 between 300ns and 600ns, which has no substantial impact on this embodiment.

[0072] Specifically, the method for performing data sampling, latching and data reconstruction control on the valid data signal according to the determination result includes the following steps.

[0073] If the valid data signal is determined to be the data "0" code, then: the sampling control signal Data_sample is generated at the sampling time (i.e., time t4), the latching control signal Data_lock is generated at the latching time (i.e., time t5), and the reconstructed data signal Data_out is stopped at the time of the falling edge of the valid data signal; wherein, the latching time (i.e., time t5) is after the sampling time (i.e., time t4).

[0074] The method of stopping the generation of the reconstructed data signal Data_out according to the falling edge of the valid data signal comprises the following steps:

[0075] An intermediate time (i.e., time t3) is set between the second edge change time (i.e., time t2) and the sampling time (i.e., time t4), and the level of the valid data signal at the intermediate time (i.e., time t3) is detected;

[0076] If the level of the valid data signal at the intermediate moment (i.e., moment t3) is low, then: the valid data signal is determined to be the data "0" code in advance, that is, the valid data signal is directly determined to be the data "0" code according to the low level detected at the intermediate moment (i.e., moment t3), without the need to judge the data "0" code and the data "1" code at the sampling moment (i.e., moment t4), and the generation of the reconstructed data signal Data_out is stopped at the intermediate moment (i.e., moment t3), such as Figure 4 As shown; in this scheme, the reconstructed data signal Data_out jumps to a low level at the middle moment (i.e., moment t3), the sampling control signal Data_sample jumps to a high level at the sampling moment (i.e., moment t4), the latch control signal Data_lock jumps to a high level at the latching moment (i.e., moment t5), and the pulse width time (i.e., high level duration) of the reconstructed data "0" code Tpulse_0_R=t3-t1;

[0077] If the level of the valid data signal at the middle time (i.e., time t3) is high, the falling edge detection of the valid data signal is performed between the middle time (i.e., time t3) and the sampling time (i.e., time t4);

[0078] If a falling edge is detected, then: the valid data signal is determined to be the data "0" code in advance, that is, the valid data signal is directly determined to be the data "0" code according to the low level detected at the time of the falling edge (i.e., time t3_4), without the need to judge the data "0" code and the data "1" code at the sampling time (i.e., time t4), and the generation of the reconstructed data signal Data_out is stopped at the time of the falling edge (i.e., time t3_4), such as Figure 5As shown; in this scheme, the reconstructed data signal Data_out jumps to a low level at the falling edge moment (i.e., moment t3_4), the sampling control signal Data_sample jumps to a high level at the sampling moment (i.e., moment t4), and the latch control signal Data_lock jumps to a high level at the latching moment (i.e., moment t5), and the pulse width time (i.e., high level duration) of the reconstructed data "0" code Tpulse_0_R=t3_4-t1;

[0079] If no falling edge is detected, then: at the sampling time (i.e., time t4), the level of the valid data signal continues to be detected to determine the data "0" code and the data "1" code. When the level of the valid data signal at the sampling time (i.e., time t4) is low, the valid data signal is determined to be the data "0" code, and the generation of the reconstructed data signal Data_out is stopped at the sampling time (i.e., time t4). Figure 6 As shown; in this scheme, the reconstructed data signal Data_out jumps to a low level at the sampling moment (i.e., moment t4), the sampling control signal Data_sample jumps to a high level at the sampling moment (i.e., moment t4), the latch control signal Data_lock jumps to a high level at the latching moment (i.e., moment t5), and the pulse width time (i.e., high level duration) of the reconstructed data "0" code Tpulse_0_R=t4-t1.

[0080] If the valid data signal is determined to be a data "1" code, then: the sampling control signal Data_sample is generated at the sampling time (i.e., time t4), the latch control signal Data_lock is generated at the latching time (i.e., time t5), and the reconstructed data signal Data_out is stopped at the pre-locking time (i.e., time t6). Figure 7 As shown; in this scheme, the sampling control signal Data_sample jumps to a high level at the sampling moment (i.e., moment t4), the latch control signal Data_lock jumps to a high level at the latching moment (i.e., moment t5), the reconstructed data signal Data_out jumps to a low level at the pre-closing moment (i.e., moment t6), and the pulse width time (i.e., high level duration) of the reconstructed data "1" code Tpulse_1_R=t6-t1. Among them, the pre-closing moment (i.e., moment t6) is located after the sampling moment (i.e., moment t4), and in this embodiment, the pre-closing moment (i.e., moment t6) is located after the latching moment (i.e., moment t5).

[0081] Further, an end time (i.e., time t7) is set, and the clock oscillator is stopped at the end time (i.e., time t7), so that the clock oscillator no longer generates a clock signal. At this time, the sampling control signal Data_sample and the latch control signal Data_lock are restored to the default level (e.g., low level), as shown in FIG. Figure 4-Figure 7As shown. The end time (i.e., time t7) and the pre-closing time (i.e., time t6) are the same time or the end time (i.e., time t7) is after the pre-closing time (i.e., time t6); in this embodiment, the end time (i.e., time t7) is after the pre-closing time (i.e., time t6).

[0082] As an optional scheme, the intermediate moment (i.e., moment t3) differs from the second edge change moment (i.e., moment t2) by at least half a clock cycle, the sampling moment (i.e., moment t4) differs from the intermediate moment (i.e., moment t3) by at least half a clock cycle, the latching moment (i.e., moment t5) differs from the sampling moment (i.e., moment t4) by at least one clock cycle, the pre-closing moment (i.e., moment t6) differs from the latching moment (i.e., moment t5) by at least half a clock cycle, and the ending moment (i.e., moment t7) differs from the pre-closing moment (i.e., moment t6) by at least half a clock cycle.

[0083] In this embodiment, the intermediate moment (i.e., moment t3) differs from the second edge change moment (i.e., moment t2) by one and a half clock cycles, the sampling moment (i.e., moment t4) differs from the intermediate moment (i.e., moment t3) by half a clock cycle, the latching moment (i.e., moment t5) differs from the sampling moment (i.e., moment t4) by one clock cycle, the pre-closing moment (i.e., moment t6) differs from the latching moment (i.e., moment t5) by half a clock cycle, and the ending moment (i.e., moment t7) differs from the pre-closing moment (i.e., moment t6) by half a clock cycle.

[0084] Embodiment 2

[0085] like Fig. 9 As shown, this embodiment provides a data recognition and latch reconstruction control circuit 110, including a recognition and latch reconstruction control module 111 and a clock oscillator 112. The recognition and latch reconstruction control module 111 uses the clock oscillator 112 to execute the data recognition and latch reconstruction control method as described in Example 1; wherein the clock oscillator 112 is controlled by the recognition and latch reconstruction control module 111 to start or stop, and provides a clock signal to the recognition and latch reconstruction control module 111 after starting.

[0086] Specifically, the identification and latching reconstruction control module 111 includes an identification and reconstruction control unit 111 a , a forwarding unit 111 b , a sampling unit 111 c and a latching unit 111 d .

[0087] The identification and reconstruction control unit 111a receives the input signal Data_in, and performs the data identification and latch reconstruction control method with the help of the clock oscillator 112 to provide the reconstructed data signal Data_out, the sampling control signal Data_sample and the latch control signal Data_lock. The identification and reconstruction control unit 111a performs data reconstruction on the valid data signal (including the header data signal and the remaining data signal) to generate the reconstructed data signal Data_out.

[0088] The identification and reconstruction control unit 111a also performs a category determination on the valid data signal to determine whether the valid data signal is a header data signal or a remaining data signal, and provides a category indication signal Data_ind based on the determination result; for example, the first 24 bits are specified as the header data signal, and the 25th bit onwards are the remaining data signal, and a category determination is performed based on the number of bits of the valid data signal and a category indication signal Data_ind is provided, wherein the category indication signal Data_ind is at a low level, indicating that the valid data signal is a header data signal, and the category indication signal Data_ind is at a high level, indicating that the valid data signal is a remaining data signal.

[0089] The forwarding unit 111b is connected to the identification and reconstruction control unit 111a, and when the valid data signal is the residual data signal, the reconstructed data signal Data_out is forwarded to facilitate the next level of LED driving display; for example, when the category indication signal Data_ind is at a high level, the forwarding unit 111c forwards the reconstructed data signal Data_out.

[0090] The sampling unit 111c is connected to the identification and reconstruction control unit 111a. When the valid data signal is a header data signal, the sampling unit 111c performs data sampling on the header data signal according to the sampling control signal Data_sample to distinguish whether the valid data signal is a data "0" code or a data "1" code; for example, when the category indication signal Data_ind is at a low level and at the rising edge of the sampling control signal Data_sample, the sampling unit 111d performs data sampling on the header data signal.

[0091] The latch unit 111d is connected to the identification and reconstruction control unit 111a and the sampling unit 111c, and is used to latch the sampled data signal of the sampling unit 111c according to the latch control signal Data_lock, so as to facilitate the LED driving display at this level; for example, at the rising edge of the latch control signal Data_lock, the latch unit 111d latches the sampled data signal.

[0092] The data identification and latch reconstruction control circuit 110 of this embodiment prohibits data sampling, latching and data reconstruction forwarding of invalid data signals when the input signal is an invalid data signal, and performs data sampling, latching and data reconstruction forwarding on valid data signals only when the input signal is a valid data signal.

[0093] Embodiment 3

[0094] like Fig.10 As shown, this embodiment provides an LED driving chip 100 , including the data recognition and latch reconstruction control circuit 110 as described in the second embodiment; further, it also includes a controller 120 and an LED driving circuit 130 .

[0095] The controller 120 sends an input signal, including a single-line return-to-zero code data signal, to the data identification and latch reconstruction control circuit 110 via the data line; the data identification and latch reconstruction control circuit 110 identifies the validity of the input signal, and when the input signal is a valid data signal, performs data sampling, latching, and data reconstruction and forwarding on the valid data signal; the LED driving circuit 130 drives and displays the LED at this level according to the latched data signal.

[0096] Embodiment 4

[0097] like Fig.11 and Fig.12 As shown, this embodiment provides an LED light strip, including the LED driver chip 100 as described in the third embodiment; further, it also includes an LED light string 200.

[0098] In practical applications, the LED driver chip 100 usually has five ports, including a positive power terminal VDD, a negative power terminal GND, a data input terminal DIN, a data output terminal DOUT, and a driver terminal LED.

[0099] Among them, the number of LED driver chips 100 is greater than or equal to two, the number of LED light strings 200 is greater than or equal to two, one LED driver chip 100 corresponds to at least one LED light string 200, and the LED light string 200 is connected between the positive power terminal VDD of the corresponding LED driver chip 100 and the driving end LED.

[0100] In one possible implementation, Fig.11As shown, the positive power terminals VDD of each LED driver chip 100 are connected to each other and serve as the positive power terminal VS of the LED light strip, and the negative power terminals GND of each LED driver chip 100 are connected to each other and serve as the negative power terminal GS of the LED light strip; the data output terminal DOUT of the previous-stage LED driver chip 100 is connected to the data input terminal DIN of the next-stage LED driver chip 100, the data input terminal DIN of the first-stage LED driver chip 100 serves as the data input terminal IN of the LED light strip, and the data output terminal DOUT of the last-stage LED driver chip 100 serves as the data output terminal OUT of the LED light strip.

[0101] In another possible implementation, Fig.12 As shown, the negative power terminal GND of the previous-stage LED driver chip 100 is connected to the positive power terminal VDD of the next-stage LED driver chip 100, the positive power terminal of the first-stage LED driver chip 100 serves as the positive power terminal VS of the LED light strip, and the negative power terminal GND of the last-stage LED driver chip 100 serves as the negative power terminal GS of the LED light strip; the data output terminal DOUT of the previous-stage LED driver chip 100 is connected to the data input terminal DIN of the next-stage LED driver chip 100, the data input terminal DIN of the first-stage LED driver chip 100 serves as the data input terminal IN of the LED light strip, and the data output terminal DOUT of the last-stage LED driver chip 100 serves as the data output terminal OUT of the LED light strip.

[0102] In summary, the data identification and latch reconstruction control method, circuit, LED driver chip and light strip of the present invention can identify invalid data signals (such as peak burr signals or narrow pulse signals, etc.) when they appear on the data line, and only perform data sampling latching and data reconstruction forwarding on valid data signals (such as single-line return-to-zero code data signals), thereby avoiding invalid data signals from being transmitted on the LED light strip data link, ensuring the correctness of data link transmission, and thus avoiding LED light strip display errors. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0103] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A data identification and latch reconstruction control method, It is characterized in that include: Performing rising edge detection on an input signal, and enabling a clock oscillator when a rising edge of the input signal is detected, the clock oscillator starts and generates a clock signal; Performing validity identification on the input signal by means of the clock signal to determine whether the input signal is an invalid data signal or a valid data signal; When the input signal is the valid data signal, a data "0" code or a data "1" code is determined for the valid data signal, and data sampling, latching and data reconstruction control are performed on the valid data signal according to the determination result.

2. The data identification and latch reconstruction control method according to claim 1, It is characterized in that Methods for identifying the validity of input signals using clock signals include: Recording the first edge change moment of the clock signal as a first edge change moment, and detecting the level of the input signal at the first edge change moment; If the level of the input signal at the first edge change moment is a low level, the input signal is determined to be the invalid data signal; otherwise, the input signal is determined to be the valid data signal.

3. The data identification and latch reconstruction control method according to claim 2, It is characterized in that The second edge change moment of the clock signal is recorded as the second edge change moment; when it is determined that the input signal is the invalid data signal, the generation of the reconstructed data signal is prohibited at the first edge change moment, and the clock oscillator is stopped at the second edge change moment to prohibit the generation of the sampling control signal and the latch control signal.

4. The data identification and latch reconstruction control method according to claim 1, It is characterized in that The method for determining whether a valid data signal is a data "0" code or a data "1" code includes: Setting a sampling time according to the pulse width time of the data "0" code and the data "1" code, and detecting the level of the valid data signal at the sampling time; If the level of the valid data signal at the sampling time is low, the valid data signal is determined to be a data "0" code; otherwise, the valid data signal is determined to be a data "1" code; The first edge change moment of the clock signal is recorded as the first edge change moment, the second edge change moment of the clock signal is recorded as the second edge change moment, and the sampling moment is located after the second edge change moment.

5. The data identification and latch reconstruction control method according to claim 4, It is characterized in that The method for performing data sampling, latching and data reconstruction control on a valid data signal according to a determination result includes: When the input signal is the valid data signal, starting to generate a reconstructed data signal at the first edge change moment; If it is determined that the valid data signal is a data "0" code, then: starting to generate a sampling control signal at the sampling time, starting to generate a latch control signal at the latching time, and stopping generating the reconstructed data signal according to the time of the falling edge of the valid data signal; If it is determined that the valid data signal is a data "1" code, then: the sampling control signal starts to be generated at the sampling time, the latch control signal starts to be generated at the latching time, and the reconstructed data signal stops to be generated at the pre-setting time; The latching time is after the sampling time, and the pre-locking time is after the sampling time.

6. The data identification and latch reconstruction control method according to claim 5, It is characterized in that The method for stopping generating a reconstructed data signal according to the time at which the falling edge of the valid data signal occurs includes: Setting an intermediate time between the second edge change time and the sampling time, and detecting the level of the valid data signal at the intermediate time; If the level of the valid data signal at the intermediate moment is a low level, then: determining in advance that the valid data signal is a data "0" code, and stopping generating the reconstructed data signal at the intermediate moment; If the level of the valid data signal at the intermediate moment is a high level, performing falling edge detection on the valid data signal between the intermediate moment and the sampling moment; If a falling edge is detected, then: determining in advance that the valid data signal is a data "0" code, and stopping generating the reconstructed data signal at the time of the falling edge; If no falling edge is detected, then: stopping generating the reconstructed data signal at the sampling time.

7. The data identification and latch reconstruction control method according to claim 5, It is characterized in that An end time is set, and the clock oscillator is stopped at the end time; wherein the end time is the same as the pre-closing time or the end time is after the pre-closing time.

8. The data identification and latch reconstruction control method according to claim 7, It is characterized in that The end time is after the pre-closure time, the intermediate time differs from the second edge change time by at least half a clock cycle, the sampling time differs from the intermediate time by at least half a clock cycle, the latching time differs from the sampling time by at least one clock cycle, the pre-closure time differs from the latching time by at least half a clock cycle, and the end time differs from the pre-closure time by at least half a clock cycle.

9. A data recognition and latch reconstruction control circuit, It is characterized in that It comprises an identification and latch reconstruction control module and a clock oscillator, and the identification and latch reconstruction control module uses the clock oscillator to execute the data identification and latch reconstruction control method as described in any one of claims 1 to 8.

10. An LED driver chip, It is characterized in that It includes the data recognition and latch reconstruction control circuit as claimed in claim 9.

11. An LED light strip, It is characterized in that Comprising the LED driver chip as claimed in claim 10.

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